diff options
| author | Andrew Jeffery <andrew@aj.id.au> | 2019-07-24 17:31:55 +0930 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-07-29 00:52:51 +0200 |
| commit | 674fa8daa8c922c42a84b6aa85bf5ddc616accf5 (patch) | |
| tree | 7252ef81faa99b19a47b143a58d54246f139ab42 /drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | |
| parent | 5f9e832c137075045d15cd6899ab0505cfb2ca4b (diff) | |
pinctrl: aspeed-g5: Delay acquisition of regmaps
While sorting out some devicetree issues I found that the pinctrl driver
was failing to acquire its GFX regmap even though the phandle was
present in the devicetree:
[ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail
Without access to the GFX regmap we fail to configure the mux for the
VPO function:
[ 1.548866] pinctrl core: add 1 pinctrl maps
[ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO
[ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display
[ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display
...
[ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display
[ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display
[ 1.563113] Muxing pin 144 for VPO
[ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000
[ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back
This turned out to be a simple problem of timing: The ASPEED pinctrl
driver is probed during arch_initcall(), while GFX is processed much
later. As such the GFX syscon is not yet registered during the pinctrl
probe() and we get an -EPROBE_DEFER when we try to look it up, however
we must not defer probing the pinctrl driver for the inability to mux
some GFX-related functions.
Switch to lazily grabbing the regmaps when they're first required by the
mux configuration. This generates a bit of noise in the patch as we have
to drop the `const` qualifier on arguments for several function
prototypes, but has the benefit of working.
I've smoke tested this for the ast2500-evb under qemu with a dummy
graphics device. We now succeed in our attempts to configure the SoC's
VPO pinmux function.
Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c')
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index 384396cbb22d..22256576b69a 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -2412,7 +2412,7 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = { { PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 }, }; -static int aspeed_g4_sig_expr_set(const struct aspeed_pinmux_data *ctx, +static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, const struct aspeed_sig_expr *expr, bool enable) { |