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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-02 16:52:55 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2023-03-09 14:07:15 +0100 |
| commit | 3abe84ea065128f5ad1025f2176156dd04b777ee (patch) | |
| tree | f2457b97dd93a30f81b5e5450b27101f768b78cb /drivers/pinctrl/qcom/pinctrl-msm.c | |
| parent | 6cf103bc03f8a915c8b5c8733a0e7404112f88d8 (diff) | |
dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
The description of second IO address is a bit confusing. It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base. The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230302155255.857065-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
0 files changed, 0 insertions, 0 deletions