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authorAgrawal, Nitesh-kumar <Nitesh-kumar.Agrawal@amd.com>2016-09-09 15:18:09 +0000
committerLinus Walleij <linus.walleij@linaro.org>2016-09-13 10:24:37 +0200
commite084448b5d26bfebe8a7b9c43bb57e685567563d (patch)
treecbb37c66f073ff12968cc57edd353232e1b5a16c /drivers/pinctrl
parent0eb9f683336d7eb99a3b75987620417c574ffb57 (diff)
pinctrl/amd: switch to using a bool for level
The earlier patch can be simplified by using a bool to indicate level trigger. Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com> Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> [Fixup to earlier manually applied patch] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/pinctrl-amd.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 962746e6ab04..be8ae98871f5 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -403,7 +403,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
int ret = 0;
u32 pin_reg;
unsigned long flags;
- u32 level_trig;
+ bool level_trig;
u32 active_level;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
@@ -416,13 +416,12 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
* default settings, ignore incoming settings from client and use
* BIOS settings to configure GPIO register.
*/
- level_trig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF);
+ level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF));
active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
- if((!level_trig) &&
- ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) {
+ if(level_trig &&
+ ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH))
type = IRQ_TYPE_EDGE_FALLING;
- }
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING: