diff options
| author | Gayatri Kammela <gayatri.kammela@intel.com> | 2020-10-06 15:47:02 -0700 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2020-10-07 23:06:29 +0200 |
| commit | 025f26de7fa0fc40c8baf6c19fb273500f3321f0 (patch) | |
| tree | 8c9a2a1e384c158cb2fc4c3370e015801caa8f67 /drivers/platform/x86/intel_pmc_core.h | |
| parent | 652036bd5be0ac94fd1db851d72ece8ee133c74d (diff) | |
platform/x86: intel_pmc_core: Fix the slp_s0 counter displayed value
slp_s0 counter value displayed via debugfs interface is calculated by
multiplying the granularity for crystal oscillator tick as 100us with
the value read from using slp_s0 offset. But the granularity of the tick
varies from platform to platform and it needs to be fixed.
Hence, specify granularity of the tick for each platform, so that the
value of the slp_s0 counter is accurate.
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20201006224702.12697-4-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform/x86/intel_pmc_core.h')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 5eae55d80226..f33cd2c34835 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -30,7 +30,7 @@ #define SPT_PMC_MPHY_CORE_STS_1 0x1142 #define SPT_PMC_MPHY_COM_STS_0 0x1155 #define SPT_PMC_MMIO_REG_LEN 0x1000 -#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 +#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68 #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) #define MTPMC_MASK 0xffff0000 #define PPFEAR_MAX_NUM_ENTRIES 12 @@ -185,8 +185,10 @@ enum ppfear_regs { #define ICL_PPFEAR_NUM_ENTRIES 9 #define ICL_NUM_IP_IGN_ALLOWED 20 #define ICL_PMC_LTR_WIGIG 0x1BFC +#define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 #define TGL_NUM_IP_IGN_ALLOWED 22 +#define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A /* * Tigerlake Power Management Controller register offsets @@ -245,6 +247,7 @@ struct pmc_reg_map { const struct pmc_bit_map *msr_sts; const struct pmc_bit_map **lpm_sts; const u32 slp_s0_offset; + const int slp_s0_res_counter_step; const u32 ltr_ignore_offset; const int regmap_length; const u32 ppfear0_offset; |