diff options
| author | Gayatri Kammela <gayatri.kammela@intel.com> | 2021-04-16 20:12:51 -0700 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2021-04-19 10:44:28 +0200 |
| commit | 43ef6c226a60b1c52890791af73f7015f68a315a (patch) | |
| tree | e071fd2764dd06b8e488ccd519eaa53dc3552708 /drivers/platform/x86/intel_pmc_core.h | |
| parent | 8074a79fad2e34fce11ea2b2c515b984fc6b2a08 (diff) | |
platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information
and supports a few additional registers. Hence add the LTR registers
specific to Tiger Lake to the cnp_ltr_show_map[].
Also adjust the number of LTR IPs for Tiger Lake to the correct amount.
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Link: https://lore.kernel.org/r/20210417031252.3020837-9-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform/x86/intel_pmc_core.h')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index c45805671c4a..e8dae9c6c45f 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -191,8 +191,10 @@ enum ppfear_regs { #define GET_X2_COUNTER(v) ((v) >> 1) #define LPM_STS_LATCH_MODE BIT(31) -#define TGL_NUM_IP_IGN_ALLOWED 22 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A +#define TGL_PMC_LTR_THC0 0x1C04 +#define TGL_PMC_LTR_THC1 0x1C08 +#define TGL_NUM_IP_IGN_ALLOWED 23 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ /* |