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authorZhang Rui <rui.zhang@intel.com>2019-07-10 21:44:23 +0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2019-07-11 15:08:57 +0200
commit8310e8202f24d674b6b2bd341af15d72299f696d (patch)
treed17f22a688e733d134989c6c196ee233645c2573 /drivers/powercap
parentf7c4e0c89bbd0f008b33d9dce02e207d9dea9f54 (diff)
intel_rapl: remove hardcoded register index
enum rapl_domain_reg_id is defined for the RAPL registers for each RAPL domain, thus use it whenever possible. Reviewed-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com> Tested-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/powercap')
-rw-r--r--drivers/powercap/intel_rapl.c44
1 files changed, 22 insertions, 22 deletions
diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
index 45d5f22d00e8..9be9f20ff056 100644
--- a/drivers/powercap/intel_rapl.c
+++ b/drivers/powercap/intel_rapl.c
@@ -642,11 +642,11 @@ static void rapl_init_domains(struct rapl_package *rp)
case BIT(RAPL_DOMAIN_PACKAGE):
rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
rd->id = RAPL_DOMAIN_PACKAGE;
- rd->regs[0] = MSR_PKG_POWER_LIMIT;
- rd->regs[1] = MSR_PKG_ENERGY_STATUS;
- rd->regs[2] = MSR_PKG_PERF_STATUS;
- rd->regs[3] = 0;
- rd->regs[4] = MSR_PKG_POWER_INFO;
+ rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PKG_POWER_LIMIT;
+ rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PKG_ENERGY_STATUS;
+ rd->regs[RAPL_DOMAIN_REG_PERF] = MSR_PKG_PERF_STATUS;
+ rd->regs[RAPL_DOMAIN_REG_POLICY] = 0;
+ rd->regs[RAPL_DOMAIN_REG_INFO] = MSR_PKG_POWER_INFO;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
rd->rpl[1].prim_id = PL2_ENABLE;
@@ -655,33 +655,33 @@ static void rapl_init_domains(struct rapl_package *rp)
case BIT(RAPL_DOMAIN_PP0):
rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
rd->id = RAPL_DOMAIN_PP0;
- rd->regs[0] = MSR_PP0_POWER_LIMIT;
- rd->regs[1] = MSR_PP0_ENERGY_STATUS;
- rd->regs[2] = 0;
- rd->regs[3] = MSR_PP0_POLICY;
- rd->regs[4] = 0;
+ rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PP0_POWER_LIMIT;
+ rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PP0_ENERGY_STATUS;
+ rd->regs[RAPL_DOMAIN_REG_PERF] = 0;
+ rd->regs[RAPL_DOMAIN_REG_POLICY] = MSR_PP0_POLICY;
+ rd->regs[RAPL_DOMAIN_REG_INFO] = 0;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
break;
case BIT(RAPL_DOMAIN_PP1):
rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
rd->id = RAPL_DOMAIN_PP1;
- rd->regs[0] = MSR_PP1_POWER_LIMIT;
- rd->regs[1] = MSR_PP1_ENERGY_STATUS;
- rd->regs[2] = 0;
- rd->regs[3] = MSR_PP1_POLICY;
- rd->regs[4] = 0;
+ rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PP1_POWER_LIMIT;
+ rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PP1_ENERGY_STATUS;
+ rd->regs[RAPL_DOMAIN_REG_PERF] = 0;
+ rd->regs[RAPL_DOMAIN_REG_POLICY] = MSR_PP1_POLICY;
+ rd->regs[RAPL_DOMAIN_REG_INFO] = 0;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
break;
case BIT(RAPL_DOMAIN_DRAM):
rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
rd->id = RAPL_DOMAIN_DRAM;
- rd->regs[0] = MSR_DRAM_POWER_LIMIT;
- rd->regs[1] = MSR_DRAM_ENERGY_STATUS;
- rd->regs[2] = MSR_DRAM_PERF_STATUS;
- rd->regs[3] = 0;
- rd->regs[4] = MSR_DRAM_POWER_INFO;
+ rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_DRAM_POWER_LIMIT;
+ rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_DRAM_ENERGY_STATUS;
+ rd->regs[RAPL_DOMAIN_REG_PERF] = MSR_DRAM_PERF_STATUS;
+ rd->regs[RAPL_DOMAIN_REG_POLICY] = 0;
+ rd->regs[RAPL_DOMAIN_REG_INFO] = MSR_DRAM_POWER_INFO;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
rd->domain_energy_unit =
@@ -1282,8 +1282,8 @@ static int __init rapl_register_psys(void)
rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
rd->id = RAPL_DOMAIN_PLATFORM;
- rd->regs[0] = MSR_PLATFORM_POWER_LIMIT;
- rd->regs[1] = MSR_PLATFORM_ENERGY_STATUS;
+ rd->regs[RAPL_DOMAIN_REG_LIMIT] = MSR_PLATFORM_POWER_LIMIT;
+ rd->regs[RAPL_DOMAIN_REG_STATUS] = MSR_PLATFORM_ENERGY_STATUS;
rd->rpl[0].prim_id = PL1_ENABLE;
rd->rpl[0].name = pl1_name;
rd->rpl[1].prim_id = PL2_ENABLE;