diff options
| author | Ondrej Zary <linux@rainbow-software.org> | 2016-01-03 16:06:15 +1100 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2016-01-06 21:43:10 -0500 |
| commit | 12150797d064e2936154a8c01be24ce1b0115cfe (patch) | |
| tree | 06c8396a0872e40d40a2f94dcf2b556208f932aa /drivers/scsi/NCR5380.h | |
| parent | f03946210d67be9a33ad63f6a0eed7cdf8c28334 (diff) | |
ncr5380: Use runtime register mapping
Convert compile-time C400_ register mapping to runtime mapping.
This removes the weird negative register offsets and allows adding
additional mappings.
While at it, convert read/write loops into insb/outsb.
Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/NCR5380.h')
| -rw-r--r-- | drivers/scsi/NCR5380.h | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/drivers/scsi/NCR5380.h b/drivers/scsi/NCR5380.h index ee83ab5f32e8..a79288682a74 100644 --- a/drivers/scsi/NCR5380.h +++ b/drivers/scsi/NCR5380.h @@ -163,8 +163,7 @@ /* Write any value to this register to start an ini mode DMA receive */ #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */ -#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */ - +/* NCR 53C400(A) Control Status Register bits: */ #define CSR_RESET 0x80 /* wo Resets 53c400 */ #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */ #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */ @@ -181,16 +180,6 @@ #define CSR_BASE CSR_53C80_INTR #endif -/* Number of 128-byte blocks to be transferred */ -#define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */ - -/* Resume transfer after disconnect */ -#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */ - -/* Access to host buffer stack */ -#define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */ - - /* Note : PHASE_* macros are based on the values of the STATUS register */ #define PHASE_MASK (SR_MSG | SR_CD | SR_IO) |