Merge tag 'staging-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging and IIO driver updates from Greg KH:
 "Here is the big staging/iio driver update for 5.4-rc1.

  Lots of churn here, with a few driver/filesystems moving out of
  staging finally:

     - erofs moved out of staging

     - greybus core code moved out of staging

  Along with that, a new filesytem has been added:

     - extfat

  to provide support for those devices requiring that filesystem (i.e.
  transfer devices to/from windows systems or printers)

  Other than that, there a number of new IIO drivers, and lots and lots
  and lots of staging driver cleanups and minor fixes as people continue
  to dig into those for easy changes.

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'staging-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (453 commits)
  Staging: gasket: Use temporaries to reduce line length.
  Staging: octeon: Avoid several usecases of strcpy
  staging: vhciq_core: replace snprintf with scnprintf
  staging: wilc1000: avoid twice IRQ handler execution for each single interrupt
  staging: wilc1000: remove unused interrupt status handling code
  staging: fbtft: make several arrays static const, makes object smaller
  staging: rtl8188eu: make two arrays static const, makes object smaller
  staging: rtl8723bs: core: Remove Macro "IS_MAC_ADDRESS_BROADCAST"
  dt-bindings: anybus-controller: move to staging/ tree
  staging: emxx_udc: remove local TRUE/FALSE definition
  staging: wilc1000: look for rtc_clk clock
  staging: dt-bindings: wilc1000: add optional rtc_clk property
  staging: nvec: make use of devm_platform_ioremap_resource
  staging: exfat: drop unused function parameter
  Staging: exfat: Avoid use of strcpy
  staging: exfat: use integer constants
  staging: exfat: cleanup spacing for casts
  staging: exfat: cleanup spacing for operators
  staging: rtl8723bs: hal: remove redundant variable n
  staging: pi433: Fix typo in documentation
  ...

1 files changed, 46 insertions, 53 deletions

diff --git a/drivers/staging/most/dim2/hal.c b/drivers/staging/most/dim2/hal.c
index 699e02f83bd4..39e17a7d2f24 100644
--- a/drivers/staging/most/dim2/hal.c
+++ b/drivers/staging/most/dim2/hal.c
@@ -13,6 +13,7 @@
 #include "reg.h"
 #include <linux/stddef.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
 
 /*
  * Size factor for isochronous DBR buffer.
@@ -143,13 +144,13 @@ static void free_dbr(int offs, int size)
 
 static void dim2_transfer_madr(u32 val)
 {
-	dimcb_io_write(&g.dim2->MADR, val);
+	writel(val, &g.dim2->MADR);
 
 	/* wait for transfer completion */
-	while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1)
+	while ((readl(&g.dim2->MCTL) & 1) != 1)
 		continue;
 
-	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */
+	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
 }
 
 static void dim2_clear_dbr(u16 addr, u16 size)
@@ -159,8 +160,8 @@ static void dim2_clear_dbr(u16 addr, u16 size)
 	u16 const end_addr = addr + size;
 	u32 const cmd = bit_mask(MADR_WNR_BIT) | bit_mask(MADR_TB_BIT);
 
-	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */
-	dimcb_io_write(&g.dim2->MDAT0, 0);
+	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
+	writel(0, &g.dim2->MDAT0);
 
 	for (; addr < end_addr; addr++)
 		dim2_transfer_madr(cmd | addr);
@@ -170,28 +171,28 @@ static u32 dim2_read_ctr(u32 ctr_addr, u16 mdat_idx)
 {
 	dim2_transfer_madr(ctr_addr);
 
-	return dimcb_io_read((&g.dim2->MDAT0) + mdat_idx);
+	return readl((&g.dim2->MDAT0) + mdat_idx);
 }
 
 static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value)
 {
 	enum { MADR_WNR_BIT = 31 };
 
-	dimcb_io_write(&g.dim2->MCTL, 0);   /* clear transfer complete */
+	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
 
 	if (mask[0] != 0)
-		dimcb_io_write(&g.dim2->MDAT0, value[0]);
+		writel(value[0], &g.dim2->MDAT0);
 	if (mask[1] != 0)
-		dimcb_io_write(&g.dim2->MDAT1, value[1]);
+		writel(value[1], &g.dim2->MDAT1);
 	if (mask[2] != 0)
-		dimcb_io_write(&g.dim2->MDAT2, value[2]);
+		writel(value[2], &g.dim2->MDAT2);
 	if (mask[3] != 0)
-		dimcb_io_write(&g.dim2->MDAT3, value[3]);
+		writel(value[3], &g.dim2->MDAT3);
 
-	dimcb_io_write(&g.dim2->MDWE0, mask[0]);
-	dimcb_io_write(&g.dim2->MDWE1, mask[1]);
-	dimcb_io_write(&g.dim2->MDWE2, mask[2]);
-	dimcb_io_write(&g.dim2->MDWE3, mask[3]);
+	writel(mask[0], &g.dim2->MDWE0);
+	writel(mask[1], &g.dim2->MDWE1);
+	writel(mask[2], &g.dim2->MDWE2);
+	writel(mask[3], &g.dim2->MDWE3);
 
 	dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr);
 }
@@ -356,15 +357,13 @@ static void dim2_configure_channel(
 	dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1);
 
 	/* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */
-	dimcb_io_write(&g.dim2->ACMR0,
-		       dimcb_io_read(&g.dim2->ACMR0) | bit_mask(ch_addr));
+	writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0);
 }
 
 static void dim2_clear_channel(u8 ch_addr)
 {
 	/* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */
-	dimcb_io_write(&g.dim2->ACMR0,
-		       dimcb_io_read(&g.dim2->ACMR0) & ~bit_mask(ch_addr));
+	writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0);
 
 	dim2_clear_cat(AHB_CAT, ch_addr);
 	dim2_clear_adt(ch_addr);
@@ -373,7 +372,7 @@ static void dim2_clear_channel(u8 ch_addr)
 	dim2_clear_cdt(ch_addr);
 
 	/* clear channel status bit */
-	dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr));
+	writel(bit_mask(ch_addr), &g.dim2->ACSR0);
 }
 
 /* -------------------------------------------------------------------------- */
@@ -471,7 +470,7 @@ static inline bool check_bytes_per_frame(u32 bytes_per_frame)
 	return true;
 }
 
-static inline u16 norm_ctrl_async_buffer_size(u16 buf_size)
+u16 dim_norm_ctrl_async_buffer_size(u16 buf_size)
 {
 	u16 const max_size = (u16)ADT1_CTRL_ASYNC_BD_MASK + 1u;
 
@@ -517,20 +516,20 @@ static inline u16 norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame)
 static void dim2_cleanup(void)
 {
 	/* disable MediaLB */
-	dimcb_io_write(&g.dim2->MLBC0, false << MLBC0_MLBEN_BIT);
+	writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0);
 
 	dim2_clear_ctram();
 
 	/* disable mlb_int interrupt */
-	dimcb_io_write(&g.dim2->MIEN, 0);
+	writel(0, &g.dim2->MIEN);
 
 	/* clear status for all dma channels */
-	dimcb_io_write(&g.dim2->ACSR0, 0xFFFFFFFF);
-	dimcb_io_write(&g.dim2->ACSR1, 0xFFFFFFFF);
+	writel(0xFFFFFFFF, &g.dim2->ACSR0);
+	writel(0xFFFFFFFF, &g.dim2->ACSR1);
 
 	/* mask interrupts for all channels */
-	dimcb_io_write(&g.dim2->ACMR0, 0);
-	dimcb_io_write(&g.dim2->ACMR1, 0);
+	writel(0, &g.dim2->ACMR0);
+	writel(0, &g.dim2->ACMR1);
 }
 
 static void dim2_initialize(bool enable_6pin, u8 mlb_clock)
@@ -538,23 +537,22 @@ static void dim2_initialize(bool enable_6pin, u8 mlb_clock)
 	dim2_cleanup();
 
 	/* configure and enable MediaLB */
-	dimcb_io_write(&g.dim2->MLBC0,
-		       enable_6pin << MLBC0_MLBPEN_BIT |
-		       mlb_clock << MLBC0_MLBCLK_SHIFT |
-		       g.fcnt << MLBC0_FCNT_SHIFT |
-		       true << MLBC0_MLBEN_BIT);
+	writel(enable_6pin << MLBC0_MLBPEN_BIT |
+	       mlb_clock << MLBC0_MLBCLK_SHIFT |
+	       g.fcnt << MLBC0_FCNT_SHIFT |
+	       true << MLBC0_MLBEN_BIT,
+	       &g.dim2->MLBC0);
 
 	/* activate all HBI channels */
-	dimcb_io_write(&g.dim2->HCMR0, 0xFFFFFFFF);
-	dimcb_io_write(&g.dim2->HCMR1, 0xFFFFFFFF);
+	writel(0xFFFFFFFF, &g.dim2->HCMR0);
+	writel(0xFFFFFFFF, &g.dim2->HCMR1);
 
 	/* enable HBI */
-	dimcb_io_write(&g.dim2->HCTL, bit_mask(HCTL_EN_BIT));
+	writel(bit_mask(HCTL_EN_BIT), &g.dim2->HCTL);
 
 	/* configure DMA */
-	dimcb_io_write(&g.dim2->ACTL,
-		       ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT |
-		       true << ACTL_SCE_BIT);
+	writel(ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT |
+	       true << ACTL_SCE_BIT, &g.dim2->ACTL);
 }
 
 static bool dim2_is_mlb_locked(void)
@@ -562,12 +560,12 @@ static bool dim2_is_mlb_locked(void)
 	u32 const mask0 = bit_mask(MLBC0_MLBLK_BIT);
 	u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) |
 			  bit_mask(MLBC1_LOCKERR_BIT);
-	u32 const c1 = dimcb_io_read(&g.dim2->MLBC1);
+	u32 const c1 = readl(&g.dim2->MLBC1);
 	u32 const nda_mask = (u32)MLBC1_NDA_MASK << MLBC1_NDA_SHIFT;
 
-	dimcb_io_write(&g.dim2->MLBC1, c1 & nda_mask);
-	return (dimcb_io_read(&g.dim2->MLBC1) & mask1) == 0 &&
-	       (dimcb_io_read(&g.dim2->MLBC0) & mask0) != 0;
+	writel(c1 & nda_mask, &g.dim2->MLBC1);
+	return (readl(&g.dim2->MLBC1) & mask1) == 0 &&
+	       (readl(&g.dim2->MLBC0) & mask0) != 0;
 }
 
 /* -------------------------------------------------------------------------- */
@@ -590,7 +588,7 @@ static inline bool service_channel(u8 ch_addr, u8 idx)
 	dim2_write_ctr_mask(ADT + ch_addr, mask, adt_w);
 
 	/* clear channel status bit */
-	dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr));
+	writel(bit_mask(ch_addr), &g.dim2->ACSR0);
 
 	return true;
 }
@@ -652,7 +650,7 @@ static bool channel_start(struct dim_channel *ch, u32 buf_addr, u16 buf_size)
 		return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, "Bad buffer size");
 
 	if (ch->packet_length == 0 && ch->bytes_per_frame == 0 &&
-	    buf_size != norm_ctrl_async_buffer_size(buf_size))
+	    buf_size != dim_norm_ctrl_async_buffer_size(buf_size))
 		return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE,
 				    "Bad control/async buffer size");
 
@@ -776,13 +774,8 @@ static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx,
 
 void dim_service_mlb_int_irq(void)
 {
-	dimcb_io_write(&g.dim2->MS0, 0);
-	dimcb_io_write(&g.dim2->MS1, 0);
-}
-
-u16 dim_norm_ctrl_async_buffer_size(u16 buf_size)
-{
-	return norm_ctrl_async_buffer_size(buf_size);
+	writel(0, &g.dim2->MS0);
+	writel(0, &g.dim2->MS1);
 }
 
 /**
@@ -829,7 +822,7 @@ u8 dim_init_async(struct dim_channel *ch, u8 is_tx, u16 ch_address,
 	if (is_tx && !g.atx_dbr.ch_addr) {
 		g.atx_dbr.ch_addr = ch->addr;
 		dbrcnt_init(ch->addr, ch->dbr_size);
-		dimcb_io_write(&g.dim2->MIEN, bit_mask(20));
+		writel(bit_mask(20), &g.dim2->MIEN);
 	}
 
 	return ret;
@@ -896,7 +889,7 @@ u8 dim_destroy_channel(struct dim_channel *ch)
 		return DIM_ERR_DRIVER_NOT_INITIALIZED;
 
 	if (ch->addr == g.atx_dbr.ch_addr) {
-		dimcb_io_write(&g.dim2->MIEN, 0);
+		writel(0, &g.dim2->MIEN);
 		g.atx_dbr.ch_addr = 0;
 	}