diff options
| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2019-01-04 08:08:24 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-01-07 11:28:15 +0100 |
| commit | 9e2ddbdd9218bf0e465d19daecdd053052ffd79c (patch) | |
| tree | 45e6008cfe6de62102bfe42b34cac0e2b92a245a /drivers/staging/mt7621-pci-phy | |
| parent | 06184ba5a33a16f1772857d2cf97f7f14c8018c7 (diff) | |
staging: mt7621-pci-phy: dt-bindings: add bindings for Mediatek MT7621 Pcie PHY
Add bindings documentation for PCie PHY of Mediatek MT7621.
This file will be moved into its appropiate documentation bindings'place
when this driver is mainlined.
CC: Device Tree mailing list <devicetree@vger.kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci-phy')
| -rw-r--r-- | drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt b/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt new file mode 100644 index 000000000000..33a8a698bdd0 --- /dev/null +++ b/drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt @@ -0,0 +1,54 @@ +Mediatek Mt7621 PCIe PHY + +Required properties: +- compatible: must be "mediatek,mt7621-pci-phy" +- reg: base address and length of the PCIe PHY block +- #address-cells: must be 1 +- #size-cells: must be 0 + +Each PCIe PHY should be represented by a child node + +Required properties For the child node: +- reg: the PHY ID +0 - PCIe RC 0 +1 - PCIe RC 1 +- #phy-cells: must be 0 + +Example: + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1a149000 0x0700>; + #address-cells = <1>; + #size-cells = <0>; + + pcie0_port: pcie-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + pcie1_port: pcie-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1a14a000 0x0700>; + #address-cells = <1>; + #size-cells = <0>; + + pcie2_port: pcie-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + /* users of the PCIe phy */ + + pcie: pcie@1e140000 { + ... + ... + phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + };
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