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authorEugen Hristev <eugen.hristev@microchip.com>2019-11-18 08:50:36 +0000
committerWim Van Sebroeck <wim@linux-watchdog.org>2020-01-27 15:55:44 +0100
commitbb44aa09e53960c0230a645144fe566e094a2a02 (patch)
tree3024a9076e1716c39a848ab65c45ac142bc6ded3 /drivers/watchdog/at91sam9_wdt.h
parentd5226fa6dbae0569ee43ecfc08bdcd6770fc4755 (diff)
watchdog: sama5d4_wdt: addition of sam9x60 compatible watchdog
Add support for SAM9X60 WDT into sama5d4_wdt. This means that this driver gets a flag inside the data struct that represents the sam9x60 support. This flag differentiates between the two hardware blocks, and is set according to the compatible of the driver instantiation. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by-off-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/1574067012-18559-3-git-send-email-eugen.hristev@microchip.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Diffstat (limited to 'drivers/watchdog/at91sam9_wdt.h')
-rw-r--r--drivers/watchdog/at91sam9_wdt.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wdt.h
index abfe34dd760a..298d545df1a1 100644
--- a/drivers/watchdog/at91sam9_wdt.h
+++ b/drivers/watchdog/at91sam9_wdt.h
@@ -24,7 +24,10 @@
#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
#define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */
#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV)
+#define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */
+#define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */
#define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */
+#define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */
#define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */
#define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */
#define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */
@@ -37,4 +40,22 @@
#define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */
#define AT91_WDT_WDERR BIT(1) /* Watchdog Error */
+/* Watchdog Timer Value Register */
+#define AT91_SAM9X60_VR 0x08
+
+/* Watchdog Window Level Register */
+#define AT91_SAM9X60_WLR 0x0c
+/* Watchdog Period Value */
+#define AT91_SAM9X60_COUNTER (0xfffUL << 0)
+#define AT91_SAM9X60_SET_COUNTER(x) ((x) & AT91_SAM9X60_COUNTER)
+
+/* Interrupt Enable Register */
+#define AT91_SAM9X60_IER 0x14
+/* Period Interrupt Enable */
+#define AT91_SAM9X60_PERINT BIT(0)
+/* Interrupt Disable Register */
+#define AT91_SAM9X60_IDR 0x18
+/* Interrupt Status Register */
+#define AT91_SAM9X60_ISR 0x1c
+
#endif