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authorColin Ian King <colin.king@canonical.com>2016-07-12 11:59:39 +0100
committerDavid S. Miller <davem@davemloft.net>2016-07-26 15:25:31 -0700
commit45969e16f9fe27ed1175b003ef40c47902a09d05 (patch)
tree2c7d75687b7f812ea77f405216365395c5a06529 /drivers
parent79f18a0637033f588accaa05621225c60301514a (diff)
ide: hpt366: fix incorrect mask when checking at cmd_high_time
According to the HPT366 data sheet, PCI config space dword 0x40-0x43 bits 11:8 specify the primary drive cmd_high_time, however, currently just 3 bits of the 4 are being used because the mask is 0x07 and not 0x0f. Fix the mask, allowing for the 40MHz clock to be detected. Also add in missing space between switch and parenthesis to clean up a checkpatch warning. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ide/hpt366.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ide/hpt366.c b/drivers/ide/hpt366.c
index f94baadbf424..0ceae5cbd89a 100644
--- a/drivers/ide/hpt366.c
+++ b/drivers/ide/hpt366.c
@@ -1012,7 +1012,7 @@ static int init_chipset_hpt366(struct pci_dev *dev)
pci_read_config_dword(dev, 0x40, &itr1);
/* Detect PCI clock by looking at cmd_high_time. */
- switch((itr1 >> 8) & 0x07) {
+ switch ((itr1 >> 8) & 0x0f) {
case 0x09:
pci_clk = 40;
break;