diff options
| author | Mark Brown <broonie@kernel.org> | 2024-01-24 19:41:45 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-01-24 19:41:45 +0000 |
| commit | 4f38ae221e282ece6e2c39b6b85031db5564f594 (patch) | |
| tree | 8ad991955ec9a76a96afe2c0c33cec7eb3f7e1cf /drivers | |
| parent | b204aa0f99cfe3c9d796ecfc0bc6f3f89585789e (diff) | |
| parent | 737cf74b38007fd5d5d2f15d4d4bc16e5f1cbfed (diff) | |
arm64: exynos: Enable SPI for Exynos850
Merge series from Sam Protsenko <semen.protsenko@linaro.org>:
This series enables SPI for Exynos850 SoC, there are also some
dependencies that will be needed at runtime which were sent as part of
the same series but will be separately applied:
1. Enable PDMA, it's needed for SPI (dts, clk)
2. Propagate SPI src clock rate change up to DIV clocks, to make it
possible to change SPI frequency (clk driver)
4. Add SPI nodes to Exynos850 SoC dtsi
All SPI instances were tested using `spidev_test' tool in all 3 possible
modes:
- Polling mode: xfer_size <= 32
- IRQ mode: 64 >= xfer_size >= 32
- DMA mode: xfer_size > 64
with 200 kHz ... 49.9 MHz SPI frequencies. The next 3 approaches were
used:
1. Software loopback ('-l' option for `spidev_test' tool)
2. Hardware loopback (by connecting MISO line to MOSI)
3. By communicating with ATMega found on Sensors Mezzanine board [1],
programmed to act as an SPI device
and all the transactions were additionally checked on my Logic Analyzer
to make sure the SCK frequencies were actually correct.
[1] https://www.96boards.org/product/sensors-mezzanine/
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/spi-s3c64xx.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 432ec60d3568..7f7eb8f742e4 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1460,6 +1460,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, @@ -1514,6 +1525,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { { .compatible = "samsung,exynos5433-spi", .data = (void *)&exynos5433_spi_port_config, }, + { .compatible = "samsung,exynos850-spi", + .data = (void *)&exynos850_spi_port_config, + }, { .compatible = "samsung,exynosautov9-spi", .data = (void *)&exynosautov9_spi_port_config, }, |