diff options
| author | Charlene Liu <charlene.liu@amd.com> | 2019-04-26 00:29:13 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:12 -0500 |
| commit | 8bb3d7e7b5de731a990af8fe6d99a30751602f15 (patch) | |
| tree | f45bdf854a486144872155361c876d172c664a94 /drivers | |
| parent | 09104d151acfb32e0d6039d8c0f8f59e22af2c46 (diff) | |
drm/amd/display: used optimum VSTARTUP instead of MaxVStartup
[Description]
Features that are desirable for minimizing the Global Sync Period:
DRR and lateflip
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
3 files changed, 12 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 9243f275d265..ca5a7791d080 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -1671,6 +1671,8 @@ int dcn20_populate_dml_pipes_from_context( /* Unknown link capabilities, so assume max */ pipes[pipe_cnt].dout.dp_lanes = 4; } + pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; + pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.display_color_depth; switch (res_ctx->pipe_ctx[i].stream->signal) { @@ -1749,6 +1751,8 @@ int dcn20_populate_dml_pipes_from_context( pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; pipes[pipe_cnt].pipe.src.is_hsplit = 0; pipes[pipe_cnt].pipe.dest.odm_combine = 0; + pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total; + pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total; } else { struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index 21d90c6f3c88..649883777f62 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -2698,8 +2698,12 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer VStartupMargin = dml_min(VStartupMargin, Margin); } - if (mode_lib->vba.UseMaximumVStartup) - mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]; + if (mode_lib->vba.UseMaximumVStartup) { + if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) { + //only use max vstart if it is not drr or lateflip. + mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]; + } + } } } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 4e0183dd634a..75028007095c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -284,6 +284,8 @@ struct vba_vars_st { unsigned int VTAPsChroma[DC__NUM_DPP__MAX]; unsigned int HTotal[DC__NUM_DPP__MAX]; unsigned int VTotal[DC__NUM_DPP__MAX]; + unsigned int VTotal_Max[DC__NUM_DPP__MAX]; + unsigned int VTotal_Min[DC__NUM_DPP__MAX]; int DPPPerPlane[DC__NUM_DPP__MAX]; double PixelClock[DC__NUM_DPP__MAX]; double PixelClockBackEnd[DC__NUM_DPP__MAX]; |