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authorQiuxu Zhuo <qiuxu.zhuo@intel.com>2019-06-26 14:16:38 +0800
committerTony Luck <tony.luck@intel.com>2019-06-26 10:06:09 -0700
commitc4a1dd9e83ceceef6ffba82b8b274ab9b929ea14 (patch)
tree243951ca06d2b99d69ae5621ad34ed20b3bcc15c /drivers
parent5c5d3ac2064ae2466c81d40186bcc09b2d5b7892 (diff)
EDAC, i10nm: Check ECC enabling status per channel
The i10nm_edac only checks the ECC enabling status for the first channel of the memory controller. If there aren't memory DIMMs populated on the first channel, but at least one DIMM populated on the second channel, it will wrongly report that the ECC for the memory controller is disabled that fails to load the i10nm_edac driver. Fix it by checking ECC enabling status per channel. [Tony: Also report which channel has ECC disabled] Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/edac/i10nm_base.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c
index 48c6cecc9683..72cc20a90ac1 100644
--- a/drivers/edac/i10nm_base.c
+++ b/drivers/edac/i10nm_base.c
@@ -168,9 +168,9 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
EDAC_MOD_STR);
}
- if (ndimms && !i10nm_check_ecc(imc, 0)) {
- i10nm_printk(KERN_ERR, "ECC is disabled on imc %d\n",
- imc->mc);
+ if (ndimms && !i10nm_check_ecc(imc, i)) {
+ i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
+ imc->mc, i);
return -ENODEV;
}
}