diff options
| author | Jouni Högander <jouni.hogander@intel.com> | 2024-06-18 08:30:26 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2024-06-19 07:42:12 +0300 |
| commit | dcaacff03a9fa2838f936e1009b4b7ad56807152 (patch) | |
| tree | 5af649494a101d8a492338881718f9b9f4dc50f4 /drivers | |
| parent | dc9cfe9f1d22b359d6f316005c887c1a6e31701d (diff) | |
intel_alpm: Fix wrong offset for PORT_ALPM_* registers
PORT_ALPM_* registers are using MMIO_TRANS2 macro. This is not correct as
they are port register. Use _PORT_MMIO instead.
Fixes: 4ee30a448255 ("drm/i915/alpm: Add ALPM register definitions")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-10-jouni.hogander@intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_alpm.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr_regs.h | 6 |
2 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 67848fc1e24d..c7092af7da33 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -310,6 +310,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + enum port port = dp_to_dig_port(intel_dp)->base.port; u32 alpm_ctl; if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && @@ -328,7 +329,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines); intel_de_write(dev_priv, - PORT_ALPM_CTL(dev_priv, cpu_transcoder), + PORT_ALPM_CTL(dev_priv, port), PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | @@ -336,7 +337,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, intel_dp->alpm_parameters.silence_period_sym_clocks)); intel_de_write(dev_priv, - PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder), + PORT_ALPM_LFPS_CTL(dev_priv, port), PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 1e503209da09..642bb15fb547 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -294,7 +294,8 @@ #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) #define _PORT_ALPM_CTL_A 0x16fa2c -#define PORT_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A) +#define _PORT_ALPM_CTL_B 0x16fc2c +#define PORT_ALPM_CTL(dev_priv, port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B) #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) @@ -304,7 +305,8 @@ #define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) #define _PORT_ALPM_LFPS_CTL_A 0x16fa30 -#define PORT_ALPM_LFPS_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A) +#define _PORT_ALPM_LFPS_CTL_B 0x16fc30 +#define PORT_ALPM_LFPS_CTL(dev_priv, port) _MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B) #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7 |