diff options
| author | Chris Zankel <chris@zankel.net> | 2007-08-22 10:14:51 -0700 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2007-08-27 13:54:16 -0700 |
| commit | 6656920b0b50beacb6cb64cf55273cbb686e436e (patch) | |
| tree | dab9fdb81821b455a29779de6ca3306dbdf05dbd /include/asm-xtensa/cache.h | |
| parent | ff6fd469885aafa5ec387babcb6537f3c00d6df0 (diff) | |
[XTENSA] Add support for cache-aliasing
Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'include/asm-xtensa/cache.h')
| -rw-r--r-- | include/asm-xtensa/cache.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h index 1c4a78f29ae2..3bba2a540cf0 100644 --- a/include/asm-xtensa/cache.h +++ b/include/asm-xtensa/cache.h @@ -19,6 +19,15 @@ #define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) +#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) +#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) + +/* Maximum cache size per way. */ +#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE +# define CACHE_WAY_SIZE DCACHE_WAY_SIZE +#else +# define CACHE_WAY_SIZE ICACHE_WAY_SIZE +#endif #endif /* _XTENSA_CACHE_H */ |