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authorHuacai Chen <chenhuacai@loongson.cn>2022-05-31 18:04:10 +0800
committerHuacai Chen <chenhuacai@loongson.cn>2022-06-03 20:09:27 +0800
commit439057ec3b748b1ff61855d09859f369493e22d8 (patch)
tree488f331128a8ba653855b4434dcf1825b12804bb /include/drm
parent08145b087e4481458f6075f3af58021a3cf8a940 (diff)
LoongArch: Add writecombine support for drm
LoongArch maintains cache coherency in hardware, but its WUC attribute (Weak-ordered UnCached, which is similar to WC) is out of the scope of cache coherency machanism. This means WUC can only used for write-only memory regions. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/drm_cache.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 22deb216b59c..08e0e3ffad13 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void)
* optimization entirely for ARM and arm64.
*/
return false;
+#elif defined(CONFIG_LOONGARCH)
+ /*
+ * LoongArch maintains cache coherency in hardware, but its WUC attribute
+ * (Weak-ordered UnCached, which is similar to WC) is out of the scope of
+ * cache coherency machanism. This means WUC can only used for write-only
+ * memory regions.
+ */
+ return false;
#else
return true;
#endif