diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2024-05-10 14:22:18 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2024-05-15 19:04:07 +0300 |
| commit | aa3d586e16242ada8e865f79249e4b6ac0c7704c (patch) | |
| tree | 987937d94d8e1086a524863ec9511fe0b366fa61 /include/drm | |
| parent | 5c8c22adc802b2abe6fc7933087d5a029545fdff (diff) | |
drm/i915/pciids: don't include WHL/CML PCI IDs in CFL
It's confusing for INTEL_CFL_IDS() to include all WHL and CML PCI
IDs. Even if we treat them the same in a lot of places, CML is a
platform of its own, and the lists of PCI IDs should not conflate them.
Largely go by the idea that if a platform has a name, group its PCI IDs
together.
That said, AML is special, having both KBL and CFL variants. Leave that
alone.
v2: Also split out WHL not just CML (Rodrigo)
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7cca91dc78ed2b5982f14e400f03a1704645e475.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'include/drm')
| -rw-r--r-- | include/drm/i915_pciids.h | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 16778d92346b..0c5a20d59801 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -488,6 +488,12 @@ INTEL_VGA_DEVICE(0x9BCA, info), \ INTEL_VGA_DEVICE(0x9BCC, info) +#define INTEL_CML_IDS(info) \ + INTEL_CML_GT1_IDS(info), \ + INTEL_CML_GT2_IDS(info), \ + INTEL_CML_U_GT1_IDS(info), \ + INTEL_CML_U_GT2_IDS(info) + #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ INTEL_KBL_GT2_IDS(info), \ @@ -527,6 +533,15 @@ INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ +#define INTEL_CFL_IDS(info) \ + INTEL_CFL_S_GT1_IDS(info), \ + INTEL_CFL_S_GT2_IDS(info), \ + INTEL_CFL_H_GT1_IDS(info), \ + INTEL_CFL_H_GT2_IDS(info), \ + INTEL_CFL_U_GT2_IDS(info), \ + INTEL_CFL_U_GT3_IDS(info), \ + INTEL_AML_CFL_GT2_IDS(info) + /* WHL/CFL U GT1 */ #define INTEL_WHL_U_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x3EA1, info), \ @@ -541,21 +556,10 @@ #define INTEL_WHL_U_GT3_IDS(info) \ INTEL_VGA_DEVICE(0x3EA2, info) -#define INTEL_CFL_IDS(info) \ - INTEL_CFL_S_GT1_IDS(info), \ - INTEL_CFL_S_GT2_IDS(info), \ - INTEL_CFL_H_GT1_IDS(info), \ - INTEL_CFL_H_GT2_IDS(info), \ - INTEL_CFL_U_GT2_IDS(info), \ - INTEL_CFL_U_GT3_IDS(info), \ +#define INTEL_WHL_IDS(info) \ INTEL_WHL_U_GT1_IDS(info), \ INTEL_WHL_U_GT2_IDS(info), \ - INTEL_WHL_U_GT3_IDS(info), \ - INTEL_AML_CFL_GT2_IDS(info), \ - INTEL_CML_GT1_IDS(info), \ - INTEL_CML_GT2_IDS(info), \ - INTEL_CML_U_GT1_IDS(info), \ - INTEL_CML_U_GT2_IDS(info) + INTEL_WHL_U_GT3_IDS(info) /* CNL */ #define INTEL_CNL_PORT_F_IDS(info) \ |