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authorChanwoo Choi <cw00.choi@samsung.com>2015-02-03 09:13:53 +0900
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-02-05 19:31:06 +0100
commit45e58aa5f751fd861d46f7b6d438c1be147458c6 (patch)
tree86a89c6836d581ddccb83ed8f52124cb5d3f6606 /include/dt-bindings/clock/exynos5433.h
parent9910b6bbaa7b16cd3a8a7d8be53980fa1b8183a6 (diff)
clk: samsung: exynos5433: Add clocks for CMU_HEVC domain
This patch adds the mux/divider/gate clocks for CMU_HEVC domain which generates the clocks for HEVC(High Efficiency Video Codec) decoder IP. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock/exynos5433.h')
-rw-r--r--include/dt-bindings/clock/exynos5433.h27
1 files changed, 26 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 3301ab72c80d..1b2d333c1786 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -154,8 +154,9 @@
#define CLK_SCLK_JPEG_MSCL 234
#define CLK_ACLK_MSCL_400 235
#define CLK_ACLK_MFC_400 236
+#define CLK_ACLK_HEVC_400 237
-#define TOP_NR_CLK 237
+#define TOP_NR_CLK 238
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -1001,4 +1002,28 @@
#define MFC_NR_CLK 19
+/* CMU_HEVC */
+#define CLK_MOUT_ACLK_HEVC_400_USER 1
+
+#define CLK_DIV_PCLK_HEVC 2
+
+#define CLK_ACLK_BTS_HEVC_1 3
+#define CLK_ACLK_BTS_HEVC_0 4
+#define CLK_ACLK_AHB2APB_HEVCP 5
+#define CLK_ACLK_XIU_HEVCX 6
+#define CLK_ACLK_HEVCNP_100 7
+#define CLK_ACLK_HEVCND_400 8
+#define CLK_ACLK_HEVC 9
+#define CLK_ACLK_SMMU_HEVC_1 10
+#define CLK_ACLK_SMMU_HEVC_0 11
+#define CLK_PCLK_BTS_HEVC_1 12
+#define CLK_PCLK_BTS_HEVC_0 13
+#define CLK_PCLK_PMU_HEVC 14
+#define CLK_PCLK_SYSREG_HEVC 15
+#define CLK_PCLK_HEVC 16
+#define CLK_PCLK_SMMU_HEVC_1 17
+#define CLK_PCLK_SMMU_HEVC_0 18
+
+#define HEVC_NR_CLK 19
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */