Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Not a ton of stuff happening in the clk framework. We got some more
  devm helpers and we seem to be going in the direction of "just turn
  this stuff on already and leave me alone!" with the addition of a
  devm_clk_bulk_get_all_enable() API. I'm hoping that we can make that
  into a pmdomain that drivers attach instead, but this API should help
  drivers simplify in the meantime.

  Outside of the devm wrappers, we've got the usual clk driver updates
  that are dominated by the major phone SoC vendors (Samsung and
  Qualcomm) and the non-critical driver fixes for things like incorrect
  topology descriptions and wrong registers or bit fields. More details
  are below, but I'd say that it looks pretty ordinary. The only thing
  that really jumps out at me is the Renesas clk driver that's ignoring
  clks that are assigned to remote processors in DeviceTree. That's a
  new feature that they're using to avoid marking clks as
  CLK_IGNORE_UNUSED based on the configuration of the system.

  Core:
   - Increase dev_id len for clkdev lookups
   - Add a devm_clk_bulk_get_all_enable() API to get and enable all clks
     for a device
   - Add a devm variant of clk_rate_exclusive_get()

  New Drivers:
   - Display, TCSR, GPU, and Camera clock controllers for Qualcomm's X1
     Elite SoC
   - Google GS101 PERIC0 and PERIC1 clock controllers
   - Exynos850 PDMA clocks
   - Exynos850 CPU cluster 0 and 1 (CMU_CPUCLK0/CMU_CPUCLK1) clock
     controllers

  Removed Drivers:
   - Remove the unused Qualcomm sc7180 modem clk driver

  Updates:
   - Fix some static checker errors in the Hisilicon clk driver
   - Polarfire MSSPLL hardware has 4 output clocks (the driver supported
     previously only one output); each of these 4 outputs feed dividers
     and the output of each divider feed individual hardware blocks
     (e.g. CAN, Crypto, eMMC); individual hardware block drivers need to
     control their clocks thus clock driver support was added for all
     MSSPLL output clocks
   - Typo fixes in the Qualcomm IPQ5018 GCC driver
   - Add "qdss_at" clk on Qualcomm IPQ6018, needed for WiFi
   - Properly terminate frequency tables in different Qualcomm clk
     drivers
   - Add MDSS, crypto, and SDCC resets on Qualcomm MSM8953
   - Add missing UFS CLKREF clks on Qualcomm SC8180X
   - Avoid significant delays during boot by adding a softdep on rpmhpd
     to Qualcomm SDM845 gcc driver
   - Add QUPv3 RCGS w/ DFS and video resets to Qualcomm SM8150 GCC
     driver
   - Fix the custom GPU GX "do-nothing" method in the Qualcomm GDSC
     driver
   - Add an external regulator to GX GDSC on Qualcomm SC8280XP GPU clk
     driver
   - Switch display, GPU, video, and camera Qualcomm clk drivers to
     module_platform_driver()
   - Set a longer delay for Venus resets on many Qualcomm SoCs
   - Correct the GDSC wait times in the Qualcomm SDM845 display clk
     driver
   - Fix clock listing Oops on Amlogic axg
   - New pll-rate for Rockchip rk3568
   - i2s rate improvements for Rockchip rk3399
   - Rockchip rk3588 syscon clock fixes and removal of overall
     clock-number from the rk3588 binding header
   - A prerequisite for later improvements to the Rockchip rk3588 linked
     clocks
   - Minor clean-ups and error handling improvements in both
     composite-8m and SCU i.MX clock drivers
   - Fix for SAI_MCLK_SEL definition for i.MX8MP
   - Register the Samsung CMU MISC clock controller earlier, so the
     Multi Core Timer clocksource can use it on Google GS101
   - Propagate Exynos850 SPI IPCLK rate change to parents, so the SPI
     will get proper clock rates
   - Refactor the generic Samsung CPU clock controllers code, preparing
     it for supporting Exynos850 CPU clocks
   - Fix some clk kerneldoc warnings
   - Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on
     Renesas R-Car V4M
   - Ignore all clocks which are assigned to a non-Linux system in the
     Renesas clk driver
   - Add watchdog clock on Renesas RZ/G3S
   - Add camera (CRU) clock and reset on Renesas RZ/G2UL
   - Add support for the Renesas R-Car V4M (R8A779H0) SoC
   - Convert some clk bindings to YAML so they can be validated"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits)
  clk: zynq: Prevent null pointer dereference caused by kmalloc failure
  clk: fractional-divider: Use bit operations consistently
  clk: fractional-divider: Move mask calculations out of lock
  clk: Fix clk_core_get NULL dereference
  clk: starfive: jh7110-vout: Convert to platform remove callback returning void
  clk: starfive: jh7110-isp: Convert to platform remove callback returning void
  clk: imx: imx8-acm: Convert to platform remove callback returning void
  clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset
  clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk'
  clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk'
  clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc
  clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays
  clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays
  clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays
  clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe()
  clk: Add a devm variant of clk_rate_exclusive_get()
  ...

1 files changed, 54 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index bc15108aa3c2..7666241520f8 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -88,6 +88,18 @@
 #define CLK_MOUT_G3D_SWITCH		76
 #define CLK_GOUT_G3D_SWITCH		77
 #define CLK_DOUT_G3D_SWITCH		78
+#define CLK_MOUT_CPUCL0_DBG		79
+#define CLK_MOUT_CPUCL0_SWITCH		80
+#define CLK_GOUT_CPUCL0_DBG		81
+#define CLK_GOUT_CPUCL0_SWITCH		82
+#define CLK_DOUT_CPUCL0_DBG		83
+#define CLK_DOUT_CPUCL0_SWITCH		84
+#define CLK_MOUT_CPUCL1_DBG		85
+#define CLK_MOUT_CPUCL1_SWITCH		86
+#define CLK_GOUT_CPUCL1_DBG		87
+#define CLK_GOUT_CPUCL1_SWITCH		88
+#define CLK_DOUT_CPUCL1_DBG		89
+#define CLK_DOUT_CPUCL1_SWITCH		90
 
 /* CMU_APM */
 #define CLK_RCO_I3C_PMIC		1
@@ -195,6 +207,48 @@
 #define CLK_GOUT_CMGP_USI1_PCLK		14
 #define CLK_GOUT_SYSREG_CMGP_PCLK	15
 
+/* CMU_CPUCL0 */
+#define CLK_FOUT_CPUCL0_PLL		1
+#define CLK_MOUT_PLL_CPUCL0		2
+#define CLK_MOUT_CPUCL0_SWITCH_USER	3
+#define CLK_MOUT_CPUCL0_DBG_USER	4
+#define CLK_MOUT_CPUCL0_PLL		5
+#define CLK_DOUT_CPUCL0_CPU		6
+#define CLK_DOUT_CPUCL0_CMUREF		7
+#define CLK_DOUT_CPUCL0_PCLK		8
+#define CLK_DOUT_CLUSTER0_ACLK		9
+#define CLK_DOUT_CLUSTER0_ATCLK		10
+#define CLK_DOUT_CLUSTER0_PCLKDBG	11
+#define CLK_DOUT_CLUSTER0_PERIPHCLK	12
+#define CLK_GOUT_CLUSTER0_ATCLK		13
+#define CLK_GOUT_CLUSTER0_PCLK		14
+#define CLK_GOUT_CLUSTER0_PERIPHCLK	15
+#define CLK_GOUT_CLUSTER0_SCLK		16
+#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK	17
+#define CLK_GOUT_CLUSTER0_CPU		18
+#define CLK_CLUSTER0_SCLK		19
+
+/* CMU_CPUCL1 */
+#define CLK_FOUT_CPUCL1_PLL		1
+#define CLK_MOUT_PLL_CPUCL1		2
+#define CLK_MOUT_CPUCL1_SWITCH_USER	3
+#define CLK_MOUT_CPUCL1_DBG_USER	4
+#define CLK_MOUT_CPUCL1_PLL		5
+#define CLK_DOUT_CPUCL1_CPU		6
+#define CLK_DOUT_CPUCL1_CMUREF		7
+#define CLK_DOUT_CPUCL1_PCLK		8
+#define CLK_DOUT_CLUSTER1_ACLK		9
+#define CLK_DOUT_CLUSTER1_ATCLK		10
+#define CLK_DOUT_CLUSTER1_PCLKDBG	11
+#define CLK_DOUT_CLUSTER1_PERIPHCLK	12
+#define CLK_GOUT_CLUSTER1_ATCLK		13
+#define CLK_GOUT_CLUSTER1_PCLK		14
+#define CLK_GOUT_CLUSTER1_PERIPHCLK	15
+#define CLK_GOUT_CLUSTER1_SCLK		16
+#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK	17
+#define CLK_GOUT_CLUSTER1_CPU		18
+#define CLK_CLUSTER1_SCLK		19
+
 /* CMU_G3D */
 #define CLK_FOUT_G3D_PLL		1
 #define CLK_MOUT_G3D_PLL		2