diff options
| author | Dmitry Rokosov <ddrokosov@salutedevices.com> | 2024-05-15 21:47:25 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2024-06-10 12:16:45 +0200 |
| commit | 96f3b978736356ba0e5a7d923681765c7ea9b12b (patch) | |
| tree | 64ddc01ff59601f3bd3329a97c4702db7cc609a3 /include/dt-bindings/clock | |
| parent | fc1c7f941c71460a730a449f76764d883e270cba (diff) | |
dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
The 'syspll' PLL is a general-purpose PLL designed specifically for the
CPU clock. It is capable of producing output frequencies within the
range of 768MHz to 1536MHz.
The 'syspll_in' source clock is an optional parent connection from the
peripherals clock controller.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h index 2b660c0f2c9f..0dfc5e78a2d5 100644 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h @@ -21,5 +21,6 @@ #define CLKID_FCLK_DIV5 8 #define CLKID_FCLK_DIV7 9 #define CLKID_HIFI_PLL 10 +#define CLKID_SYS_PLL 11 #endif /* __A1_PLL_CLKC_H */ |