diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-07-27 14:04:12 +0200 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2019-08-23 09:40:46 +0530 |
| commit | 088e88be5a380cc4e81963a9a02815da465d144f (patch) | |
| tree | ec242ae0abb9475407832087969bead2f0ef43bb /include/dt-bindings/phy | |
| parent | 609488bc979f99f805f34e9a32c1e3b71179d10b (diff) | |
dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs.
The IP block contains settings for the PHY and a PLL.
The PLL mode is configurable through a dedicated #phy-cell in .dts.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'include/dt-bindings/phy')
| -rw-r--r-- | include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h b/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h new file mode 100644 index 000000000000..95a7896356d6 --- /dev/null +++ b/include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com> + */ + +#define LANTIQ_PCIE_PHY_MODE_25MHZ 0 +#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1 +#define LANTIQ_PCIE_PHY_MODE_36MHZ 2 +#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3 +#define LANTIQ_PCIE_PHY_MODE_100MHZ 4 +#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5 |