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authorStephen Boyd <sboyd@kernel.org>2020-08-03 15:07:18 -0700
committerStephen Boyd <sboyd@kernel.org>2020-08-03 15:07:18 -0700
commitdd9c697a944a02066877404b01e9fb7dcb3a2218 (patch)
tree33bcf43bb3e1075f8af74ec361f5504cbc7a5152 /include/dt-bindings
parent1a91e318c09777f4708c38d6fb98f4da47d9e067 (diff)
parent53727eb6b3c210e826bb4c9d0aa89f65a5ae9342 (diff)
parent4aeccdf0671125adee903b651fb134a4759ce161 (diff)
parent6cfde88418fe95240e32d2955b51988360ee0942 (diff)
parentcb783bbbcf54c36256006895c215e86c5e7266d8 (diff)
Merge branches 'clk-microchip', 'clk-mmp', 'clk-unused' and 'clk-at91' into clk-next
- Add support for SAMA7G5 SoC clks - Microchip Sparx5 DPLL clk * clk-microchip: clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file * clk-mmp: clk: mmp: avoid missing prototype warning * clk-unused: clk: drop unused function __clk_get_flags * clk-at91: clk: at91: sama7g5: add clock support for sama7g5 clk: at91: clk-utmi: add utmi support for sama7g5 clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs clk: at91: add macro for pll ids mask clk: at91: clk-programmable: add mux_table option clk: at91: clk-peripheral: add support for changeable parent rate clk: at91: clk-master: add master clock support for SAMA7G5 clk: at91: clk-generated: add mux_table option clk: at91: clk-generated: pass the id of changeable parent at registration clk: at91: replace conditional operator with double logical not clk: at91: sckc: register slow_rc with accuracy option clk: at91: sam9x60: fix main rc oscillator frequency clk: at91: sam9x60-pll: use frac when setting frequency clk: at91: sam9x60-pll: check fcore against ranges clk: at91: sam9x60-pll: use logical or for range check clk: at91: clk-sam9x60-pll: fix mul mask clk: at91: clk-generated: check best_rate against ranges clk: at91: clk-generated: continue if __clk_determine_rate() returns error clk: at91: fix possible dead lock in new drivers