diff options
| author | Fugang Duan <b38611@freescale.com> | 2015-07-28 15:30:39 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2015-08-05 20:52:07 +0800 |
| commit | 9f55eb92441883a1afca48dc8d32bf62c4d8e833 (patch) | |
| tree | 6c774be9860055d0551dec98c8e75fb836666282 /include/linux/mfd/syscon | |
| parent | cec13c26e90e53015360c09574a7a2cde8d29495 (diff) | |
ARM: imx6ul: add fec bits to GPR syscon definition
FEC requires additional bits to select refrence clock.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'include/linux/mfd/syscon')
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d16f4c82c568..558a485d03ab 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -435,4 +435,12 @@ #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1) #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) +/* For imx6ul iomux gpr register field define */ +#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) +#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) +#define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) +#define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) +#define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) +#define IMX6UL_GPR1_ENET_CLK_OUTPUT (0x3 << 17) + #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ |