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authorFaiz Abbas <faiz_abbas@ti.com>2020-01-08 20:39:19 +0530
committerUlf Hansson <ulf.hansson@linaro.org>2020-03-24 14:35:41 +0100
commit8ee5fc0e0b3bed087b38f46f4c272b64c0b33d47 (patch)
treecc5d4f12693ea83d5eb387757493e2c76de32d81 /include/linux/mmc
parent70fd681e7ee1c27b02255010f201ac138862bb05 (diff)
mmc: sdhci_am654: Update OTAPDLY writes
According to the latest AM65x Data Manual[1], a different output tap delay value is optimum for a given speed mode. Therefore, deprecate the ti,otap-del-sel binding and introduce a new binding for each of the possible MMC/SD speed modes. If the legacy mode is not found, fall back to old binding to maintain dts compatibility. [1] http://www.ti.com/lit/gpn/am6526 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200108150920.14547-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'include/linux/mmc')
-rw-r--r--include/linux/mmc/host.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 94e3c87c1a58..f5db24a6a860 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -322,6 +322,8 @@ struct mmc_host {
#define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */
#define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */
#define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */
+#define MMC_CAP_DDR (MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | \
+ MMC_CAP_1_2V_DDR)
#define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */
#define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */
#define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */