diff options
| author | Balsam CHIHI <bchihi@baylibre.com> | 2022-10-21 10:47:07 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2022-11-07 15:42:53 +0100 |
| commit | d459a2352211bf01c532def4f85eb8c2545c610a (patch) | |
| tree | 11201d96257ab23211f0a5836c17885edcf6898b /init/do_mounts_initrd.c | |
| parent | 76f3768132eab2c26c9d67022b452358adc28b2c (diff) | |
pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken SET/CLR modes
On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly.
Add mt8365_set_clr_mode() callback for such SoCs, so that instead of
using the SET/CLR register, use the main R/W register to
read/update/write the modes.
Co-developed-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Link: https://lore.kernel.org/r/20221021084708.1109986-2-bchihi@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'init/do_mounts_initrd.c')
0 files changed, 0 insertions, 0 deletions