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| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2017-11-16 12:16:00 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-12-05 14:14:52 +0100 |
| commit | b16cd900de7911f96af17327a081a2141a0b763f (patch) | |
| tree | b743016a9153b41523fd1e0d6f2ab565dec8736a /net/rds | |
| parent | 82d2de5a4f646f7265ac5bc779f4a58164f2c0e9 (diff) | |
pinctrl: sh-pfc: r8a7795-es1: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24]
value when STP_ISEN_1_D pin function is selected for IPSR16 bit[27:24].
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E.
Fixes: 0b0ffc96dbe30fa9 ("pinctrl: sh-pfc: Initial R8A7795 PFC support)
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'net/rds')
0 files changed, 0 insertions, 0 deletions