diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2022-12-01 14:22:10 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-12-05 13:28:38 -0800 |
| commit | c46c5fb725bedd73cf33511b6a52d82b57eaba2a (patch) | |
| tree | b55d600e1e5e47f86b5c5518efc2fb61bf14c99e /rust/bindgen_parameters | |
| parent | c04712efb3755306ff3ab72a91df94108bff1f30 (diff) | |
drm/i915/gen12: Apply recommended L3 hashing mask
The TGL/RKL/DG1/ADL performance tuning guide suggests programming a
literal value of 0x2FC0100F for this register. The register's hardware
default value is 0x2FC0108F, so this translates to just clearing one
bit.
Take this opportunity to also clean up the register definition and
re-write its existing bits/fields in the preferred notation.
Bspec: 31870
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221201222210.344152-1-matthew.d.roper@intel.com
Diffstat (limited to 'rust/bindgen_parameters')
0 files changed, 0 insertions, 0 deletions