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authorRanjani Sridharan <ranjani.sridharan@linux.intel.com>2021-12-07 13:39:41 -0600
committerMark Brown <broonie@kernel.org>2021-12-13 19:32:44 +0000
commitc697ef868f596aba7a5e90be8eb10bf4d4a98990 (patch)
treea3f871dfddc0e27df677bc466dce2557162c1234 /sound/soc/sof/intel/hda-loader.c
parentbefe304536eeef71f8529ff877444ae2b72a37db (diff)
ASoC: SOF: Intel: ICL: move ICL-specific ops to icl.c
Move the ICL specific ops to icl.c. Also introduce a macro ICL_DSP_HPRO_CORE_ID to define the core that should be powered up when HPRO is enabled. Reviewed-by: Bard Liao <bard.liao@intel.com> Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20211207193947.71080-2-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/sof/intel/hda-loader.c')
-rw-r--r--sound/soc/sof/intel/hda-loader.c64
1 files changed, 0 insertions, 64 deletions
diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c
index 40201e5ac201..bfb0e374ebab 100644
--- a/sound/soc/sof/intel/hda-loader.c
+++ b/sound/soc/sof/intel/hda-loader.c
@@ -481,49 +481,6 @@ int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
return hda_dsp_ctrl_clock_power_gating(sdev, true);
}
-/*
- * post fw run operations for ICL,
- * Core 3 will be powered up and in stall when HPRO is enabled
- */
-int hda_dsp_post_fw_run_icl(struct snd_sof_dev *sdev)
-{
- struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
- int ret;
-
- if (sdev->first_boot) {
- ret = hda_sdw_startup(sdev);
- if (ret < 0) {
- dev_err(sdev->dev,
- "error: could not startup SoundWire links\n");
- return ret;
- }
- }
-
- hda_sdw_int_enable(sdev, true);
-
- /*
- * The recommended HW programming sequence for ICL is to
- * power up core 3 and keep it in stall if HPRO is enabled.
- * Major difference between ICL and TGL, on ICL core 3 is managed by
- * the host whereas on TGL it is handled by the firmware.
- */
- if (!hda->clk_config_lpro) {
- ret = hda_dsp_enable_core(sdev, BIT(3));
- if (ret < 0) {
- dev_err(sdev->dev, "error: dsp core power up failed on core 3\n");
- return ret;
- }
-
- sdev->enabled_cores_mask |= BIT(3);
- sdev->dsp_core_ref_count[3]++;
-
- snd_sof_dsp_stall(sdev, BIT(3));
- }
-
- /* re-enable clock gating and power gating */
- return hda_dsp_ctrl_clock_power_gating(sdev, true);
-}
-
int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
const struct sof_ext_man_elem_header *hdr)
{
@@ -561,24 +518,3 @@ int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
return 0;
}
-
-int hda_dsp_core_stall_icl(struct snd_sof_dev *sdev, unsigned int core_mask)
-{
- struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
- const struct sof_intel_dsp_desc *chip = hda->desc;
-
- /* make sure core_mask in host managed cores */
- core_mask &= chip->host_managed_cores_mask;
- if (!core_mask) {
- dev_err(sdev->dev, "error: core_mask is not in host managed cores\n");
- return -EINVAL;
- }
-
- /* stall core */
- snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
- HDA_DSP_REG_ADSPCS,
- HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
- HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
-
- return 0;
-}