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| author | Sean Christopherson <seanjc@google.com> | 2024-07-19 16:51:06 -0700 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com> | 2024-08-29 16:25:06 -0700 |
| commit | 0cb26ec320851f685280ff061f84855d0e97bf86 (patch) | |
| tree | 087a57b05ab0dc716024acbc5229c6294525b49a /tools/arch/microblaze/include/uapi | |
| parent | 3426cb48adb4dc00b75e89c95d257d699f4d75ce (diff) | |
KVM: selftests: Verify the guest can read back the x2APIC ICR it wrote
Now that the BUSY bit mess is gone (for x2APIC), verify that the *guest*
can read back the ICR value that it wrote. Due to the divergent
behavior between AMD and Intel with respect to the backing storage of the
ICR in the vAPIC page, emulating a seemingly simple MSR write is quite
complex.
Link: https://lore.kernel.org/r/20240719235107.3023592-10-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'tools/arch/microblaze/include/uapi')
0 files changed, 0 insertions, 0 deletions