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authorHarini Katakam <harini.katakam@xilinx.com>2022-07-22 16:33:30 +0530
committerDavid S. Miller <davem@davemloft.net>2022-07-25 12:29:54 +0100
commit8a1c9753f1653f30e508547a971f6a7ed365a4fb (patch)
tree42d7015fc7e9f3e7aec48f50ef3338c7bc02f9d1 /tools/pci
parent1d3ded642535cbb30b376dc3b321284762878e11 (diff)
net: macb: Update tsu clk usage in runtime suspend/resume for Versal
On Versal TSU clock cannot be disabled irrespective of whether PTP is used. Hence introduce a new Versal config structure with a "need tsu" caps flag and check the same in runtime_suspend/resume before cutting off clocks. More information on this for future reference: This is an IP limitation on versions 1p11 and 1p12 when Qbv is enabled (See designcfg1, bit 3). However it is better to rely on an SoC specific check rather than the IP version because tsu clk property itself may not represent actual HW tsu clock on some chip designs. Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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