diff options
| author | Ian Rogers <irogers@google.com> | 2022-12-14 22:54:57 -0800 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2022-12-21 14:52:41 -0300 |
| commit | 2c3fd22bb3ff166a072c083e6b7468259c37e46a (patch) | |
| tree | 0fe5cf65b2a210b4d7872afb9578cad80914b6ba /tools/perf/pmu-events/arch/x86/knightslanding/frontend.json | |
| parent | e85af8a641ba3e8e4dab3e82f4a17f06378d47ff (diff) | |
perf vendor events intel: Refresh knightslanding events
Update the knightslanding events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed. This
increases consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-11-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/knightslanding/frontend.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/knightslanding/frontend.json | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json index 63343a0d1e86..9001f5019848 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json @@ -1,7 +1,6 @@ [ { "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.", - "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.ALL", "SampleAfterValue": "200003", @@ -9,7 +8,6 @@ }, { "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.", - "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.COND", "SampleAfterValue": "200003", @@ -17,7 +15,6 @@ }, { "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.", - "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.RETURN", "SampleAfterValue": "200003", @@ -25,7 +22,6 @@ }, { "BriefDescription": "Counts all instruction fetches, including uncacheable fetches.", - "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200003", @@ -33,7 +29,6 @@ }, { "BriefDescription": "Counts all instruction fetches that hit the instruction cache.", - "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "200003", @@ -41,7 +36,6 @@ }, { "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", - "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", @@ -49,7 +43,6 @@ }, { "BriefDescription": "Counts the number of times the MSROM starts a flow of uops.", - "Counter": "0,1", "EventCode": "0xE7", "EventName": "MS_DECODED.MS_ENTRY", "SampleAfterValue": "200003", |