diff options
| author | Zhang Rui <rui.zhang@intel.com> | 2023-08-27 14:07:08 +0800 |
|---|---|---|
| committer | Zhang Rui <rui.zhang@intel.com> | 2023-09-27 22:14:19 +0800 |
| commit | ff206149551f09117f44883650a45ae692745703 (patch) | |
| tree | f28b7a720b0cc0c97f6e5b5fa03c7cb019e100c1 /tools/power/x86 | |
| parent | 192cbf0468ae31062526287e257f5b56214d2da5 (diff) | |
tools/power/turbostat: Adjust cstate for has_slv_msrs() models
Disable PC2/PC3/PC7 and enable PC6 for has_slv_msrs() models.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/power/x86')
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index f3d44e81d7d5..972f5a9b14e6 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -635,7 +635,7 @@ static const struct platform_features spr_features = { static const struct platform_features slv_features = { .has_nhm_msrs = 1, .bclk_freq = BCLK_SLV, - .supported_cstates = CC1 | CC3 | CC6 | PC3 | PC6, + .supported_cstates = CC1 | CC3 | CC6 | PC6, .cst_limit = CST_LIMIT_SLV, .trl_msrs = TRL_ATOM, .rapl_msrs = RAPL_PKG | RAPL_CORE, @@ -5829,10 +5829,6 @@ void process_cpuid() do_irtl_snb = has_snb_msrs(family, model); if (has_slv_msrs(family, model)) { - BIC_NOT_PRESENT(BIC_Pkgpc2); - BIC_NOT_PRESENT(BIC_Pkgpc3); - BIC_PRESENT(BIC_Pkgpc6); - BIC_NOT_PRESENT(BIC_Pkgpc7); BIC_PRESENT(BIC_Mod_c6); use_c1_residency_msr = 1; } |