diff options
| -rw-r--r-- | arch/sh/Kconfig | 1 | ||||
| -rw-r--r-- | arch/sh/Kconfig.cpu | 3 | ||||
| -rw-r--r-- | arch/sh/kernel/cpu/sh4/probe.c | 61 |
3 files changed, 15 insertions, 50 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index c815975b8d75..e9392aa8c561 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -174,7 +174,6 @@ config CPU_SH4 bool select CPU_HAS_INTEVT select CPU_HAS_SR_RB - select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2 select CPU_HAS_FPU if !CPU_SH4AL_DSP select SYS_SUPPORTS_TMU diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu index 9eb1712372d8..cd6e3ea598d5 100644 --- a/arch/sh/Kconfig.cpu +++ b/arch/sh/Kconfig.cpu @@ -96,9 +96,6 @@ config CPU_HAS_SR_RB See <file:Documentation/sh/register-banks.txt> for further information on SR.RB and register banking in the kernel in general. -config CPU_HAS_PTEA - bool - config CPU_HAS_PTEAEX bool diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index 28a2f0db01db..6c78d0a9c857 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -60,12 +60,18 @@ int __init detect_cpu_and_cache_system(void) if ((cvr & 0x10000000) == 0) boot_cpu_data.flags |= CPU_HAS_DSP; - boot_cpu_data.flags |= CPU_HAS_LLSC; + boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER; boot_cpu_data.cut_major = pvr & 0x7f; + + boot_cpu_data.icache.ways = 4; + boot_cpu_data.dcache.ways = 4; + } else { + /* And some SH-4 defaults.. */ + boot_cpu_data.flags |= CPU_HAS_PTEA; } /* FPU detection works for everyone */ - if ((cvr & 0x20000000) == 1) + if ((cvr & 0x20000000)) boot_cpu_data.flags |= CPU_HAS_FPU; /* Mask off the upper chip ID */ @@ -78,25 +84,20 @@ int __init detect_cpu_and_cache_system(void) switch (pvr) { case 0x205: boot_cpu_data.type = CPU_SH7750; - boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | - CPU_HAS_PERF_COUNTER; + boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | + CPU_HAS_PERF_COUNTER; break; case 0x206: boot_cpu_data.type = CPU_SH7750S; - boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | - CPU_HAS_PERF_COUNTER; + boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | + CPU_HAS_PERF_COUNTER; break; case 0x1100: boot_cpu_data.type = CPU_SH7751; - boot_cpu_data.flags |= CPU_HAS_FPU; break; case 0x2001: case 0x2004: boot_cpu_data.type = CPU_SH7770; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC; break; case 0x2006: case 0x200A: @@ -107,45 +108,26 @@ int __init detect_cpu_and_cache_system(void) else boot_cpu_data.type = CPU_SH7780; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | - CPU_HAS_LLSC; break; case 0x3000: case 0x3003: case 0x3009: boot_cpu_data.type = CPU_SH7343; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_LLSC; break; case 0x3004: case 0x3007: boot_cpu_data.type = CPU_SH7785; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | - CPU_HAS_LLSC; break; case 0x4004: boot_cpu_data.type = CPU_SH7786; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | - CPU_HAS_LLSC | CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE; + boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE; break; case 0x3008: - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_LLSC; - switch (prr) { case 0x50: case 0x51: boot_cpu_data.type = CPU_SH7723; - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE; + boot_cpu_data.flags |= CPU_HAS_L2_CACHE; break; case 0x70: boot_cpu_data.type = CPU_SH7366; @@ -158,17 +140,11 @@ int __init detect_cpu_and_cache_system(void) break; case 0x300b: boot_cpu_data.type = CPU_SH7724; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_FPU | CPU_HAS_L2_CACHE; + boot_cpu_data.flags |= CPU_HAS_L2_CACHE; break; case 0x4000: /* 1st cut */ case 0x4001: /* 2nd cut */ boot_cpu_data.type = CPU_SHX3; - boot_cpu_data.icache.ways = 4; - boot_cpu_data.dcache.ways = 4; - boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | - CPU_HAS_LLSC; break; case 0x700: boot_cpu_data.type = CPU_SH4_501; @@ -179,7 +155,6 @@ int __init detect_cpu_and_cache_system(void) boot_cpu_data.type = CPU_SH4_202; boot_cpu_data.icache.ways = 2; boot_cpu_data.dcache.ways = 2; - boot_cpu_data.flags |= CPU_HAS_FPU; break; case 0x500 ... 0x501: switch (prr) { @@ -197,18 +172,12 @@ int __init detect_cpu_and_cache_system(void) boot_cpu_data.icache.ways = 2; boot_cpu_data.dcache.ways = 2; - boot_cpu_data.flags |= CPU_HAS_FPU; - break; default: boot_cpu_data.type = CPU_SH_NONE; break; } -#ifdef CONFIG_CPU_HAS_PTEA - boot_cpu_data.flags |= CPU_HAS_PTEA; -#endif - /* * On anything that's not a direct-mapped cache, look to the CVR * for I/D-cache specifics. |