diff options
1027 files changed, 29728 insertions, 15394 deletions
diff --git a/Documentation/devicetree/bindings/arm/adapteva.txt b/Documentation/devicetree/bindings/arm/adapteva.txt deleted file mode 100644 index 1d8af9e36065..000000000000 --- a/Documentation/devicetree/bindings/arm/adapteva.txt +++ /dev/null @@ -1,7 +0,0 @@ -Adapteva Platforms Device Tree Bindings ---------------------------------------- - -Parallella board - -Required root node properties: - - compatible = "adapteva,parallella"; diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 69880560c0f0..b5c2b5c35766 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -41,6 +41,14 @@ Boards with the Amlogic Meson GXL S905D SoC shall have the following properties: Required root node property: compatible: "amlogic,s905d", "amlogic,meson-gxl"; +Boards with the Amlogic Meson GXL S805X SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s805x", "amlogic,meson-gxl"; + +Boards with the Amlogic Meson GXL S905W SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s905w", "amlogic,meson-gxl"; + Boards with the Amlogic Meson GXM S912 SoC shall have the following properties: Required root node property: compatible: "amlogic,s912", "amlogic,meson-gxm"; @@ -79,6 +87,11 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,p230" (Meson gxl s905d) - "amlogic,p231" (Meson gxl s905d) + - "amlogic,p241" (Meson gxl s805x) + + - "amlogic,p281" (Meson gxl s905w) + - "oranth,tx3-mini" (Meson gxl s905w) + - "amlogic,q200" (Meson gxm s912) - "amlogic,q201" (Meson gxm s912) - "khadas,vim2" (Meson gxm s912) diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt deleted file mode 100644 index 795cc78543fe..000000000000 --- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Power Management Controller (PMC) - -Required properties: -- compatible: Should be "atmel,<chip>-pmc". - <chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12, - at91sam9x5, sama5d3 - -- reg: Should contain PMC registers location and length - -Examples: - pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc"; - reg = <0xfffffc00 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index c052caad36e8..104cc9b41df4 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -189,7 +189,11 @@ Power-Down (SRPD), among other things. Required properties: - compatible : should contain one of these + "brcm,brcmstb-memc-ddr-rev-b.2.1" "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.2.3" + "brcm,brcmstb-memc-ddr-rev-b.3.0" + "brcm,brcmstb-memc-ddr-rev-b.3.1" "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 29e1dc5d506d..96dfccc0faa8 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -183,6 +183,7 @@ described below. "marvell,sheeva-v5" "nvidia,tegra132-denver" "nvidia,tegra186-denver" + "nvidia,tegra194-carmel" "qcom,krait" "qcom,kryo" "qcom,kryo385" @@ -219,6 +220,7 @@ described below. "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" "renesas,apmu" + "renesas,r9a06g032-smp" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" diff --git a/Documentation/devicetree/bindings/arm/freescale/m4if.txt b/Documentation/devicetree/bindings/arm/freescale/m4if.txt new file mode 100644 index 000000000000..93bd7b867a53 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/m4if.txt @@ -0,0 +1,12 @@ +* Freescale Multi Master Multi Memory Interface (M4IF) module + +Required properties: +- compatible : Should be "fsl,imx51-m4if" +- reg : Address and length of the register set for the device + +Example: + +m4if: m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; +}; diff --git a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt new file mode 100644 index 000000000000..19e2aad63d6e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt @@ -0,0 +1,12 @@ +* Freescale Tigerp platform module + +Required properties: +- compatible : Should be "fsl,imx51-tigerp" +- reg : Address and length of the register set for the device + +Example: + +tigerp: tigerp@83fa0000 { + compatible = "fsl,imx51-tigerp"; + reg = <0x83fa0000 0x28>; +}; diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index cdb9dd705754..8a1baa2b9723 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board Required root node properties: - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +i.MX6SLL EVK board +Required root node properties: + - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + Generic i.MX boards ------------------- diff --git a/Documentation/devicetree/bindings/arm/insignal-boards.txt b/Documentation/devicetree/bindings/arm/insignal-boards.txt deleted file mode 100644 index 524c3dc5d808..000000000000 --- a/Documentation/devicetree/bindings/arm/insignal-boards.txt +++ /dev/null @@ -1,8 +0,0 @@ -* Insignal's Exynos4210 based Origen evaluation board - -Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC. - -Required root node properties: - - compatible = should be one or more of the following. - (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. - (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC. diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index 48fac4ec91fc..8f260e5cfd16 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -51,6 +51,9 @@ Supported boards: - Evaluation board for MT6797(Helio X20): Required root node properties: - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; +- Mediatek X20 Development Board: + Required root node properties: + - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; - Reference board variant 1 for MT7622: Required root node properties: - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; @@ -63,9 +66,6 @@ Supported boards: - Reference board for MT7623n with eMMC: Required root node properties: - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; -- Reference board for MT7623n with NAND: - Required root node properties: - - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623"; - Bananapi BPI-R2 board: - compatible = "bananapi,bpi-r2", "mediatek,mt7623"; - MTK mt8127 tablet moose EVB: diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt index b4f8a16e7e3b..6816adcdc15f 100644 --- a/Documentation/devicetree/bindings/arm/omap/l4.txt +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -7,6 +7,7 @@ Required properties: Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus + Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus @@ -15,11 +16,21 @@ Required properties: Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus - ranges : contains the IO map range for the bus +- reg : registers link agent and interconnect agent and access protection +- reg-names : "la" for link agent, "ia0" to "ia3" for one to three + interconnect agent instances, "ap" for access if it exists Examples: -l4: l4@48000000 { - compatible "ti,omap2-l4", "simple-bus"; +l4: interconnect@48000000 { + compatible "ti,omap4-l4-per", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x48000000 0x100000>; diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 1c1d62d03c4f..acfd3c773dd0 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -1,5 +1,10 @@ Rockchip platforms device tree bindings --------------------------------------- + +- 96boards RK3399 Ficus (ROCK960 Enterprise Edition) + Required root node properties: + - compatible = "vamrs,ficus", "rockchip,rk3399"; + - Amarula Vyasa RK3288 board Required root node properties: - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; @@ -66,6 +71,15 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "geekbuying,geekbox", "rockchip,rk3368"; +- Google Bob (Asus Chromebook Flip C101PA): + Required root node properties: + compatible = "google,bob-rev13", "google,bob-rev12", + "google,bob-rev11", "google,bob-rev10", + "google,bob-rev9", "google,bob-rev8", + "google,bob-rev7", "google,bob-rev6", + "google,bob-rev5", "google,bob-rev4", + "google,bob", "google,gru", "rockchip,rk3399"; + - Google Brain (dev-board): Required root node properties: - compatible = "google,veyron-brain-rev0", "google,veyron-brain", diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 6970f30a3770..56021bf2a916 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -1,7 +1,10 @@ -* Samsung's Exynos SoC based boards +* Samsung's Exynos and S5P SoC based boards Required root node properties: - compatible = should be one or more of the following. + - "samsung,aries" - for S5PV210-based Samsung Aries board. + - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board. + - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board. - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module. - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board. - "samsung,monk" - for Exynos3250-based Samsung Simband board. diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index d8cf740132c6..89b4a389fbc7 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -51,7 +51,8 @@ SoCs: compatible = "renesas,r8a77990" - R-Car D3 (R8A77995) compatible = "renesas,r8a77995" - + - RZ/N1D (R9A06G032) + compatible = "renesas,r9a06g032" Boards: @@ -112,6 +113,8 @@ Boards: compatible = "renesas,porter", "renesas,r8a7791" - RSKRZA1 (YR0K77210C000BE) compatible = "renesas,rskrza1", "renesas,r7s72100" + - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) + compatible = "renesas,rzn1d400-db", "renesas,r9a06g032" - Salvator-X (RTP0RC7795SIPB0010S) compatible = "renesas,salvator-x", "renesas,r8a7795" - Salvator-X (RTP0RC7796SIPB0011S) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt new file mode 100644 index 000000000000..6a059cabb2da --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/k3.txt @@ -0,0 +1,23 @@ +Texas Instruments K3 Multicore SoC architecture device tree bindings +-------------------------------------------------------------------- + +Platforms based on Texas Instruments K3 Multicore SoC architecture +shall follow the following scheme: + +SoCs +---- + +Each device tree root node must specify which exact SoC in K3 Multicore SoC +architecture it uses, using one of the following compatible values: + +- AM654 + compatible = "ti,am654"; + +Boards +------ + +In addition, each device tree root node must specify which one or more +of the following board-specific compatible values: + +- AM654 EVM + compatible = "ti,am654-evm", "ti,am654"; diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index b9043bc35c14..26fe5ecc4332 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -8,18 +8,38 @@ Required root node properties: Additional compatible strings: -- Xilinx internal board cc108 +- Adapteva Parallella board + "adapteva,parallella" + +- Avnet MicroZed board + "avnet,zynq-microzed" + "xlnx,zynq-microzed" + +- Avnet ZedBoard board + "avnet,zynq-zed" + "xlnx,zynq-zed" + +- Digilent Zybo board + "digilent,zynq-zybo" + +- Digilent Zybo Z7 board + "digilent,zynq-zybo-z7" + +- Xilinx CC108 internal board "xlnx,zynq-cc108" -- Xilinx internal board zc770 with different FMC cards +- Xilinx ZC702 internal board + "xlnx,zynq-zc702" + +- Xilinx ZC706 internal board + "xlnx,zynq-zc706" + +- Xilinx ZC770 internal board, with different FMC cards "xlnx,zynq-zc770-xm010" "xlnx,zynq-zc770-xm011" "xlnx,zynq-zc770-xm012" "xlnx,zynq-zc770-xm013" -- Digilent Zybo Z7 board - "digilent,zynq-zybo-z7" - --------------------------------------------------------------- Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index c760ecb81381..663766685818 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -17,7 +17,6 @@ Required properties: - "marvell,armada-380-ahci" - "marvell,armada-3700-ahci" - "snps,dwc-ahci" - - "snps,exynos5440-ahci" - "snps,spear-ahci" - "generic-ahci" - interrupts : <interrupt mapping for SATA IRQ> diff --git a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt new file mode 100644 index 000000000000..87dfb33fb3be --- /dev/null +++ b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt @@ -0,0 +1,37 @@ +Device tree bindings for Allwinner A64 DE2 bus + +The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C) +to be claimed for enabling the access. + +Required properties: + + - compatible: Should contain "allwinner,sun50i-a64-de2" + - reg: A resource specifier for the register space + - #address-cells: Must be set to 1 + - #size-cells: Must be set to 1 + - ranges: Must be set up to map the address space inside the + DE2, for the sub-blocks of DE2. + - allwinner,sram: the SRAM that needs to be claimed + +Example: + + de2@1000000 { + compatible = "allwinner,sun50i-a64-de2"; + reg = <0x1000000 0x400000>; + allwinner,sram = <&de2_sram 1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000000 0x400000>; + + display_clocks: clock@0 { + compatible = "allwinner,sun50i-a64-de2-clk"; + reg = <0x0 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt index d8ed5b780ed9..91dc2333af01 100644 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt @@ -36,6 +36,7 @@ Required standard properties: "ti,sysc-omap-aes" "ti,sysc-mcasp" "ti,sysc-usb-host-fs" + "ti,sysc-dra7-mcan" - reg shall have register areas implemented for the interconnect target module in question such as revision, sysc and syss diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt index 09968ee224d8..8f8f95056f3d 100644 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt @@ -17,14 +17,13 @@ Required properties: "atmel,at91sam9x5-clk-slow-rc-osc": at91 internal slow RC oscillator - "atmel,at91rm9200-pmc" or - "atmel,at91sam9g45-pmc" or - "atmel,at91sam9n12-pmc" or - "atmel,at91sam9x5-pmc" or - "atmel,sama5d3-pmc": + "atmel,<chip>-pmc": at91 PMC (Power Management Controller) All at91 specific clocks (clocks defined below) must be child node of the PMC node. + <chip> can be: at91rm9200, at91sam9260, at91sam9261, + at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9x5, + sama5d2, sama5d3 or sama5d4. "atmel,at91sam9x5-clk-slow" (under sckc node) or diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt deleted file mode 100644 index c7d227c31e95..000000000000 --- a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Samsung Exynos5440 Clock Controller - -The Exynos5440 clock controller generates and supplies clock to various -controllers within the Exynos5440 SoC. - -Required Properties: - -- compatible: should be "samsung,exynos5440-clock". - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/exynos5440.h header and can be used in device -tree sources. - -Example: An example of a clock controller node is listed below. - - clock: clock-controller@10010000 { - compatible = "samsung,exynos5440-clock"; - reg = <0x160000 0x10000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt deleted file mode 100644 index caff1a57436f..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt +++ /dev/null @@ -1,28 +0,0 @@ - -Exynos5440 cpufreq driver -------------------- - -Exynos5440 SoC cpufreq driver for CPU frequency scaling. - -Required properties: -- interrupts: Interrupt to know the completion of cpu frequency change. -- operating-points: Table of frequencies and voltage CPU could be transitioned into, - in the decreasing order. Frequency should be in KHz units and voltage - should be in microvolts. - -Optional properties: -- clock-latency: Clock monitor latency in microsecond. - -All the required listed above must be defined under node cpufreq. - -Example: --------- - cpufreq@160000 { - compatible = "samsung,exynos5440-cpufreq"; - reg = <0x160000 0x1000>; - interrupts = <0 57 0>; - operating-points = < - 1000000 975000 - 800000 925000>; - clock-latency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/display/marvell,pxa2xx-lcdc.txt b/Documentation/devicetree/bindings/display/marvell,pxa2xx-lcdc.txt index f79641bd5f18..45ffd6c41748 100644 --- a/Documentation/devicetree/bindings/display/marvell,pxa2xx-lcdc.txt +++ b/Documentation/devicetree/bindings/display/marvell,pxa2xx-lcdc.txt @@ -10,6 +10,9 @@ Required properties: - interrupts : framebuffer controller interrupt. - clocks: phandle to input clocks +Optional properties: + - lcd-supply: A phandle to a power regulator that controls the LCD voltage. + Required nodes: - port: connection to the LCD panel (see video-interfaces.txt) This node must have its properties bus-width and remote-endpoint set. diff --git a/Documentation/devicetree/bindings/display/marvell,pxa300-gcu.txt b/Documentation/devicetree/bindings/display/marvell,pxa300-gcu.txt new file mode 100644 index 000000000000..9cfae5c4e8ec --- /dev/null +++ b/Documentation/devicetree/bindings/display/marvell,pxa300-gcu.txt @@ -0,0 +1,17 @@ +PXA3xx GCU Controller +--------------------- + +Required properties: + - compatible : "marvell,pxa300-gcu" + - reg : should contain the register range (address and length). + - interrupts : Controller interrupt. + - clocks: phandle to the PXA specific input clock. + +Example for PXA300: + + display-controller@54000000 { + compatible = "marvell,pxa300-gcu"; + reg = <0x54000000 0x1000>; + interrupts = <39>; + clocks = <&clks CLK_PXA300_GCU>; + }; diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt index 53c20cae309f..df5db732138d 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt @@ -40,6 +40,7 @@ video decode local arbiter, all these ports are according to the video HW. Required properties: - compatible : must be one of the following string: "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. + "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. - reg : m4u register base and size. - interrupts : the interrupt of m4u. @@ -50,8 +51,9 @@ Required properties: according to the local arbiter index, like larb0, larb1, larb2... - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as defined in - dt-binding/memory/mt2701-larb-port.h for mt2701 and - dt-binding/memory/mt8173-larb-port.h for mt8173 + dt-binding/memory/mt2701-larb-port.h for mt2701, + dt-binding/memory/mt2712-larb-port.h for mt2712, and + dt-binding/memory/mt8173-larb-port.h for mt8173. Example: iommu: iommu@10205000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt index aa614b2d7cab..615abdd0eb0d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt @@ -2,8 +2,9 @@ SMI (Smart Multimedia Interface) Common The hardware block diagram please check bindings/iommu/mediatek,iommu.txt -Mediatek SMI have two generations of HW architecture, mt8173 uses the second -generation of SMI HW while mt2701 uses the first generation HW of SMI. +Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use +the second generation of SMI HW while mt2701 uses the first generation HW of +SMI. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -15,6 +16,7 @@ not needed for SMI generation 2. Required properties: - compatible : must be one of : "mediatek,mt2701-smi-common" + "mediatek,mt2712-smi-common" "mediatek,mt8173-smi-common" - reg : the register and size of the SMI block. - power-domains : a phandle to the power domain of this local arbiter. diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt index ddf46b8856a5..083155cdc2a0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt @@ -4,8 +4,9 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt Required properties: - compatible : must be one of : - "mediatek,mt8173-smi-larb" "mediatek,mt2701-smi-larb" + "mediatek,mt2712-smi-larb" + "mediatek,mt8173-smi-larb" - reg : the register and size of this local arbiter. - mediatek,smi : a phandle to the smi_common node. - power-domains : a phandle to the power domain of this local arbiter. @@ -15,7 +16,7 @@ Required properties: the register. - "smi" : It's the clock for transfer data and command. -Required property for mt2701: +Required property for mt2701 and mt2712: - mediatek,larb-id :the hardware id of this larb. Example: diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt index 132e0007d7d6..e9cb3ec5e502 100644 --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt @@ -16,6 +16,8 @@ Required properties: * "allwinner,sun9i-a80-mmc" * "allwinner,sun50i-a64-emmc" * "allwinner,sun50i-a64-mmc" + * "allwinner,sun50i-h6-emmc", "allwinner.sun50i-a64-emmc" + * "allwinner,sun50i-h6-mmc", "allwinner.sun50i-a64-mmc" - reg : mmc controller base registers - clocks : a list with 4 phandle + clock specifier pairs - clock-names : must contain "ahb", "mmc", "output" and "sample" diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index cfe724398a12..5bb3a18cc38d 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -19,8 +19,6 @@ Required properties: - reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt -- #address-cells: shall be 1 -- #size-cells: shall be 0 - syscon: A phandle to the device containing the EMAC or GMAC clock register Optional properties: @@ -86,8 +84,6 @@ emac: ethernet@1c0b000 { reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; phy-handle = <&int_mii_phy>; phy-mode = "mii"; @@ -137,8 +133,6 @@ emac: ethernet@1c0b000 { reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; phy-handle = <&ext_rgmii_phy>; phy-mode = "rgmii"; @@ -191,8 +185,6 @@ emac: ethernet@1c0b000 { reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; phy-handle = <&ext_rgmii_phy>; phy-mode = "rgmii"; diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt index 3899d6a557c1..576ad002bc83 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt @@ -16,7 +16,10 @@ modes in device tree. Required properties: -- compatible: Should be "fsl,vf610-ftm-pwm". +- compatible : should be "fsl,<soc>-ftm-pwm" and one of the following + compatible strings: + - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610 + - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM - reg: Physical base address and length of the controller's registers - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format. diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index ef8bd3cb67ab..991728cb46cb 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -5,11 +5,13 @@ Required properties: - "mediatek,mt2712-pwm": found on mt2712 SoC. - "mediatek,mt7622-pwm": found on mt7622 SoC. - "mediatek,mt7623-pwm": found on mt7623 SoC. + - "mediatek,mt7628-pwm": found on mt7628 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of the cell format. - clocks: phandle and clock specifier of the PWM reference clock. - - clock-names: must contain the following: + - clock-names: must contain the following, except for MT7628 which + has no clocks - "top": the top clock generator - "main": clock used by the PWM core - "pwm1-8": the eight per PWM clocks for mt2712 diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt index 35a3b9761ee5..e1ef6afbe3a7 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -12,6 +12,7 @@ Required Properties: - "renesas,pwm-r8a7795": for R-Car H3 - "renesas,pwm-r8a7796": for R-Car M3-W - "renesas,pwm-r8a77965": for R-Car M3-N + - "renesas,pwm-r8a77990": for R-Car E3 - "renesas,pwm-r8a77995": for R-Car D3 - reg: base address and length of the registers block for the PWM. - #pwm-cells: should be 2. See pwm.txt in this directory for a description of diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt new file mode 100644 index 000000000000..510c748656ec --- /dev/null +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt @@ -0,0 +1,52 @@ +Qualcomm AOSS Reset Controller +====================================== + +This binding describes a reset-controller found on AOSS-CC (always on subsystem) +for Qualcomm SDM845 SoCs. + +Required properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be: + "qcom,sdm845-aoss-cc" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: must specify the base address and size of the register + space. + +- #reset-cells: + Usage: required + Value type: <uint> + Definition: must be 1; cell entry represents the reset index. + +Example: + +aoss_reset: reset-controller@c2a0000 { + compatible = "qcom,sdm845-aoss-cc"; + reg = <0xc2a0000 0x31000>; + #reset-cells = <1>; +}; + +Specifying reset lines connected to IP modules +============================================== + +Device nodes that need access to reset lines should +specify them as a reset phandle in their corresponding node as +specified in reset.txt. + +For list of all valid reset indicies see +<dt-bindings/reset/qcom,sdm845-aoss.h> + +Example: + +modem-pil@4080000 { + ... + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; + reset-names = "mss_restart"; + + ... +}; diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt index 93efed629900..101743dda223 100644 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt @@ -118,3 +118,59 @@ Example: other nodes ... }; + + +USB3 core reset +--------------- + +USB3 core reset belongs to USB3 glue layer. Before using the core reset, +it is necessary to control the clocks and resets to enable this layer. +These clocks and resets should be described in each property. + +Required properties: +- compatible: Should be + "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC + "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC + "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC + "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC +- #reset-cells: Should be 1. +- reg: Specifies offset and length of the register set for the device. +- clocks: A list of phandles to the clock gate for USB3 glue layer. + According to the clock-names, appropriate clocks are required. +- clock-names: Should contain + "gio", "link" - for Pro4 SoC + "link" - for others +- resets: A list of phandles to the reset control for USB3 glue layer. + According to the reset-names, appropriate resets are required. +- reset-names: Should contain + "gio", "link" - for Pro4 SoC + "link" - for others + +Example: + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_rst: reset@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + regulator { + ... + }; + + phy { + ... + }; + ... + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index bf80e3f96f8c..f9987c30f0d5 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -19,6 +19,7 @@ IP Pairing Required properties in pwrap device node. - compatible: "mediatek,mt2701-pwrap" for MT2701/7623 SoCs + "mediatek,mt6797-pwrap" for MT6797 SoCs "mediatek,mt7622-pwrap" for MT7622 SoCs "mediatek,mt8135-pwrap" for MT8135 SoCs "mediatek,mt8173-pwrap" for MT8173 SoCs diff --git a/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt b/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt index 93b982e9419f..feef39b4a4fd 100644 --- a/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt +++ b/Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt @@ -17,20 +17,18 @@ Example: /* upstream device */ - ssp0: ssp@41000000 { + ssp1: ssp@41000000 { compatible = "mrvl,pxa3xx-ssp"; reg = <0x41000000 0x40>; interrupts = <24>; clock-names = "pxa27x-ssp.0"; - dmas = <&dma 13 - &dma 14>; - dma-names = "rx", "tx"; }; /* DAI as user */ ssp_dai0: ssp_dai@0 { compatible = "mrvl,pxa-ssp-dai"; - port = <&ssp0>; + port = <&ssp1>; + #sound-dai-cells = <0>; }; diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt index d087f04a4d7f..c51ade86578c 100644 --- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt +++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt @@ -10,8 +10,14 @@ Controller Node Required properties: - compatible : should be: - - "allwinner,sun4i-a10-sram-controller" - - "allwinner,sun50i-a64-sram-controller" + - "allwinner,sun4i-a10-sram-controller" (deprecated) + - "allwinner,sun4i-a10-system-control" + - "allwinner,sun5i-a13-system-control" + - "allwinner,sun7i-a20-system-control", "allwinner,sun4i-a10-system-control" + - "allwinner,sun8i-a23-system-control" + - "allwinner,sun8i-h3-system-control" + - "allwinner,sun50i-a64-sram-controller" (deprecated) + - "allwinner,sun50i-a64-system-control" - reg : sram controller register offset + length SRAM nodes @@ -26,8 +32,25 @@ once again the representation described in the mmio-sram binding. The valid sections compatible for A10 are: - allwinner,sun4i-a10-sram-a3-a4 + - allwinner,sun4i-a10-sram-c1 - allwinner,sun4i-a10-sram-d +The valid sections compatible for A13 are: + - allwinner,sun5i-a13-sram-a3-a4, allwinner,sun4i-a10-sram-a3-a4 + - allwinner,sun5i-a13-sram-c1, allwinner,sun4i-a10-sram-c1 + - allwinner,sun5i-a13-sram-d, allwinner,sun4i-a10-sram-d + +The valid sections compatible for A20 are: + - allwinner,sun7i-a20-sram-a3-a4, allwinner,sun4i-a10-sram-a3-a4 + - allwinner,sun7i-a20-sram-c1, allwinner,sun4i-a10-sram-c1 + - allwinner,sun7i-a20-sram-d, allwinner,sun4i-a10-sram-d + +The valid sections compatible for A23/A33 are: + - allwinner,sun8i-a23-sram-c1, allwinner,sun4i-a10-sram-c1 + +The valid sections compatible for H3 are: + - allwinner,sun8i-h3-sram-c1, allwinner,sun4i-a10-sram-c1 + The valid sections compatible for A64 are: - allwinner,sun50i-a64-sram-c @@ -47,8 +70,8 @@ This valid values for this argument are: Example ------- -sram-controller@1c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; +system-control@1c00000 { + compatible = "allwinner,sun4i-a10-system-control"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt b/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt new file mode 100644 index 000000000000..29bf91ccf5b7 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt @@ -0,0 +1,37 @@ +* Device tree bindings for Texas Instruments DaVinci timer + +This document provides bindings for the 64-bit timer in the DaVinci +architecture devices. The timer can be configured as a general-purpose 64-bit +timer, dual general-purpose 32-bit timers. When configured as dual 32-bit +timers, each half can operate in conjunction (chain mode) or independently +(unchained mode) of each other. + +The timer is a free running up-counter and can generate interrupts when the +counter reaches preset counter values. + +Also see ../watchdog/davinci-wdt.txt for timers that are configurable as +watchdog timers. + +Required properties: + +- compatible : should be "ti,da830-timer". +- reg : specifies base physical address and count of the registers. +- interrupts : interrupts generated by the timer. +- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1", + "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6", + "cmpint7" ("cmpintX" may be omitted if not present in the + hardware). +- clocks : the clock feeding the timer clock. + +Example: + + clocksource: timer@20000 { + compatible = "ti,da830-timer"; + reg = <0x20000 0x1000>; + interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>, + <80>, <81>; + interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1", + "cmpint2", "cmpint3", "cmpint4", "cmpint5", + "cmpint6", "cmpint7"; + clocks = <&pll0_auxclk>; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 2f3620547249..2c3fc512e746 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -142,6 +142,7 @@ geekbuying GeekBuying gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. geniatech Geniatech, Inc. +giantec Giantec Semiconductor, Inc. giantplus Giantplus Technology Co., Ltd. globalscale Globalscale Technologies, Inc. gmt Global Mixed-mode Technology, Inc. @@ -200,6 +201,7 @@ koe Kaohsiung Opto-Electronics Inc. kosagi Sutajio Ko-Usagi PTE Ltd. kyo Kyocera Corporation lacie LaCie +laird Laird PLC lantiq Lantiq Semiconductor lattice Lattice Semiconductor lego LEGO Systems A/S @@ -279,6 +281,7 @@ opalkelly Opal Kelly Incorporated opencores OpenCores.org openrisc OpenRISC.io option Option NV +oranth Shenzhen Oranth Technology Co., Ltd. ORCL Oracle Corporation orisetech Orise Technology ortustech Ortus Technology Co., Ltd. @@ -322,6 +325,7 @@ rohm ROHM Semiconductor Co., Ltd roofull Shenzhen Roofull Technology Co, Ltd samsung Samsung Semiconductor samtec Samtec/Softing company +sancloud Sancloud Ltd sandisk Sandisk Corporation sbs Smart Battery System schindler Schindler @@ -401,6 +405,7 @@ upisemi uPI Semiconductor Corp. urt United Radiant Technology Corporation usi Universal Scientific Industrial Co., Ltd. v3 V3 Semiconductor +vamrs Vamrs Ltd. variscite Variscite Ltd. via VIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium diff --git a/Documentation/fb/fbcon.txt b/Documentation/fb/fbcon.txt index d4d642e1ce9c..62af30511a95 100644 --- a/Documentation/fb/fbcon.txt +++ b/Documentation/fb/fbcon.txt @@ -18,9 +18,10 @@ made available by the underlying graphics card are also possible. A. Configuration The framebuffer console can be enabled by using your favorite kernel -configuration tool. It is under Device Drivers->Graphics Support->Support for -framebuffer devices->Framebuffer Console Support. Select 'y' to compile -support statically, or 'm' for module support. The module will be fbcon. +configuration tool. It is under Device Drivers->Graphics Support->Frame +buffer Devices->Console display driver support->Framebuffer Console Support. +Select 'y' to compile support statically or 'm' for module support. The +module will be fbcon. In order for fbcon to activate, at least one framebuffer driver is required, so choose from any of the numerous drivers available. For x86 @@ -29,10 +30,10 @@ always be available. However, using a chipset-specific driver will give you more speed and features, such as the ability to change the video mode dynamically. - To display the penguin logo, choose any logo available in Logo -Configuration->Boot up logo. + To display the penguin logo, choose any logo available in Graphics +support->Bootup logo. - Also, you will need to select at least one compiled-in fonts, but if + Also, you will need to select at least one compiled-in font, but if you don't do anything, the kernel configuration tool will select one for you, usually an 8x16 font. @@ -135,16 +136,16 @@ C. Boot options The angle can be changed anytime afterwards by 'echoing' the same numbers to any one of the 2 attributes found in - /sys/class/graphics/fbcon + /sys/class/graphics/fbcon: rotate - rotate the display of the active console rotate_all - rotate the display of all consoles - Console rotation will only become available if Console Rotation - Support is compiled in your kernel. + Console rotation will only become available if Framebuffer Console + Rotation support is compiled in your kernel. NOTE: This is purely console rotation. Any other applications that - use the framebuffer will remain at their 'normal'orientation. + use the framebuffer will remain at their 'normal' orientation. Actually, the underlying fb driver is totally ignorant of console rotation. @@ -164,7 +165,7 @@ C. Boot options C. Attaching, Detaching and Unloading -Before going on how to attach, detach and unload the framebuffer console, an +Before going on to how to attach, detach and unload the framebuffer console, an illustration of the dependencies may help. The console layer, as with most subsystems, needs a driver that interfaces with @@ -182,7 +183,7 @@ because fbcon is an intermediate layer between the console and the drivers: console ---> fbcon ---> fbdev drivers ---> hardware -The fbdev drivers cannot be unloaded if it's bound to fbcon, and fbcon cannot +The fbdev drivers cannot be unloaded if bound to fbcon, and fbcon cannot be unloaded if it's bound to the console layer. So to unload the fbdev drivers, one must first unbind fbcon from the console, @@ -232,7 +233,7 @@ restored properly. The following is one of the several methods that you can do: echo 0 > /sys/class/vtconsole/vtcon1/bind 6. That's it, you're back to VGA mode. And if you compiled fbcon as a module, - you can unload it by 'rmmod fbcon' + you can unload it by 'rmmod fbcon'. 7. To reattach fbcon: @@ -290,7 +291,7 @@ Samples: ======== Here are 2 sample bash scripts that you can use to bind or unbind the -framebuffer console driver if you are in an X86 box: +framebuffer console driver if you are on an X86 box: --------------------------------------------------------------------------- #!/bin/bash diff --git a/Documentation/hwmon/raspberrypi-hwmon b/Documentation/hwmon/raspberrypi-hwmon new file mode 100644 index 000000000000..3c92e2cb52d6 --- /dev/null +++ b/Documentation/hwmon/raspberrypi-hwmon @@ -0,0 +1,22 @@ +Kernel driver raspberrypi-hwmon +=============================== + +Supported boards: + * Raspberry Pi A+ (via GPIO on SoC) + * Raspberry Pi B+ (via GPIO on SoC) + * Raspberry Pi 2 B (via GPIO on SoC) + * Raspberry Pi 3 B (via GPIO on port expander) + * Raspberry Pi 3 B+ (via PMIC) + +Author: Stefan Wahren <stefan.wahren@i2se.com> + +Description +----------- + +This driver periodically polls a mailbox property of the VC4 firmware to detect +undervoltage conditions. + +Sysfs entries +------------- + +in0_lcrit_alarm Undervoltage alarm diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt b/Documentation/networking/dpaa2/dpio-driver.rst index 72ba9da3d179..13588104161b 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt +++ b/Documentation/networking/dpaa2/dpio-driver.rst @@ -1,7 +1,15 @@ -Copyright 2016 NXP +.. include:: <isonum.txt> + +DPAA2 DPIO (Data Path I/O) Overview +=================================== + +:Copyright: |copy| 2016-2018 NXP + +This document provides an overview of the Freescale DPAA2 DPIO +drivers Introduction ------------- +============ A DPAA2 DPIO (Data Path I/O) is a hardware object that provides interfaces to enqueue and dequeue frames to/from network interfaces @@ -27,8 +35,11 @@ provides services that: The Linux DPIO driver consists of 3 primary components-- DPIO object driver-- fsl-mc driver that manages the DPIO object + DPIO service-- provides APIs to other Linux drivers for services + QBman portal interface-- sends portal commands, gets responses +:: fsl-mc other bus drivers @@ -45,8 +56,9 @@ The Linux DPIO driver consists of 3 primary components-- | hardware + The diagram below shows how the DPIO driver components fit with the other -DPAA2 Linux driver components: +DPAA2 Linux driver components:: +------------+ | OS Network | | Stack | @@ -98,20 +110,29 @@ DPIO service (dpio-service.c, dpaa2-io.h) Notification handling dpaa2_io_service_register() + dpaa2_io_service_deregister() + dpaa2_io_service_rearm() Queuing dpaa2_io_service_pull_fq() + dpaa2_io_service_pull_channel() + dpaa2_io_service_enqueue_fq() + dpaa2_io_service_enqueue_qd() + dpaa2_io_store_create() + dpaa2_io_store_destroy() + dpaa2_io_store_next() Buffer pool management dpaa2_io_service_release() + dpaa2_io_service_acquire() QBman portal interface (qbman-portal.c) @@ -120,7 +141,9 @@ QBman portal interface (qbman-portal.c) The qbman-portal component provides APIs to do the low level hardware bit twiddling for operations such as: -initializing Qman software portals + -building and sending portal commands + -portal interrupt configuration and processing The qbman-portal APIs are not public to other drivers, and are diff --git a/Documentation/networking/dpaa2/index.rst b/Documentation/networking/dpaa2/index.rst index 4c6586c87969..10bea113a7bc 100644 --- a/Documentation/networking/dpaa2/index.rst +++ b/Documentation/networking/dpaa2/index.rst @@ -6,3 +6,4 @@ DPAA2 Documentation :maxdepth: 1 overview + dpio-driver diff --git a/MAINTAINERS b/MAINTAINERS index efb08d70cc28..8cd5c1bd6441 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1295,11 +1295,6 @@ F: arch/arm/mach-aspeed/ F: arch/arm/boot/dts/aspeed-* N: aspeed -ARM/ATMEL AT91 Clock Support -M: Boris Brezillon <boris.brezillon@bootlin.com> -S: Maintained -F: drivers/clk/at91 - ARM/CALXEDA HIGHBANK ARCHITECTURE M: Rob Herring <robh@kernel.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -1481,6 +1476,16 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git F: arch/arm/mach-imx/*vf610* F: arch/arm/boot/dts/vf* +ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE +M: Shawn Guo <shawnguo@kernel.org> +M: Li Yang <leoyang.li@nxp.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git +F: arch/arm/boot/dts/ls1021a* +F: arch/arm64/boot/dts/freescale/fsl-* +F: arch/arm64/boot/dts/freescale/qoriq-* + ARM/GLOMATION GESBC9312SX MACHINE SUPPORT M: Lennert Buytenhek <kernel@wantstofly.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2009,6 +2014,7 @@ S: Supported F: arch/arm/boot/dts/emev2* F: arch/arm/boot/dts/r7s* F: arch/arm/boot/dts/r8a* +F: arch/arm/boot/dts/r9a* F: arch/arm/boot/dts/sh* F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S @@ -2127,6 +2133,15 @@ L: linux-kernel@vger.kernel.org S: Maintained F: drivers/memory/*emif* +ARM/TEXAS INSTRUMENTS K3 ARCHITECTURE +M: Tero Kristo <t-kristo@ti.com> +M: Nishanth Menon <nm@ti.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/arm/ti/k3.txt +F: arch/arm64/boot/dts/ti/Makefile +F: arch/arm64/boot/dts/ti/k3-* + ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE M: Santosh Shilimkar <ssantosh@kernel.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -4507,7 +4522,7 @@ DPAA2 DATAPATH I/O (DPIO) DRIVER M: Roy Pledge <Roy.Pledge@nxp.com> L: linux-kernel@vger.kernel.org S: Maintained -F: drivers/staging/fsl-mc/bus/dpio +F: drivers/soc/fsl/dpio DPAA2 ETHERNET DRIVER M: Ioana Radulescu <ruxandra.radulescu@nxp.com> @@ -10571,6 +10586,7 @@ F: arch/arm/plat-omap/ F: arch/arm/configs/omap1_defconfig F: drivers/i2c/busses/i2c-omap.c F: include/linux/platform_data/i2c-omap.h +F: include/linux/platform_data/ams-delta-fiq.h OMAP2+ SUPPORT M: Tony Lindgren <tony@atomide.com> diff --git a/arch/Kconfig b/arch/Kconfig index 4426e9687d89..6801123932a5 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -362,6 +362,9 @@ config HAVE_ARCH_JUMP_LABEL config HAVE_RCU_TABLE_FREE bool +config HAVE_RCU_TABLE_INVALIDATE + bool + config ARCH_HAVE_NMI_SAFE_CMPXCHG bool @@ -841,6 +844,14 @@ config REFCOUNT_FULL against various use-after-free conditions that can be used in security flaw exploits. +config HAVE_ARCH_COMPILER_H + bool + help + An architecture can select this if it provides an + asm/compiler.h header that should be included after + linux/compiler-*.h in order to override macro definitions that those + headers generally provide. + config HAVE_ARCH_PREL32_RELOCATIONS bool help diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f69613fd4e68..e8cd55a5b04c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -603,13 +603,16 @@ config ARCH_S3C24XX config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL - select CLKDEV_LOOKUP + select COMMON_CLK select CPU_ARM926T select GENERIC_ALLOCATOR select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select GPIOLIB select HAVE_IDE + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select RESET_CONTROLLER select USE_OF select ZONE_DMA help diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index b48dc083d1b1..f6fcb8a79889 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -204,6 +204,14 @@ choice depends on ARCH_BCM_HR2 select DEBUG_UART_8250 + config DEBUG_BCM_IPROC_UART3 + bool "Kernel low-level debugging on BCM IPROC UART3" + depends on ARCH_BCM_CYGNUS + select DEBUG_UART_8250 + help + Say Y here if you want the debug print routines to direct + their output to the third serial port on these devices. + config DEBUG_BCM_KONA_UART bool "Kernel low-level debugging messages via BCM KONA UART" depends on ARCH_BCM_MOBILE @@ -1562,14 +1570,15 @@ config DEBUG_UART_PHYS default 0x18000400 if DEBUG_BCM_HR2 default 0x18010000 if DEBUG_SIRFATLAS7_UART0 default 0x18020000 if DEBUG_SIRFATLAS7_UART1 + default 0x18023000 if DEBUG_BCM_IPROC_UART3 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 default 0x20001000 if DEBUG_HIP01_UART default 0x20060000 if DEBUG_RK29_UART0 default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 default 0x20201000 if DEBUG_BCM2835 - default 0x3f201000 if DEBUG_BCM2836 default 0x3e000000 if DEBUG_BCM_KONA_UART + default 0x3f201000 if DEBUG_BCM2836 default 0x4000e400 if DEBUG_LL_UART_EFM32 default 0x40028000 if DEBUG_AT91_SAMV7_USART1 default 0x40081000 if DEBUG_LPC18XX_UART0 @@ -1682,6 +1691,7 @@ config DEBUG_UART_VIRT default 0xf1002000 if DEBUG_MT8127_UART0 default 0xf1006000 if DEBUG_MT6589_UART0 default 0xf1009000 if DEBUG_MT8135_UART3 + default 0xf1023000 if DEBUG_BCM_IPROC_UART3 default 0xf11f1000 if DEBUG_VERSATILE default 0xf1600000 if DEBUG_INTEGRATOR default 0xf1c28000 if DEBUG_SUNXI_UART0 @@ -1797,7 +1807,7 @@ config DEBUG_UART_8250_WORD DEBUG_KEYSTONE_UART0 || DEBUG_KEYSTONE_UART1 || \ DEBUG_ALPINE_UART0 || \ DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ - DEBUG_DAVINCI_DA8XX_UART2 || \ + DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \ DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 config DEBUG_UART_8250_PALMCHIP diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e7d703d8fac3..ed94cf7e3157 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -219,7 +219,6 @@ machine-$(CONFIG_ARCH_TANGO) += tango machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U300) += u300 machine-$(CONFIG_ARCH_U8500) += ux500 -machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSATILE) += versatile machine-$(CONFIG_ARCH_VEXPRESS) += vexpress machine-$(CONFIG_ARCH_VT8500) += vt8500 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..b5bd3de87c33 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -38,6 +38,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91-ariettag25.dtb \ at91-cosino_mega2560.dtb \ at91-kizboxmini.dtb \ + at91-wb45n.dtb \ at91sam9g15ek.dtb \ at91sam9g25ek.dtb \ at91sam9g35ek.dtb \ @@ -50,7 +51,10 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ at91-sama5d3_xplained.dtb \ + at91-dvk_som60.dtb \ + at91-gatwick.dtb \ at91-tse850-3.dtb \ + at91-wb50n.dtb \ sama5d31ek.dtb \ sama5d33ek.dtb \ sama5d34ek.dtb \ @@ -73,6 +77,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-b-rev2.dtb \ bcm2835-rpi-b-plus.dtb \ bcm2835-rpi-a-plus.dtb \ + bcm2835-rpi-cm1-io1.dtb \ bcm2836-rpi-2-b.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ @@ -200,6 +205,7 @@ dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-dlink-dns-313.dtb \ gemini-nas4220b.dtb \ gemini-rut1xx.dtb \ + gemini-sl93512r.dtb \ gemini-sq201.dtb \ gemini-wbd111.dtb \ gemini-wbd222.dtb @@ -345,7 +351,8 @@ dtb-$(CONFIG_SOC_IMX27) += \ imx27-phytec-phycore-rdk.dtb \ imx27-phytec-phycard-s-rdk.dtb dtb-$(CONFIG_SOC_IMX31) += \ - imx31-bug.dtb + imx31-bug.dtb \ + imx31-lite.dtb dtb-$(CONFIG_SOC_IMX35) += \ imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-pdk.dtb @@ -358,10 +365,14 @@ dtb-$(CONFIG_SOC_IMX51) += \ imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ imx51-ts4800.dtb \ - imx51-zii-rdu1.dtb + imx51-zii-rdu1.dtb \ + imx51-zii-scu2-mezz.dtb \ + imx51-zii-scu3-esb.dtb dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ + imx53-kp-ddc.dtb \ + imx53-kp-hsc.dtb \ imx53-m53evk.dtb \ imx53-mba53.dtb \ imx53-ppd.dtb \ @@ -400,6 +411,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-hummingboard2-emmc-som-v15.dtb \ imx6dl-hummingboard2-som-v15.dtb \ imx6dl-icore.dtb \ + imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ imx6dl-mamoj.dtb \ imx6dl-nit6xlite.dtb \ @@ -521,6 +533,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ imx6sl-warp.dtb +dtb-$(CONFIG_SOC_IMX6SLL) += \ + imx6sll-evk.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-nitrogen6sx.dtb \ imx6sx-sabreauto.dtb \ @@ -533,6 +547,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-udoo-neo-full.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ + imx6ul-ccimx6ulsbcexpress.dtb \ imx6ul-geam.dtb \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ @@ -567,8 +582,10 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610-cosmic.dtb \ vf610m4-cosmic.dtb \ vf610-twr.dtb \ + vf610-zii-cfu1.dtb \ vf610-zii-dev-rev-b.dtb \ - vf610-zii-dev-rev-c.dtb + vf610-zii-dev-rev-c.dtb \ + vf610-zii-ssmb-spu3.dtb dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ imx23-olinuxino.dtb \ @@ -695,10 +712,12 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-pepper.dtb \ am335x-phycore-rdk.dtb \ am335x-pocketbeagle.dtb \ + am335x-sancloud-bbe.dtb \ am335x-shc.dtb \ am335x-sbc-t335.dtb \ am335x-sl50.dtb \ - am335x-wega-rdk.dtb + am335x-wega-rdk.dtb \ + am335x-osd3358-sm-red.dtb dtb-$(CONFIG_ARCH_OMAP4) += \ omap4-droid4-xt894.dtb \ omap4-duovero-parlor.dtb \ @@ -819,6 +838,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7793-gose.dtb \ r8a7794-alt.dtb \ r8a7794-silk.dtb \ + r9a06g032-rzn1d400-db.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-evb.dtb \ @@ -859,6 +879,8 @@ dtb-$(CONFIG_ARCH_S3C64XX) += \ s3c6410-smdk6410.dtb dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-aquila.dtb \ + s5pv210-fascinate4g.dtb \ + s5pv210-galaxys.dtb \ s5pv210-goni.dtb \ s5pv210-smdkc110.dtb \ s5pv210-smdkv210.dtb \ @@ -1039,7 +1061,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \ tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-harmony.dtb \ - tegra20-iris-512.dtb \ + tegra20-colibri-iris.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ tegra20-plutux.dtb \ @@ -1109,6 +1131,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ + zynq-zturn.dtb \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ @@ -1138,6 +1161,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-388-clearfog-pro.dtb \ armada-388-db.dtb \ armada-388-gp.dtb \ + armada-388-helios4.dtb \ armada-388-rd.dtb dtb-$(CONFIG_MACH_ARMADA_39X) += \ armada-398-db.dtb @@ -1168,7 +1192,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-rfb-emmc.dtb \ mt7623a-rfb-nand.dtb \ mt7623n-rfb-emmc.dtb \ - mt7623n-rfb-nand.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index ed7a5a3daa42..8c6fc4161ad7 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -396,7 +396,7 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 1356fd6f8da3..c87d01297a01 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -778,7 +778,7 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio3>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 0c096a795e37..bf1a40e45c97 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -690,7 +690,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ + interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts new file mode 100755 index 000000000000..4d969013f99a --- /dev/null +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -0,0 +1,457 @@ +//SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2018 Octavo Systems LLC - http://www.octavosystems.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-osd335x-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +#include <dt-bindings/display/tda998x.h> + +/ { + model = "Octavo Systems OSD3358-SM-RED"; + compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&am33xx_pinmux { + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; + + flash_enable: flash-enable { + pinctrl-single,pins = < + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ + >; + }; + + imu_interrupt: imu-interrupt { + pinctrl-single,pins = < + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rx_er.gpio3_2 */ + >; + }; + + ethernet_interrupt: ethernet-interrupt{ + pinctrl-single,pins = < + AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; +}; + +&lcdc { + status = "okay"; + + /* If you want to get 24 bit RGB and 16 BGR mode instead of + * current 16 bit RGB and 24 BGR modes, set the propety + * below to "crossed" and uncomment the video-ports -property + * in tda19988 node. + * AM335x errata for wiring: + * http://www.ti.com/lit/er/sprz360i/sprz360i.pdf + */ + + blue-and-red-wiring = "straight"; + + port { + lcdc_0: endpoint { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + tda19988: hdmi-encoder@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ + /* video-ports = <0x234501>; */ + + #sound-dai-cells = <0>; + audio-ports = < TDA998x_I2S 0x03>; + + port { + hdmi_0: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + + mpu9250: imu@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ax8975@c { + compatible = "ak,ak8975"; + reg = <0x0c>; + }; + }; + /*invensense,int_config = <0x10>; + invensense,level_shifter = <0>; + invensense,orientation = [01 00 00 00 01 00 00 00 01]; + invensense,sec_slave_type = <0>; + invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ + }; + + bmp280: pressure@78 { + compatible = "bosch,bmp280"; + reg = <0x76>; + }; +}; + +&rtc { + system-power-controller; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +/ { + clk_mcasp0_fixed: clk-mcasp0-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk-mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Black"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led2 { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led3 { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user-leds-s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux-clkout2-pin { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw-default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_txd3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_txd2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_txclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rxclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw-sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci-mdio-default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci-mdio-sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux-mmc1-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + >; + }; + + emmc_pins: pinmux-emmc-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; + interrupts-extended = <&intc 18 &tps 0>; + interrupt-names = "mc", "vbus"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <4>; + phy-mode = "rgmii-txid"; +}; + +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&mmc1 { + status = "okay"; + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&rtc { + clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clock-names = "ext-clk", "int-clk"; +}; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts new file mode 100644 index 000000000000..7b8e7417a11e --- /dev/null +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "SanCloud BeagleBone Enhanced"; + compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + usb_hub_ctrl: usb_hub_ctrl { + pinctrl-single,pins = < + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLUP | MUX_MODE7) /* rmii1_refclk.gpio0_29 */ + >; + }; + + mpu6050_pins: pinmux_mpu6050_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE7) /* uart0_ctsn.gpio1_8 */ + >; + }; + + lps3331ap_pins: pinmux_lps3331ap_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + >; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii-txid"; +}; + +&i2c0 { + lps331ap: barometer@5c { + compatible = "st,lps331ap-press"; + st,drdy-int-pin = <1>; + reg = <0x5c>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + }; + + mpu6050: accelerometer@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + interrupt-parent = <&gpio0>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + orientation = <0xff 0 0 0 1 0 0 0 0xff>; + }; + + usb2512b: usb-hub@2c { + compatible = "microchip,usb2512b"; + reg = <0x2c>; + reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + /* wifi on port 4 */ + }; +}; diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 1bcc60424ecd..38d57b89f7d3 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -8,6 +8,8 @@ /dts-v1/; #include "am33xx.dtsi" +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "Toby Churchill SL50 Series"; @@ -34,25 +36,25 @@ pinctrl-0 = <&led_pins>; led0 { - label = "sl50:green:usr0"; + label = "sl50:red:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; default-state = "off"; }; led1 { - label = "sl50:red:usr1"; + label = "sl50:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; led2 { - label = "sl50:green:usr2"; + label = "sl50:red:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; default-state = "off"; }; led3 { - label = "sl50:red:usr3"; + label = "sl50:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "off"; }; @@ -60,16 +62,44 @@ backlight0: disp0 { compatible = "pwm-backlight"; - pwms = <&ehrpwm1 0 500000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&backlight0_pins>; + pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_sys_reg>; }; backlight1: disp1 { compatible = "pwm-backlight"; - pwms = <&ehrpwm1 1 500000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&backlight1_pins>; + pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_sys_reg>; }; clocks { @@ -78,27 +108,85 @@ #size-cells = <0>; /* audio external oscillator */ - tlv320aic3x_mclk: oscillator@0 { + audio_mclk_fixed: oscillator@0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; /* 24.576MHz */ }; + + audio_mclk: audio_mclk_gate@0 { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_mclk_pins>; + clocks = <&audio_mclk_fixed>; + enable-gpios = <&gpio1 27 0>; + }; + }; + + panel: lcd_panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + tft-alt-mode = <0>; + mono-8bit-mode = <0>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + native-mode = <&timing0>; + timing0: 960x128 { + clock-frequency = <18000000>; + hactive = <960>; + vactive = <272>; + + hback-porch = <40>; + hfront-porch = <16>; + hsync-len = <24>; + hsync-active = <0>; + + vback-porch = <3>; + vfront-porch = <8>; + vsync-len = <4>; + vsync-active = <0>; + }; + }; }; sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM335x-SL50"; - ti,audio-codec = <&audio_codec>; - ti,mcasp-controller = <&mcasp0>; + compatible = "audio-graph-card"; + label = "sound-card"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_pa_pins>; + + widgets = "Headphone", "Headphone Jack", + "Speaker", "Speaker External", + "Line", "Line In", + "Microphone", "Microphone Jack"; - clocks = <&tlv320aic3x_mclk>; - clock-names = "mclk"; + routing = "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Amplifier", "MONO_LOUT", + "Speaker External", "Amplifier", + "LINE1R", "Line In", + "LINE1L", "Line In", + "MIC3L", "Microphone Jack", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1R", "Line In", - "LINE1L", "Line In"; + dais = <&cpu_port>; + + pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; }; emmc_pwrseq: pwrseq@0 { @@ -108,6 +196,14 @@ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; }; + vdd_sys_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_sys_reg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; @@ -120,6 +216,65 @@ pinctrl-names = "default"; pinctrl-0 = <&lwb_pins>; + audio_pins: pinmux_audio_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ + >; + }; + + audio_pa_pins: pinmux_audio_pa_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ + >; + }; + + audio_mclk_pins: pinmux_audio_mclk_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; + + backlight0_pins: pinmux_backlight0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ + >; + }; + + backlight1_pins: pinmux_backlight1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + >; + }; + + lcd_pins: pinmux_lcd_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + led_pins: pinmux_led_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ @@ -207,6 +362,8 @@ /* MDIO */ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + /* Ethernet */ + AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ >; }; @@ -245,20 +402,16 @@ >; }; - audio_pins: pinmux_audio_pins { + ehrpwm1_pins: pinmux_ehrpwm1a_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */ >; }; - ehrpwm1_pins: pinmux_ehrpwm1a_pins { + rtc0_irq_pins: pinmux_rtc0_irq_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */ + AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad9.gpio0_23 */ >; }; @@ -274,15 +427,18 @@ lwb_pins: pinmux_lwb_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */ AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */ AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ /* PDI Bus - Battery system */ AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ + /* FPGA */ + AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ + AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ >; }; }; @@ -298,9 +454,14 @@ reg = <0x24>; }; - bq32000: rtc@68 { - compatible = "ti,bq32000"; - trickle-resistor-ohms = <1120>; + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc0_irq_pins>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */ + wakeup-source; + trickle-resistor-ohms = <2000>; reg = <0x68>; }; @@ -326,12 +487,21 @@ audio_codec: tlv320aic3106@1b { status = "okay"; compatible = "ti,tlv320aic3106"; + #sound-dai-cells = <0>; reg = <0x1b>; + ai3x-micbias-vg = <2>; /* 2.5V */ AVDD-supply = <&ldo4_reg>; IOVDD-supply = <&ldo4_reg>; DRVDD-supply = <&ldo4_reg>; DVDD-supply = <&ldo3_reg>; + + codec_port: port { + codec_endpoint: endpoint { + remote-endpoint = <&cpu_endpoint>; + clocks = <&audio_mclk>; + }; + }; }; /* Ambient Light Sensor */ @@ -363,7 +533,7 @@ &usb0 { status = "okay"; - dr_mode = "peripheral"; + dr_mode = "otg"; }; &usb1 { @@ -397,17 +567,27 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&audio_pins>; - + #sound-dai-cells = <0>; op-mode = <0>; /* MCASP_ISS_MODE */ tdm-slots = <2>; - serial-dir = < - 2 0 1 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 >; - tx-num-evt = <1>; - rx-num-evt = <1>; + tx-num-evt = <32>; + rx-num-evt = <32>; + + cpu_port: port { + cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + + dai-format = "dsp_b"; + bitclock-master = <&codec_port>; + frame-master = <&codec_port>; + bitclock-inversion; + clocks = <&audio_mclk>; + }; + }; }; &uart0 { @@ -507,13 +687,8 @@ }; &cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "mii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; phy-mode = "mii"; + phy-handle = <ðphy0>; }; &mac { @@ -528,6 +703,12 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; + reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <100>; /* PHY datasheet states 100us min */ + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; }; &sham { @@ -547,3 +728,15 @@ pinctrl-names = "default"; pinctrl-0 = <&ehrpwm1_pins>; }; + +&lcdc { + status = "okay"; +}; + +&tscadc { + status = "okay"; +}; + +&am335x_adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 9cd62bc2ca35..d3dd6a16e70a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -29,8 +29,8 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - d_can0 = &dcan0; - d_can1 = &dcan1; + d-can0 = &dcan0; + d-can1 = &dcan1; usb0 = &usb0; usb1 = &usb1; phy0 = &usb0_phy; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 98aadb0f81c5..1d158cfda15f 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -127,6 +127,7 @@ status = "okay"; pinctrl-names = "default"; enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ + vcc-supply = <&vdd_io_reg>; port { lcd_in: endpoint { @@ -154,6 +155,7 @@ bl: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; + power-supply = <&vdd_io_reg>; pinctrl-0 = <&backlight_pins>; pwms = <&pwm11 0 5000000 0>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; @@ -168,6 +170,13 @@ ti,timers = <&timer11>; #pwm-cells = <3>; }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ + #phy-cells = <0>; + }; }; &davinci_emac { @@ -203,6 +212,7 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <&vdd_io_reg>; }; }; @@ -220,15 +230,21 @@ cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */ }; -&mmc2 { +&mmc3 { status = "disabled"; }; -&mmc3 { - status = "disabled"; +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; }; &omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_rst_pins>; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < @@ -287,4 +303,32 @@ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ >; }; + + hsusb1_rst_pins: pinmux_hsusb1_rst_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; + + hsusb1_pins: pinmux_hsusb1_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + >; + }; }; diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi index a6d5ff73c163..dae6e458e59f 100644 --- a/arch/arm/boot/dts/am3517-som.dtsi +++ b/arch/arm/boot/dts/am3517-som.dtsi @@ -14,6 +14,32 @@ cpu0-supply = <&vdd_core_reg>; }; }; + + wl12xx_buffer: wl12xx_buf { + compatible = "regulator-fixed"; + regulator-name = "wl1271_buf"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_buffer_pins>; + gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */ + regulator-always-on; + vin-supply = <&vdd_1v8_reg>; + }; + + wl12xx_vmmc2: wl12xx_vmmc2 { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_wkup_pins>; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */ + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; + vin-supply = <&wl12xx_buffer>; + }; }; &gpmc { @@ -64,7 +90,6 @@ regulators { vdd_core_reg: VDCDC1 { regulator-name = "vdd_core"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -72,7 +97,6 @@ vdd_io_reg: VDCDC2 { regulator-name = "vdd_io"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -80,7 +104,6 @@ vdd_1v8_reg: VDCDC3 { regulator-name = "vdd_1v8"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -88,7 +111,6 @@ vdd_usb18_reg: LDO1 { regulator-name = "vdd_usb18"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -96,7 +118,6 @@ vdd_usb33_reg: LDO2 { regulator-name = "vdd_usb33"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -126,8 +147,63 @@ }; }; +&mmc2 { + interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>; + + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; + non-removable; + bus-width = <4>; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + bluetooth { + compatible = "ti,wl1271-st"; + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */ + max-speed = <3000000>; + }; +}; + &omap3_pmx_core { + wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */ + OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + rtc_pins: pinmux_rtc_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ @@ -139,4 +215,23 @@ OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ + OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ + >; + }; +}; + +&omap3_pmx_wkup { + + wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ + >; + }; }; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 60414b1ca404..5b97c20c5ed4 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -790,7 +790,7 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio1>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <23 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 5bb9d68d6e90..d9a2049a1ea8 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -66,10 +66,6 @@ }; }; -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - &extcon_usb2 { id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi index c6d858b31011..784639ddf451 100644 --- a/arch/arm/boot/dts/am572x-idk-common.dtsi +++ b/arch/arm/boot/dts/am572x-idk-common.dtsi @@ -57,10 +57,6 @@ }; }; -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - &extcon_usb2 { id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index ad87f1ae904d..c9063ffca524 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -395,8 +395,13 @@ dr_mode = "host"; }; +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb2 { - dr_mode = "peripheral"; + extcon = <&extcon_usb2>; + dr_mode = "otg"; }; &mmc1 { diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts index 50ed4ae5c621..53b4bd35522a 100644 --- a/arch/arm/boot/dts/armada-388-clearfog-base.dts +++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts @@ -3,11 +3,6 @@ * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ /dts-v1/; diff --git a/arch/arm/boot/dts/armada-388-clearfog-pro.dts b/arch/arm/boot/dts/armada-388-clearfog-pro.dts index 24e4b5a509be..ff890c09c3ed 100644 --- a/arch/arm/boot/dts/armada-388-clearfog-pro.dts +++ b/arch/arm/boot/dts/armada-388-clearfog-pro.dts @@ -3,11 +3,6 @@ * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ #include "armada-388-clearfog.dts" diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 5fd0f6f61e77..89a354b43978 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -3,11 +3,6 @@ * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828) * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ /dts-v1/; @@ -235,7 +230,7 @@ &spi1 { /* * Add SPI CS pins for clearfog: - * CS0: W25Q32 (not populated on uSOM) + * CS0: W25Q32 * CS1: * CS2: mikrobus */ diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi index 0d9dfdfe977e..7c6ad2afb094 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dtsi +++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi @@ -3,11 +3,6 @@ * Device Tree include file for SolidRun Clearfog 88F6828 based boards * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ #include "armada-388.dtsi" @@ -230,7 +225,7 @@ &spi1 { /* * Add SPI CS pins for clearfog: - * CS0: W25Q32 (not populated on uSOM) + * CS0: W25Q32 * CS1: PIC microcontroller (Pro models) * CS2: mikrobus */ diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/armada-388-helios4.dts new file mode 100644 index 000000000000..705adfa8c680 --- /dev/null +++ b/arch/arm/boot/dts/armada-388-helios4.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Helios4 + * based on SolidRun Clearfog revision A1 rev 2.0 (88F6828) + * + * Copyright (C) 2017 Aditya Prayoga <aditya@kobol.io> + * + */ + +/dts-v1/; +#include "armada-388.dtsi" +#include "armada-38x-solidrun-microsom.dtsi" + +/ { + model = "Helios4"; + compatible = "kobol,helios4", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + aliases { + /* So that mvebu u-boot can update the MAC addresses */ + ethernet1 = ð0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "power_brick_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_5p0v_hdd: regulator-5v-hdd { + compatible = "regulator-fixed"; + regulator-name = "5V_HDD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_5p0v_usb: regulator-5v-usb { + compatible = "regulator-fixed"; + regulator-name = "USB-PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&expander0 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_12v>; + }; + + system-leds { + compatible = "gpio-leds"; + status-led { + label = "helios4:green:status"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + fault-led { + label = "helios4:red:fault"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + + io-leds { + compatible = "gpio-leds"; + sata1-led { + label = "helios4:green:ata1"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata1"; + default-state = "off"; + }; + sata2-led { + label = "helios4:green:ata2"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata2"; + default-state = "off"; + }; + sata3-led { + label = "helios4:green:ata3"; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata3"; + default-state = "off"; + }; + sata4-led { + label = "helios4:green:ata4"; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + linux,default-trigger = "ata4"; + default-state = "off"; + }; + usb-led { + label = "helios4:green:usb"; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usb-host"; + default-state = "off"; + }; + }; + + fan1: j10-pwm { + compatible = "pwm-fan"; + pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */ + }; + + fan2: j17-pwm { + compatible = "pwm-fan"; + pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */ + }; + + usb2_phy: usb2-phy { + compatible = "usb-nop-xceiv"; + vbus-regulator = <®_5p0v_usb>; + }; + + usb3_phy: usb3-phy { + compatible = "usb-nop-xceiv"; + }; + + soc { + internal-regs { + i2c@11000 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * PCA9655 GPIO expander, up to 1MHz clock. + * 0-Board Revision bit 0 # + * 1-Board Revision bit 1 # + * 5-USB3 overcurrent + * 6-USB3 power + */ + expander0: gpio-expander@20 { + /* + * This is how it should be: + * compatible = "onnn,pca9655", + * "nxp,pca9555"; + * but you can't do this because of + * the way I2C works. + */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pca0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + board_rev_bit_0 { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "board-rev-0"; + }; + board_rev_bit_1 { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "board-rev-1"; + }; + usb3_ilimit { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; + line-name = "usb-overcurrent-status"; + }; + }; + + temp_sensor: temp@4c { + compatible = "ti,lm75"; + reg = <0x4c>; + vcc-supply = <®_3p3v>; + }; + }; + + i2c@11100 { + /* + * External I2C Bus for user peripheral + */ + clock-frequency = <400000>; + pinctrl-0 = <&helios_i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + }; + + sata1: sata-port@1 { + reg = <1>; + }; + }; + + sata@e0000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + sata2: sata-port@0 { + reg = <0>; + }; + + sata3: sata-port@1 { + reg = <1>; + }; + }; + + spi@10680 { + pinctrl-0 = <&spi1_pins + µsom_spi1_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + sdhci@d8000 { + bus-width = <4>; + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&helios_sdhci_pins + &helios_sdhci_cd_pins>; + pinctrl-names = "default"; + status = "okay"; + vmmc = <®_3p3v>; + wp-inverted; + }; + + usb@58000 { + usb-phy = <&usb2_phy>; + status = "okay"; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + + pinctrl@18000 { + pca0_pins: pca0-pins { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + microsom_phy0_int_pins: microsom-phy0-int-pins { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + helios_i2c1_pins: i2c1-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c1"; + }; + helios_sdhci_cd_pins: helios-sdhci-cd-pins { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + helios_sdhci_pins: helios-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + helios_led_pins: helios-led-pins { + marvell,pins = "mpp24", "mpp25", + "mpp49", "mpp50", + "mpp52", "mpp53", + "mpp54"; + marvell,function = "gpio"; + }; + helios_fan_pins: helios-fan-pins { + marvell,pins = "mpp41", "mpp43", + "mpp48", "mpp55"; + marvell,function = "gpio"; + }; + microsom_spi1_cs_pins: spi1-cs-pins { + marvell,pins = "mpp59"; + marvell,function = "spi1"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi index 2d1cea131e71..3a7f9c1ac346 100644 --- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi @@ -3,11 +3,6 @@ * Device Tree file for SolidRun Armada 38x Microsom * * Copyright (C) 2015 Russell King - * - * This board is in development; the contents of this file work with - * the A1 rev 2.0 of the board, which does not represent final - * production board. Things will change, don't expect this file to - * remain compatible info the future. */ #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> @@ -99,7 +94,6 @@ compatible = "w25q32", "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <3000000>; - status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index ede11c597673..2375449c02d0 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -80,20 +80,20 @@ }; }; -&ehci0 { +/* + * Enable port A as device (via the virtual hub) and port B as + * host by default on the eval board. This can be easily changed + * by replacing the override below with &ehci0 { ... } to enable + * host on both ports. + */ +&vhub { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ah_default>; }; &ehci1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2bh_default>; }; &uhci { status = "okay"; - - /* No pinctrl, this follows the above EHCI settings */ }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 0b9b37d4d6ef..7d28c03a9e0b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -21,9 +21,9 @@ #size-cells = <1>; ranges; - vga_memory: framebuffer@bf000000 { + vga_memory: framebuffer@9f000000 { no-map; - reg = <0xbf000000 0x01000000>; /* 16M */ + reg = <0x9f000000 0x01000000>; /* 16M */ }; flash_memory: region@98000000 { diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 75df1573380e..b23a983f95a5 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -92,6 +92,12 @@ reg = <0x1e6c0080 0x80>; }; + cvic: copro-interrupt-controller@1e6c2000 { + compatible = "aspeed,ast2400-cvic", "aspeed-cvic"; + valid-sources = <0x7fffffff>; + reg = <0x1e6c2000 0x80>; + }; + mac0: ethernet@1e660000 { compatible = "aspeed,ast2400-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; @@ -113,6 +119,8 @@ reg = <0x1e6a1000 0x100>; interrupts = <5>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2h_default>; status = "disabled"; }; @@ -123,6 +131,20 @@ #ports = <3>; clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; status = "disabled"; + /* + * No default pinmux, it will follow EHCI, use an explicit pinmux + * override if you don't enable EHCI + */ + }; + + vhub: usb-vhub@1e6a0000 { + compatible = "aspeed,ast2400-usb-vhub"; + reg = <0x1e6a0000 0x300>; + interrupts = <5>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2d_default>; + status = "disabled"; }; apb { @@ -161,7 +183,7 @@ status = "disabled"; }; - sram@1e720000 { + sram: sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x8000>; // 32K }; @@ -224,7 +246,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_APB>; + clocks = <&syscon ASPEED_CLK_24M>; resets = <&syscon ASPEED_RESET_PWM>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 17f2714d18a7..87fdc146ff52 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -127,6 +127,13 @@ reg = <0x1e6c0080 0x80>; }; + cvic: copro-interrupt-controller@1e6c2000 { + compatible = "aspeed,ast2500-cvic", "aspeed-cvic"; + valid-sources = <0xffffffff>; + copro-sw-interrupts = <1>; + reg = <0x1e6c2000 0x80>; + }; + mac0: ethernet@1e660000 { compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; @@ -148,6 +155,8 @@ reg = <0x1e6a1000 0x100>; interrupts = <5>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ah_default>; status = "disabled"; }; @@ -156,6 +165,8 @@ reg = <0x1e6a3000 0x100>; interrupts = <13>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bh_default>; status = "disabled"; }; @@ -166,6 +177,20 @@ #ports = <2>; clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; status = "disabled"; + /* + * No default pinmux, it will follow EHCI, use an explicit pinmux + * override if you don't enable EHCI + */ + }; + + vhub: usb-vhub@1e6a0000 { + compatible = "aspeed,ast2500-usb-vhub"; + reg = <0x1e6a0000 0x300>; + interrupts = <5>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad_default>; + status = "disabled"; }; apb { @@ -211,7 +236,7 @@ status = "disabled"; }; - sram@1e720000 { + sram: sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x9000>; // 36K }; @@ -281,7 +306,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_APB>; + clocks = <&syscon ASPEED_CLK_24M>; resets = <&syscon ASPEED_RESET_PWM>; status = "disabled"; }; @@ -1417,6 +1442,11 @@ groups = "USB2AH"; }; + pinctrl_usb2ad_default: usb2ad_default { + function = "USB2AD"; + groups = "USB2AD"; + }; + pinctrl_usb11bhid_default: usb11bhid_default { function = "USB11BHID"; groups = "USB11BHID"; diff --git a/arch/arm/boot/dts/at91-dvk_som60.dts b/arch/arm/boot/dts/at91-dvk_som60.dts new file mode 100644 index 000000000000..ededd5b0d27b --- /dev/null +++ b/arch/arm/boot/dts/at91-dvk_som60.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_som60.dts - Device Tree file for the DVK SOM60 board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten <ben.whitten@lairdtech.com> + * + */ +/dts-v1/; +#include "at91-som60.dtsi" +#include "at91-dvk_su60_somc.dtsi" +#include "at91-dvk_su60_somc_lcm.dtsi" + +/ { + model = "Laird DVK SOM60"; + compatible = "laird,dvk-som60", "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + tick-timer = &pit; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&ssc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&usart1 { + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&pit { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&macb0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi new file mode 100644 index 000000000000..bb86f17ed5ed --- /dev/null +++ b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_su60_somc.dtsi - Device Tree file for the DVK SOM60 base board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten <ben.whitten@lairdtech.com> + * + */ + +/ { + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; + + atmel,model = "wm8904 @ DVK-SOM60"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "okay"; + }; +}; + +&mmc0 { + status = "okay"; + + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + slot@0 { + bus-width = <4>; + cd-gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; + cd-inverted; + }; +}; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */ + spi-flash@0 { + compatible = "mxicy,mx25u4035", "jedec,spi-nor"; + spi-max-frequency = <33000000>; + reg = <0>; + }; +}; + +&ssc0 { + atmel,clk-from-rk-pin; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck2>; + clock-names = "mclk"; + }; +}; + +&i2c1 { + status = "okay"; + + eeprom@87 { + compatible = "giantec,gt24c32a", "atmel,24c32"; + reg = <87>; + pagesize = <32>; + }; +}; + +&usart1 { + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&pit { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&macb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@7 { + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_geth_int>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; +}; + +&macb1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>; + interrupt-parent = <&pioC>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi new file mode 100644 index 000000000000..4b9176dc5d02 --- /dev/null +++ b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-dvk_su60_somc_lcm.dtsi - Device Tree file for the DVK SOM60 LCD board + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten <ben.whitten@lairdtech.com> + * + */ + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + panel: panel { + compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + vcc_lcd_reg: fixedregulator_lcd { + compatible = "regulator-fixed"; + regulator-name = "VCC LCM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + status = "okay"; + }; +}; + +&pinctrl { + board { + pinctrl_lcd_ctp_int: lcd_ctp_int { + atmel,pins = + <AT91_PIOC 28 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + ft5426@56 { + compatible = "focaltech,ft5426", "edt,edt-ft5406"; + reg = <56>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_ctp_int>; + + interrupt-parent = <&pioC>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&hlcdc { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/at91-gatwick.dts new file mode 100644 index 000000000000..5a81cab5fc3a --- /dev/null +++ b/arch/arm/boot/dts/at91-gatwick.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-gatwick.dts - Device Tree file for the Gatwick board + * + * Copyright (C) 2018 Laird + * + */ +/dts-v1/; +#include "at91-wb50n.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Laird Workgroup Bridge 50N - Project Gatwick"; + compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + gpio_keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + reset-button { + label = "Reset Button"; + linux,code = <KEY_SETUP>; + gpios = <&pioE 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + ethernet { + label = "gatwick:yellow:ethernet"; + gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + wifi { + label = "gatwick:green:wifi"; + gpios = <&pioA 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + ble { + label = "gatwick:blue:ble"; + gpios = <&pioA 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + lora { + label = "gatwick:orange:lora"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blank { + label = "gatwick:green:blank"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + user { + label = "gatwick:yellow:user"; + gpios = <&pioA 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&pinctrl { + board { + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pullup deglitch */ + }; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +/* FTDI USART */ +&usart0 { + status = "okay"; +}; + +/* GPS USART */ +&usart1 { + pinctrl-0 = <&pinctrl_usart1>; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + spidev@0 { + compatible = "semtech,sx1301"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&usb1 { + status = "okay"; + /delete-property/atmel,oc-gpio; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/at91-som60.dtsi b/arch/arm/boot/dts/at91-som60.dtsi new file mode 100644 index 000000000000..241682a207c5 --- /dev/null +++ b/arch/arm/boot/dts/at91-som60.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-som60.dtsi - Device Tree file for the SOM60 module + * + * Copyright (C) 2018 Laird, + * 2018 Ben Whitten <ben.whitten@lairdtech.com> + * + */ +#include "sama5d36.dtsi" + +/ { + model = "Laird SOM60"; + compatible = "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; +}; + +&pinctrl { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_mmc0_en: mmc0_en { + atmel,pins = + <AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + pinctrl_nand0_wp: nand0_wp { + atmel,pins = + <AT91_PIOE 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_usb_vbus: usb_vbus { + atmel,pins = + <AT91_PIOE 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + /* Conflicts with USART2_SCK */ + }; + + pinctrl_usart2_sck: usart2_sck { + atmel,pins = + <AT91_PIOE 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; + /* Conflicts with USB_VBUS */ + }; + + pinctrl_usb_oc: usb_oc { + atmel,pins = + <AT91_PIOE 15 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + /* Conflicts with USART3_SCK */ + }; + + pinctrl_usart3_sck: usart3_sck { + atmel,pins = + <AT91_PIOE 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; + /* Conflicts with USB_OC */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_geth_int: geth_int { + atmel,pins = + <AT91_PIOB 25 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + /* Conflicts with USART1_SCK */ + }; + + pinctrl_usart1_sck: usart1_sck { + atmel,pins = + <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; + /* Conflicts with GETH_INT */ + }; + + pinctrl_eth_int: eth_int { + atmel,pins = + <AT91_PIOC 10 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { + atmel,pins = + <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; +}; + +&mmc0 { + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc1 { + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&spi0 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; +}; + +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; +}; + +&usart1 { + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; +}; + +&usart2 { + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts_cts>; +}; + +&usart3 { + pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; +}; + +&adc0 { + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + >; +}; + +&macb0 { + phy-mode = "rgmii"; +}; + +&macb1 { + phy-mode = "rmii"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand: nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ubootspl@0 { + label = "u-boot-spl"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x20000>; + }; + + ubi@e0000 { + label = "ubi"; + reg = <0xe0000 0xfe00000>; + }; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + atmel,vbus-gpio = <&pioC 14 GPIO_ACTIVE_HIGH>; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_vbus &pinctrl_usb_oc>; + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 20 GPIO_ACTIVE_HIGH + 0>; + atmel,oc-gpio = <0 + &pioE 15 GPIO_ACTIVE_LOW + 0>; +}; diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts new file mode 100644 index 000000000000..5b9512a6c89c --- /dev/null +++ b/arch/arm/boot/dts/at91-wb45n.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb45n.dts - Device Tree file for WB45NBT board + * + * Copyright (C) 2018 Laird + * + */ +/dts-v1/; +#include "at91-wb45n.dtsi" + +/ { + model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; + compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + irqbtn@18 { + reg = <18>; + label = "IRQBTN"; + linux,code = <99>; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; + gpio-key,wakeup = <1>; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&macb0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&usart0 { + status = "okay"; +}; + +&usart3 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/at91-wb45n.dtsi new file mode 100644 index 000000000000..ebe61a25ca96 --- /dev/null +++ b/arch/arm/boot/dts/at91-wb45n.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb45n.dtsi - Device Tree file for WB45NBT board + * + * Copyright (C) 2018 Laird + * + */ + +#include "at91sam9g25.dtsi" + +/ { + model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; + compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + atheros { + compatible = "atheros,ath6kl"; + atheros,board-id = "SD32"; + }; +}; + +&reset_controller { + compatible = "atmel,sama5d3-rstc"; +}; + +&shutdown_controller { + atmel,wakeup-mode = "low"; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&ebi { + status = "okay"; + nand_controller: nand-controller { + pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>; + pinctrl-names = "default"; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bs"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "redund-env"; + reg = <0xc0000 0x20000>; + }; + + kernel-a@e0000 { + label = "kernel-a"; + reg = <0xe0000 0x280000>; + }; + + kernel-b@360000 { + label = "kernel-b"; + reg = <0x360000 0x280000>; + }; + + rootfs-a@5e0000 { + label = "rootfs-a"; + reg = <0x5e0000 0x2600000>; + }; + + rootfs-b@2be0000 { + label = "rootfs-b"; + reg = <0x2be0000 0x2600000>; + }; + + user@51e0000 { + label = "user"; + reg = <0x51e0000 0x2dc0000>; + }; + + logs@7fa0000 { + label = "logs"; + reg = <0x7fa0000 0x60000>; + }; + + }; + }; + }; +}; + +&usb0 { + num-ports = <2>; + atmel,vbus-gpio = < + &pioB 12 GPIO_ACTIVE_HIGH + &pioA 31 GPIO_ACTIVE_HIGH + >; + atmel,oc-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; +}; + +&macb0 { + phy-mode = "rmii"; +}; + +&spi0 { + cs-gpios = <&pioA 14 0>, <&pioA 7 0>, <0>, <0>; +}; + +&usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_board_usb2>; + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; +}; + +&mmc0 { + pinctrl-0 = < + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&pinctrl { + usb2 { + pinctrl_board_usb2: usb2-board { + atmel,pins = + <AT91_PIOB 11 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB11 gpio vbus sense, deglitch */ + }; + }; +}; + diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts new file mode 100644 index 000000000000..8cecc7051a86 --- /dev/null +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb50n.dts - Device Tree file for wb50n evaluation board + * + * Copyright (C) 2018 Laird + * + */ + +/dts-v1/; +#include "at91-wb50n.dtsi" + +/ { + model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; + compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + btn0@10 { + reg = <10>; + label = "BTNESC"; + linux,code = <1>; /* ESC button */ + gpios = <&pioA 10 GPIO_ACTIVE_LOW>; + gpio-key,wakeup = <1>; + }; + + irqbtn@31 { + reg = <31>; + label = "IRQBTN"; + linux,code = <99>; /* SysReq button */ + gpios = <&pioE 31 GPIO_ACTIVE_LOW>; + gpio-key,wakeup = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "wb50n:blue:led0"; + gpios = <&pioA 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led1 { + label = "wb50n:green:led1"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "wb50n:red:led2"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&mmc0 { + status = "okay"; +}; + +&macb1 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +/* On BB40 this port is labeled UART1 */ +&usart0 { + status = "okay"; +}; + +/* On BB40 this port is labeled UART0 */ +&usart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi new file mode 100644 index 000000000000..85692c8ef2b1 --- /dev/null +++ b/arch/arm/boot/dts/at91-wb50n.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module + * + * Copyright (C) 2018 Laird + * + */ + +#include "sama5d31.dtsi" + +/ { + model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; + compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; +}; + +&pinctrl { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = <AT91_PIOC 26 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC26 GPIO with pullup deglitch */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = <AT91_PIOB 13 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB13 GPIO with deglitch */ + }; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&slow_osc { + atmel,osc-bypass; +}; + +&usart1_clk { + atmel,clk-output-range = <0 132000000>; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>; + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "okay"; + atheros@0 { + compatible = "atheros,ath6kl"; + atheros,board-id = "SD32"; + reg = <0>; + bus-width = <4>; + }; +}; + +&macb1 { + phy-mode = "rmii"; +}; + +&dbgu { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ +}; + +/* On BB40 this port is labeled UART1 */ +&usart0 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; +}; + +/* On BB40 this port is labeled UART0 */ +&usart1 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + dtr-gpios = <&pioD 13 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 11 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 7 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 8 GPIO_ACTIVE_LOW>; +}; + +/* USART3 is direct-connect to the Bluetooth UART on the radio SIP */ +&usart3 { + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>; + status = "okay"; +}; + +&spi1 { + cs-gpios = <&pioC 25 0>, <0>, <0>, <0>; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand: nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bs"; + reg = <0x0 0x20000>; + }; + + uboot@20000 { + label = "u-boot"; + reg = <0x20000 0x80000>; + }; + + ubootenv@a0000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + }; + + ubootenv@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x20000>; + }; + + kernel-a@e0000 { + label = "kernel-a"; + reg = <0xe0000 0x500000>; + }; + + kernel-b@5e0000 { + label = "kernel-b"; + reg = <0x5e0000 0x500000>; + }; + + rootfs-a@ae0000 { + label = "rootfs-a"; + reg = <0xae0000 0x3000000>; + }; + + rootfs-b@3ae0000 { + label = "rootfs-b"; + reg = <0x3ae0000 0x3000000>; + }; + + user@6ae0000 { + label = "user"; + reg = <0x6ae0000 0x14e0000>; + }; + }; + }; +}; + +&usb0 { + atmel,vbus-gpio = <&pioB 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <&pioA 2 GPIO_ACTIVE_LOW>; + atmel,oc-gpio = <&pioA 4 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 53c63d0a418a..33f09d5ea020 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -590,7 +590,7 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; + compatible = "atmel,at91sam9261-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 87fb0660ab5d..af68a86c9973 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -93,7 +93,7 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc", "syscon"; + compatible = "atmel,at91sam9263-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index bd001cca25a4..8fb22030f00b 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -832,7 +832,7 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91sam9g45-pmc", "syscon"; + compatible = "atmel,at91sam9rl-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index a3c3c3128148..11c0ef102ab1 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -389,13 +389,13 @@ }; }; - rstc@fffffe00 { + reset_controller: rstc@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; }; - shdwc@fffffe10 { + shutdown_controller: shdwc@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; @@ -470,7 +470,7 @@ clock-names = "dma_clk"; }; - pinctrl@fffff400 { + pinctrl: pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; @@ -1206,7 +1206,7 @@ }; }; - watchdog@fffffe40 { + watchdog: watchdog@fffffe40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 2c4df2d2d4a6..253df7170a4e 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -41,6 +41,10 @@ model = "Broadcom Cygnus SoC"; interrupt-parent = <&gic>; + aliases { + ethernet0 = ð0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -417,6 +421,11 @@ status = "disabled"; }; + rng: rng@18032000 { + compatible = "brcm,iproc-rng200"; + reg = <0x18032000 0x28>; + }; + sdhci0: sdhci@18041000 { compatible = "brcm,sdhci-iproc-cygnus"; reg = <0x18041000 0x100>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts new file mode 100644 index 000000000000..4764a25585ab --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835-rpi-cm1.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,compute-module", "brcm,bcm2835"; + model = "Raspberry Pi Compute Module IO board rev1"; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "GPIO40", + "GPIO41", + "GPIO42", + "GPIO43", + "GPIO44", + "GPIO45", + "HDMI_HPD_N", + /* Also used as ACT LED */ + "EMMC_EN_N", + /* Used by eMMC */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi new file mode 100644 index 000000000000..ef22c2da783a --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" + +/ { + leds { + act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; + }; + }; + + reg_3v3: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&sdhost { + non-removable; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; +}; diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 7704bb029605..beb6c502dadc 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -17,6 +17,12 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&local_intc>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + }; + timer { compatible = "arm,armv7-timer"; interrupt-parent = <&local_intc>; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 61315cf734ef..31b29646b14c 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -66,6 +66,12 @@ clock-frequency = <1000000>; }; + txp@7e004000 { + compatible = "brcm,bcm2835-txp"; + reg = <0x7e004000 0x20>; + interrupts = <1 11>; + }; + dma: dma@7e007000 { compatible = "brcm,bcm2835-dma"; reg = <0x7e007000 0xf00>; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts index ff2e551b9058..79d454ff3be4 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts @@ -90,3 +90,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts index 3bcc03788f38..99365bb8c41e 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts @@ -80,3 +80,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index a587384f8e40..bc330b1f6de0 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -146,3 +146,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts index 6c8f0ad82332..258d2b251900 100644 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts @@ -38,3 +38,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index ebda45fe9ea4..e7fdaed99bd0 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -57,3 +57,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 9dd0e22c906a..42bafc644013 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -64,3 +64,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index d7c34fa72b4b..dce35eb79dbe 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -91,3 +91,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts index 2642494c97a1..b7a024b7951b 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -83,3 +83,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index e7b09b7b7d25..f7f834cd3448 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -158,3 +158,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts index 16314fcc6e56..76a2bab3bc6f 100644 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -74,3 +74,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 328aa90240ce..69e3570e03dd 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -118,3 +118,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index 8ea46eed26e2..0f6f0fe13bfb 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -104,3 +104,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 5eeac7302329..f77089744996 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -57,3 +57,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index da4d9ec62fc6..4d427863756f 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -105,3 +105,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index c94c732188fb..5f663f848db1 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -99,3 +99,7 @@ &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts index 22271818f901..2033411240c7 100644 --- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts @@ -62,3 +62,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index 79a9633ec417..77d1687b4228 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -127,3 +127,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts index db744a5e122d..983149b55269 100644 --- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts +++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts @@ -39,3 +39,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts index 9e267d38df4c..ca41481b44bd 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts @@ -101,3 +101,7 @@ &usb3 { vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index d266131652ad..aa69e656d395 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -182,3 +182,7 @@ &usb3 { vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts index f5bf6586ae07..c7143a9daa1a 100644 --- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts @@ -104,3 +104,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index d173bcd93b91..03c1ab188576 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -115,3 +115,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index f47afe36d857..36efe410dcd7 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -31,5 +31,238 @@ linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; + + rfkill { + label = "WiFi"; + linux,code = <KEY_RFKILL>; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + wps { + label = "bcm53xx:white:wps"; + gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>; + }; + + usb2 { + label = "bcm53xx:green:usb2"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + power { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + }; + + wifi-disabled { + label = "bcm53xx:amber:wifi-disabled"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + wifi-enabled { + label = "bcm53xx:white:wifi-enabled"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + bluebar1 { + label = "bcm53xx:white:bluebar1"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + }; + + bluebar2 { + label = "bcm53xx:white:bluebar2"; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + + bluebar3 { + label = "bcm53xx:white:bluebar3"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + + bluebar4 { + label = "bcm53xx:white:bluebar4"; + gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; + }; + + bluebar5 { + label = "bcm53xx:white:bluebar5"; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + }; + + bluebar6 { + label = "bcm53xx:white:bluebar6"; + gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + }; + + bluebar7 { + label = "bcm53xx:white:bluebar7"; + gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; + }; + + bluebar8 { + label = "bcm53xx:white:bluebar8"; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + }; + }; + + mdio-bus-mux { + /* BIT(9) = 1 => external mdio */ + mdio_ext: mdio@200 { + reg = <0x200>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mii-mux { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio_ext>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1800c1c0 0x4>; + + /* BIT(6) = mdc, BIT(7) = mdio */ + mux-mask = <0xc0>; + + mdio-mii@0 { + /* Enable MII function */ + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "brcm,bcm53125"; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + reset-names = "robo_reset"; + reg = <0>; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan5"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan6"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + sw1_p8: port@8 { + reg = <8>; + ethernet = <&sw0_p0>; + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 14 GPIO_ACTIVE_HIGH>; +}; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; + status = "okay"; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan7"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "lan8"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@8 { + reg = <8>; + ethernet = <&gmac2>; + label = "cpu"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + sw0_p0: port@0 { + reg = <0>; + label = "extsw"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index a5cef51cfe4f..3e5e9972cd97 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -60,3 +60,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index 7496aabf8f77..7acbecd42950 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -60,3 +60,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index 53aaa5212610..f4558d9d2769 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -100,3 +100,7 @@ &spi_nor { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index 0e718edc065a..30719380b6c0 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -91,3 +91,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index 4840a782fc05..f7c3e274b354 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -7,9 +7,10 @@ #include "bcm4708.dtsi" / { - usb3_phy: usb3-phy { - compatible = "brcm,ns-bx-usb3-phy"; - }; +}; + +&usb3_phy { + compatible = "brcm,ns-bx-usb3-phy"; }; &uart0 { diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index ef995e50ee12..bc607d11eef8 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -154,13 +154,6 @@ clock-names = "phy-ref-clk"; }; - usb3_phy: usb3-phy { - compatible = "brcm,ns-ax-usb3-phy"; - reg = <0x18105000 0x1000>, <0x18003000 0x1000>; - reg-names = "dmp", "ccb-mii"; - #phy-cells = <0>; - }; - axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -359,7 +352,33 @@ reg = <0x18003000 0x8>; #size-cells = <1>; #address-cells = <0>; - status = "disabled"; + }; + + mdio-bus-mux { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x18003000 0x4>; + mux-mask = <0x200>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb3_dmp: syscon@18105000 { + reg = <0x18105000 0x1000>; }; i2c0: i2c@18009000 { diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 16007d72c346..453a2a37dabd 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -48,6 +48,14 @@ }; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts index 2e08c895f281..934f07adfe3c 100644 --- a/arch/arm/boot/dts/bcm94708.dts +++ b/arch/arm/boot/dts/bcm94708.dts @@ -42,3 +42,7 @@ reg = <0x00000000 0x08000000>; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts index c37616c67edc..31e4dd098776 100644 --- a/arch/arm/boot/dts/bcm94709.dts +++ b/arch/arm/boot/dts/bcm94709.dts @@ -42,3 +42,7 @@ reg = <0x00000000 0x08000000>; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 40e694bfe5ca..17f63c7a0437 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -90,3 +90,7 @@ }; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts index 3076e81699cf..11b0f5ed99e6 100644 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ b/arch/arm/boot/dts/bcm953012hr.dts @@ -95,3 +95,7 @@ reg = <0x00700000 0x00900000>; }; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index 79c168e2714b..e798055d6989 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -113,3 +113,7 @@ &uart1 { status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index db67377af266..d2f7d984bba5 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -50,6 +50,16 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; }; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 516a7ce25791..99d6872a6dfc 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -45,6 +45,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; cpu2: cpu@2 { @@ -52,6 +63,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <2>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; cpu3: cpu@3 { @@ -59,6 +81,17 @@ device_type = "cpu"; next-level-cache = <&l2>; reg = <3>; + + clocks = <&chip_clk CLKID_CPU>; + clock-latency = <100000>; + /* Can be modified by the bootloader */ + operating-points = < + /* kHz uV */ + 1200000 1200000 + 1000000 1200000 + 800000 1200000 + 600000 1200000 + >; }; }; diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts index 14dff3e188ed..0102ffc5aa53 100644 --- a/arch/arm/boot/dts/da850-enbw-cmc.dts +++ b/arch/arm/boot/dts/da850-enbw-cmc.dts @@ -35,6 +35,10 @@ }; }; +&ref_clk { + clock-frequency = <24000000>; +}; + &edma0 { ti,edma-reserved-slot-ranges = <32 50>; }; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 0e82bb988fde..f9b757905845 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -27,6 +27,65 @@ spi0 = &spi1; }; + backlight: backlight-pwm { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + power-supply = <&backlight_lcd>; + compatible = "pwm-backlight"; + /* + * The PWM here corresponds to production hardware. The + * schematic needs to be 1015171 (15 March 2010), Rev A + * or newer. + */ + pwms = <&ecap2 0 50000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; + default-brightness-level = <7>; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + /* + * The vpif and the LCD are mutually exclusive. + * To enable VPIF, change the status below to 'disabled' then + * then change the status of the vpif below to 'okay' + */ + status = "okay"; + enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + native-mode = <&timing0>; + timing0: 480x272 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <3>; + vfront-porch = <4>; + vsync-len = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -35,6 +94,15 @@ regulator-boot-on; }; + backlight_lcd: backlight-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_backlight_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ + enable-active-high; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "DA850/OMAP-L138 EVM"; @@ -63,6 +131,14 @@ }; }; +&ecap2 { + status = "okay"; +}; + +&ref_clk { + clock-frequency = <24000000>; +}; + &pmx_core { status = "okay"; @@ -93,6 +169,10 @@ }; }; +&sata { + status = "okay"; +}; + &serial0 { status = "okay"; }; @@ -109,6 +189,10 @@ status = "okay"; }; +&lcdc { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <100000>; @@ -336,5 +420,10 @@ &vpif { pinctrl-names = "default"; pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; - status = "okay"; + /* + * The vpif and the LCD are mutually exclusive. + * To enable VPIF, disable the ti,tilcdc,panel then + * change the status below to 'okay' + */ + status = "disabled"; }; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index 0edf769ea95c..0177e3ed20fe 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -123,6 +123,10 @@ }; }; +&ref_clk { + clock-frequency = <24000000>; +}; + &pmx_core { status = "okay"; @@ -175,6 +179,11 @@ status = "okay"; }; +&sata_refclk { + status = "okay"; + clock-frequency = <100000000>; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts index ee3932475ce7..c4729d0e6c19 100644 --- a/arch/arm/boot/dts/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/da850-lego-ev3.dts @@ -173,6 +173,15 @@ rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>; }; + bt_slow_clk: bt-clock { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>, <&bt_clock_bias>; + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&ecap2 0 30518 0>; + }; + /* ARM local RAM */ memory@ffff0000 { compatible = "syscon", "simple-mfd"; @@ -191,6 +200,10 @@ }; }; +&ref_clk { + clock-frequency = <24000000>; +}; + &pmx_core { status = "okay"; @@ -212,6 +225,20 @@ bias-disable; }; }; + + bt_clock_bias: bt-clock-bias-groups { + disable { + groups = "cp2"; + bias-disable; + }; + }; + + bt_pic_bias: bt-pic-bias-groups { + disable { + groups = "cp20"; + bias-disable; + }; + }; }; /* Input port 1 */ @@ -221,6 +248,22 @@ pinctrl-0 = <&serial1_rxtx_pins>; }; +&serial2 { + pinctrl-names = "default"; + pinctrl-0 = <&serial2_rxtx_pins>, <&serial2_rtscts_pins>, <&bt_pic_bias>; + status = "okay"; + + bluetooth { + compatible = "ti,cc2560"; + clocks = <&bt_slow_clk>; + clock-names = "ext_clock"; + enable-gpios = <&gpio 73 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + nvmem-cells = <&bdaddr>; + nvmem-cell-names = "bd-address"; + }; +}; + &rtc0 { status = "okay"; }; @@ -239,6 +282,12 @@ pagesize = <64>; read-only; reg = <0x50>; + #address-cells = <1>; + #size-cells = <1>; + + bdaddr: bdaddr@3f06 { + reg = <0x3f06 0x06>; + }; }; }; @@ -323,6 +372,10 @@ }; }; +&ecap2 { + status = "okay"; +}; + &ehrpwm0 { status = "okay"; }; @@ -336,6 +389,39 @@ gpios = <6 GPIO_ACTIVE_HIGH>; output-high; }; + + /* Don't impede Bluetooth clock signal */ + bt_clock_en { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + input; + }; + + /* + * There is a PIC microcontroller for interfacing with an Apple MFi + * chip. This interferes with normal Bluetooth operation, so we need + * to make sure it is turned off. Note: The publicly available + * schematics from LEGO don't show that these pins are connected to + * anything, but they are present in the source code from LEGO. + */ + + bt_pic_en { + gpio-hog; + gpios = <51 GPIO_ACTIVE_HIGH>; + output-low; + }; + + bt_pic_rst { + gpio-hog; + gpios = <78 GPIO_ACTIVE_HIGH>; + output-high; + }; + + bt_pic_cts { + gpio-hog; + gpios = <87 GPIO_ACTIVE_HIGH>; + input; + }; }; &usb_phy { diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 0f4f817a9e22..47aa53ba6b92 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -32,6 +32,25 @@ reg = <0xfffee000 0x2000>; }; }; + clocks: clocks { + ref_clk: ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "ref_clk"; + }; + sata_refclk: sata_refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sata_refclk"; + status = "disabled"; + }; + usb_refclkin: usb_refclkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "usb_refclkin"; + status = "disabled"; + }; + }; dsp: dsp@11800000 { compatible = "ti,da850-dsp"; reg = <0x11800000 0x40000>, @@ -42,6 +61,8 @@ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; interrupt-parent = <&intc>; interrupts = <28>; + clocks = <&psc0 15>; + resets = <&psc0 15>; status = "disabled"; }; soc@1c00000 { @@ -52,6 +73,38 @@ ranges = <0x0 0x01c00000 0x400000>; interrupt-parent = <&intc>; + psc0: clock-controller@10000 { + compatible = "ti,da850-psc0"; + reg = <0x10000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, + <&pll0_sysclk 4>, <&pll0_sysclk 6>, + <&async1_clk>; + clock-names = "pll0_sysclk1", "pll0_sysclk2", + "pll0_sysclk4", "pll0_sysclk6", + "async1"; + }; + pll0: clock-controller@11000 { + compatible = "ti,da850-pll0"; + reg = <0x11000 0x1000>; + clocks = <&ref_clk>, <&pll1_sysclk 3>; + clock-names = "clksrc", "extclksrc"; + + pll0_pllout: pllout { + #clock-cells = <0>; + }; + pll0_sysclk: sysclk { + #clock-cells = <1>; + }; + pll0_auxclk: auxclk { + #clock-cells = <0>; + }; + pll0_obsclk: obsclk { + #clock-cells = <0>; + }; + }; pmx_core: pinmux@14120 { compatible = "pinctrl-single"; reg = <0x14120 0x50>; @@ -281,8 +334,41 @@ usb_phy: usb-phy { compatible = "ti,da830-usb-phy"; #phy-cells = <1>; + clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; + clock-names = "usb0_clk48", "usb1_clk48"; status = "disabled"; }; + usb_phy_clk: usb-phy-clocks { + compatible = "ti,da830-usb-phy-clocks"; + #clock-cells = <1>; + clocks = <&psc1 1>, <&usb_refclkin>, + <&pll0_auxclk>; + clock-names = "fck", "usb_refclkin", "auxclk"; + }; + ehrpwm_tbclk: ehrpwm_tbclk { + compatible = "ti,da830-tbclksync"; + #clock-cells = <0>; + clocks = <&psc1 17>; + clock-names = "fck"; + }; + div4p5_clk: div4.5 { + compatible = "ti,da830-div4p5ena"; + #clock-cells = <0>; + clocks = <&pll0_pllout>; + clock-names = "pll0_pllout"; + }; + async1_clk: async1 { + compatible = "ti,da850-async1-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 3>, <&div4p5_clk>; + clock-names = "pll0_sysclk3", "div4.5"; + }; + async3_clk: async3 { + compatible = "ti,da850-async3-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; + clock-names = "pll0_sysclk2", "pll1_sysclk2"; + }; }; edma0: edma@0 { compatible = "ti,edma3-tpcc"; @@ -294,18 +380,21 @@ #dma-cells = <2>; ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; + power-domains = <&psc0 0>; }; edma0_tptc0: tptc@8000 { compatible = "ti,edma3-tptc"; reg = <0x8000 0x400>; interrupts = <13>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc0 1>; }; edma0_tptc1: tptc@8400 { compatible = "ti,edma3-tptc"; reg = <0x8400 0x400>; interrupts = <32>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc0 2>; }; edma1: edma@230000 { compatible = "ti,edma3-tpcc"; @@ -317,12 +406,14 @@ #dma-cells = <2>; ti,tptcs = <&edma1_tptc0 7>; + power-domains = <&psc1 0>; }; edma1_tptc0: tptc@238000 { compatible = "ti,edma3-tptc"; reg = <0x238000 0x400>; interrupts = <95>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc1 21>; }; serial0: serial@42000 { compatible = "ti,da830-uart", "ns16550a"; @@ -330,6 +421,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <25>; + clocks = <&psc0 9>; + power-domains = <&psc0 9>; status = "disabled"; }; serial1: serial@10c000 { @@ -338,6 +431,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <53>; + clocks = <&psc1 12>; + power-domains = <&psc1 12>; status = "disabled"; }; serial2: serial@10d000 { @@ -346,6 +441,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <61>; + clocks = <&psc1 13>; + power-domains = <&psc1 13>; status = "disabled"; }; rtc0: rtc@23000 { @@ -353,6 +450,8 @@ reg = <0x23000 0x1000>; interrupts = <19 19>; + clocks = <&pll0_auxclk>; + clock-names = "int-clk"; status = "disabled"; }; i2c0: i2c@22000 { @@ -361,6 +460,7 @@ interrupts = <15>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pll0_auxclk>; status = "disabled"; }; i2c1: i2c@228000 { @@ -369,11 +469,21 @@ interrupts = <51>; #address-cells = <1>; #size-cells = <0>; + clocks = <&psc1 11>; + power-domains = <&psc1 11>; status = "disabled"; }; + clocksource: timer@20000 { + compatible = "ti,da830-timer"; + reg = <0x20000 0x1000>; + interrupts = <12>, <13>; + interrupt-names = "tint12", "tint34"; + clocks = <&pll0_auxclk>; + }; wdt: wdt@21000 { compatible = "ti,davinci-wdt"; reg = <0x21000 0x1000>; + clocks = <&pll0_auxclk>; status = "disabled"; }; mmc0: mmc@40000 { @@ -384,12 +494,14 @@ interrupts = <16>; dmas = <&edma0 16 0>, <&edma0 17 0>; dma-names = "rx", "tx"; + clocks = <&psc0 5>; status = "disabled"; }; vpif: video@217000 { compatible = "ti,da850-vpif"; reg = <0x217000 0x1000>; interrupts = <92>; + power-domains = <&psc1 9>; status = "disabled"; /* VPIF capture port */ @@ -412,6 +524,7 @@ interrupts = <72>; dmas = <&edma1 28 0>, <&edma1 29 0>; dma-names = "rx", "tx"; + clocks = <&psc1 18>; status = "disabled"; }; ehrpwm0: pwm@300000 { @@ -419,6 +532,9 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; + power-domains = <&psc1 17>; status = "disabled"; }; ehrpwm1: pwm@302000 { @@ -426,6 +542,9 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; + power-domains = <&psc1 17>; status = "disabled"; }; ecap0: ecap@306000 { @@ -433,6 +552,9 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; ecap1: ecap@307000 { @@ -440,6 +562,9 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; ecap2: ecap@308000 { @@ -447,6 +572,9 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; spi0: spi@41000 { @@ -459,6 +587,8 @@ interrupts = <20>; dmas = <&edma0 14 0>, <&edma0 15 0>; dma-names = "rx", "tx"; + clocks = <&psc0 4>; + power-domains = <&psc0 4>; status = "disabled"; }; spi1: spi@30e000 { @@ -471,6 +601,8 @@ interrupts = <56>; dmas = <&edma0 18 0>, <&edma0 19 0>; dma-names = "rx", "tx"; + clocks = <&psc1 10>; + power-domains = <&psc1 10>; status = "disabled"; }; usb0: usb@200000 { @@ -482,6 +614,8 @@ dr_mode = "otg"; phys = <&usb_phy 0>; phy-names = "usb-phy"; + clocks = <&psc1 1>; + clock-ranges; status = "disabled"; #address-cells = <1>; @@ -505,6 +639,7 @@ interrupts = <58>; #dma-cells = <2>; #dma-channels = <4>; + power-domains = <&psc1 1>; status = "okay"; }; }; @@ -512,13 +647,31 @@ compatible = "ti,da850-ahci"; reg = <0x218000 0x2000>, <0x22c018 0x4>; interrupts = <67>; + clocks = <&psc1 8>, <&sata_refclk>; + clock-names = "fck", "refclk"; status = "disabled"; }; + pll1: clock-controller@21a000 { + compatible = "ti,da850-pll1"; + reg = <0x21a000 0x1000>; + clocks = <&ref_clk>; + clock-names = "clksrc"; + + pll1_sysclk: sysclk { + #clock-cells = <1>; + }; + pll1_obsclk: obsclk { + #clock-cells = <0>; + }; + }; mdio: mdio@224000 { compatible = "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x224000 0x1000>; + clocks = <&psc1 5>; + clock-names = "fck"; + power-domains = <&psc1 5>; status = "disabled"; }; eth0: ethernet@220000 { @@ -534,6 +687,8 @@ 35 36 >; + clocks = <&psc1 5>; + power-domains = <&psc1 5>; status = "disabled"; }; usb1: usb@225000 { @@ -542,6 +697,7 @@ interrupts = <59>; phys = <&usb_phy 1>; phy-names = "usb-phy"; + clocks = <&psc1 2>; status = "disabled"; }; gpio: gpio@226000 { @@ -552,6 +708,8 @@ interrupts = <42 43 44 45 46 47 48 49 50>; ti,ngpio = <144>; ti,davinci-gpio-unbanked = <0>; + clocks = <&psc1 3>; + clock-names = "gpio"; status = "disabled"; interrupt-controller; #interrupt-cells = <2>; @@ -700,6 +858,17 @@ <&pmx_core 142 147 1>, <&pmx_core 143 146 1>; }; + psc1: clock-controller@227000 { + compatible = "ti,da850-psc1"; + reg = <0x227000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, + <&async3_clk>; + clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; + assigned-clocks = <&async3_clk>; + assigned-clock-parents = <&pll1_sysclk 2>; + }; pinconf: pin-controller@22c00c { compatible = "ti,da850-pupd"; reg = <0x22c00c 0x8>; @@ -713,6 +882,7 @@ reg-names = "mpu", "dat"; interrupts = <54>; interrupt-names = "common"; + power-domains = <&psc1 7>; status = "disabled"; dmas = <&edma0 1 1>, <&edma0 0 1>; @@ -724,6 +894,9 @@ reg = <0x213000 0x1000>; interrupts = <52>; max-pixelclock = <37500>; + clocks = <&psc1 16>; + clock-names = "fck"; + power-domains = <&psc1 16>; status = "disabled"; }; }; @@ -735,6 +908,9 @@ reg = <0x68000000 0x00008000>; ranges = <0 0 0x60000000 0x08000000 1 0 0x68000000 0x00008000>; + clocks = <&psc0 3>; + clock-names = "aemif"; + clock-ranges; status = "disabled"; }; memctrl: memory-controller@b0000000 { diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 33230c8b2951..7e18147dc563 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -20,6 +20,11 @@ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; }; + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "DRA7xx-EVM"; @@ -198,8 +203,13 @@ extcon = <&extcon_usb1>; }; +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + &usb2 { dr_mode = "host"; + extcon = <&extcon_usb2>; }; &atl { diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 0894593860d6..6ed5f9156270 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -106,11 +106,6 @@ enable-active-high; }; - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - vtt_fixed: fixedregulator-vtt { compatible = "regulator-fixed"; regulator-name = "vtt_fixed"; @@ -406,10 +401,6 @@ vdd-supply = <&smps123_reg>; }; -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - &elm { status = "okay"; }; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e03495a799ce..a0ddf497e8cd 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1893,7 +1893,7 @@ }; }; - dcan1: can@481cc000 { + dcan1: can@4ae3c000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan1"; reg = <0x4ae3c000 0x2000>; @@ -1903,7 +1903,7 @@ status = "disabled"; }; - dcan2: can@481d0000 { + dcan2: can@48480000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan2"; reg = <0x48480000 0x2000>; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index b7aeaeeead3b..c471bf3277b4 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -265,3 +265,11 @@ /* Supplied by VDA_1V8_PHY */ vdda_video-supply = <&lp8732_ldo1_reg>; }; + +&extcon_usb1 { + vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; +}; + +&extcon_usb2 { + vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index df174f5c15d1..e297b923b71a 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -391,6 +391,7 @@ &usb2 { dr_mode = "host"; + extcon = <&extcon_usb2>; }; &mmc1 { diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 91e93ab588ca..8f9df09155d8 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -18,6 +18,16 @@ compatible = "arm,cortex-a15"; reg = <1>; operating-points-v2 = <&cpu0_opp_table>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ + + vbb-supply = <&abb_mpu>; }; }; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index c07f0051844d..5a46163d465f 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -436,3 +436,17 @@ phys = <&pcie1_phy>, <&pcie2_phy>; phy-names = "pcie-phy0", "pcie-phy1"; }; + +&extcon_usb1 { + vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; +}; + +&extcon_usb2 { + vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; +}; + +&m_can0 { + can-transceiver { + max-bitrate = <5000000>; + }; +}; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index 1c88c581ff18..613e4dc0ed3e 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -11,9 +11,73 @@ / { compatible = "ti,dra762", "ti,dra7"; + ocp { + target-module@42c01900 { + compatible = "ti,sysc-dra7-mcan", "ti,sysc"; + ranges = <0x0 0x42c00000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x42c01900 0x4>, + <0x42c01904 0x4>, + <0x42c01908 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | + SYSC_DRA7_MCAN_ENAWAKEUP)>; + ti,syss-mask = <1>; + clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>; + clock-names = "fck"; + + m_can0: mcan@1a00 { + compatible = "bosch,m_can"; + reg = <0x1a00 0x4000>, <0x0 0x18FC>; + reg-names = "m_can", "message_ram"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&mcan_clk>, <&l3_iclk_div>; + clock-names = "cclk", "hclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; + }; + }; + }; + }; /* MCAN interrupts are hard-wired to irqs 67, 68 */ &crossbar_mpu { ti,irqs-skip = <10 67 68 133 139 140>; }; + +&scm_conf_clocks { + dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + reg = <0x03fc>; + ti,bit-shift=<20>; + ti,latch-bit=<26>; + assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; + assigned-clock-rates = <80000000>; + }; + + dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; + reg = <0x3fc>; + ti,bit-shift = <29>; + ti,latch-bit=<26>; + assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; + assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; + }; + + mcan_clk: mcan_clk@3fc { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; + ti,bit-shift = <27>; + reg = <0x3fc>; + }; +}; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 0af44b7eadb9..1bb8e5c9d029 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the KZM9D board * * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index fec1241b858f..373ea8720769 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the EMEV2 SoC * * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 962af97c1883..27a1ee28c3bb 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -78,6 +78,22 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cmu CLK_ARM_CLK>; + clock-names = "cpu"; + #cooling-cells = <2>; + + operating-points = < + 1000000 1150000 + 900000 1112500 + 800000 1075000 + 700000 1037500 + 600000 1000000 + 500000 962500 + 400000 925000 + 300000 887500 + 200000 850000 + 100000 850000 + >; }; }; @@ -226,7 +242,7 @@ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_TMU_APBIF>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index dfe41b698745..6085e92ac2d7 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -735,7 +735,7 @@ reg = <0x100C0000 0x100>; interrupts = <2 4>; status = "disabled"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; jpeg_codec: jpeg-codec@11840000 { diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 88fb47cef9a8..b6091c27f155 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -55,6 +55,19 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x901>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <160000>; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index dc11ca1673e8..c0476c290977 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -94,6 +94,8 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; key-down { gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; @@ -138,6 +140,8 @@ compatible = "maxim,max77693"; interrupt-parent = <&gpx1>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_irq>; reg = <0x66>; regulators { @@ -184,6 +188,8 @@ compatible = "maxim,max17047"; interrupt-parent = <&gpx2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_fuel_irq>; reg = <0x36>; maxim,over-heat-temp = <700>; @@ -574,6 +580,8 @@ compatible = "maxim,max77686"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; + pinctrl-0 = <&max77686_irq>; + pinctrl-names = "default"; reg = <0x09>; #clock-cells = <1>; @@ -1007,6 +1015,31 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; + gpio_keys: gpio-keys { + samsung,pins = "gpx0-1", "gpx2-2", "gpx2-7", "gpx3-3"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + max77686_irq: max77686-irq { + samsung,pins = "gpx0-7"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + max77693_irq: max77693-irq { + samsung,pins = "gpx1-5"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + max77693_fuel_irq: max77693-fuel-irq { + samsung,pins = "gpx2-3"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + sdhci2_cd: sdhci2-cd-irq { + samsung,pins = "gpx3-4"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + hdmi_hpd: hdmi-hpd { samsung,pins = "gpx3-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; @@ -1238,7 +1271,7 @@ bus-width = <4>; cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; cd-inverted; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; pinctrl-names = "default"; vmmc-supply = <&ldo21_reg>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi deleted file mode 100644 index 489b58c619ee..000000000000 --- a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos4412 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> - */ - -#include <dt-bindings/thermal/thermal_exynos.h> - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <55>; -samsung,tmu_min_efuse_value = <40>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7b43c10c510b..51f72f0327e5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -49,21 +49,30 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu@a02 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA02>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu@a03 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA03>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 5d2f0a06fbef..67f9b4504a42 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -169,6 +169,11 @@ pwm: pwm@12dd0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x12DD0000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; samsung,pwm-outputs = <0>, <1>, <2>, <3>; #pwm-cells = <3>; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 2daf505b3d08..da163a40af15 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -84,6 +84,29 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1700000000>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <140000>; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; + #cooling-cells = <2>; /* min followed by max */ }; }; @@ -278,7 +301,7 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; sata: sata@122f0000 { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 20e789ea136f..57fc9c949e54 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -93,7 +93,7 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu1: tmu@10064000 { @@ -102,7 +102,7 @@ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu2: tmu@10068000 { @@ -111,7 +111,7 @@ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu3: tmu@1006c000 { @@ -120,7 +120,7 @@ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; mmc_0: mmc@12200000 { diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index a8e449471304..0ee6e92a3c29 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -38,6 +38,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -49,6 +50,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -60,6 +62,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -83,6 +86,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -94,6 +98,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -105,6 +110,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; diff --git a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi deleted file mode 100644 index fbc77cb58473..000000000000 --- a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos5420 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> - * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> - */ - -#include <dt-bindings/thermal/thermal_exynos.h> - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <55>; -samsung,tmu_min_efuse_value = <0>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index f4e8c5823bc2..aaff15880761 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -738,7 +738,7 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu1: tmu@10064000 { @@ -747,7 +747,7 @@ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu2: tmu@10068000 { @@ -756,7 +756,7 @@ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu3: tmu@1006c000 { @@ -765,7 +765,7 @@ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_gpu: tmu@100a0000 { @@ -774,7 +774,7 @@ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos5420-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; sysmmu_g2dr: sysmmu@10a60000 { diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index 7c130a00d1a8..e4a5857c135f 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -37,6 +37,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -48,6 +49,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -59,6 +61,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; @@ -69,8 +72,8 @@ cpu4: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; - clocks = <&clock CLK_ARM_CLK>; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -82,6 +85,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -93,6 +97,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; @@ -104,6 +109,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts new file mode 100644 index 000000000000..ebefb7297379 --- /dev/null +++ b/arch/arm/boot/dts/gemini-sl93512r.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the Storm Semiconductor SL93512R_BRD + * Gemini reference design, also initially called + * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor. + * The series were later acquired by Cortina Systems. + */ + +/dts-v1/; + +#include "gemini.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD"; + compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB Samsung K4H511638B */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait"; + stdout-path = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-wps { + debounce-interval = <50>; + wakeup-source; + linux,code = <KEY_WPS_BUTTON>; + label = "WPS"; + /* Conflict with NAND flash */ + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + + button-setup { + debounce-interval = <50>; + wakeup-source; + linux,code = <KEY_SETUP>; + label = "factory reset"; + /* Conflict with NAND flash */ + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + led-green-harddisk { + label = "sq201:green:harddisk"; + /* Conflict with LCD (no problem) */ + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "disk-activity"; + }; + led-green-wireless { + label = "sq201:green:wireless"; + /* Conflict with NAND flash CE0 (no problem) */ + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Marvell 88E1111 ethernet transciever */ + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + /* Check pin collisions */ + gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + switch@0 { + compatible = "vitesse,vsc7385"; + reg = <0>; + /* Specified for 2.5 MHz or below */ + spi-max-frequency = <2500000>; + gpio-controller; + #gpio-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + port@1 { + reg = <1>; + label = "lan2"; + }; + port@2 { + reg = <2>; + label = "lan3"; + }; + port@3 { + reg = <3>; + label = "lan4"; + }; + vsc: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + + soc { + flash@30000000 { + status = "okay"; + /* 16MB of flash */ + reg = <0x30000000 0x01000000>; + + partition@0 { + label = "BOOT"; + reg = <0x00000000 0x00020000>; + read-only; + }; + partition@120000 { + label = "Kern"; + reg = <0x00020000 0x00300000>; + }; + partition@320000 { + label = "Ramdisk"; + reg = <0x00320000 0x00600000>; + }; + partition@920000 { + label = "Application"; + reg = <0x00920000 0x00600000>; + }; + partition@f20000 { + label = "VCTL"; + reg = <0x00f20000 0x00020000>; + read-only; + }; + partition@f40000 { + label = "CurConf"; + reg = <0x00f40000 0x000a0000>; + read-only; + }; + partition@fe0000 { + label = "FIS directory"; + reg = <0x00fe0000 0x00020000>; + read-only; + }; + }; + + syscon: syscon@40000000 { + pinctrl { + /* + * gpio0egrp cover line 16 used by HD LED + * gpio0fgrp cover line 17, 18 used by wireless LED and reset button + * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY + * gpio0kgrp cover line 31 used by USB LED + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0egrp", + "gpio0fgrp", + "gpio0hgrp"; + }; + }; + /* + * gpio1dgrp cover lines used by SPI for + * the Vitesse chip (28-31) + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + /* Control pad skew comes from sl_switch.c in the vendor code */ + conf0 { + pins = "P10 GMAC1 TXC"; + skew-delay = <5>; + }; + conf1 { + pins = "V11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf2 { + pins = "T11 GMAC1 RXC"; + skew-delay = <8>; + }; + conf3 { + pins = "U11 GMAC1 RXDV"; + skew-delay = <7>; + }; + conf4 { + pins = "V7 GMAC0 TXC"; + skew-delay = <10>; + }; + conf5 { + pins = "P8 GMAC0 TXEN"; + skew-delay = <7>; /* 5 at another place? */ + }; + conf6 { + pins = "T8 GMAC0 RXC"; + skew-delay = <15>; + }; + conf7 { + pins = "R8 GMAC0 RXDV"; + skew-delay = <0>; + }; + conf8 { + /* The data lines all have default skew */ + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Appears in sl351x_gmac.c in the vendor code */ + conf9 { + pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; + skew-delay = <5>; + }; + }; + }; + }; + + /* Both interfaces brought out on SATA connectors */ + sata: sata@46000000 { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; + }; + + gpio0: gpio@4d000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; + }; + + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + + pci@50000000 { + status = "okay"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4800 0 0 2 &pci_intc 1>, + <0x4800 0 0 3 &pci_intc 2>, + <0x4800 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ + <0x5000 0 0 2 &pci_intc 2>, + <0x5000 0 0 3 &pci_intc 3>, + <0x5000 0 0 4 &pci_intc 0>, + <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ + <0x5800 0 0 2 &pci_intc 3>, + <0x5800 0 0 3 &pci_intc 0>, + <0x5800 0 0 4 &pci_intc 1>, + <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ + <0x6000 0 0 2 &pci_intc 0>, + <0x6000 0 0 3 &pci_intc 1>, + <0x6000 0 0 4 &pci_intc 2>; + }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + ata@63000000 { + status = "okay"; + }; + + ata@63400000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index e5cf9d1a98cd..3787cf3763c4 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -55,6 +55,75 @@ }; }; + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + /* Uses MDC and MDIO */ + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* This is a Marvell 88E1111 ethernet transciever */ + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + /* Check pin collisions */ + gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + switch@0 { + compatible = "vitesse,vsc7395"; + reg = <0>; + /* Specified for 2.5 MHz or below */ + spi-max-frequency = <2500000>; + gpio-controller; + #gpio-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + port@1 { + reg = <1>; + label = "lan2"; + }; + port@2 { + reg = <2>; + label = "lan3"; + }; + port@3 { + reg = <3>; + label = "lan4"; + }; + vsc: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + soc { flash@30000000 { /* @@ -108,6 +177,7 @@ /* * gpio0fgrp cover line 18 used by reset button * gpio0ggrp cover line 20 used by info LED + * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY * gpio0kgrp cover line 31 used by USB LED */ gpio0_default_pins: pinctrl-gpio0 { @@ -115,9 +185,76 @@ function = "gpio0"; groups = "gpio0fgrp", "gpio0ggrp", + "gpio0hgrp", "gpio0kgrp"; }; }; + /* + * gpio0dgrp cover lines used by the SPI + * to the Vitesse G5x chip. + */ + gpio1_default_pins: pinctrl-gpio1 { + mux { + function = "gpio1"; + groups = "gpio1dgrp"; + }; + }; + pinctrl-gmii { + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + /* Settings come from memory dump in PLATO */ + conf0 { + pins = "V8 GMAC0 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "Y7 GMAC0 RXC"; + skew-delay = <15>; + }; + conf2 { + pins = "T8 GMAC0 TXEN"; + skew-delay = <7>; + }; + conf3 { + pins = "U8 GMAC0 TXC"; + skew-delay = <10>; + }; + conf4 { + pins = "T10 GMAC1 RXDV"; + skew-delay = <7>; + }; + conf5 { + pins = "Y11 GMAC1 RXC"; + skew-delay = <8>; + }; + conf6 { + pins = "W11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf7 { + pins = "V11 GMAC1 TXC"; + skew-delay = <5>; + }; + conf8 { + /* The data lines all have default skew */ + pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; + skew-delay = <7>; + }; + /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */ + conf9 { + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + drive-strength = <16>; + }; + }; }; }; @@ -132,6 +269,11 @@ pinctrl-0 = <&gpio0_default_pins>; }; + gpio1: gpio@4e000000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_default_pins>; + }; + pci@50000000 { status = "okay"; interrupt-map-mask = <0xf800 0 0 7>; @@ -154,6 +296,23 @@ <0x6000 0 0 4 &pci_intc 2>; }; + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + ata@63000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi new file mode 100644 index 000000000000..e31a9e3c18a2 --- /dev/null +++ b/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the GR-Peach audiocamera shield expansion board + * + * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org> + */ + +#include "r7s72100.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> + +/ { + /* On-board camera clock. */ + camera_clk: camera_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&pinctrl { + i2c1_pins: i2c1 { + /* P1_2 as SCL; P1_3 as SDA */ + pinmux = <RZA1_PINMUX(1, 2, 1)>, <RZA1_PINMUX(1, 3, 1)>; + }; + + vio_pins: vio { + /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ + pinmux = <RZA1_PINMUX(1, 0, 5)>, /* VIO_VD */ + <RZA1_PINMUX(1, 1, 5)>, /* VIO_HD */ + <RZA1_PINMUX(2, 0, 7)>, /* VIO_D0 */ + <RZA1_PINMUX(2, 1, 7)>, /* VIO_D1 */ + <RZA1_PINMUX(2, 2, 7)>, /* VIO_D2 */ + <RZA1_PINMUX(2, 3, 7)>, /* VIO_D3 */ + <RZA1_PINMUX(2, 4, 7)>, /* VIO_D4 */ + <RZA1_PINMUX(2, 5, 7)>, /* VIO_D5 */ + <RZA1_PINMUX(2, 6, 7)>, /* VIO_D6 */ + <RZA1_PINMUX(2, 7, 7)>, /* VIO_D7 */ + <RZA1_PINMUX(10, 0, 6)>; /* VIO_CLK */ + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + camera@48 { + compatible = "aptina,mt9v111"; + reg = <0x48>; + + clocks = <&camera_clk>; + + port { + mt9v111_out: endpoint { + remote-endpoint = <&ceu_in>; + }; + }; + }; +}; + +&ceu { + pinctrl-names = "default"; + pinctrl-0 = <&vio_pins>; + + status = "okay"; + + port { + ceu_in: endpoint { + hsync-active = <1>; + vsync-active = <1>; + bus-width = <8>; + pclk-sample = <1>; + remote-endpoint = <&mt9v111_out>; + }; + }; +}; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index ed14aeac0566..50278715de76 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -56,6 +56,16 @@ next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; }; cpu@902 { @@ -65,6 +75,16 @@ next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; }; cpu@903 { @@ -74,6 +94,16 @@ next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; }; }; diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/imx31-lite.dts new file mode 100644 index 000000000000..db52ddccabc3 --- /dev/null +++ b/arch/arm/boot/dts/imx31-lite.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com> + +/dts-v1/; + +#include "imx31.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "LogicPD i.MX31 Lite"; + compatible = "logicpd,imx31-lite", "fsl,imx31"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + reg = <0x80000000 0x8000000>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ata { + status = "okay"; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1a { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw1b { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2b { /* NVCC10 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + violo { /* NVCC1 and NVCC7 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi { /* VIOHI */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio { /* VAUDIO */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vcam { /* NVCC4 */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc2 { /* NVCC3 */ + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&uart1 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart2 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart3 { + uart-has-rtscts; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x0 0x200000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; + }; + + ethernet@4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + reg = <4 0x0 0x100>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; + }; +}; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 4642c8169a65..ca1419ca303c 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ // +// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com> // Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> / { @@ -15,11 +16,20 @@ memory { device_type = "memory"; }; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; }; cpus { @@ -47,6 +57,14 @@ interrupt-parent = <&avic>; ranges; + iram: iram@1fffc000 { + compatible = "mmio-sram"; + reg = <0x1fffc000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1fffc000 0x4000>; + }; + aips@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -54,6 +72,34 @@ reg = <0x43f00000 0x100000>; ranges; + i2c1: i2c@43f80000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + interrupts = <10>; + clocks = <&clks 33>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + interrupts = <3>; + clocks = <&clks 35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ata: ata@43f8c000 { + compatible = "fsl,imx31-pata", "fsl,imx27-pata"; + reg = <0x43f8c000 0x4000>; + interrupts = <15>; + clocks = <&clks 26>; + status = "disabled"; + }; + uart1: serial@43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; @@ -72,6 +118,29 @@ status = "disabled"; }; + i2c2: i2c@43f98000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + interrupts = <4>; + clocks = <&clks 34>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@43fa4000 { + compatible = "fsl,imx31-cspi"; + reg = <0x43fa4000 0x4000>; + interrupts = <14>; + clocks = <&clks 10>, <&clks 53>; + clock-names = "ipg", "per"; + dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kpp: kpp@43fa8000 { compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; @@ -106,6 +175,28 @@ reg = <0x50000000 0x100000>; ranges; + sdhci1: sdhci@50004000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50004000 0x4000>; + interrupts = <9>; + clocks = <&clks 10>, <&clks 20>; + clock-names = "ipg", "per"; + dmas = <&sdma 20 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci@50008000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50008000 0x4000>; + interrupts = <8>; + clocks = <&clks 10>, <&clks 21>; + clock-names = "ipg", "per"; + dmas = <&sdma 21 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + uart3: serial@5000c000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; @@ -115,6 +206,19 @@ status = "disabled"; }; + spi2: cspi@50010000 { + compatible = "fsl,imx31-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 10>, <&clks 54>; + clock-names = "ipg", "per"; + dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + iim: iim@5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; @@ -137,6 +241,19 @@ #clock-cells = <1>; }; + spi3: cspi@53f84000 { + compatible = "fsl,imx31-cspi"; + reg = <0x53f84000 0x4000>; + interrupts = <17>; + clocks = <&clks 10>, <&clks 28>; + clock-names = "ipg", "per"; + dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpt: timer@53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; @@ -144,6 +261,112 @@ clocks = <&clks 10>, <&clks 22>; clock-names = "ipg", "per"; }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rng@53fb0000 { + compatible = "fsl,imx31-rnga"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&clks 29>; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: sdma@53fd4000 { + compatible = "fsl,imx31-sdma"; + reg = <0x53fd4000 0x4000>; + interrupts = <34>; + clocks = <&clks 10>, <&clks 27>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; + }; + + rtc: rtc@53fd8000 { + compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; + reg = <0x53fd8000 0x4000>; + interrupts = <25>; + clocks = <&clks 2>, <&clks 40>; + clock-names = "ref", "ipg"; + }; + + wdog: wdog@53fdc000 { + compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 41>; + }; + + pwm: pwm@53fe0000 { + compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; + reg = <0x53fe0000 0x4000>; + interrupts = <26>; + clocks = <&clks 10>, <&clks 42>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + emi@b8000000 { /* External Memory Interface */ + compatible = "simple-bus"; + reg = <0xb8000000 0x5000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + nfc: nand@b8000000 { + compatible = "fsl,imx31-nand", "fsl,imx27-nand"; + reg = <0xb8000000 0x1000>; + interrupts = <33>; + clocks = <&clks 9>; + dmas = <&sdma 30 17 0>; + dma-names = "rx-tx"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + weim: weim@b8002000 { + compatible = "fsl,imx31-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + clocks = <&clks 56>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xa0000000 0x08000000 + 1 0 0xa8000000 0x08000000 + 2 0 0xb0000000 0x02000000 + 3 0 0xb2000000 0x02000000 + 4 0 0xb4000000 0x02000000 + 5 0 0xb6000000 0x02000000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts index f0622ec4ba9c..682a99783ee6 100644 --- a/arch/arm/boot/dts/imx50-evk.dts +++ b/arch/arm/boot/dts/imx50-evk.dts @@ -98,14 +98,6 @@ status = "okay"; }; -&usbh2 { - status = "okay"; -}; - -&usbh3 { - status = "okay"; -}; - &usbotg { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/imx50-pinfunc.h index 97e6e7f4ebdd..43863347362e 100644 --- a/arch/arm/boot/dts/imx50-pinfunc.h +++ b/arch/arm/boot/dts/imx50-pinfunc.h @@ -34,7 +34,7 @@ #define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 #define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 #define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL2__KPP_COL_1 0x030 0x2dc 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL2__KPP_COL_2 0x030 0x2dc 0x000 0x0 0x0 #define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 #define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 #define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 @@ -44,7 +44,7 @@ #define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 #define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 #define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL3__KPP_COL_2 0x038 0x2e4 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL3__KPP_COL_3 0x038 0x2e4 0x000 0x0 0x0 #define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 #define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 #define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a9b712db9f6c..7fae2ffb76fe 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -209,24 +209,6 @@ status = "disabled"; }; - usbh2: usb@53f80400 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@53f80600 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - gpio1: gpio@53f84000 { compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; reg = <0x53f84000 0x4000>; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index b8ca73d3d379..ba60b0cb3cc1 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -170,20 +170,15 @@ mux-ext-port = <3>; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbh1phy: usbh1phy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clk_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1reg>; + clocks = <&clk_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; }; }; @@ -401,6 +396,10 @@ status = "okay"; }; +&pmu { + secure-reg-access; +}; + &ssi2 { status = "okay"; }; @@ -429,7 +428,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; vbus-supply = <®_hub_reset>; - fsl,usbphy = <&usbh1phy>; + fsl,usbphy = <&usbphy1>; phy_type = "ulpi"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index b3d952f37cdc..e9e819f2b0b7 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -83,19 +83,12 @@ fsl,mux-ext-port = <3>; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbh1phy: usbh1phy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + #phy-cells = <0>; }; }; @@ -275,7 +268,7 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; - fsl,usbphy = <&usbh1phy>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; phy_type = "ulpi"; status = "okay"; diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 8a878687197b..469cce2c0357 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -476,6 +476,17 @@ status = "okay"; }; +&gpio1 { + unused-sd3-wp-gpio { + /* + * See pinctrl_esdhc1 below for more details on this + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; @@ -542,7 +553,7 @@ rmi4-f11@11 { reg = <0x11>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; @@ -554,6 +565,10 @@ remote-endpoint = <&display_in>; }; +&pmu { + secure-reg-access; +}; + &ssi2 { status = "okay"; }; @@ -578,10 +593,47 @@ rave-sp { compatible = "zii,rave-sp-rdu1"; current-speed = <38400>; + #address-cells = <1>; + #size-cells = <1>; watchdog { compatible = "zii,rave-sp-watchdog"; }; + + backlight { + compatible = "zii,rave-sp-backlight"; + }; + + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "dds-eeprom"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + + eeprom@ae { + compatible = "zii,rave-sp-eeprom"; + reg = <0xae 0x200>; + zii,eeprom-name = "switch-eeprom"; + /* + * Not all RDU1s have this functionality, so we + * rely on the bootloader to enable this + */ + status = "disabled"; + }; }; }; @@ -620,6 +672,10 @@ status = "okay"; }; +&wdog1 { + status = "disabled"; +}; + &iomuxc { pinctrl_ampgpio: ampgpiogrp { fsl,pins = < @@ -660,6 +716,23 @@ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + /* + * GPIO1_1 is not directly used by eSDHC1 in + * any capacity, but earlier versions of RDU1 + * used that pin as WP GPIO for eSDHC3 and + * because of that that pad has an external + * pull-up resistor. This is problematic + * because out of reset the pad is configured + * as ALT0 which serves as SD1_WP, which, when + * pulled high by and external pull-up, will + * inhibit execution of any write request to + * attached eMMC device. + * + * To avoid this problem we configure the pad + * to ALT1/GPIO and avoid driving SD1_WP + * signal high. + */ + MX51_PAD_GPIO1_1__GPIO1_1 0x0000 >; }; diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts new file mode 100644 index 000000000000..26cf08549df4 --- /dev/null +++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx51.dtsi" + +/ { + model = "ZII SCU2 Mezz Board"; + compatible = "zii,imx51-scu2-mezz", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + reg = <0x90000000 0>; + }; + + aliases { + mdio-gpio0 = &mdio_gpio; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mmc_reset>; + gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; + startup-delay-us = <150000>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + mdio_gpio: mdio-gpio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swmdio>; + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */ + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port4"; + }; + + port@1 { + reg = <1>; + label = "port5"; + }; + + port@2 { + reg = <2>; + label = "port6"; + }; + + port@3 { + reg = <3>; + label = "port7"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "mezz2esb"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled3: led3@3 { + reg = <3>; + label = "system:red:power"; + linux,default-trigger = "default-on"; + }; + + sysled4: led4@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <1>; + spi-max-frequency = <25000000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc4>; + bus-width = <4>; + no-1-8-v; + no-sdio; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-supply = <&vgen3_reg>; + phy-handle = <ðphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-mezz"; + current-speed = <57600>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog-legacy"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb2_reg>; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 + MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 + MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 + MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 + >; + }; + + pinctrl_esdhc4: esdhc4grp { + fsl,pins = < + MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 + MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 + MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 + MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 + MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 + MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 + MX51_PAD_NANDF_D0__GPIO4_8 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_DI_GP3__FEC_TX_ER 0x2004 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 + MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 + MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 + MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 + MX51_PAD_EIM_A20__GPIO2_14 0x0085 + MX51_PAD_EIM_A21__GPIO2_15 0x00e5 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x85 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 + >; + }; + + pinctrl_swmdio: swmdiogrp { + fsl,pins = < + MX51_PAD_EIM_D22__GPIO2_6 0x100 + MX51_PAD_EIM_D23__GPIO2_7 0x100 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usb_mmc_reset: usbmmcgrp { + fsl,pins = < + MX51_PAD_CSI1_D9__GPIO3_13 0x85 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts new file mode 100644 index 000000000000..e6ebac8f43e4 --- /dev/null +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx51.dtsi" + +/ { + model = "ZII SCU3 ESB board"; + compatible = "zii,imx51-scu3-esb", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + reg = <0x90000000 0>; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mmc_reset>; + gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; + startup-delay-us = <150000>; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled3: led3@3 { + reg = <3>; + label = "system:red:power"; + linux,default-trigger = "default-on"; + }; + + sysled4: led4@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc4>; + bus-width = <4>; + no-1-8-v; + no-sdio; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port1"; + }; + + port@1 { + reg = <1>; + label = "port2"; + }; + + port@2 { + reg = <2>; + label = "port3"; + }; + + port@3 { + reg = <3>; + label = "scu2scu"; + }; + + port@4 { + reg = <4>; + label = "esb2host"; + }; + + port@5 { + reg = <5>; + label = "esb2mezz"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + phy-mode = "mii"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&ipu { + status = "disabled"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-esb"; + current-speed = <57600>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog-legacy"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb2_reg>; +}; + +&wdog1 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 + MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 + MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 + MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 + >; + }; + + pinctrl_esdhc4: esdhc4grp { + fsl,pins = < + MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 + MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 + MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 + MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 + MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 + MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 + MX51_PAD_NANDF_D0__GPIO4_8 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 + + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 + MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 + MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 + MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x85 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 + >; + }; + + pinctrl_switch: switchgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5 + MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usb_mmc_reset: usbmmcgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index fe01b890c715..5c4ba91e43ba 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -93,18 +93,17 @@ }; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; + pmu: pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; + usbphy0: usbphy0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; }; display-subsystem { @@ -250,6 +249,11 @@ }; }; + aipstz1: bridge@73f00000 { + compatible = "fsl,imx51-aipstz"; + reg = <0x73f00000 0x60>; + }; + usbotg: usb@73f80000 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80000 0x0200>; @@ -435,6 +439,11 @@ reg = <0x80000000 0x10000000>; ranges; + aipstz2: bridge@83f00000 { + compatible = "fsl,imx51-aipstz"; + reg = <0x83f00000 0x60>; + }; + iim: iim@83f98000 { compatible = "fsl,imx51-iim", "fsl,imx27-iim"; reg = <0x83f98000 0x4000>; @@ -442,6 +451,11 @@ clocks = <&clks IMX5_CLK_IIM_GATE>; }; + tigerp: tigerp@83fa0000 { + compatible = "fsl,imx51-tigerp"; + reg = <0x83fa0000 0x28>; + }; + owire: owire@83fa4000 { compatible = "fsl,imx51-owire", "fsl,imx21-owire"; reg = <0x83fa4000 0x4000>; @@ -528,6 +542,11 @@ status = "disabled"; }; + m4if: m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; + }; + weim: weim@83fda000 { #address-cells = <2>; #size-cells = <1>; @@ -588,6 +607,26 @@ clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; + + vpu@83ff4000 { + compatible = "fsl,imx51-vpu", "cnm,codahx4"; + reg = <0x83ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, + <&clks IMX5_CLK_VPU_GATE>; + clock-names = "per", "ahb"; + resets = <&src 1>; + iram = <&iram>; + }; + + sahara: crypto@83ff8000 { + compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; + reg = <0x83ff8000 0x4000>; + interrupts = <19 20>; + clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, + <&clks IMX5_CLK_SAHARA_IPG_GATE>; + clock-names = "ipg", "ahb"; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx53-kp-ddc.dts b/arch/arm/boot/dts/imx53-kp-ddc.dts new file mode 100644 index 000000000000..0e7f071fd10e --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp-ddc.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-kp.dtsi" + +/ { + model = "K+P imx53 DDC"; + compatible = "kiebackpeter,imx53-ddc", "fsl,imx53"; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + power-supply = <®_backlight>; + brightness-levels = <0 24 28 32 36 + 40 44 48 52 56 + 60 64 68 72 76 + 80 84 88 92 96 100>; + default-brightness-level = <20>; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp>; + + port@0 { + reg = <0>; + + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + lcd_panel: lcd-panel { + compatible = "koe,tx14d24vm1bpa"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight-supply"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + regulator-always-on; + }; +}; + +&fec { + status = "okay"; +}; + +&i2c3 { + adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + + gpio-expander2@21 { + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&iomuxc { + imx53-kp-ddc { + pinctrl_disp: dispgrp { + fsl,pins = < + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 + MX53_PAD_GPIO_1__PWM2_PWMO 0x4 + >; + }; + }; +}; + +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + +&pmic { + fsl,mc13xxx-uses-touch; +}; diff --git a/arch/arm/boot/dts/imx53-kp-hsc.dts b/arch/arm/boot/dts/imx53-kp-hsc.dts new file mode 100644 index 000000000000..6e3d71baac0f --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp-hsc.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-kp.dtsi" + +/ { + model = "K+P imx53 HSC"; + compatible = "kiebackpeter,imx53-hsc", "fsl,imx53"; +}; + +&fec { + status = "okay"; + + fixed-link { /* RMII fixed link to LAN9303 */ + speed = <100>; + full-duplex; + }; +}; + +&i2c3 { + switch: switch@a { + compatible = "smsc,lan9303-i2c"; + reg = <0xa>; + reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + reset-duration = <400>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { /* RMII fixed link to master */ + reg = <0>; + label = "cpu"; + ethernet = <&fec>; + }; + + port@1 { /* external port 1 */ + reg = <1>; + label = "lan1"; + }; + + port@2 { /* external port 2 */ + reg = <2>; + label = "lan2"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/imx53-kp.dtsi new file mode 100644 index 000000000000..8b25416a5303 --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-tqma53.dtsi" +#include <dt-bindings/input/input.h> + +/ { + buzzer { + compatible = "pwm-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buzzer>; + pwms = <&pwm1 0 500000>; + }; + + gpio-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + + button-kalt { + label = "Kaltstart"; + linux,code = <KEY_F6>; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + }; + + button-pwr { + label = "PowerFailInterrupt"; + linux,code = <KEY_F7>; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-bus { + label = "bus"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-error { + label = "error"; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-flash { + label = "flash"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + gpio-expander1@22 { + compatible = "nxp,pcf8574"; + reg = <0x22>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kp_common>; + + imx53-kp-common { + pinctrl_buzzer: buzzergrp { + fsl,pins = < + MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 + >; + }; + + pinctrl_gpiobuttons: gpiobuttonsgrp { + fsl,pins = < + MX53_PAD_EIM_RW__GPIO2_26 0x1e4 + MX53_PAD_EIM_D22__GPIO3_22 0x1e4 + >; + }; + + pinctrl_kp_common: kpcommongrp { + fsl,pins = < + MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 + MX53_PAD_GPIO_19__GPIO4_5 0x1e4 + MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 + MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 + MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 + MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 + MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 + MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 + MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 + MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 + >; + }; + + pinctrl_leds: ledgrp { + fsl,pins = < + MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 + MX53_PAD_EIM_D28__GPIO3_28 0x1d4 + MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 + >; + }; + }; +}; + +&pinctrl_uart1 { + fsl,pins = < + MX53_PAD_EIM_D23__GPIO3_23 0x1e4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 + MX53_PAD_EIM_D19__GPIO3_19 0x1e4 + MX53_PAD_EIM_D20__GPIO3_20 0x1e4 + >; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy0 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 3aa6f693fa9f..cdb90bee7b4a 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -140,6 +140,25 @@ regulator-always-on; }; + reg_3v3: regulator-3v3 { + /* TPS54320 */ + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3_lcd: regulator-3v3-lcd { + /* MIC2009 */ + compatible = "regulator-fixed"; + regulator-name = "LCD_3V3"; + vin-supply = <®_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + pwm_bl: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 50000>; @@ -154,6 +173,7 @@ 234 237 239 242 244 247 249 252 255>; default-brightness-level = <0>; enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3_lcd>; }; leds { @@ -198,8 +218,9 @@ }; }; - usbphy2: usbphy2 { + usbphy2: usbphy-2 { compatible = "usb-nop-xceiv"; + vcc-supply = <®_3v3>; reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; clock-names = "main_clk"; clock-frequency = <24000000>; @@ -208,8 +229,9 @@ assigned-clock-parents = <&clks IMX5_CLK_OSC>; }; - usbphy3: usbphy3 { + usbphy3: usbphy-3 { compatible = "usb-nop-xceiv"; + vcc-supply = <®_3v3>; reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; clock-names = "main_clk"; @@ -221,6 +243,7 @@ panel-lvds0 { compatible = "nvd,9128"; + power-supply = <®_3v3_lcd>; port { panel_in_lvds0: endpoint { @@ -230,6 +253,14 @@ }; }; +&usbphy0 { + vcc-supply = <®_3v3>; +}; + +&usbphy1 { + vcc-supply = <®_3v3>; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; @@ -414,6 +445,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; + phy-supply = <®_3v3>; phy-mode = "rmii"; phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; status = "okay"; @@ -562,6 +594,10 @@ }; }; +&pmu { + secure-reg-access; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index ef7658a78836..7423d462d1e4 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -153,7 +153,6 @@ imx53-qsb { pinctrl_hog: hoggrp { fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 MX53_PAD_GPIO_8__GPIO1_8 0x80000000 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 @@ -180,6 +179,12 @@ >; }; + pinctrl_codec: codecgrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 @@ -310,6 +315,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; #sound-dai-cells = <0>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 1a7a7bb3df45..6386185ae234 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -113,7 +113,7 @@ }; }; - pmu { + pmu: pmu { compatible = "arm,cortex-a8-pmu"; interrupt-parent = <&tzic>; interrupts = <77>; @@ -672,6 +672,11 @@ status = "disabled"; }; + tigerp: tigerp@63fa0000 { + compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; + reg = <0x63fa0000 0x28>; + }; + owire: owire@63fa4000 { compatible = "fsl,imx53-owire", "fsl,imx21-owire"; reg = <0x63fa4000 0x4000>; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 3dee3af1a4c1..9de45a717356 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -221,9 +221,6 @@ /* Colibri MMC */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc_cd>; - cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/imx6dl-icore-mipi.dts new file mode 100644 index 000000000000..bf53f0552aa1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-icore-mipi.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Engicam S.r.l. + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6dl"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index 6b2d29138bed..df8607fe4142 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -6,11 +6,156 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "imx6dl.dtsi" / { model = "BTicino i.MX6DL Mamoj board"; compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ + brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; + default-brightness-level = <7>; + }; + + display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "rocktech,rk070er9427"; + backlight = <&backlight_lcd>; + power-supply = <®_lcd_lr>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_lcd_3v3: regulator-lcd-dvdd { + compatible = "regulator-fixed"; + regulator-name = "lcd-dvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 1 0>; + enable-active-high; + startup-delay-us = <21000>; + }; + + reg_lcd_power: regulator-lcd-power { + compatible = "regulator-fixed"; + regulator-name = "lcd-enable"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 6 0>; + enable-active-high; + vin-supply = <®_lcd_3v3>; + }; + + reg_lcd_vgl: regulator-lcd-vgl { + compatible = "regulator-fixed"; + regulator-name = "lcd-vgl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_power>; + }; + + reg_lcd_vgh: regulator-lcd-vgh { + compatible = "regulator-fixed"; + regulator-name = "lcd-vgh"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_avdd>; + }; + + reg_lcd_vcom: regulator-lcd-vcom { + compatible = "regulator-fixed"; + regulator-name = "lcd-vcom"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <11000>; + enable-active-high; + vin-supply = <®_lcd_vgh>; + }; + + reg_lcd_lr: regulator-lcd-lr { + compatible = "regulator-fixed"; + regulator-name = "lcd-lr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_lcd_vcom>; + }; + + reg_lcd_avdd: regulator-lcd-avdd { + compatible = "regulator-fixed"; + regulator-name = "lcd-avdd"; + regulator-min-microvolt = <10280000>; + regulator-max-microvolt = <10280000>; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_vgl>; + }; + + reg_usb_host: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbhost-vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhost>; + regulator-min-microvolt = <50000000>; + regulator-max-microvolt = <50000000>; + gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wl18xx_vmmc: regulator-wl18xx-vmcc { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; }; &fec { @@ -147,12 +292,56 @@ }; }; +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; +&usbh1 { + vbus-supply = <®_usb_host>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; + &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -200,6 +389,59 @@ >; }; + pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */ + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */ + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 @@ -207,6 +449,23 @@ >; }; + pinctrl_usbhost: usbhostgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -221,4 +480,10 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6dl-nit6xlite.dts b/arch/arm/boot/dts/imx6dl-nit6xlite.dts index 30ce2c0cec2b..61fa30991d67 100644 --- a/arch/arm/boot/dts/imx6dl-nit6xlite.dts +++ b/arch/arm/boot/dts/imx6dl-nit6xlite.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts index ec53d7a09572..ef58d3b0ea0d 100644 --- a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts +++ b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 2e98c92adff7..dd3226fe5ecd 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -19,36 +19,8 @@ reg = <0x10000000 0x40000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; + chosen { + stdout-path = "serial1:115200n8"; }; leds { @@ -82,6 +54,28 @@ mux-int-port = <1>; mux-ext-port = <3>; }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; }; &audmux { diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index b384913c34dd..f0607eb41df4 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -33,6 +33,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, @@ -50,6 +51,29 @@ device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index aa0e631f3c0a..707ac9a46115 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -62,6 +62,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -109,6 +113,7 @@ */ compatible = "edt,et057090dhu"; backlight = <&backlight>; + power-supply = <®_3v3_sw>; port { lcd_panel_in: endpoint { @@ -127,19 +132,30 @@ enable-active-high; status = "okay"; }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &backlight { brightness-levels = <0 127 191 223 239 247 251 255>; default-brightness-level = <1>; + power-supply = <®_3v3_sw>; status = "okay"; }; &can1 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; &can2 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index e8dccf552122..4e1c8feaef82 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -63,6 +63,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 6831dfd24cc1..469e3d0e2827 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -62,6 +62,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 65ef4cacbc71..18ae4f3be6e3 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -187,6 +187,72 @@ >; }; +&cpu1 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu2 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu3 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + &ecspi1 { cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-icore-mipi.dts b/arch/arm/boot/dts/imx6q-icore-mipi.dts index acd3d33476d4..95b2efda17b4 100644 --- a/arch/arm/boot/dts/imx6q-icore-mipi.dts +++ b/arch/arm/boot/dts/imx6q-icore-mipi.dts @@ -20,6 +20,14 @@ status = "okay"; }; +&mipi_csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + &usdhc3 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts index 2a3c44f98eed..03bec0c53063 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts index c5d59baa1a07..eb4eecb6ed22 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts index df8ff397a914..435445a34ad0 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6x.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6x.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts index f2368a073d07..c54362fcc508 100644 --- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts @@ -177,6 +177,7 @@ touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; + wakeup-source; }; rtc@68 { diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 77f8f030dd07..0193ee6fe964 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -38,6 +38,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, @@ -50,25 +51,106 @@ soc-supply = <®_soc>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 64fbee61de44..05f07ea3e8c8 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -61,25 +61,17 @@ status = "disabled"; }; - reg_1p8v: regulator-1p8v { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_3p3v: regulator-3p3v { + reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + regulator-name = "+V3.3_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -297,7 +289,7 @@ vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -322,8 +314,9 @@ compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; }; /* STMPE811 touch screen controller */ @@ -455,9 +448,10 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; - voltage-ranges = <3300 3300>; + disable-wp; + no-1-8-v; status = "disabled"; }; @@ -465,9 +459,10 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <4>; - voltage-ranges = <3300 3300>; + disable-wp; + no-1-8-v; status = "disabled"; }; @@ -475,9 +470,9 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; non-removable; status = "okay"; }; @@ -952,38 +947,4 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 >; }; - - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 76035db96f67..87e15e7cb32b 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -56,25 +56,17 @@ status = "disabled"; }; - reg_1p8v: regulator-1p8v { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_3p3v: regulator-3p3v { + reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + regulator-name = "+V3.3_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -227,7 +219,7 @@ vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -252,8 +244,9 @@ compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; lrclk-strength = <3>; }; @@ -385,10 +378,12 @@ /* Colibri MMC */ &usdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vqmmc-supply = <®_3p3v>; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + disable-wp; + vqmmc-supply = <®_module_3v3>; bus-width = <4>; - voltage-ranges = <3300 3300>; + no-1-8-v; status = "disabled"; }; @@ -396,9 +391,9 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; non-removable; status = "okay"; }; @@ -479,8 +474,7 @@ pinctrl_gpio_keys: gpiokeys { fsl,pins = < - /* Power button */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 >; }; @@ -567,7 +561,7 @@ pinctrl_mmc_cd: gpiommccd { fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 >; }; @@ -698,40 +692,6 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; - pinctrl_weim_cs0: weimcs0grp { fsl,pins = < /* nEXT_CS0 */ diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index 0a1574998fc6..9ce993776160 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -65,8 +65,7 @@ regulator-always-on; }; - - reg_2p5v: regulator-3p3v { + reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; @@ -215,6 +214,29 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + ov5640: camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + sgtl5000: codec@a { #sound-dai-cells = <0>; compatible = "fsl,sgtl5000"; @@ -226,6 +248,20 @@ }; }; +&mipi_csi { + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; @@ -353,7 +389,14 @@ fsl,pins = < MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index aab088f318e8..29baf25ae5d0 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -292,6 +256,7 @@ reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; rtc@6f { diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 87ca6ead4098..39200e5dc896 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -442,6 +406,7 @@ reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index f5b763d39285..572abd7499b1 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -360,6 +324,7 @@ reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 596866b0a0d2..98384a6c5d12 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -370,6 +334,7 @@ reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 0e28e36ddbb2..9f11f1fcc3e6 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -6,6 +6,10 @@ #include <dt-bindings/gpio/gpio.h> / { + chosen { + stdout-path = &uart4; + }; + memory@10000000 { reg = <0x10000000 0x80000000>; }; @@ -155,6 +159,27 @@ gpio-controller; #gpio-cells = <2>; }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + }; + + magnetometer@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + }; + + accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 15744ad52535..6e46a195b399 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -341,6 +341,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index e1afa54404d0..381bf61fcd28 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -8,30 +8,6 @@ #include <dt-bindings/gpio/gpio.h> / { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - sound { compatible = "fsl,imx6-wandboard-sgtl5000", "fsl,imx-audio-sgtl5000"; @@ -52,6 +28,32 @@ spdif-controller = <&spdif>; spdif-out; }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgvbus>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; }; &audmux { @@ -174,6 +176,12 @@ >; }; + pinctrl_usbotgvbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 @@ -248,10 +256,11 @@ }; &usbotg { + vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index f14df0baf2ab..7fff3717cf7c 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -320,10 +320,36 @@ rave-sp { compatible = "zii,rave-sp-rdu2"; current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; watchdog { compatible = "zii,rave-sp-watchdog"; }; + + backlight { + compatible = "zii,rave-sp-backlight"; + }; + + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "dds-eeprom"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; }; }; @@ -569,14 +595,14 @@ rmi4-f11@11 { reg = <0x11>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; rmi4-f12@12 { reg = <0x12>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 911141e24681..61d2d26afbf4 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -922,7 +922,6 @@ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts index a39b86036581..741d1ed338ca 100644 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts index 011726c836cd..1593ac86b2a4 100644 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2017 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 92ad01f676e3..679b4482ab13 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -12,6 +12,10 @@ model = "Freescale i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + chosen { + stdout-path = &uart1; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -73,6 +77,8 @@ reg_lcd_3v3: regulator-lcd-3v3 { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; regulator-name = "lcd-3v3"; gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; enable-active-high; @@ -195,6 +201,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { @@ -406,6 +413,12 @@ >; }; + pinctrl_reg_lcd_3v3: reglcd3v3grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 994e48dc1df0..7a4f5dace902 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -60,6 +60,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PLL1_SYS>; @@ -523,8 +524,8 @@ regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; regulator-always-on; anatop-reg-offset = <0x110>; anatop-vol-bit-shift = <8>; @@ -553,8 +554,8 @@ regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2850000>; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; regulator-always-on; anatop-reg-offset = <0x130>; anatop-vol-bit-shift = <8>; @@ -680,10 +681,36 @@ #interrupt-cells = <3>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - pu-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; - #power-domain-cells = <1>; + clocks = <&clks IMX6SL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_GPU2D_PODF>; + }; + + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_LCDIF_PIX>, + <&clks IMX6SL_CLK_EPDC_AXI>, + <&clks IMX6SL_CLK_EPDC_PIX>, + <&clks IMX6SL_CLK_PXP_AXI>; + }; + }; }; gpr: iomuxc-gpr@20e0000 { @@ -738,6 +765,7 @@ <&clks IMX6SL_CLK_DUMMY>; clock-names = "pix", "axi", "disp_axi"; status = "disabled"; + power-domains = <&pd_disp>; }; dcp: dcp@20fc000 { @@ -921,5 +949,25 @@ status = "disabled"; }; }; + + gpu_2d: gpu@2200000 { + compatible = "vivante,gc"; + reg = <0x02200000 0x4000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; + + gpu_vg: gpu@2204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; }; }; diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts new file mode 100644 index 000000000000..c8e115564ba2 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "imx6sll.dtsi" + +/ { + model = "Freescale i.MX6SLL EVK Board"; + compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + }; + + backlight_display: backlight-display { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_usb_otg1_vbus: regulator-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud3v: regulator-aud3v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator-aud4v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd1_vmmc>; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd3_vmmc: regulator-sd3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd3_vmmc>; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_reg_sd3_vmmc: sd3vmmcgrp { + fsl,pins = < + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 + >; + }; + + pinctrl_usb_otg1_vbus: vbus1grp { + fsl,pins = < + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + >; + }; + + pinctrl_usb_otg2_vbus: vbus2grp { + fsl,pins = < + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + >; + }; + + pinctrl_reg_lcd_3v3: reglcd3v3grp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 + >; + }; + + pinctrl_reg_sd1_vmmc: sd1vmmcgrp { + fsl,pins = < + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/imx6sll-pinfunc.h new file mode 100644 index 000000000000..713a346f4c89 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-pinfunc.h @@ -0,0 +1,880 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#ifndef __DTS_IMX6SLL_PINFUNC_H +#define __DTS_IMX6SLL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 +#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 +#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 +#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 +#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 +#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 +#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 +#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 +#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 +#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 +#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 +#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 +#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 +#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 +#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 +#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 +#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 +#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 +#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 +#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 +#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 +#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 +#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 +#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 +#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 +#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 +#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 +#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 +#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 +#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 +#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 +#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 +#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 +#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 +#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 +#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 +#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 +#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 +#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 +#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 +#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 +#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 +#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 +#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 +#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 +#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 +#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 +#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 +#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 +#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 +#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 +#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 +#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 +#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 +#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 +#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 +#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 +#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 +#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 +#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 +#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 +#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 +#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 +#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 +#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 +#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 +#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 +#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 +#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 +#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 +#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 +#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 +#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 +#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 +#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 +#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 +#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 +#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 +#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 +#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 +#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 +#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 +#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 +#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 +#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 +#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 +#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 +#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 +#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 +#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 +#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 +#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 +#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 +#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 +#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 +#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 +#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 +#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 +#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 +#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 +#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 +#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 +#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 + +#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi new file mode 100644 index 000000000000..000e6136a9d6 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -0,0 +1,780 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#include <dt-bindings/clock/imx6sll-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx6sll-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL2_PFD2>, + <&clks IMX6SLL_CLK_STEP>, + <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + }; + }; + + intc: interrupt-controller@a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + ckil: clock-ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-ipp-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-ipp-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + tempmon: temperature-sensor { + compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + }; + + L2: l2-cache@a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + aips1: aips-bus@2000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba: spba-bus@2000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@2004000 { + compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, + <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_SPDIF>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_IPG>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; + }; + + ecspi1: spi@2008000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI1>, + <&clks IMX6SLL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@200c000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI2>, + <&clks IMX6SLL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@2010000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI3>, + <&clks IMX6SLL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: spi@2014000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI4>, + <&clks IMX6SLL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@2018000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART4_IPG>, + <&clks IMX6SLL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@2020000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART1_IPG>, + <&clks IMX6SLL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@2024000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART2_IPG>, + <&clks IMX6SLL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi1: ssi-controller@2028000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, + <&clks IMX6SLL_CLK_SSI1>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi2: ssi-controller@202c000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, + <&clks IMX6SLL_CLK_SSI2>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi3: ssi-controller@2030000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, + <&clks IMX6SLL_CLK_SSI3>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + uart3: serial@2034000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02034000 0x4000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-name = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART3_IPG>, + <&clks IMX6SLL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + pwm1: pwm@2080000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_PWM1>, + <&clks IMX6SLL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@2084000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_PWM2>, + <&clks IMX6SLL_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@2088000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_PWM3>, + <&clks IMX6SLL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@208c000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_PWM4>, + <&clks IMX6SLL_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + gpt1: timer@2098000 { + compatible = "fsl,imx6sl-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_GPT_BUS>, + <&clks IMX6SLL_CLK_GPT_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@209c000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20a0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20a4000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@20a8000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@20ac000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@20b0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: keypad@20b8000 { + compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_KPP>; + status = "disabled"; + }; + + wdog1: watchdog@20bc000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_WDOG1>; + }; + + wdog2: watchdog@20c0000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: clock-controller@20c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + + assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; + assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; + }; + + anatop: anatop@20c8000 { + compatible = "fsl,imx6sll-anatop", + "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x4000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p0: regulator-3p0@20c8120 { + compatible = "fsl,anatop-regulator"; + reg = <0x20c8120>; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + }; + + usbphy1: usb-phy@20c9000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usb-phy@20ca000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_USBPHY2>; + phy-reg_3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@20cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x61>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + src: reset-controller@20d8000 { + compatible = "fsl,imx6sll-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: interrupt-controller@20dc000 { + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; + }; + + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6sll-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@20e4000 { + compatible = "fsl,imx6sll-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + csi: csi@20e8000 { + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; + reg = <0x020e8000 0x4000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_CSI>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + sdma: dma-controller@20ec000 { + compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_SDMA>, + <&clks IMX6SLL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + lcdif: lcd-controller@20f8000 { + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; + reg = <0x020f8000 0x4000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, + <&clks IMX6SLL_CLK_LCDIF_APB>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + dcp: dcp@20fc000 { + compatible = "fsl,imx28-dcp"; + reg = <0x020fc000 0x4000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_DCP>; + clock-names = "dcp"; + }; + }; + + aips2: aips-bus@2100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@2184000 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@2184200 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@2184800 { + #index-cells = <1>; + compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + usdhc1: mmc@2190000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc2: mmc@2194000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc3: mmc@2198000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + i2c1: i2c@21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@21a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@21a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_I2C3>; + status = "disabled"; + }; + + mmdc: memory-controller@21b0000 { + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + ocotp: ocotp-ctrl@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sll-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SLL_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + }; + + audmux: audmux@21d8000 { + compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + uart5: serial@21f4000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART5_IPG>, + <&clks IMX6SLL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 59e52f504922..adb5cc7d8ce2 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright (C) 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -47,11 +11,6 @@ model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; - aliases { - fb-lcd = &lcdif1; - t-lcd = &t_lcd; - }; - memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -261,38 +220,6 @@ status = "okay"; }; -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif1>; - lcd-supply = <®_3p3v>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - clock-frequency = <74160000>; - hactive = <1280>; - vactive = <720>; - hback-porch = <220>; - hfront-porch = <110>; - vback-porch = <20>; - vfront-porch = <5>; - hsync-len = <40>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -524,40 +451,6 @@ >; }; - pinctrl_lcdif1: lcdif1grp { - fsl,pins = < - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - >; - }; - pinctrl_pcie: pciegrp { fsl,pins = < MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index e3533e74ccc8..9cc6ff206aea 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -63,6 +63,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 4e4a55aad5c9..844caa39364f 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -79,6 +79,7 @@ 198000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SX_CLK_ARM>, <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, @@ -165,6 +166,12 @@ interrupt-parent = <&gpc>; ranges; + ocram_s: sram@8f8000 { + compatible = "mmio-sram"; + reg = <0x008f8000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCRAM_S>; + }; + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; @@ -591,8 +598,8 @@ regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; regulator-always-on; anatop-reg-offset = <0x110>; anatop-vol-bit-shift = <8>; @@ -621,8 +628,8 @@ regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2875000>; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; regulator-always-on; anatop-reg-offset = <0x130>; anatop-vol-bit-shift = <8>; @@ -814,7 +821,6 @@ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts new file mode 100644 index 000000000000..3792679c0c90 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore6UL SBC Express board device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6ul.dtsi" +#include "imx6ul-ccimx6ulsom.dtsi" + +/ { + model = "Digi International ConnectCore 6UL SBC Express."; + compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom", + "fsl,imx6ul"; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <&ext_3v3>; + status = "okay"; +}; + +&ecspi3 { + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3_master>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + smsc,disable-energy-detect; + reg = <0>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + broken-cd; /* no carrier detect line (use polling) */ + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */ + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_ecspi3_master: ecspi3grp1 { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */ + >; + }; + + pinctrl_ecspi3_slave: ecspi3grp2 { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + /* General purpose pinctrl */ + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIOs BANK 3 */ + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi new file mode 100644 index 000000000000..c71a84da1af0 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore 6UL System-On-Module device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x4000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <&vdda_adc_3v3>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + int_3v3: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm_soc_in: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <925000>; + }; + }; + + ext_3v3: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr3: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1300000>; + }; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vdd_snvs_3v3: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vdda_adc_3v3: vldo1 { + compatible = "regulator-fixed"; + regulator-name = "vref-adc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo2_ext: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vdda_wlan: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_high_in: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_int: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4_ext: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vcoin_chg: vcoin { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmigrp { + fsl,pins = < + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; +}; + +®_arm { + vin-supply = <&vdd_arm_soc_in>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&vdd_arm_soc_in>; + regulator-allow-bypass; +}; diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 47682b8c023c..0c09420f9951 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -51,8 +51,9 @@ model = "Technexion Pico i.MX6UL Board"; compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; + /* Will be filled by the bootloader */ memory@80000000 { - reg = <0x80000000 0x10000000>; + reg = <0x80000000 0>; }; chosen { diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 47a3453a4211..6dc0b569acdf 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -62,6 +62,7 @@ device_type = "cpu"; reg = <0>; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; operating-points = < /* kHz uV */ 696000 1275000 @@ -433,6 +434,7 @@ reg = <0x0209c000 0x4000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -446,6 +448,7 @@ reg = <0x020a0000 0x4000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -458,6 +461,7 @@ reg = <0x020a4000 0x4000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -470,6 +474,7 @@ reg = <0x020a8000 0x4000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -482,6 +487,7 @@ reg = <0x020ac000 0x4000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO5>; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 3dffbcd50bf6..183193e8580d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -20,20 +20,6 @@ &cpu0 { clock-frequency = <792000000>; - operating-points = < - /* kHz uV */ - 792000 1225000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 792000 1175000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index ebc25c98e5e1..cd1776a7015a 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -1,43 +1,6 @@ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2016 Freescale Semiconductor, Inc. #include "imx6ul.dtsi" #include "imx6ull-pinfunc.h" @@ -48,6 +11,25 @@ /* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ /delete-node/ &crypto; +&cpu0 { + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1175000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + / { soc { aips3: aips-bus@2200000 { diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 70c53e50b2fc..d8aac4a2d02a 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -48,11 +11,6 @@ model = "Boundary Devices i.MX7 Nitrogen7 Board"; compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; - aliases { - fb-lcd = &lcdif; - t-lcd = &t_lcd; - }; - memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -65,7 +23,7 @@ default-on; }; - backlight-j20 { + backlight_lcd: backlight-j20 { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -73,6 +31,17 @@ status = "okay"; }; + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -317,35 +286,11 @@ }; &lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - lcd-supply = <®_vref_3v3>; - display = <&display0>; status = "okay"; - display0: lcd-display { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - /* default to Okaya display */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <48>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + port { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 940849163104..c9b3c60b0eb2 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -10,6 +10,10 @@ model = "Freescale i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + chosen { + stdout-path = &uart1; + }; + memory@80000000 { reg = <0x80000000 0x80000000>; }; @@ -71,14 +75,6 @@ enable-active-high; }; - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - reg_vref_1v8: regulator-vref-1v8 { compatible = "regulator-fixed"; regulator-name = "vref-1v8"; @@ -116,10 +112,17 @@ gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + panel { compatible = "innolux,at043tn24"; - pinctrl-0 = <&pinctrl_backlight>; - enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; power-supply = <®_lcd_3v3>; port { @@ -712,6 +715,12 @@ }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &iomuxc_lpsr { pinctrl_wdog: wdoggrp { fsl,pins = < @@ -719,9 +728,9 @@ >; }; - pinctrl_backlight: backlightgrp { + pinctrl_pwm1: pwm1grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0 + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 >; }; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 8d3d123d0a5c..7cbc2ffa4b3a 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -11,6 +11,7 @@ cpu0: cpu@0 { clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu1: cpu@1 { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9ced589bfa96..a052198f6e96 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -842,7 +842,6 @@ crypto: caam@30900000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <8>; #address-cells = <1>; #size-cells = <1>; reg = <0x30900000 0x40000>; diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index 66954aaf2c47..5cae74eb6cdd 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi index 476273b3f994..0e99df218252 100644 --- a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ / { diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi index a17311c602aa..1db17ec744b1 100644 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi @@ -225,3 +225,23 @@ netcp: netcp@24000000 { }; }; }; + +sa_subsys: subsys@24080000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x24080000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 154fdd7a7022..b7f10bf94576 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -37,6 +37,14 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 { + compatible = "regulator-fixed"; + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; }; &k2g_pinctrl { @@ -128,6 +136,30 @@ K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ >; }; + + emac_pins: pinmux_emac_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ + K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ + K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ + K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ + K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ + K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ + K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ + K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ + K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ + >; + }; + + mdio_pins: pinmux_mdio_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ + >; + }; }; &uart0 { @@ -144,6 +176,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; vmmc-supply = <&vcc3v3_dcin_reg>; + vqmmc-supply = <&vcc3v3_dcin_reg>; cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -152,6 +185,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ + vqmmc-supply = <&vcc1v8_ldo1_reg>; ti,non-removable; status = "okay"; }; @@ -294,3 +328,32 @@ pinctrl-0 = <&dcan1_pins>; status = "okay"; }; + +&qmss { + status = "okay"; +}; + +&knav_dmas { + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&gbe0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&netcp { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts index d820ed2474bb..2a2d38cf0fff 100644 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "keystone-k2g.dtsi" +#include <dt-bindings/net/ti-dp83867.h> / { compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; @@ -281,6 +282,30 @@ K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */ >; }; + + emac_pins: pinmux_emac_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ + K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ + K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ + K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ + K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ + K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ + K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ + K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ + K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ + >; + }; + + mdio_pins: pinmux_mdio_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ + >; + }; }; &uart0 { @@ -386,3 +411,37 @@ vcc-supply = <&vdd_3v3>; }; }; + +&qmss { + status = "okay"; +}; + +&knav_dmas { + status = "okay"; +}; + +&netcp { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins>; + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&gbe0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi new file mode 100644 index 000000000000..d0e6a9a43402 --- /dev/null +++ b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for K2G Netcp driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +qmss: qmss@4020000 { + compatible = "ti,66ak2g-navss-qm"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 0>; + clock-names = "nss_vclk"; + ranges; + queue-range = <0 0x80>; + linkram0 = <0x4020000 0x7ff>; + status = "disabled"; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x80>; + reg = <0x4100000 0x800>, + <0x4040000 0x100>, + <0x4080000 0x800>, + <0x40c0000 0x800>; + reg-names = "peek", "config", + "region", "push"; + }; + + }; + queue-pools { + qpend { + qpend-0 { + qrange = <77 8>; + interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 + 0 311 0xf04 0 312 0xf04 0 313 0xf04 + 0 314 0xf04 0 315 0xf04>; + qalloc-by-id; + }; + }; + general-purpose { + gp-0 { + qrange = <112 8>; + }; + netcp-tx { + qrange = <5 8>; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <1023 128>; /* num_desc desc_size */ + link-index = <0x400>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 0>; + clock-names = "nss_vclk"; + ranges; + ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x4010000 0x100>, + <0x4011000 0x2a0>, /* 21 Tx channels */ + <0x4012000 0x400>, /* 32 Rx channels */ + <0x4010100 0x80>, + <0x4013000 0x400>; /* 32 Rx flows */ + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; + +}; + +netcp: netcp@4000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + power-domains = <&k2g_pds 0x0018>; + clocks = <&k2g_clks 0x0018 3>, <&k2g_clks 0x0018 8>; + clock-names = "ethss_clk", "cpts"; + + /* NetCP address range */ + ranges = <0 0x4000000 0x1000000>; + + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; + ti,navigator-dma-names = "netrx0", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe: gbe@200000 { + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-2"; + reg = <0x200000 0x20>, <0x220000 0x20000>; + enable-ale; + tx-queue = <5>; + tx-channel = "nettx"; + cpts-rftclk-sel = <0>; + cpts-ext-ts-inputs = <8>; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <5>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <512 12>; + tx-pool = <511 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <77>; + tx-completion-queue = <78>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index da78c0034427..738b44cf2b0b 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -391,13 +391,10 @@ }; mmc0: mmc@23000000 { - compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; + compatible = "ti,k2g-sdhci"; reg = <0x23000000 0x400>; interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>; - dmas = <&edma1 24 0>, <&edma1 25 0>; - dma-names = "tx", "rx"; bus-width = <4>; - ti,needs-special-reset; no-1-8-v; max-frequency = <96000000>; power-domains = <&k2g_pds 0xb>; @@ -407,13 +404,12 @@ }; mmc1: mmc@23100000 { - compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; + compatible = "ti,k2g-sdhci"; reg = <0x23100000 0x400>; interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>; - dmas = <&edma1 26 0>, <&edma1 27 0>; - dma-names = "tx", "rx"; bus-width = <8>; - ti,needs-special-reset; + no-1-8-v; + non-removable; max-frequency = <96000000>; power-domains = <&k2g_pds 0xc>; clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; @@ -609,5 +605,18 @@ reg = <0x21010000 0x200>; interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>; }; + + mdio: mdio@4200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + reg = <0x04200f00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k2g_clks 0x0018 3>; + clock-names = "fck"; + power-domains = <&k2g_pds 0x0018>; + status = "disabled"; + bus_freq = <2500000>; + }; + #include "keystone-k2g-netcp.dtsi" }; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi index b88c0689c285..e203145acbea 100644 --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi @@ -228,3 +228,23 @@ netcp: netcp@2000000 { }; }; }; + +sa_subsys: subsys@20c0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x20c0000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi index 9ec84228bc16..a2e47bad3307 100644 --- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi @@ -208,3 +208,23 @@ netcp: netcp@26000000 { }; }; }; + +sa_subsys: subsys@26080000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x26080000 0x40000>; + + sa_config: subsys@0 { + compatible = "syscon"; + reg = <0x0 0x100>; + }; + + rng@24000 { + compatible = "ti,keystone-rng"; + reg = <0x24000 0x1000>; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index 3bb28c03ca74..ac343330d0c8 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -142,7 +142,7 @@ compatible = "ti,wl1273"; reg = <2>; interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */ + interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */ ref-clock-frequency = <26000000>; }; }; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 234afd6d60ec..9d5d53fbe9c0 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -48,7 +48,7 @@ compatible = "ti,wl1283"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ + interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */ ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index c55d479971cc..f18490548c78 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -84,6 +84,7 @@ device_type = "cpu"; reg = <0xf01>; clocks = <&clockgen 1 0>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index d1eb123bc73b..1cdc346a05e8 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -92,6 +92,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; clock-frequency = <1300000000>; }; @@ -103,6 +104,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; clock-frequency = <1300000000>; }; @@ -114,6 +116,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; clock-frequency = <1300000000>; }; }; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 531d905d924f..2b760f90f38c 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -91,19 +91,19 @@ blue { label = "bpi-r2:pio:blue"; - gpios = <&pio 241 GPIO_ACTIVE_HIGH>; + gpios = <&pio 240 GPIO_ACTIVE_LOW>; default-state = "off"; }; green { label = "bpi-r2:pio:green"; - gpios = <&pio 240 GPIO_ACTIVE_HIGH>; + gpios = <&pio 241 GPIO_ACTIVE_LOW>; default-state = "off"; }; red { label = "bpi-r2:pio:red"; - gpios = <&pio 239 GPIO_ACTIVE_HIGH>; + gpios = <&pio 239 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts deleted file mode 100644 index 96ff3c9068ae..000000000000 --- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: John Crispin <john@phrozen.org> - * - */ - -/dts-v1/; -#include "mt7623n-rfb.dtsi" - -/ { - model = "MediaTek MT7623N NAND reference board"; - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623"; -}; - -&bch { - status = "okay"; -}; - -&nandc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_default>; - - nand@0 { - reg = <0>; - spare_per_sector = <64>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <12>; - nand-ecc-step-size = <1024>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "preloader"; - reg = <0x0 0x40000>; - }; - - partition@40000 { - label = "uboot"; - reg = <0x40000 0x80000>; - }; - - partition@c0000 { - label = "uboot-env"; - reg = <0xC0000 0x40000>; - }; - - partition@140000 { - label = "bootimg"; - reg = <0x140000 0x2000000>; - }; - - partition@2140000 { - label = "recovery"; - reg = <0x2140000 0x2000000>; - }; - - partition@4140000 { - label = "rootfs"; - reg = <0x4140000 0x1000000>; - }; - - partition@5140000 { - label = "usrdata"; - reg = <0x5140000 0x1000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi b/arch/arm/boot/dts/mt7623n-rfb.dtsi deleted file mode 100644 index 5c5cc7da5dd2..000000000000 --- a/arch/arm/boot/dts/mt7623n-rfb.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: John Crispin <john@phrozen.org> - * Sean Wang <sean.wang@mediatek.com> - * - */ - -/dts-v1/; -#include "mt7623.dtsi" -#include "mt6323.dtsi" - -/ { - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - cpus { - cpu0 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu1 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu2 { - proc-supply = <&mt6323_vproc_reg>; - }; - - cpu3 { - proc-supply = <&mt6323_vproc_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - usb_p1_vbus: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 135 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&mmc0 { - vmmc-supply = <&mt6323_vemc3v3_reg>; - vqmmc-supply = <&mt6323_vio18_reg>; -}; - -&mmc1 { - vmmc-supply = <&mt6323_vmch_reg>; - vqmmc-supply = <&mt6323_vmc_reg>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb1 { - vbus-supply = <&usb_p1_vbus>; - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index 4994e33bf663..632f52efdf98 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -141,7 +141,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 145 */ + interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 145 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 8c63ac5bbb12..6e944dfa0f3d 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -81,7 +81,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ + interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index ee64191e41ca..4c1227d1e79b 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -133,7 +133,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */ + interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 149 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts index 321c2b7a4e9f..285681d7af49 100644 --- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts @@ -49,6 +49,6 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio6>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; /* gpio 177 */ + interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */ }; }; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts index 76dc08868bfb..1adc73bd2ca0 100644 --- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts @@ -71,6 +71,6 @@ compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio5>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; /* gpio 136 */ + interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */ }; }; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index 96d0301a336a..aac27a441331 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -202,7 +202,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio6>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 162 */ + interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 162 */ ref-clock-frequency = <26000000>; }; }; diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index e7c3c563ff8f..12d6822f0057 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -128,6 +128,8 @@ gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ linux,code = <KEY_VOLUMEDOWN>; linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; }; slider { @@ -136,7 +138,8 @@ linux,input-type = <EV_SW>; linux,code = <SW_KEYPAD_SLIDE>; linux,can-disable; - + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; }; }; @@ -369,7 +372,7 @@ compatible = "ti,wl1285", "ti,wl1283"; reg = <2>; interrupt-parent = <&gpio4>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */ + interrupts = <4 IRQ_TYPE_EDGE_RISING>; /* gpio100 */ ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index a9a584b5b955..cfcac0d73851 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -36,6 +36,8 @@ label = "button0"; linux,code = <BTN_0>; gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; wakeup-source; }; }; @@ -140,7 +142,7 @@ ethernet@gpmc { reg = <5 0 0xff>; interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; /* gpio_44 */ phy-mode = "mii"; diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index eb123b24c8e3..5e8169153414 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -248,6 +248,7 @@ ti,bus-width = <4>; ti,non-removable; cap-power-off-card; + keep-power-in-suspend; }; &twl_usb_comparator { diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi new file mode 100644 index 000000000000..6eb26b837446 --- /dev/null +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -0,0 +1,2444 @@ +// SPDX-License-Identifier: GPL-2.0 +&l4_cfg { /* 0x4a000000 */ + compatible = "ti,omap4-l4-cfg", "simple-bus"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ + <0x00080000 0x4a080000 0x080000>, /* segment 1 */ + <0x00100000 0x4a100000 0x080000>, /* segment 2 */ + <0x00180000 0x4a180000 0x080000>, /* segment 3 */ + <0x00200000 0x4a200000 0x080000>, /* segment 4 */ + <0x00280000 0x4a280000 0x080000>, /* segment 5 */ + <0x00300000 0x4a300000 0x080000>; /* segment 6 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00002000 0x00002000 0x001000>, /* ap 3 */ + <0x00003000 0x00003000 0x001000>, /* ap 4 */ + <0x00004000 0x00004000 0x001000>, /* ap 5 */ + <0x00005000 0x00005000 0x001000>, /* ap 6 */ + <0x00056000 0x00056000 0x001000>, /* ap 7 */ + <0x00057000 0x00057000 0x001000>, /* ap 8 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ + <0x00058000 0x00058000 0x004000>, /* ap 10 */ + <0x00062000 0x00062000 0x001000>, /* ap 11 */ + <0x00063000 0x00063000 0x001000>, /* ap 12 */ + <0x00008000 0x00008000 0x002000>, /* ap 23 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 24 */ + <0x00066000 0x00066000 0x001000>, /* ap 25 */ + <0x00067000 0x00067000 0x001000>, /* ap 26 */ + <0x0005e000 0x0005e000 0x002000>, /* ap 80 */ + <0x00060000 0x00060000 0x001000>, /* ap 81 */ + <0x00064000 0x00064000 0x001000>, /* ap 86 */ + <0x00065000 0x00065000 0x001000>; /* ap 87 */ + + target-module@2000 { /* 0x4a002000, ap 3 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ctrl_module_core"; + reg = <0x2000 0x4>, + <0x2010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + + omap4_scm_core: scm@0 { + compatible = "ti,omap4-scm-core", "simple-bus"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; + + omap_control_usb2phy: control-phy@300 { + compatible = "ti,control-phy-usb2"; + reg = <0x300 0x4>; + reg-names = "power"; + }; + + omap_control_usbotg: control-phy@33c { + compatible = "ti,control-phy-otghs"; + reg = <0x33c 0x4>; + reg-names = "otghs_control"; + }; + }; + }; + + target-module@4000 { /* 0x4a004000, ap 5 02.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + cm1: cm1@0 { + compatible = "ti,omap4-cm1", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + cm1_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm1_clockdomains: clockdomains { + }; + }; + }; + + target-module@8000 { /* 0x4a008000, ap 23 32.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x8000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x2000>; + + cm2: cm2@0 { + compatible = "ti,omap4-cm2", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + cm2_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm2_clockdomains: clockdomains { + }; + }; + }; + + target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "dma_system"; + reg = <0x56000 0x4>, + <0x5602c 0x4>, + <0x56028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */ + clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap4430-sdma"; + reg = <0x0 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; + }; + }; + + target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hsi"; + reg = <0x58000 0x4>, + <0x58010 0x4>, + <0x58014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58000 0x4000>; + + hsi: hsi@0 { + compatible = "ti,omap4-hsi"; + reg = <0x0 0x4000>, + <0x4a05c000 0x1000>; + reg-names = "sys", "gdd"; + + clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; + clock-names = "hsi_fck"; + + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x4000>; + + hsi_port1: hsi-port@2000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x2000 0x800>, + <0x2800 0x800>; + reg-names = "tx", "rx"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + }; + + hsi_port2: hsi-port@3000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x3000 0x800>, + <0x3800 0x800>; + reg-names = "tx", "rx"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + + target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x2000>; + }; + + target-module@62000 { /* 0x4a062000, ap 11 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_tll_hs"; + reg = <0x62000 0x4>, + <0x62010 0x4>, + <0x62014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x62000 0x1000>; + + usbhstll: usbhstll@0 { + compatible = "ti,usbhs-tll"; + reg = <0x0 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_host_hs"; + reg = <0x64000 0x4>, + <0x64010 0x4>, + <0x64014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x1000>; + + usbhshost: usbhshost@0 { + compatible = "ti,usbhs-host"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + clocks = <&init_60m_fclk>, + <&xclk60mhsp1_ck>, + <&xclk60mhsp2_ck>; + clock-names = "refclk_60m_int", + "refclk_60m_ext_p1", + "refclk_60m_ext_p2"; + + usbhsohci: ohci@800 { + compatible = "ti,ohci-omap3"; + reg = <0x800 0x400>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + remote-wakeup-connected; + }; + + usbhsehci: ehci@c00 { + compatible = "ti,ehci-omap"; + reg = <0xc00 0x400>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + + target-module@66000 { /* 0x4a066000, ap 25 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmu_dsp"; + reg = <0x66000 0x4>, + <0x66010 0x4>, + <0x66014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ + clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + + /* mmu_dsp cannot be moved before reset driver */ + status = "disabled"; + }; + }; + + segment@80000 { /* 0x4a080000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ + <0x0005a000 0x000da000 0x001000>, /* ap 14 */ + <0x0005b000 0x000db000 0x001000>, /* ap 15 */ + <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ + <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ + <0x0005e000 0x000de000 0x001000>, /* ap 18 */ + <0x00060000 0x000e0000 0x001000>, /* ap 19 */ + <0x00061000 0x000e1000 0x001000>, /* ap 20 */ + <0x00074000 0x000f4000 0x001000>, /* ap 27 */ + <0x00075000 0x000f5000 0x001000>, /* ap 28 */ + <0x00076000 0x000f6000 0x001000>, /* ap 29 */ + <0x00077000 0x000f7000 0x001000>, /* ap 30 */ + <0x00036000 0x000b6000 0x001000>, /* ap 69 */ + <0x00037000 0x000b7000 0x001000>, /* ap 70 */ + <0x0004d000 0x000cd000 0x001000>, /* ap 78 */ + <0x0004e000 0x000ce000 0x001000>, /* ap 79 */ + <0x00029000 0x000a9000 0x001000>, /* ap 82 */ + <0x0002a000 0x000aa000 0x001000>, /* ap 83 */ + <0x0002b000 0x000ab000 0x001000>, /* ap 84 */ + <0x0002c000 0x000ac000 0x001000>, /* ap 85 */ + <0x0002d000 0x000ad000 0x001000>, /* ap 88 */ + <0x0002e000 0x000ae000 0x001000>; /* ap 89 */ + + target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x29000 0x1000>; + }; + + target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2b000 0x1000>; + + usb_otg_hs: usb_otg_hs@0 { + compatible = "ti,omap4-musb"; + reg = <0x0 0x7ff>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc", "dma"; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + multipoint = <1>; + num-eps = <16>; + ram-bits = <12>; + ctrl-module = <&omap_control_usbotg>; + }; + }; + + target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp_usb_phy"; + reg = <0x2d000 0x4>, + <0x2d010 0x4>, + <0x2d014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2d000 0x1000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + reg = <0x0 0x1f>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + usb2_phy: usb2phy@80 { + compatible = "ti,omap-usb2"; + reg = <0x80 0x58>; + ctrl-module = <&omap_control_usb2phy>; + clocks = <&usb_phy_cm_clk32k>; + clock-names = "wkupclk"; + #phy-cells = <0>; + }; + }; + }; + + target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000 0x1000>; + }; + + target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu"; + reg = <0x59038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + + smartreflex_mpu: smartreflex@0 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_iva"; + reg = <0x5b038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + smartreflex_iva: smartreflex@0 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */ + compatible = "ti,sysc-omap4-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x5d038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */ + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; + reg = <0x74000 0x4>, + <0x74010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x74000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + mbox_ipu: mbox_ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox_dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; + }; + }; + + target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; + reg = <0x76000 0x4>, + <0x76010 0x4>, + <0x76014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x76000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; + }; + }; + + segment@100000 { /* 0x4a100000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */ + <0x00001000 0x00101000 0x001000>, /* ap 22 */ + <0x00002000 0x00102000 0x001000>, /* ap 61 */ + <0x00003000 0x00103000 0x001000>, /* ap 62 */ + <0x00008000 0x00108000 0x001000>, /* ap 63 */ + <0x00009000 0x00109000 0x001000>, /* ap 64 */ + <0x0000a000 0x0010a000 0x001000>, /* ap 65 */ + <0x0000b000 0x0010b000 0x001000>; /* ap 66 */ + + target-module@0 { /* 0x4a100000, ap 21 2a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ctrl_module_pad_core"; + reg = <0x0 0x4>, + <0x10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + omap4_pmx_core: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap4_padconf_global: omap4_padconf_global@5a0 { + compatible = "syscon", + "simple-bus"; + reg = <0x5a0 0x170>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5a0 0x170>; + + pbias_regulator: pbias_regulator@60 { + compatible = "ti,pbias-omap4", "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap4_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap4 { + regulator-name = "pbias_mmc_omap4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + }; + + target-module@2000 { /* 0x4a102000, ap 61 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@8000 { /* 0x4a108000, ap 63 62.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "fdif"; + reg = <0xa000 0x4>, + <0xa010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-delay-us = <2>; + /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */ + clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + + /* No child device binding or driver in mainline */ + }; + }; + + segment@180000 { /* 0x4a180000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@200000 { /* 0x4a200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */ + <0x0001f000 0x0021f000 0x001000>, /* ap 32 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 33 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 34 */ + <0x00004000 0x00204000 0x001000>, /* ap 35 */ + <0x00005000 0x00205000 0x001000>, /* ap 36 */ + <0x00006000 0x00206000 0x001000>, /* ap 37 */ + <0x00007000 0x00207000 0x001000>, /* ap 38 */ + <0x00012000 0x00212000 0x001000>, /* ap 39 */ + <0x00013000 0x00213000 0x001000>, /* ap 40 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 41 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 42 */ + <0x00010000 0x00210000 0x001000>, /* ap 43 */ + <0x00011000 0x00211000 0x001000>, /* ap 44 */ + <0x00016000 0x00216000 0x001000>, /* ap 45 */ + <0x00017000 0x00217000 0x001000>, /* ap 46 */ + <0x00014000 0x00214000 0x001000>, /* ap 47 */ + <0x00015000 0x00215000 0x001000>, /* ap 48 */ + <0x00018000 0x00218000 0x001000>, /* ap 49 */ + <0x00019000 0x00219000 0x001000>, /* ap 50 */ + <0x00020000 0x00220000 0x001000>, /* ap 51 */ + <0x00021000 0x00221000 0x001000>, /* ap 52 */ + <0x00026000 0x00226000 0x001000>, /* ap 53 */ + <0x00027000 0x00227000 0x001000>, /* ap 54 */ + <0x00028000 0x00228000 0x001000>, /* ap 55 */ + <0x00029000 0x00229000 0x001000>, /* ap 56 */ + <0x0002a000 0x0022a000 0x001000>, /* ap 57 */ + <0x0002b000 0x0022b000 0x001000>, /* ap 58 */ + <0x0001c000 0x0021c000 0x001000>, /* ap 59 */ + <0x0001d000 0x0021d000 0x001000>; /* ap 60 */ + + target-module@4000 { /* 0x4a204000, ap 35 42.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a206000, ap 37 4a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x1000>; + }; + + target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@c000 { /* 0x4a20c000, ap 41 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@10000 { /* 0x4a210000, ap 43 52.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@12000 { /* 0x4a212000, ap 39 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000 0x1000>; + }; + + target-module@14000 { /* 0x4a214000, ap 47 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@16000 { /* 0x4a216000, ap 45 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@18000 { /* 0x4a218000, ap 49 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x1000>; + }; + + target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x4a220000, ap 51 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@26000 { /* 0x4a226000, ap 53 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x4a228000, ap 55 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + }; + + segment@280000 { /* 0x4a280000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ + <0x00040000 0x00340000 0x001000>, /* ap 68 */ + <0x00020000 0x00320000 0x004000>, /* ap 71 */ + <0x00024000 0x00324000 0x002000>, /* ap 72 */ + <0x00026000 0x00326000 0x001000>, /* ap 73 */ + <0x00027000 0x00327000 0x001000>, /* ap 74 */ + <0x00028000 0x00328000 0x001000>, /* ap 75 */ + <0x00029000 0x00329000 0x001000>, /* ap 76 */ + <0x00030000 0x00330000 0x010000>, /* ap 77 */ + <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ + <0x0002c000 0x0032c000 0x004000>; /* ap 91 */ + + l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00020000>, + <0x00020000 0x00020000 0x00004000>, + <0x00024000 0x00024000 0x00002000>, + <0x00026000 0x00026000 0x00001000>, + <0x00027000 0x00027000 0x00001000>, + <0x00028000 0x00028000 0x00001000>, + <0x00029000 0x00029000 0x00001000>, + <0x0002a000 0x0002a000 0x00002000>, + <0x0002c000 0x0002c000 0x00004000>, + <0x00030000 0x00030000 0x00010000>; + }; + }; +}; + +&l4_wkup { /* 0x4a300000 */ + compatible = "ti,omap4-l4-wkup", "simple-bus"; + reg = <0x4a300000 0x800>, + <0x4a300800 0x800>, + <0x4a301000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */ + <0x00010000 0x4a310000 0x010000>, /* segment 1 */ + <0x00020000 0x4a320000 0x010000>; /* segment 2 */ + + segment@0 { /* 0x4a300000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00006000 0x00006000 0x002000>, /* ap 3 */ + <0x00008000 0x00008000 0x001000>, /* ap 4 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ + <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ + <0x00004000 0x00004000 0x001000>, /* ap 17 */ + <0x00005000 0x00005000 0x001000>, /* ap 18 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ + + target-module@4000 { /* 0x4a304000, ap 17 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "counter_32k"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x20>; + }; + }; + + target-module@6000 { /* 0x4a306000, ap 3 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x2000>; + + prm: prm@0 { + compatible = "ti,omap4-prm"; + reg = <0x0 0x2000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + }; + + target-module@a000 { /* 0x4a30a000, ap 15 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xa000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + + scrm: scrm@0 { + compatible = "ti,omap4-scrm"; + reg = <0x0 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + }; + + target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ctrl_module_wkup"; + reg = <0xc000 0x4>, + <0xc010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + omap4_scm_wkup: scm@c000 { + compatible = "ti,omap4-scm-wkup"; + reg = <0xc000 0x1000>; + }; + }; + }; + + segment@10000 { /* 0x4a310000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ + <0x00001000 0x00011000 0x001000>, /* ap 6 */ + <0x00004000 0x00014000 0x001000>, /* ap 7 */ + <0x00005000 0x00015000 0x001000>, /* ap 8 */ + <0x00008000 0x00018000 0x001000>, /* ap 9 */ + <0x00009000 0x00019000 0x001000>, /* ap 10 */ + <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ + <0x0000d000 0x0001d000 0x001000>, /* ap 12 */ + <0x0000e000 0x0001e000 0x001000>, /* ap 21 */ + <0x0000f000 0x0001f000 0x001000>; /* ap 22 */ + + gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>, + <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + ti,gpio-always-on; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@4000 { /* 0x4a314000, ap 7 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer1"; + reg = <0x8000 0x4>, + <0x8010 0x4>, + <0x8014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; + clock-names = "fck"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-alwon; + }; + }; + + target-module@c000 { /* 0x4a31c000, ap 11 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "kbd"; + reg = <0xc000 0x4>, + <0xc010 0x4>, + <0xc014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + keypad: keypad@0 { + compatible = "ti,omap4-keypad"; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + reg-names = "mpu"; + }; + }; + + target-module@e000 { /* 0x4a31e000, ap 21 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ctrl_module_pad_wkup"; + reg = <0xe000 0x4>, + <0xe010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + + omap4_pmx_wkup: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + }; + }; + + segment@20000 { /* 0x4a320000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ + <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ + <0x00000000 0x00020000 0x001000>, /* ap 23 */ + <0x00001000 0x00021000 0x001000>, /* ap 24 */ + <0x00002000 0x00022000 0x001000>, /* ap 25 */ + <0x00003000 0x00023000 0x001000>, /* ap 26 */ + <0x00004000 0x00024000 0x001000>, /* ap 27 */ + <0x00005000 0x00025000 0x001000>, /* ap 28 */ + <0x00007000 0x00027000 0x000400>, /* ap 29 */ + <0x00008000 0x00028000 0x000800>, /* ap 30 */ + <0x00009000 0x00029000 0x000400>; /* ap 31 */ + + target-module@0 { /* 0x4a320000, ap 23 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x4a322000, ap 25 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x4a324000, ap 27 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a326000, ap 13 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00006000 0x00001000>, + <0x00001000 0x00007000 0x00000400>, + <0x00002000 0x00008000 0x00000800>, + <0x00003000 0x00009000 0x00000400>; + }; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,omap4-l4-per", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ + <0x00200000 0x48200000 0x200000>; /* segment 1 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00020000 0x00020000 0x001000>, /* ap 3 */ + <0x00021000 0x00021000 0x001000>, /* ap 4 */ + <0x00032000 0x00032000 0x001000>, /* ap 5 */ + <0x00033000 0x00033000 0x001000>, /* ap 6 */ + <0x00034000 0x00034000 0x001000>, /* ap 7 */ + <0x00035000 0x00035000 0x001000>, /* ap 8 */ + <0x00036000 0x00036000 0x001000>, /* ap 9 */ + <0x00037000 0x00037000 0x001000>, /* ap 10 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ + <0x00040000 0x00040000 0x010000>, /* ap 13 */ + <0x00050000 0x00050000 0x001000>, /* ap 14 */ + <0x00055000 0x00055000 0x001000>, /* ap 15 */ + <0x00056000 0x00056000 0x001000>, /* ap 16 */ + <0x00057000 0x00057000 0x001000>, /* ap 17 */ + <0x00058000 0x00058000 0x001000>, /* ap 18 */ + <0x00059000 0x00059000 0x001000>, /* ap 19 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 20 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 21 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 22 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 23 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 24 */ + <0x00060000 0x00060000 0x001000>, /* ap 25 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 26 */ + <0x0006b000 0x0006b000 0x001000>, /* ap 27 */ + <0x0006c000 0x0006c000 0x001000>, /* ap 28 */ + <0x0006d000 0x0006d000 0x001000>, /* ap 29 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 30 */ + <0x0006f000 0x0006f000 0x001000>, /* ap 31 */ + <0x00070000 0x00070000 0x001000>, /* ap 32 */ + <0x00071000 0x00071000 0x001000>, /* ap 33 */ + <0x00072000 0x00072000 0x001000>, /* ap 34 */ + <0x00073000 0x00073000 0x001000>, /* ap 35 */ + <0x00061000 0x00061000 0x001000>, /* ap 36 */ + <0x00096000 0x00096000 0x001000>, /* ap 37 */ + <0x00097000 0x00097000 0x001000>, /* ap 38 */ + <0x00076000 0x00076000 0x001000>, /* ap 39 */ + <0x00077000 0x00077000 0x001000>, /* ap 40 */ + <0x00078000 0x00078000 0x001000>, /* ap 41 */ + <0x00079000 0x00079000 0x001000>, /* ap 42 */ + <0x00086000 0x00086000 0x001000>, /* ap 43 */ + <0x00087000 0x00087000 0x001000>, /* ap 44 */ + <0x00088000 0x00088000 0x001000>, /* ap 45 */ + <0x00089000 0x00089000 0x001000>, /* ap 46 */ + <0x000b0000 0x000b0000 0x001000>, /* ap 47 */ + <0x000b1000 0x000b1000 0x001000>, /* ap 48 */ + <0x00098000 0x00098000 0x001000>, /* ap 49 */ + <0x00099000 0x00099000 0x001000>, /* ap 50 */ + <0x0009a000 0x0009a000 0x001000>, /* ap 51 */ + <0x0009b000 0x0009b000 0x001000>, /* ap 52 */ + <0x0009c000 0x0009c000 0x001000>, /* ap 53 */ + <0x0009d000 0x0009d000 0x001000>, /* ap 54 */ + <0x0009e000 0x0009e000 0x001000>, /* ap 55 */ + <0x0009f000 0x0009f000 0x001000>, /* ap 56 */ + <0x00090000 0x00090000 0x002000>, /* ap 57 */ + <0x00092000 0x00092000 0x001000>, /* ap 58 */ + <0x000a4000 0x000a4000 0x001000>, /* ap 59 */ + <0x000a6000 0x000a6000 0x001000>, /* ap 60 */ + <0x000a8000 0x000a8000 0x004000>, /* ap 61 */ + <0x000ac000 0x000ac000 0x001000>, /* ap 62 */ + <0x000ad000 0x000ad000 0x001000>, /* ap 63 */ + <0x000ae000 0x000ae000 0x001000>, /* ap 64 */ + <0x000b2000 0x000b2000 0x001000>, /* ap 65 */ + <0x000b3000 0x000b3000 0x001000>, /* ap 66 */ + <0x000b4000 0x000b4000 0x001000>, /* ap 67 */ + <0x000b5000 0x000b5000 0x001000>, /* ap 68 */ + <0x000b8000 0x000b8000 0x001000>, /* ap 69 */ + <0x000b9000 0x000b9000 0x001000>, /* ap 70 */ + <0x000ba000 0x000ba000 0x001000>, /* ap 71 */ + <0x000bb000 0x000bb000 0x001000>, /* ap 72 */ + <0x000d1000 0x000d1000 0x001000>, /* ap 73 */ + <0x000d2000 0x000d2000 0x001000>, /* ap 74 */ + <0x000d5000 0x000d5000 0x001000>, /* ap 75 */ + <0x000d6000 0x000d6000 0x001000>, /* ap 76 */ + <0x000a2000 0x000a2000 0x001000>, /* ap 79 */ + <0x000a3000 0x000a3000 0x001000>, /* ap 80 */ + <0x00001400 0x00001400 0x000400>, /* ap 81 */ + <0x00001800 0x00001800 0x000400>, /* ap 82 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 83 */ + <0x000a5000 0x000a5000 0x001000>; /* ap 84 */ + + target-module@20000 { /* 0x48020000, ap 3 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + uart3: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + }; + }; + + target-module@32000 { /* 0x48032000, ap 5 02.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer2"; + reg = <0x32000 0x4>, + <0x32010 0x4>, + <0x32014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>; + clock-names = "fck"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@34000 { /* 0x48034000, ap 7 04.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; + reg = <0x34000 0x4>, + <0x34010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + + timer3: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>; + clock-names = "fck"; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@36000 { /* 0x48036000, ap 9 0e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; + reg = <0x36000 0x4>, + <0x36010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + + timer4: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>; + clock-names = "fck"; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + timer9: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; + clock-names = "fck"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; + }; + }; + + target-module@40000 { /* 0x48040000, ap 13 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x10000>; + }; + + target-module@55000 { /* 0x48055000, ap 15 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; + reg = <0x55000 0x4>, + <0x55010 0x4>, + <0x55114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@57000 { /* 0x48057000, ap 17 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; + reg = <0x57000 0x4>, + <0x57010 0x4>, + <0x57114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@59000 { /* 0x48059000, ap 19 10.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; + reg = <0x59000 0x4>, + <0x59010 0x4>, + <0x59114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5b000 { /* 0x4805b000, ap 21 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio5"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>, + <0x5b114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5d000 { /* 0x4805d000, ap 23 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio6"; + reg = <0x5d000 0x4>, + <0x5d010 0x4>, + <0x5d114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>, + <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + + gpio6: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@60000 { /* 0x48060000, ap 25 1e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; + reg = <0x60000 0x8>, + <0x60010 0x8>, + <0x60090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + + i2c3: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@6a000 { /* 0x4806a000, ap 26 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; + reg = <0x6a050 0x4>, + <0x6a054 0x4>, + <0x6a058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6a000 0x1000>; + + uart1: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + }; + }; + + target-module@6c000 { /* 0x4806c000, ap 28 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; + reg = <0x6c050 0x4>, + <0x6c054 0x4>, + <0x6c058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x1000>; + + uart2: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + }; + }; + + target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; + reg = <0x6e050 0x4>, + <0x6e054 0x4>, + <0x6e058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6e000 0x1000>; + + uart4: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + }; + }; + + target-module@70000 { /* 0x48070000, ap 32 28.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; + reg = <0x70000 0x8>, + <0x70010 0x8>, + <0x70090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@72000 { /* 0x48072000, ap 34 30.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; + reg = <0x72000 0x8>, + <0x72010 0x8>, + <0x72090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x72000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@76000 { /* 0x48076000, ap 39 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "slimbus2"; + reg = <0x76000 0x4>, + <0x76010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x76000 0x1000>; + + /* No child device binding or driver in mainline */ + }; + + target-module@78000 { /* 0x48078000, ap 41 1a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; + reg = <0x78000 0x4>, + <0x78010 0x4>, + <0x78014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x1000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + target-module@86000 { /* 0x48086000, ap 43 24.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer10"; + reg = <0x86000 0x4>, + <0x86010 0x4>, + <0x86014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + + timer10: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>; + clock-names = "fck"; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; + }; + }; + + target-module@88000 { /* 0x48088000, ap 45 2e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; + reg = <0x88000 0x4>, + <0x88010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x88000 0x1000>; + + timer11: timer@0 { + compatible = "ti,omap4430-timer"; + reg = <0x0 0x80>; + clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>; + clock-names = "fck"; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; + }; + }; + + target-module@90000 { /* 0x48090000, ap 57 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x2000>; + }; + + target-module@96000 { /* 0x48096000, ap 37 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mcbsp4"; + reg = <0x9608c 0x4>; + reg-names = "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x96000 0x1000>; + + mcbsp4: mcbsp@0 { + compatible = "ti,omap4-mcbsp"; + reg = <0x0 0xff>; /* L4 Interconnect */ + reg-names = "mpu"; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common"; + ti,buffer-size = <128>; + dmas = <&sdma 31>, + <&sdma 32>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + target-module@98000 { /* 0x48098000, ap 49 22.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi1"; + reg = <0x98000 0x4>, + <0x98010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000 0x1000>; + + mcspi1: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <4>; + dmas = <&sdma 35>, + <&sdma 36>, + <&sdma 37>, + <&sdma 38>, + <&sdma 39>, + <&sdma 40>, + <&sdma 41>, + <&sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + }; + + target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi2"; + reg = <0x9a000 0x4>, + <0x9a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9a000 0x1000>; + + mcspi2: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 43>, + <&sdma 44>, + <&sdma 45>, + <&sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + }; + + target-module@9c000 { /* 0x4809c000, ap 53 36.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc1"; + reg = <0x9c000 0x4>, + <0x9c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; + }; + }; + + target-module@9e000 { /* 0x4809e000, ap 55 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9e000 0x1000>; + }; + + target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x480a4000, ap 59 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x000a4000 0x00001000>, + <0x00001000 0x000a5000 0x00001000>; + }; + + target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x4000>; + }; + + target-module@ad000 { /* 0x480ad000, ap 63 50.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc3"; + reg = <0xad000 0x4>, + <0xad010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xad000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + ti,needs-special-reset; + dmas = <&sdma 77>, <&sdma 78>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b0000 { /* 0x480b0000, ap 47 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb0000 0x1000>; + }; + + target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hdq1w"; + reg = <0xb2000 0x4>, + <0xb2014 0x4>, + <0xb2018 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + ti,no-reset-on-init; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb2000 0x1000>; + + hdqw1w: 1w@0 { + compatible = "ti,omap3-1w"; + reg = <0x0 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@b4000 { /* 0x480b4000, ap 67 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc2"; + reg = <0xb4000 0x4>, + <0xb4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */ + clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb4000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + ti,needs-special-reset; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b8000 { /* 0x480b8000, ap 69 58.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi3"; + reg = <0xb8000 0x4>, + <0xb8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb8000 0x1000>; + + mcspi3: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 15>, <&sdma 16>; + dma-names = "tx0", "rx0"; + }; + }; + + target-module@ba000 { /* 0x480ba000, ap 71 32.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi4"; + reg = <0xba000 0x4>, + <0xba010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xba000 0x1000>; + + mcspi4: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <1>; + dmas = <&sdma 70>, <&sdma 71>; + dma-names = "tx0", "rx0"; + }; + }; + + target-module@d1000 { /* 0x480d1000, ap 73 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc4"; + reg = <0xd1000 0x4>, + <0xd1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd1000 0x1000>; + + mmc4: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + ti,needs-special-reset; + dmas = <&sdma 57>, <&sdma 58>; + dma-names = "tx", "rx"; + }; + }; + + target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc5"; + reg = <0xd5000 0x4>, + <0xd5010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd5000 0x1000>; + + mmc5: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + ti,needs-special-reset; + dmas = <&sdma 59>, <&sdma 60>; + dma-names = "tx", "rx"; + }; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */ + <0x00151000 0x00351000 0x001000>; /* ap 78 */ + + target-module@150000 { /* 0x48350000, ap 77 4c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c4"; + reg = <0x150000 0x8>, + <0x150010 0x8>, + <0x150090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */ + clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x150000 0x1000>; + + i2c4: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 5501d1b4e6cd..27895c1604b9 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -5,6 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <dt-bindings/input/input.h> #include "elpida_ecb240abacn.dtsi" / { @@ -43,6 +44,21 @@ }; }; + gpio_keys: gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = < + &button_pins + >; + + buttonS2 { + label = "button S2"; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ + linux,code = <BTN_0>; + wakeup-source; + }; + }; + sound: sound { compatible = "ti,abe-twl6040"; ti,model = "PandaBoard"; @@ -357,6 +373,12 @@ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ >; }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ + >; + }; }; &omap4_pmx_wkup { @@ -464,7 +486,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 940fe4f7c5f6..19d02df8d8a5 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -46,6 +46,12 @@ OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ >; }; + + button_pins: pinmux_button_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ + >; + }; }; &led_wkgpio_pins { @@ -68,6 +74,12 @@ }; }; -&gpio1 { +&gpio_keys { + buttonS2 { + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */ + }; +}; + +&gpio1_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 280d92d42bf1..490726b52216 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -493,7 +493,7 @@ compatible = "ti,wl1281"; reg = <2>; interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */ + interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */ ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi index 1c5f6f35e1cf..878923473023 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi @@ -72,7 +72,7 @@ compatible = "ti,wl1271"; reg = <2>; interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */ + interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */ ref-clock-frequency = <38400000>; }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index e554b6e039f3..1a96d4317c97 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -139,174 +139,13 @@ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - l4_cfg: l4@4a000000 { - compatible = "ti,omap4-l4-cfg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x1000000>; - - cm1: cm1@4000 { - compatible = "ti,omap4-cm1", "simple-bus"; - reg = <0x4000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4000 0x2000>; - - cm1_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm1_clockdomains: clockdomains { - }; - }; - - cm2: cm2@8000 { - compatible = "ti,omap4-cm2", "simple-bus"; - reg = <0x8000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8000 0x2000>; - - cm2_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm2_clockdomains: clockdomains { - }; - }; - - omap4_scm_core: scm@2000 { - compatible = "ti,omap4-scm-core", "simple-bus"; - reg = <0x2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x1000>; - ti,hwmods = "ctrl_module_core"; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - omap4_padconf_core: scm@100000 { - compatible = "ti,omap4-scm-padconf-core", - "simple-bus"; - reg = <0x100000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x100000 0x1000>; - ti,hwmods = "ctrl_module_pad_core"; - - omap4_pmx_core: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap4_padconf_global: omap4_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0x170>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0x170>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap4", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap4_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap4 { - regulator-name = "pbias_mmc_omap4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; - }; - - l4_wkup: l4@300000 { - compatible = "ti,omap4-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300000 0x40000>; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x20>; - ti,hwmods = "counter_32k"; - }; - - prm: prm@6000 { - compatible = "ti,omap4-prm"; - reg = <0x6000 0x2000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x6000 0x2000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@a000 { - compatible = "ti,omap4-scrm"; - reg = <0xa000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - omap4_scm_wkup: scm@c000 { - compatible = "ti,omap4-scm-wkup"; - reg = <0xc000 0x1000>; - ti,hwmods = "ctrl_module_wkup"; - }; + l4_wkup: interconnect@4a300000 { + }; - omap4_padconf_wkup: padconf@1e000 { - compatible = "ti,omap4-scm-padconf-wkup", - "simple-bus"; - reg = <0x1e000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e000 0x1000>; - ti,hwmods = "ctrl_module_pad_wkup"; + l4_cfg: interconnect@4a000000 { + }; - omap4_pmx_wkup: pinmux@40 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x40 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - }; - }; + l4_per: interconnect@48000000 { }; ocmcram: ocmcram@40304000 { @@ -314,114 +153,6 @@ reg = <0x40304000 0xa000>; /* 40k */ }; - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - ti,hwmods = "dma_system"; - }; - - gpio1: gpio@4a310000 { - compatible = "ti,omap4-gpio"; - reg = <0x4a310000 0x200>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - reg = <0x48055000 0x200>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - reg = <0x48057000 0x200>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - reg = <0x48059000 0x200>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805b000 0x200>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805d000 0x200>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - target-module@48076000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "slimbus2"; - reg = <0x48076000 0x4>, - <0x48076010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48076000 0x001000>; - - /* No child device binding or driver in mainline */ - }; - - elm: elm@48078000 { - compatible = "ti,am3352-elm"; - reg = <0x48078000 0x2000>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "elm"; - status = "disabled"; - }; - gpmc: gpmc@50000000 { compatible = "ti,omap4430-gpmc"; reg = <0x50000000 0x1000>; @@ -442,302 +173,6 @@ #gpio-cells = <2>; }; - uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap4-uart"; - reg = <0x4806c000 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - }; - - uart3: serial@48020000 { - compatible = "ti,omap4-uart"; - reg = <0x48020000 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - }; - - uart4: serial@4806e000 { - compatible = "ti,omap4-uart"; - reg = <0x4806e000 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - - target-module@4a0db000 { - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_iva"; - reg = <0x4a0db038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a0db000 0x001000>; - - smartreflex_iva: smartreflex@0 { - compatible = "ti,omap4-smartreflex-iva"; - reg = <0 0x80>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@4a0dd000 { - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0x4a0dd038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a0dd000 0x001000>; - - smartreflex_core: smartreflex@0 { - compatible = "ti,omap4-smartreflex-core"; - reg = <0 0x80>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@4a0d9000 { - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu"; - reg = <0x4a0d9038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a0d9000 0x001000>; - - smartreflex_mpu: smartreflex@0 { - compatible = "ti,omap4-smartreflex-mpu"; - reg = <0 0x80>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - reg = <0x48070000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - reg = <0x48072000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - reg = <0x48060000 0x100>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - i2c4: i2c@48350000 { - compatible = "ti,omap4-i2c"; - reg = <0x48350000 0x100>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "hdq1w"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480b4000 0x400>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480ad000 0x400>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d1000 0x400>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc4"; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - - mmc5: mmc@480d5000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d5000 0x400>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc5"; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - - hsi: hsi@4a058000 { - compatible = "ti,omap4-hsi"; - reg = <0x4a058000 0x4000>, - <0x4a05c000 0x1000>; - reg-names = "sys", "gdd"; - ti,hwmods = "hsi"; - - clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; - clock-names = "hsi_fck"; - - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gdd_mpu"; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a058000 0x4000>; - - hsi_port1: hsi-port@2000 { - compatible = "ti,omap4-hsi-port"; - reg = <0x2000 0x800>, - <0x2800 0x800>; - reg-names = "tx", "rx"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - }; - - hsi_port2: hsi-port@3000 { - compatible = "ti,omap4-hsi-port"; - reg = <0x3000 0x800>, - <0x3800 0x800>; - reg-names = "tx", "rx"; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; @@ -779,20 +214,33 @@ #iommu-cells = <0>; ti,iommu-bus-err-back; }; - - wdt2: wdt@4a314000 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x4a314000 0x80>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "wd_timer2"; - }; - - wdt3: wdt@40130000 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x40130000 0x80>, /* MPU private access */ - <0x49030000 0x80>; /* L3 Interconnect */ - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + target-module@40130000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "wd_timer3"; + reg = <0x40130000 0x4>, + <0x40130010 0x4>, + <0x40130014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */ + <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */ + + wdt3: wdt@0 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + }; }; mcpdm: mcpdm@40132000 { @@ -938,28 +386,6 @@ */ }; - mcbsp4: mcbsp@48096000 { - compatible = "ti,omap4-mcbsp"; - reg = <0x48096000 0xff>; /* L4 Interconnect */ - reg-names = "mpu"; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common"; - ti,buffer-size = <128>; - ti,hwmods = "mcbsp4"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - keypad: keypad@4a31c000 { - compatible = "ti,omap4-keypad"; - reg = <0x4a31c000 0x80>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - reg-names = "mpu"; - ti,hwmods = "kbd"; - }; - dmm@4e000000 { compatible = "ti,omap4-dmm"; reg = <0x4e000000 0x800>; @@ -991,95 +417,6 @@ hw-caps-temp-alert; }; - ocp2scp@4a0ad000 { - compatible = "ti,omap-ocp2scp"; - reg = <0x4a0ad000 0x1f>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp_usb_phy"; - usb2_phy: usb2phy@4a0ad080 { - compatible = "ti,omap-usb2"; - reg = <0x4a0ad080 0x58>; - ctrl-module = <&omap_control_usb2phy>; - clocks = <&usb_phy_cm_clk32k>; - clock-names = "wkupclk"; - #phy-cells = <0>; - }; - }; - - mailbox: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - - target-module@4a10a000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "fdif"; - reg = <0x4a10a000 0x4>, - <0x4a10a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-delay-us = <2>; - clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a10a000 0x1000>; - - /* No child device binding or driver in mainline */ - }; - - timer1: timer@4a318000 { - compatible = "ti,omap3430-timer"; - reg = <0x4a318000 0x80>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - }; - - timer2: timer@48032000 { - compatible = "ti,omap3430-timer"; - reg = <0x48032000 0x80>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48034000 { - compatible = "ti,omap4430-timer"; - reg = <0x48034000 0x80>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48036000 { - compatible = "ti,omap4430-timer"; - reg = <0x48036000 0x80>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer4"; - }; - timer5: timer@40138000 { compatible = "ti,omap4430-timer"; reg = <0x40138000 0x80>, @@ -1117,92 +454,6 @@ ti,timer-dsp; }; - timer9: timer@4803e000 { - compatible = "ti,omap4430-timer"; - reg = <0x4803e000 0x80>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap3430-timer"; - reg = <0x48086000 0x80>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap4430-timer"; - reg = <0x48088000 0x80>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3"; - reg = <0x4a064800 0x400>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - remote-wakeup-connected; - }; - - usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap"; - reg = <0x4a064c00 0x400>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - omap_control_usb2phy: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usbotg: control-phy@4a00233c { - compatible = "ti,control-phy-otghs"; - reg = <0x4a00233c 0x4>; - reg-names = "otghs_control"; - }; - - usb_otg_hs: usb_otg_hs@4a0ab000 { - compatible = "ti,omap4-musb"; - reg = <0x4a0ab000 0x7ff>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - ctrl-module = <&omap_control_usbotg>; - }; - aes1: aes@4b501000 { compatible = "ti,omap4-aes"; ti,hwmods = "aes1"; @@ -1377,4 +628,5 @@ }; }; +#include "omap4-l4.dtsi" #include "omap44xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index ad97493e4e46..2223dc0d63c0 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -92,4 +92,40 @@ coefficients = <348 (-9301)>; }; +/* Only some L4 CFG interconnect ranges are different on 4460 */ +&l4_cfg_segment_300000 { + ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */ + <0x00040000 0x00340000 0x001000>, /* ap 68 */ + <0x00020000 0x00320000 0x004000>, /* ap 71 */ + <0x00024000 0x00324000 0x002000>, /* ap 72 */ + <0x00026000 0x00326000 0x001000>, /* ap 73 */ + <0x00027000 0x00327000 0x001000>, /* ap 74 */ + <0x00028000 0x00328000 0x001000>, /* ap 75 */ + <0x00029000 0x00329000 0x001000>, /* ap 76 */ + <0x00030000 0x00330000 0x010000>, /* ap 77 */ + <0x0002a000 0x0032a000 0x002000>, /* ap 90 */ + <0x0002c000 0x0032c000 0x004000>, /* ap 91 */ + <0x00010000 0x00310000 0x008000>, /* ap 92 */ + <0x00018000 0x00318000 0x004000>, /* ap 93 */ + <0x0001c000 0x0031c000 0x002000>, /* ap 94 */ + <0x0001e000 0x0031e000 0x002000>; /* ap 95 */ +}; + +&l4_cfg_target_0 { + ranges = <0x00000000 0x00000000 0x00010000>, + <0x00010000 0x00010000 0x00008000>, + <0x00018000 0x00018000 0x00004000>, + <0x0001c000 0x0001c000 0x00002000>, + <0x0001e000 0x0001e000 0x00002000>, + <0x00020000 0x00020000 0x00004000>, + <0x00024000 0x00024000 0x00002000>, + <0x00026000 0x00026000 0x00001000>, + <0x00027000 0x00027000 0x00001000>, + <0x00028000 0x00028000 0x00001000>, + <0x00029000 0x00029000 0x00001000>, + <0x0002a000 0x0002a000 0x00002000>, + <0x0002c000 0x0002c000 0x00004000>, + <0x00030000 0x00030000 0x00010000>; +}; + /include/ "omap446x-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 3b2244560c28..ab6f640b282b 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -364,7 +364,7 @@ pinctrl-names = "default"; pinctrl-0 = <&wlcore_irq_pin>; interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ + interrupts = <14 IRQ_TYPE_EDGE_RISING>; /* gpio 14 */ ref-clock-frequency = <26000000>; }; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 732b61a0e990..574ac11c0489 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -61,6 +61,20 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1500000 1250000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index e4ebcde17837..a520b4c14ea9 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -141,7 +141,7 @@ interrupts = <30 31>; }; - lcd-controller@40500000 { + lcdc: lcd-controller@40500000 { compatible = "marvell,pxa2xx-lcdc"; reg = <0x44000000 0x10000>; interrupts = <17>; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 132a3b8ab148..3a8f0edc3af9 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -135,6 +135,7 @@ reg = <0x43100000 90>; interrupts = <45>; clocks = <&clks CLK_NAND>; + clock-names = "core"; dmas = <&pdma 97 3>; dma-names = "data"; #address-cells = <1>; @@ -242,6 +243,38 @@ clocks = <&clks CLK_PWM1>; status = "disabled"; }; + + ssp1: ssp@41000000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41000000 0x40>; + interrupts = <24>; + clocks = <&clks CLK_SSP1>; + status = "disabled"; + }; + + ssp2: ssp@41700000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41700000 0x40>; + interrupts = <16>; + clocks = <&clks CLK_SSP2>; + status = "disabled"; + }; + + ssp3: ssp@41900000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41900000 0x40>; + interrupts = <0>; + clocks = <&clks CLK_SSP3>; + status = "disabled"; + }; + + ssp4: ssp@41a00000 { + compatible = "mrvl,pxa3xx-ssp"; + reg = <0x41a00000 0x40>; + interrupts = <13>; + clocks = <&clks CLK_SSP4>; + status = "disabled"; + }; }; clocks { diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 7bcd7635e723..78db67337ed4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -77,6 +77,14 @@ reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; cpu@2 { @@ -88,6 +96,14 @@ reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; cpu@3 { @@ -99,6 +115,14 @@ reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 1e0a3b446f7a..70790ac242d1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,gcc-ipq806x.h> #include <dt-bindings/clock/qcom,lcc-ipq806x.h> #include <dt-bindings/soc/qcom,gsbi.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { model = "Qualcomm IPQ8064"; @@ -43,7 +44,8 @@ cpu-pmu { compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; + interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; }; reserved-memory { @@ -97,7 +99,7 @@ clock-names = "ahbix-clk", "mi2s-osr-clk", "mi2s-bit-clk"; - interrupts = <0 85 1>; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; interrupt-names = "lpass-irq-lpaif"; reg = <0x28100000 0x10000>; reg-names = "lpass-lpaif"; @@ -111,7 +113,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 16 0x4>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; }; intc: interrupt-controller@2000000 { @@ -125,11 +127,16 @@ timer@200a000 { compatible = "qcom,kpss-timer", "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>, - <1 4 0x301>, - <1 5 0x301>; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>; reg = <0x0200a000 0x100>; clock-frequency = <25000000>, <32768>; @@ -177,7 +184,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12490000 0x1000>, <0x12480000 0x1000>; - interrupts = <0 195 0x0>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -186,7 +193,7 @@ i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; - interrupts = <0 196 0>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; clock-names = "core", "iface"; @@ -215,7 +222,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16340000 0x1000>, <0x16300000 0x1000>; - interrupts = <0 152 0x0>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -224,7 +231,7 @@ i2c@16380000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; clock-names = "core", "iface"; @@ -252,7 +259,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x1000>, <0x1a200000 0x1000>; - interrupts = <0 154 0x0>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -261,7 +268,7 @@ i2c@1a280000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -274,7 +281,7 @@ spi@1a280000 { compatible = "qcom,spi-qup-v1.1.1"; reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -301,7 +308,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; - interrupts = <0 158 0x0>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -323,7 +330,7 @@ compatible = "qcom,ipq806x-ahci", "generic-ahci"; reg = <0x29000000 0x180>; - interrupts = <0 209 0x0>; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SFAB_SATA_S_H_CLK>, <&gcc SATA_H_CLK>, diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 4dc0b347b1ee..c2dc9d09484a 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -189,6 +189,8 @@ regulator-max-microvolt = <2950000>; regulator-boot-on; + regulator-system-load = <200000>; + regulator-allow-set-load; }; l21 { diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 5af2a0116ff2..474baa0c7cfc 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Genmai board * * Copyright (C) 2013-14 Renesas Solutions Corp. * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index 779f724b4531..fe1a4aa4d7cb 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the GR-Peach board * * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org> * Copyright (C) 2016 Renesas Electronics - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index 5dcaaf131d27..8ee44a100e9a 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the RZ/A1H RSK board * * Copyright (C) 2016 Renesas Electronics - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index a54822e97bac..2211f88ede2a 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r7s72100 SoC * * Copyright (C) 2013-14 Renesas Solutions Corp. * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r7s72100-clock.h> diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 125c39c0222f..d530f451467e 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the APE6EVM board * * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 080d037f5733..dd865f3c2eda 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a73a4 SoC * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Magnus Damm - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a73a4-clock.h> diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 03b00d87b39b..32757caa2584 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the armadillo 800 eva board * * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index eb9a911deefb..383cba68dbba 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7740 SoC * * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7740-clock.h> diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts index d90eb8464222..327545119ee3 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 6aa6b7467704..b683db4da8b1 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZ/G1M Qseven board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index d364685d9184..0e2e033cc849 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZG1M-20M Qseven SOM * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7743.dtsi" diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts index 3d918d106593..ca0e0fc9b246 100644 --- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the SK-RZG1M board * * Copyright (C) 2016-2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 142949d7066f..24715f74ae08 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7743 SoC * * Copyright (C) 2016-2017 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/interrupt-controller/irq.h> @@ -98,8 +95,17 @@ reg = <1>; clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7743_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; L2_CA15: cache-controller-0 { diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts index d34de8266ccd..2aeebfc9e4f1 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZG1E SODIMM carrier board + HDMI daughter * board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7745-iwg22d-sodimm.dts" diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index a4058f4cfbcd..1db220cfc1a1 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZG1E SODIMM carrier board * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi index 29b6e10fdf96..41f111b99a75 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM * * Copyright (C) 2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7745.dtsi" diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts index b4d679b04ad6..655b10bb42d5 100644 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the SK-RZG1E board * * Copyright (C) 2016-2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 1cb7a7ab0418..c53f7ff20695 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7745 SoC * * Copyright (C) 2016-2017 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index c85032f9605b..87d32d3e23de 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -7,7 +7,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/renesas-cpg-mssr.h> +#include <dt-bindings/clock/r8a77470-cpg-mssr.h> / { compatible = "renesas,r8a77470"; #address-cells = <2>; @@ -22,7 +22,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE 0>; + clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; power-domains = <&sysc 5>; next-level-cache = <&L2_CA7>; }; @@ -209,7 +209,7 @@ reg = <0 0xe6e60000 0 0x40>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; @@ -225,7 +225,7 @@ reg = <0 0xe6e68000 0 0x40>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; @@ -241,7 +241,7 @@ reg = <0 0xe6e58000 0 0x40>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; @@ -257,7 +257,7 @@ reg = <0 0xe6ea8000 0 0x40>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; @@ -273,7 +273,7 @@ reg = <0 0xe6ee0000 0 0x40>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 715>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, <&dmac1 0xfb>, <&dmac1 0xfc>; @@ -289,7 +289,7 @@ reg = <0 0xe6ee8000 0 0x40>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 714>, - <&cpg CPG_CORE 5>, <&scif_clk>; + <&cpg CPG_CORE R8A77470_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, <&dmac1 0xfd>, <&dmac1 0xfe>; diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index c79d55eb43c5..de808d2ea856 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Reference Device Tree Source for the Bock-W board * @@ -8,10 +9,6 @@ * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 3b49f9ed2e2b..1bce16cc6b20 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Renesas r8a7778 * @@ -8,10 +9,6 @@ * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7778-clock.h> diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 4b9006bac3cb..a4d0038363f0 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Marzen board * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index e79ae306eedd..6b997bc016ee 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Renesas r8a7779 * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7779-clock.h> diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 092610e3f953..50312e752e2f 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Lager board * * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded, Inc. * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 4d06b154bd7e..0925bdca438f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7790 SoC * * Copyright (C) 2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7790-cpg-mssr.h> @@ -79,12 +76,12 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1300000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -104,6 +101,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu2: cpu@2 { @@ -115,6 +122,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu3: cpu@3 { @@ -126,6 +143,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu4: cpu@100 { diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 8ab793d8b2fd..ce22db01fbba 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Koelsch board * * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index a01101b49d99..f02036e5de01 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Porter board * * Copyright (C) 2015 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* @@ -375,10 +372,43 @@ clock-frequency = <400000>; }; +&i2c6 { + status = "okay"; + clock-frequency = <100000>; + + pmic@5a { + compatible = "dlg,da9063l"; + reg = <0x5a>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + &sata0 { status = "okay"; }; +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + /* composite video input */ &vin0 { status = "okay"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 6e1dd7ad7bd6..991ac6feedd5 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7791 SoC * * Copyright (C) 2013-2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7791-cpg-mssr.h> @@ -78,11 +75,11 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -101,6 +98,16 @@ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; L2_CA15: cache-controller-0 { diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 04fb70931b3b..f92301290b02 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Blanche board * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index db01de7a3811..f46f4567b3d4 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Wheat board * * Copyright (C) 2016 Renesas Electronics Corporation * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index f44257dd86f6..63a978ec81cc 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7792 SoC * * Copyright (C) 2016 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7792-cpg-mssr.h> diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index aa209f6e5d71..6b2f3a4fd13d 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Gose board * * Copyright (C) 2014-2015 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 4abecfc0ca98..620a570307ff 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7793 SoC * * Copyright (C) 2014-2015 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7793-cpg-mssr.h> @@ -70,10 +67,10 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7793_PD_CA15_CPU0>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -92,6 +89,17 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + next-level-cache = <&L2_CA15>; }; L2_CA15: cache-controller-0 { diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index e17027532941..ef7e2a837df6 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Alt board * * Copyright (C) 2014 Renesas Electronics Corporation - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 7808aaee6644..daec965889d3 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the SILK board * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2014-2015 Renesas Solutions Corp. * Copyright (C) 2014-2015 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 736196903d22..ea2ca4bdaf1c 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7794 SoC * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2014 Ulrich Hecht - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7794-cpg-mssr.h> diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi index 238d14bb0ebe..79fce67ebb1c 100644 --- a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi +++ b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Common file for the AA104XD12 panel connected to Renesas R-Car boards * * Copyright (C) 2014 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ / { diff --git a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi index 04aafd479775..6e7589ea7562 100644 --- a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi +++ b/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Common file for the AA121TD01 panel connected to Renesas R-Car boards * * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ / { diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts new file mode 100644 index 000000000000..4e57ae2688fc --- /dev/null +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZN1D-DB Board + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +/dts-v1/; + +#include "r9a06g032.dtsi" + +/ { + model = "RZN1D-DB Board"; + compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi new file mode 100644 index 000000000000..afe29c95a006 --- /dev/null +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "renesas,r9a06g032"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clocks = <&sysctrl 84>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clocks = <&sysctrl 84>; + enable-method = "renesas,r9a06g032-smp"; + cpu-release-addr = <0 0x4000c204>; + }; + }; + + ext_jtag_clk: extjtagclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_mclk: extmclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + + ext_rgmii_ref: extrgmiiref { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_rtc_clk: extrtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + status = "okay"; + #clock-cells = <1>; + + clocks = <&ext_mclk>, <&ext_rtc_clk>, + <&ext_jtag_clk>, <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + }; + + uart0: serial@40060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl 146>; + clock-names = "baudclk"; + status = "disabled"; + }; + + gic: gic@44101000 { + compatible = "arm,cortex-a7-gic", "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x44101000 0x1000>, /* Distributer */ + <0x44102000 0x2000>, /* CPU interface */ + <0x44104000 0x2000>, /* Virt interface control */ + <0x44106000 0x2000>; /* Virt CPU interface */ + interrupts = + <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + timer { + compatible = "arm,cortex-a7-timer", + "arm,armv7-timer"; + interrupt-parent = <&gic>; + arm,cpu-registers-not-fw-configured; + always-on; + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts index c0953410121b..2a7e6624efb9 100644 --- a/arch/arm/boot/dts/rk3036-evb.dts +++ b/arch/arm/boot/dts/rk3036-evb.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index e2a0f576946f..0fd19f9723df 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 567a6a725f9c..67f57200d9a0 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index ef1eabf2512c..1c925f20dba0 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index d23ee6d911ac..ce525b956ae5 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014 Romain Perier <romain.perier@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 13e285c53def..b6a8a82d219e 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 PaweÅ‚ Jarosz <paweljarosz3691@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 4d7057a10a4c..cd126b927ba8 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 06523caca27d..2ab3c4b32003 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index 8ba9e06062f3..375129b62102 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andy Yan <andy.yan@rock-chips.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 00e05a6662ac..45fd2b302dda 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index aa10caae51c3..aa123f93f181 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index 1be9daacc4f9..5670b33fd1bd 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 73e384585755..4df7accc3ad7 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi index 6fe6c15fc13a..cb7d3fad8e60 100644 --- a/arch/arm/boot/dts/rk3229.dtsi +++ b/arch/arm/boot/dts/rk3229.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "rk322x.dtsi" diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index be80e9a2c9af..cd8f2a3b0e91 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -80,6 +42,7 @@ reg = <0xf01>; resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ enable-method = "psci"; }; @@ -89,6 +52,7 @@ reg = <0xf02>; resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ enable-method = "psci"; }; @@ -98,6 +62,7 @@ reg = <0xf03>; resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ enable-method = "psci"; }; }; diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index b9418d170502..6592c809e2a5 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; #include "rk3288-evb.dtsi" diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index 56c266df01c1..16788209625b 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; #include "rk3288-evb.dtsi" diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 39b61dce97ad..97e4d552ff0f 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include <dt-bindings/input/input.h> #include <dt-bindings/pwm/pwm.h> @@ -232,7 +194,7 @@ #address-cells = <1>; #size-cells = <0>; - edp_out_panel: endpoint { + edp_out_panel: endpoint@0 { reg = <0>; remote-endpoint = <&panel_in_edp>; }; diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts index 41405974253a..b1b56dfdfdba 100644 --- a/arch/arm/boot/dts/rk3288-fennec.dts +++ b/arch/arm/boot/dts/rk3288-fennec.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts index 0195d9721660..0f3c29d7fbab 100644 --- a/arch/arm/boot/dts/rk3288-firefly-beta.dts +++ b/arch/arm/boot/dts/rk3288-firefly-beta.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index 5f1e336dbaac..f57f286a93c3 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device tree file for Firefly Rockchip RK3288 Core board * Copyright (c) 2016 Randy Li <ayaka@soulik.info> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index eab176e3dfc3..58ea8bed040a 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device tree file for Firefly Rockchip RK3288 Core board * Copyright (c) 2016 Randy Li <ayaka@soulik.info> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts index 14271be72f30..556ab42dd81c 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dts +++ b/arch/arm/boot/dts/rk3288-firefly.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index b9e6f3a97240..a6ff7eac4aa8 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 4d923aa6ed11..504ab1177aa7 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts index 985743fa134c..7077c3403483 100644 --- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device tree file for Phytec PCM-947 carrier board * Copyright (C) 2017 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index aaab2d171ffe..c218dd54c9b5 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device tree file for Phytec phyCORE-RK3288 SoM * Copyright (C) 2017 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/net/ti-dp83867.h> diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index c06d0f4ceb81..596435e03132 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2014, 2015 Andy Yan <andy.yan@rock-chips.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index e95215c9788b..28972fb4e221 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index 51f36a1b698e..50325489c0ce 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include <dt-bindings/pwm/pwm.h> #include "rk3288.dtsi" diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index 8ccc89dbdfaf..6a30cadad88a 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts index 127488f9f174..ceade5962899 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dts +++ b/arch/arm/boot/dts/rk3288-tinker.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi index 280aceae25d5..eaf921694e68 100644 --- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Google Veyron (and derivatives) fragment for the max98090 audio * codec and analog headphone jack. * * Copyright 2016 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ / { diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts index ed4255294ad4..5c94a33d695d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-brain.dts +++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Brain Rev 0 board device tree source * * Copyright 2014 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index b16d570ff029..b54746df3661 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -1,46 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron (and derivatives) board device tree source * Chromebook specific parts * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/rockchip,rk808.h> @@ -174,7 +137,7 @@ reg = <1>; #address-cells = <1>; #size-cells = <0>; - edp_out_panel: endpoint { + edp_out_panel: endpoint@0 { reg = <0>; remote-endpoint = <&panel_in_edp>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index d33f5763c39c..9d6814c7f285 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Jaq Rev 1+ board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index cdea751f2a8c..2ba89895c33a 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Jerry Rev 3+ board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts index f0994f0e5774..1e0158acf895 100644 --- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts +++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Mickey Rev 0 board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 4c5307e62001..f95d0c5fcf71 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Minnie Rev 0+ board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 995cff42fa43..2950aadf49f0 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Pinky Rev 2 board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi index 95e9bee8bca2..a4570444cc79 100644 --- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron (and derivatives) fragment for sdmmc cards * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ &io_domains { diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index cc0b78cefe34..e16421d80d22 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron Speedy Rev 1+ board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 6e5bd8974f22..2075120cfc4d 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Veyron (and derivatives) board device tree source * * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/rockchip,rk808.h> @@ -128,22 +91,26 @@ &cpu0 { cpu0-supply = <&vdd_cpu>; - operating-points = < - /* KHz uV */ - 1800000 1400000 - 1704000 1350000 - 1608000 1300000 - 1512000 1250000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 216000 900000 - 126000 900000 - >; +}; + +/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ +&cpu_opp_table { + /delete-node/ opp-312000000; + + opp-1512000000 { + opp-microvolt = <1250000>; + }; + opp-1608000000 { + opp-microvolt = <1300000>; + }; + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <1350000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1400000>; + }; }; &emmc { diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 14c896bfc639..4856a9fc0aea 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index d7e49d29ace5..0840ffb3205c 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -98,21 +60,7 @@ compatible = "arm,cortex-a12"; reg = <0x500>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 1608000 1350000 - 1512000 1300000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 312000 900000 - 216000 900000 - 126000 900000 - >; + operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; @@ -122,18 +70,84 @@ compatible = "arm,cortex-a12"; reg = <0x501>; resets = <&cru SRST_CORE1>; + operating-points = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu2: cpu@502 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x502>; resets = <&cru SRST_CORE2>; + operating-points = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu3: cpu@503 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x503>; resets = <&cru SRST_CORE3>; + operating-points = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + }; + + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-126000000 { + opp-hz = /bits/ 64 <126000000>; + opp-microvolt = <900000>; + }; + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <900000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <900000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + }; + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <950000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1200000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1300000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; }; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 49584b6a4195..d752dc611fd7 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 70f0106d1252..203d83e3bbf5 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 76ea24636feb..ed8f6ca52c5b 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -1,42 +1,4 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi new file mode 100644 index 000000000000..575094ea7024 --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5PV210 based Galaxy Aries board device tree source + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "s5pv210.dtsi" + +/ { + compatible = "samsung,aries", "samsung,s5pv210"; + + aliases { + i2c6 = &i2c_pmic; + i2c9 = &i2c_fuel; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x05000000 + 0x40000000 0x10000000 + 0x50000000 0x08000000>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_gpio_rst>; + post-power-on-delay-ms = <500>; + power-off-delay-us = <500>; + }; + + i2c_pmic: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max8998"; + reg = <0x66>; + interrupt-parent = <&gph0>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + max8998,pmic-buck1-default-dvs-idx = <1>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>, + <1050000>, <950000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; + max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3600000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VLCD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* Till we get panel driver */ + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_AF_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VGA_VDDIO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VGA_DVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_ISP_HOST_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VGA_AVDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* Till we get panel driver */ + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "vddarm"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1250000>; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "vddint"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + + cp32khz_reg: EN32KHz-CP { + regulator-name = "32KHz CP"; + }; + + vichg_reg: ENVICHG { + regulator-name = "VICHG"; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + }; + }; + }; + }; + + i2c_fuel: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fuelgauge@36 { + compatible = "maxim,max17040"; + interrupt-parent = <&vic0>; + interrupts = <7>; + reg = <0x36>; + }; + }; +}; + +&fimd { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_clk &lcd_data24>; + status = "okay"; + + samsung,invert-vden; + samsung,invert-vclk; + + display-timings { + timing-0 { + /* 480x800@60Hz */ + clock-frequency = <25628040>; + hactive = <480>; + vactive = <800>; + hfront-porch = <16>; + hback-porch = <16>; + hsync-len = <2>; + vfront-porch = <28>; + vback-porch = <1>; + vsync-len = <2>; + }; + }; +}; + +&hsotg { + vusb_a-supply = <&ldo8_reg>; + vusb_d-supply = <&ldo3_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&pinctrl0 { + wlan_bt_en: wlan-bt-en { + samsung,pins = "gpb-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-val = <1>; + }; + + wlan_gpio_rst: wlan-gpio-rst { + samsung,pins = "gpg1-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + }; + + wifi_host_wake: wifi-host-wake { + samsung,pins = "gph2-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + tf_detect: tf-detect { + samsung,pins = "gph3-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + wifi_wake: wifi-wake { + samsung,pins = "gph3-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + }; +}; + +&sdhci1 { + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + max-frequency = <38400000>; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>; + pinctrl-names = "default"; + cap-sd-highspeed; + cap-mmc-highspeed; + + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; + + wlan@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gph2>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <&ldo5_reg>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + status = "okay"; + vbus-supply = <&safe1_sreg>; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts new file mode 100644 index 000000000000..ccf761b1babf --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "s5pv210-aries.dtsi" + +/ { + model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210"; + compatible = "samsung,fascinate4g", "samsung,aries", "samsung,s5pv210"; + + chosen { + stdout-path = &uart2; + /* + * It's hard to change those parameters in stock bootloader, + * since it requires special hardware/cable. + * Let's hardocde bootargs for now, till u-boot port is finished, + * with which it should be easier. + */ + bootargs = "root=/dev/mmcblk1p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + gpios = <&gph2 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + wakeup-source; + }; + + vol-down { + label = "volume_down"; + gpios = <&gph3 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + vol-up { + label = "volume_up"; + gpios = <&gph3 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; +}; diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts new file mode 100644 index 000000000000..842276749717 --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "s5pv210-aries.dtsi" + +/ { + model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210"; + compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210"; + + chosen { + stdout-path = &uart2; + /* + * It's hard to change those parameters in stock bootloader, + * since it requires special hardware/cable. + * Let's hardocde bootargs for now, till u-boot port is finished, + * with which it should be easier. + */ + bootargs = "root=/dev/mmcblk2p1 rw rootwait ignore_loglevel earlyprintk"; + }; + + nand_pwrseq: nand-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&massmemory_en>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "power"; + gpios = <&gph2 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + wakeup-source; + }; + + vol-down { + label = "volume_down"; + gpios = <&gph3 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + vol-up { + label = "volume_up"; + gpios = <&gph3 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + home { + label = "home"; + gpios = <&gph3 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + wakeup-source; + }; + }; +}; + +&pinctrl0 { + massmemory_en: massmemory-en { + samsung,pins = "gpj2-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; +}; + +&sdhci0 { + bus-width = <4>; + non-removable; + mmc-pwrseq = <&nand_pwrseq>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 3a79feab11c3..7f0c9d447871 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -258,6 +258,8 @@ gph2: gph2 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/sama5d2-pinfunc.h b/arch/arm/boot/dts/sama5d2-pinfunc.h index e57191fb83de..1c01a6f843d8 100644 --- a/arch/arm/boot/dts/sama5d2-pinfunc.h +++ b/arch/arm/boot/dts/sama5d2-pinfunc.h @@ -375,7 +375,7 @@ #define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) #define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) #define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) -#define PIN_PB22__TDO PINMUX_PIN(PIN_PB22, 3, 1) +#define PIN_PB22__TD0 PINMUX_PIN(PIN_PB22, 3, 1) #define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) #define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) #define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) @@ -556,7 +556,7 @@ #define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) #define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) #define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) -#define PIN_PC14__TDO PINMUX_PIN(PIN_PC14, 5, 2) +#define PIN_PC14__TD0 PINMUX_PIN(PIN_PC14, 5, 2) #define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) #define PIN_PC15 79 #define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index eae5e1ee9cd8..1408fa4a62e4 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -494,7 +494,7 @@ atmel,external-irqs = <47>; }; - pinctrl@fffff200 { + pinctrl: pinctrl@fffff200 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; @@ -1340,13 +1340,13 @@ }; }; - rstc@fffffe00 { + reset_controller: rstc@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; }; - shutdown-controller@fffffe10 { + shutdown_controller: shutdown-controller@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; @@ -1359,7 +1359,7 @@ clocks = <&mck>; }; - watchdog@fffffe40 { + watchdog: watchdog@fffffe40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 0cf9beddd556..92a35a1942b6 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -392,7 +392,7 @@ }; pmc: pmc@f0018000 { - compatible = "atmel,sama5d3-pmc", "syscon"; + compatible = "atmel,sama5d4-pmc", "syscon"; reg = <0xf0018000 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-controller; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 3d65f1f6d78b..daac0c6078c5 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the KZM-A9-GT board * @@ -5,10 +6,6 @@ * * Based on sh73a0-kzm9g.dts * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index c953648a5f41..e8f0a07c4564 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the SH73A0 SoC * * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/sh73a0-clock.h> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 791ca15c799e..a4dcb68f4322 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -587,6 +587,18 @@ status = "disabled"; }; + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x100>; + interrupts = <0 101 4>; + num-cs = <4>; + /*32bit_access;*/ + clocks = <&spi_m_clk>; + status = "disabled"; + }; + spi1: spi@ffda5000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 733678b75b88..fca76a696d9d 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -661,7 +661,6 @@ reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; clocks = <&hclksmc>; status = "okay"; - timings = /bits/ 8 <0 0 0 0x10 0x0a 0>; partition@0 { label = "X-Loader(NAND)"; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index ede77e0f1c41..e35d782e7e5f 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -302,7 +302,7 @@ interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; @@ -310,6 +310,7 @@ compatible = "st,stm32-iwdg"; reg = <0x40003000 0x400>; clocks = <&clk_lsi>; + clock-names = "lsi"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 1479e3eb05fa..f48d06a80d1d 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -297,7 +297,7 @@ interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 4839db146890..c4851271e810 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -157,6 +157,52 @@ }; }; + ethernet0_rgmii_pins_a: rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ @@ -187,6 +233,19 @@ }; }; + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -281,7 +340,6 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - status = "disabled"; gpioz: gpio@54004000 { gpio-controller; @@ -305,6 +363,21 @@ slew-rate = <0>; }; }; + + spi1_pins_a: spi1-0 { + pins1 { + pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index ae336530b59b..f77bea49c079 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -49,10 +49,27 @@ }; }; +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + &rng1 { status = "okay"; }; +&rtc { + status = "okay"; +}; + &timers6 { status = "okay"; timer@5 { @@ -60,14 +77,6 @@ }; }; -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 9382d8063031..372bc2ea6b92 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -17,6 +17,26 @@ aliases { serial0 = &uart4; + ethernet0 = ðernet0; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; @@ -42,6 +62,12 @@ status = "okay"; }; +&m_can1 { + pinctrl-names = "default"; + pinctrl-0 = <&m_can1_pins_a>; + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; @@ -67,6 +93,12 @@ }; }; +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "disabled"; +}; + &timers2 { status = "disabled"; pwm { @@ -103,6 +135,19 @@ }; }; +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + &usbphyc { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 7d1753893453..661be948ab74 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -35,20 +35,6 @@ cpu_on = <0x84000003>; }; - aliases { - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; - }; - intc: interrupt-controller@a0021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; @@ -311,6 +297,34 @@ }; }; + spi2: spi@4000b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 39 0x400 0x05>, + <&dmamux1 40 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + dmas = <&dmamux1 61 0x400 0x05>, + <&dmamux1 62 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; @@ -494,6 +508,34 @@ status = "disabled"; }; + spi1: spi@44004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@44005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44005000 0x400>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + dmas = <&dmamux1 83 0x400 0x05>, + <&dmamux1 84 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timers15: timer@44006000 { #address-cells = <1>; #size-cells = <0>; @@ -556,6 +598,116 @@ }; }; + spi5: spi@44009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44009000 0x400>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + dmas = <&dmamux1 85 0x400 0x05>, + <&dmamux1 86 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <0>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <1>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm2: filter@2 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <2>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 103 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm3: filter@3 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <3>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 104 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm4: filter@4 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <4>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 91 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm5: filter@5 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <5>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 92 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + dma1: dma@48000000 { compatible = "st,stm32-dma"; reg = <0x48000000 0x400>; @@ -600,6 +752,57 @@ clocks = <&rcc DMAMUX>; }; + adc: adc@48003000 { + compatible = "st,stm32mp1-adc-core"; + reg = <0x48003000 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + adc2: adc@100 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + interrupt-parent = <&adc>; + interrupts = <1>; + dmas = <&dmamux1 10 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + + usbotg_hs: usb-otg@49000000 { + compatible = "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + dr_mode = "otg"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -614,6 +817,11 @@ reg = <0x5000d000 0x400>; }; + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + }; + lptimer2: timer@50021000 { #address-cells = <1>; #size-cells = <0>; @@ -709,6 +917,18 @@ status = "disabled"; }; + hash1: hash@54002000 { + compatible = "st,stm32f756-hash"; + reg = <0x54002000 0x400>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; + status = "disabled"; + }; + rng1: rng@54003000 { compatible = "st,stm32-rng"; reg = <0x54003000 0x400>; @@ -744,6 +964,36 @@ status = "disabled"; }; + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + ethernet0: ethernet@5800a000 { + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "syscfg-clk"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHSTP>, + <&rcc SYSCFG>; + st,syscon = <&syscfg 0x4>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; + status = "disabled"; + }; + usbh_ohci: usbh-ohci@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; @@ -784,6 +1034,14 @@ status = "disabled"; }; + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; @@ -812,6 +1070,20 @@ status = "disabled"; }; + spi6: spi@5c001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x5c001000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0>, + <&mdma1 35 0x0 0x40002 0x0 0x0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2c4: i2c@5c002000 { compatible = "st,stm32f7-i2c"; reg = <0x5c002000 0x400>; @@ -825,6 +1097,15 @@ status = "disabled"; }; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + clocks = <&rcc RTCAPB>, <&rcc RTC>; + clock-names = "pclk", "rtc_ck"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2c6: i2c@5c009000 { compatible = "st,stm32f7-i2c"; reg = <0x5c009000 0x400>; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 3a1c6b45c9a1..3d62a8950720 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -190,8 +190,8 @@ #size-cells = <1>; ranges; - sram-controller@1c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; + system-control@1c00000 { + compatible = "allwinner,sun4i-a10-system-control"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; @@ -1001,6 +1001,27 @@ status = "disabled"; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <69>, + <70>, + <71>, + <72>, + <73>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pmu"; + clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + fe0: display-frontend@1e00000 { compatible = "allwinner,sun4i-a10-display-frontend"; reg = <0x01e00000 0x20000>; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 07f2248ed5f8..8bfb36651177 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -114,8 +114,8 @@ #size-cells = <1>; ranges; - sram-controller@1c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; + system-control@1c00000 { + compatible = "allwinner,sun5i-a13-system-control"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; @@ -127,12 +127,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00000000 0xc000>; - }; - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; + emac_sram: sram-section@8000 { + compatible = "allwinner,sun5i-a13-sram-a3-a4", + "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "disabled"; + }; }; sram_d: sram@10000 { @@ -143,11 +144,26 @@ ranges = <0 0x00010000 0x1000>; otg_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-d"; + compatible = "allwinner,sun5i-a13-sram-d", + "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; }; }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun5i-a13-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; }; dma: dma-controller@1c02000 { diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c72992556a86..debc0bf22ea3 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -119,18 +119,48 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e529e4ff2174..9c52712af241 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -122,6 +122,19 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 960000 1400000 + 912000 1400000 + 864000 1300000 + 720000 1200000 + 528000 1100000 + 312000 1000000 + 144000 1000000 + >; + #cooling-cells = <2>; }; }; @@ -239,8 +252,9 @@ #size-cells = <1>; ranges; - sram-controller@1c00000 { - compatible = "allwinner,sun4i-a10-sram-controller"; + system-control@1c00000 { + compatible = "allwinner,sun7i-a20-system-control", + "allwinner,sun4i-a10-system-control"; reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>; @@ -254,7 +268,8 @@ ranges = <0 0x00000000 0xc000>; emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; + compatible = "allwinner,sun7i-a20-sram-a3-a4", + "allwinner,sun4i-a10-sram-a3-a4"; reg = <0x8000 0x4000>; status = "disabled"; }; @@ -268,11 +283,26 @@ ranges = <0 0x00010000 0x1000>; otg_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-d"; + compatible = "allwinner,sun7i-a20-sram-d", + "allwinner,sun4i-a10-sram-d"; reg = <0x0000 0x1000>; status = "disabled"; }; }; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun7i-a20-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; }; nmi_intc: interrupt-controller@1c00030 { diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 44f3cad3de75..c16ffcc4db7d 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -124,6 +124,28 @@ #size-cells = <1>; ranges; + system-control@1c00000 { + compatible = "allwinner,sun8i-a23-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x80000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-a23-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 8d278ee001e9..4e92741b24a7 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -132,21 +132,30 @@ }; cpu@1 { + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 36ecebaff3c0..1c012a4def16 100644 --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -79,6 +79,14 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + &ehci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 3b579d7567c8..c7ce4158d6c8 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -107,6 +107,14 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index 88decb0747ac..e5f0645e53a7 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -145,6 +145,14 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + &ehci0 { /* GL830 USB-to-SATA bridge here */ status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 2be23d600957..00a02b037320 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -902,8 +902,6 @@ reset-names = "stmmaceth"; clocks = <&ccu 27>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; mdio: mdio { diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 7d01f9322658..1db2541135a7 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -48,6 +48,23 @@ }; }; + reg_vdd_cpux: vdd-cpux-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + + gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ + enable-active-high; + gpios-states = <0x1>; + states = <1100000 0x0 + 1300000 0x1>; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -55,6 +72,10 @@ }; }; +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + &ehci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index cf1f970b0c6f..5d23667dc2d2 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -123,6 +123,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &hdmi { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 41d57c76f290..f0096074a467 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -84,21 +84,30 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; @@ -111,6 +120,28 @@ }; soc { + system-control@1c00000 { + compatible = "allwinner,sun8i-h3-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x80000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-h3-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + mali: gpu@1c40000 { compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; reg = <0x01c40000 0x10000>; diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 25fb048c7df2..c39b9169ea64 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -59,6 +59,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -94,6 +105,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -118,6 +133,16 @@ }; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; @@ -226,6 +251,10 @@ regulator-name = "vcc-wifi"; }; +&tcon_tv0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index bd97ca3dc2fa..ffd9f00f74a4 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -42,8 +42,10 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r40-ccu.h> #include <dt-bindings/reset/sun8i-r40-ccu.h> +#include <dt-bindings/reset/sun8i-de2.h> / { #address-cells = <1>; @@ -99,12 +101,75 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-r40-display-engine"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-r40-de2-clk", + "allwinner,sun8i-h3-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-r40-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + mixer0_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@1200000 { + compatible = "allwinner,sun8i-r40-de2-mixer-1"; + reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + mixer1_out_tcon_top: endpoint { + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; @@ -474,8 +539,6 @@ reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_GMAC>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; gmac_mdio: mdio { @@ -485,6 +548,213 @@ }; }; + tcon_top: tcon-top@1c70000 { + compatible = "allwinner,sun8i-r40-tcon-top"; + reg = <0x01c70000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>, + <&ccu CLK_TVE0>, + <&ccu CLK_TCON_TV1>, + <&ccu CLK_TVE1>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", + "tcon-tv0", + "tve0", + "tcon-tv1", + "tve1", + "dsi"; + clock-output-names = "tcon-top-tv0", + "tcon-top-tv1", + "tcon-top-dsi"; + resets = <&ccu RST_BUS_TCON_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon_top>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon_top>; + }; + }; + + tcon_top_mixer1_out: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + }; + + tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { + reg = <1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv1: endpoint@3 { + reg = <3>; + remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_tv0_out_tcon_top>; + }; + + tcon_top_hdmi_in_tcon_tv1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_tv1_out_tcon_top>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + + tcon_tv0: lcd-controller@1c73000 { + compatible = "allwinner,sun8i-r40-tcon-tv"; + reg = <0x01c73000 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_tv0_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + tcon_tv1: lcd-controller@1c74000 { + compatible = "allwinner,sun8i-r40-tcon-tv"; + reg = <0x01c74000 0x1000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV1>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_tv1_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; + }; + + tcon_tv1_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; + }; + }; + + tcon_tv1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_tv1_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; + }; + }; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, @@ -495,6 +765,51 @@ #interrupt-cells = <3>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-r40-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon_top: endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-r40-hdmi-phy", + "allwinner,sun50i-a64-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, + <&ccu 7>, <&ccu 16>; + clock-names = "bus", "mod", "pll-0", "pll-1"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; }; timer { diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c3bff1105e5d..fc6131315c47 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -506,8 +506,6 @@ reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; mdio: mdio { diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index f7ffdd6658a2..1eadc132390c 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -178,6 +178,15 @@ status = "okay"; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc_io>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &ohci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index eafff16765b4..1788556b4977 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -23,7 +23,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 7ed7370ee67a..3d3835591cd2 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -28,7 +28,7 @@ }; }; - memory { + memory@80000000 { /* memory >= 0x79600000 is reserved for firmware usage */ reg = <0x80000000 0x79600000>; }; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 7fc4a8b31e45..bfdd1bf61816 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -28,7 +28,7 @@ }; }; - memory { + memory@80000000 { /* memory >= 0x37e00000 is reserved for firmware usage */ reg = <0x80000000 0x37e00000>; }; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 84c4358dacac..0d7a6327e404 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -5,11 +5,16 @@ #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra114"; interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x0>; + }; host1x@50000000 { compatible = "nvidia,tegra114-host1x", "simple-bus"; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 3455822350c5..573aaa50fff1 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -15,7 +15,7 @@ compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", "nvidia,tegra124"; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 9f960c84ba10..0f0d4a4988b9 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -50,7 +50,7 @@ model = "Toradex Apalis TK1"; compatible = "toradex,apalis-tk1", "nvidia,tegra124"; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 6dbcf84dafbc..9151b3ebb839 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -24,7 +24,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 3609367037a6..d5f11d6d987e 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -13,7 +13,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 89bcc178994d..82d139648ef1 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 174092bfac90..183c5acafb22 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -7,14 +7,17 @@ #include <dt-bindings/reset/tegra124-car.h> #include <dt-bindings/thermal/tegra124-soctherm.h> -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra124"; interrupt-parent = <&lic>; #address-cells = <2>; #size-cells = <2>; + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + pcie@1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 40126388946d..57f16c0e9917 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include "tegra20-colibri-512.dtsi" +#include "tegra20-colibri.dtsi" / { - model = "Toradex Colibri T20 512MB on Iris"; + model = "Toradex Colibri T20 256/512 MB on Iris"; compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; aliases { diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 5c202b3e3bb1..e7b9ab09908a 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -2,7 +2,7 @@ #include "tegra20.dtsi" / { - model = "Toradex Colibri T20 512MB"; + model = "Toradex Colibri T20 256/512 MB"; compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; aliases { @@ -10,8 +10,13 @@ rtc1 = "/rtc@7000e000"; }; - memory { - reg = <0x00000000 0x20000000>; + memory@0 { + /* + * Set memory to 256 MB to be safe as this could be used on + * 256 or 512 MB module. It is expected from bootloader + * to fix this up for 512 MB version. + */ + reg = <0x00000000 0x10000000>; }; host1x@50000000 { @@ -213,6 +218,22 @@ GPIO_ACTIVE_HIGH>; }; + nand-controller@70008000 { + status = "okay"; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-on-flash-bbt; + nand-ecc-algo = "bch"; + nand-is-boot-medium; + nand-ecc-maximize; + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; + /* * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier * board) diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 628a55a9318b..1d96d92b72a7 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 30436969adc0..ef245291924f 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -19,7 +19,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 284aae351ff2..f91441683aad 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 872046d48709..20137fc578b1 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index d55c6b240a30..9eb26dc15f6b 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index ee3fbf941e79..f44551e2d9d0 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 983dd5c14794..15b73bd377f0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -1,14 +1,20 @@ // SPDX-License-Identifier: GPL-2.0 #include <dt-bindings/clock/tegra20-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/memory/tegra20-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra20"; interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + device_type = "memory"; + reg = <0 0>; + }; iram@40000000 { compatible = "mmio-sram"; @@ -282,7 +288,8 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ interrupt-names = "sync-token", "bsev", "sxe"; clocks = <&tegra_car TEGRA20_CLK_VDE>; - resets = <&tegra_car 61>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; }; apbmisc@70000800 { @@ -425,6 +432,21 @@ status = "disabled"; }; + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + assigned-clock-rates = <150000000>; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; @@ -593,11 +615,12 @@ clock-names = "pclk", "clk32k_in"; }; - memory-controller@7000f000 { + mc: memory-controller@7000f000 { compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; }; iommu@7000f024 { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index d1d21ec2a844..2f807d40c1b7 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -10,6 +10,10 @@ model = "Toradex Apalis T30"; compatible = "toradex,apalis_t30", "nvidia,tegra30"; + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + pcie@3000 { avdd-pexa-supply = <&vdd2_reg>; vdd-pexa-supply = <&vdd2_reg>; @@ -118,6 +122,7 @@ nvidia,function = "spi4"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; /* CAN_INT2 */ spi2_cs2_n_pw3 { @@ -585,8 +590,6 @@ /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; @@ -595,7 +598,7 @@ blocks = <0x5>; irq-trigger = <0x1>; - stmpe_touchscreen@0 { + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index ae52a5039506..b0d40ac8ac6e 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x80000000 0x7ff00000>; }; @@ -1790,9 +1790,6 @@ vccio-supply = <&vdd_5v_in_reg>; regulators { - #address-cells = <1>; - #size-cells = <0>; - vdd1_reg: vdd1 { regulator-name = "vddio_ddr_1v2"; regulator-min-microvolt = <1200000>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 92a9740c533f..fb9222b479d2 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -40,7 +40,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -206,6 +206,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index c44d8c40c410..526ed71cf7a3 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -10,7 +10,7 @@ model = "Toradex Colibri T30"; compatible = "toradex,colibri_t30", "nvidia,tegra30"; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -351,8 +351,6 @@ /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 09087b9c5e26..a6781f653310 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -5,11 +5,16 @@ #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" - / { compatible = "nvidia,tegra30"; interrupt-parent = <&lic>; + #address-cells = <1>; + #size-cells = <1>; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x0>; + }; pcie@3000 { compatible = "nvidia,tegra30-pcie"; @@ -404,7 +409,8 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ interrupt-names = "sync-token", "bsev", "sxe"; clocks = <&tegra_car TEGRA30_CLK_VDE>; - resets = <&tegra_car 61>; + reset-names = "vde", "mc"; + resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; }; apbmisc@70000800 { @@ -712,6 +718,7 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; + #reset-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 641d96119d4f..e2d1a22c5950 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -36,6 +36,7 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -46,6 +47,7 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -56,6 +58,7 @@ enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts new file mode 100644 index 000000000000..37777cf22e67 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 CFU1 Board"; + compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + + led-fail { + label = "zii:red:fail"; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + max-brightness = <1>; + }; + + led-status { + label = "zii:green:status"; + gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + + led-debug-a { + label = "zii:green:debug_a"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + + led-debug-b { + label = "zii:green:debug_b"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6085"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reg = <0>; + eeprom-length = <512>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "eth_cu_1000_1"; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_2"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + pca9554@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + label = "nvm"; + }; + + at24c04@54 { + compatible = "atmel,24c04"; + reg = <0x54>; + label = "nameplate"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + VF610_PAD_PTE3__GPIO_108 0x31c2 + VF610_PAD_PTE4__GPIO_109 0x31c2 + VF610_PAD_PTE5__GPIO_110 0x31c2 + VF610_PAD_PTE6__GPIO_111 0x31c2 + >; + }; + + pinctrl_switch: switch-grp { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x3061 + VF610_PAD_PTE2__GPIO_107 0x1042 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts new file mode 100644 index 000000000000..fe357668865b --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SSMB SPU3 board + * + * SSMB - SPU3 Switch Management Board + * SPU - Seat Power Unit + * + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SSMB SPU3 Board"; + compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + /* + * Some SPU3s come with SPI-NOR chip DNPed, so we leave this + * node disabled by default and rely on bootloader to enable + * it when appropriate. + */ + status = "disabled"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_1"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_3"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_4"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_5"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_6"; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio6: pca9505@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + at24c04@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTE2__GPIO_107 0x31c2 + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/zynq-cc108.dts b/arch/arm/boot/dts/zynq-cc108.dts index 1a0f631c1d8d..8b9ab9bba23b 100644 --- a/arch/arm/boot/dts/zynq-cc108.dts +++ b/arch/arm/boot/dts/zynq-cc108.dts @@ -12,8 +12,8 @@ /include/ "zynq-7000.dtsi" / { + model = "Xilinx CC108 board"; compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem0; diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts index aa4a0b6defb8..6ed84fb15902 100644 --- a/arch/arm/boot/dts/zynq-microzed.dts +++ b/arch/arm/boot/dts/zynq-microzed.dts @@ -7,8 +7,8 @@ /include/ "zynq-7000.dtsi" / { - model = "Zynq MicroZED Development Board"; - compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + model = "Avnet MicroZed board"; + compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index c05f4b67d4c1..54592aeb92b9 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -12,7 +12,7 @@ /include/ "zynq-7000.dtsi" / { - model = "Adapteva Parallella Board"; + model = "Adapteva Parallella board"; compatible = "adapteva,parallella", "xlnx,zynq-7000"; aliases { diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index f2330b0cb63d..cc5a3dc2b4a0 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -7,13 +7,14 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC702 Development Board"; + model = "Xilinx ZC702 board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory@0 { @@ -28,8 +29,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw14 { label = "sw14"; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 3ad1260ff2a1..77943c16d33f 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -7,13 +7,14 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZC706 Development Board"; + model = "Xilinx ZC706 board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory@0 { diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/zynq-zc770-xm010.dts index 6884f1ad66b7..0e1bfdd3421f 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm010.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm010.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM010 board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem0; diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/zynq-zc770-xm011.dts index b78883cee96a..b7f65862c022 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm011.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm011.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM011 board"; compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { i2c0 = &i2c1; diff --git a/arch/arm/boot/dts/zynq-zc770-xm012.dts b/arch/arm/boot/dts/zynq-zc770-xm012.dts index c3169d63600d..d2359b789eb8 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm012.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm012.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM012 board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { i2c0 = &i2c0; diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts index 8bb66859d774..651913f1afa2 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm013.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm013.dts @@ -8,8 +8,8 @@ #include "zynq-7000.dtsi" / { + model = "Xilinx ZC770 XM013 board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; - model = "Xilinx Zynq"; aliases { ethernet0 = &gem1; diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 53c6883ce1f6..6a5a93aa6552 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -7,12 +7,13 @@ #include "zynq-7000.dtsi" / { - model = "Zynq Zed Development Board"; - compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + model = "Avnet ZedBoard board"; + compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory@0 { diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts new file mode 100644 index 000000000000..b38704657960 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zturn.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com> + * Copyright (C) 2017 Alexander Graf <agraf@suse.de> + * + * Based on zynq-zed.dts which is: + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board"; + compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + usr-led1 { + label = "usr-led1"; + gpios = <&gpio0 0x0 0x1>; + default-state = "off"; + }; + + usr-led2 { + label = "usr-led2"; + gpios = <&gpio0 0x9 0x1>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + K1 { + label = "K1"; + gpios = <&gpio0 0x32 0x1>; + linux,code = <0x66>; + gpio-key,wakeup; + autorepeat; + }; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0x0>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + stlm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; + + accelerometer@53 { + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + reg = <0x53>; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + }; +}; diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts index 1e713dc98920..357b78a5c11b 100644 --- a/arch/arm/boot/dts/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/zynq-zybo-z7.dts @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /dts-v1/; #include "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> / { - model = "Zynq ZYBO Z7 Development Board"; + model = "Digilent Zybo Z7 board"; compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; aliases { @@ -13,7 +14,7 @@ memory@0 { device_type = "memory"; - reg = <0x0 0x20000000>; + reg = <0x0 0x40000000>; }; chosen { @@ -21,10 +22,19 @@ stdout-path = "serial0:115200n8"; }; + gpio-leds { + compatible = "gpio-leds"; + + ld4 { + label = "zynq-zybo-z7:green:ld4"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + }; + usb_phy0: phy0 { #phy-cells = <0>; compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio0 46 1>; + reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts index a6c00e7fa767..755f6f109d5a 100644 --- a/arch/arm/boot/dts/zynq-zybo.dts +++ b/arch/arm/boot/dts/zynq-zybo.dts @@ -7,12 +7,13 @@ #include "zynq-7000.dtsi" / { - model = "Zynq ZYBO Development Board"; + model = "Digilent Zybo board"; compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory@0 { diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig index 95946dee9c77..1446262921b4 100644 --- a/arch/arm/configs/aspeed_g4_defconfig +++ b/arch/arm/configs/aspeed_g4_defconfig @@ -3,30 +3,39 @@ CONFIG_KERNEL_XZ=y CONFIG_SYSVIPC=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_LOG_BUF_SHIFT=14 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set -CONFIG_KALLSYMS_ALL=y -CONFIG_BPF_SYSCALL=y +# CONFIG_UID16 is not set +# CONFIG_SYSFS_SYSCALL is not set # CONFIG_AIO is not set +CONFIG_BPF_SYSCALL=y CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y +CONFIG_SLAB_FREELIST_RANDOM=y CONFIG_JUMP_LABEL=y +CONFIG_STRICT_KERNEL_RWX=y CONFIG_GCC_PLUGINS=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y # CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEBUG_FS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_ASPEED=y CONFIG_MACH_ASPEED_G4=y CONFIG_VMSPLIT_2G=y CONFIG_AEABI=y -# CONFIG_CPU_SW_DOMAIN_PAN is not set # CONFIG_COMPACTION is not set +CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_SECCOMP=y # CONFIG_ATAGS is not set CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -47,8 +56,14 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_ADVANCED is not set +CONFIG_VLAN_8021Q=y CONFIG_NET_NCSI=y +CONFIG_BPF_STREAM_PARSER=y # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y @@ -58,11 +73,12 @@ CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_PARTITIONED_MASTER=y CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set CONFIG_SPI_ASPEED_SMC=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y -CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_LOOP=y CONFIG_ASPEED_LPC_CTRL=y CONFIG_ASPEED_LPC_SNOOP=y CONFIG_EEPROM_AT24=y @@ -70,18 +86,26 @@ CONFIG_NETDEVICES=y CONFIG_NETCONSOLE=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CORTINA is not set # CONFIG_NET_VENDOR_EZCHIP is not set CONFIG_FTGMAC100=y # CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set # CONFIG_NET_VENDOR_ROCKER is not set @@ -89,13 +113,20 @@ CONFIG_FTGMAC100=y # CONFIG_NET_VENDOR_SEEQ is not set # CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_BROADCOM_PHY=y CONFIG_REALTEK_PHY=y +# CONFIG_USB_NET_DRIVERS is not set # CONFIG_WLAN is not set -# CONFIG_INPUT is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set @@ -108,15 +139,16 @@ CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_ASPEED_VUART=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_ASPEED_KCS_IPMI_BMC=y CONFIG_ASPEED_BT_IPMI_BMC=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y +CONFIG_HW_RANDOM_TIMERIOMEM=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_ASPEED=y +CONFIG_I2C_FSI=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_ASPEED=y @@ -129,19 +161,45 @@ CONFIG_SENSORS_LM75=y CONFIG_SENSORS_NCT7904=y CONFIG_PMBUS=y CONFIG_SENSORS_ADM1275=y +CONFIG_SENSORS_IBM_CFFPS=y +CONFIG_SENSORS_IR35221=y CONFIG_SENSORS_LM25066=y +CONFIG_SENSORS_MAX31785=y CONFIG_SENSORS_UCD9000=y +CONFIG_SENSORS_UCD9200=y CONFIG_SENSORS_TMP421=y +CONFIG_SENSORS_W83773G=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_DRM=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_GADGET=y +CONFIG_U_SERIAL_CONSOLE=y +CONFIG_USB_ASPEED_VHUB=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=y CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=y +CONFIG_LEDS_PCA955X_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y @@ -150,33 +208,56 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_RV8803=y -CONFIG_MAILBOX=y +# CONFIG_VIRTIO_MENU is not set # CONFIG_IOMMU_SUPPORT is not set CONFIG_IIO=y CONFIG_ASPEED_ADC=y +CONFIG_MAX1363=y CONFIG_BMP280=y +CONFIG_FSI=y +CONFIG_FSI_MASTER_GPIO=y +CONFIG_FSI_MASTER_HUB=y +CONFIG_FSI_MASTER_AST_CF=y +CONFIG_FSI_SCOM=y +CONFIG_FSI_SBEFIFO=y CONFIG_FIRMWARE_MEMMAP=y CONFIG_FANOTIFY=y CONFIG_OVERLAY_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +# CONFIG_JFFS2_FS_WRITEBUFFER is not set CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_DEBUG_INFO_DWARF4=y +CONFIG_GDB_SCRIPTS=y CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_FS=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_DETECT_HUNG_TASK is not set CONFIG_WQ_WATCHDOG=y +CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=-1 # CONFIG_SCHED_DEBUG is not set CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_STACKTRACE=y -# CONFIG_FTRACE is not set +CONFIG_FUNCTION_TRACER=y +# CONFIG_TRACING_EVENTS_GPIO is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_DEBUG_WX=y CONFIG_DEBUG_USER=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y # CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_USER_API_HASH=y # CONFIG_CRYPTO_HW is not set # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig index 8c7ea033cdc2..02fa3a41add5 100644 --- a/arch/arm/configs/aspeed_g5_defconfig +++ b/arch/arm/configs/aspeed_g5_defconfig @@ -3,40 +3,47 @@ CONFIG_KERNEL_XZ=y CONFIG_SYSVIPC=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_LOG_BUF_SHIFT=14 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set -CONFIG_KALLSYMS_ALL=y -CONFIG_BPF_SYSCALL=y +# CONFIG_UID16 is not set +# CONFIG_SYSFS_SYSCALL is not set # CONFIG_AIO is not set +CONFIG_BPF_SYSCALL=y CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y +CONFIG_SLAB_FREELIST_RANDOM=y CONFIG_JUMP_LABEL=y +CONFIG_STRICT_KERNEL_RWX=y CONFIG_GCC_PLUGINS=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y # CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEBUG_FS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_ARCH_MULTI_V6=y # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_ASPEED=y CONFIG_MACH_ASPEED_G5=y # CONFIG_CACHE_L2X0 is not set CONFIG_VMSPLIT_2G=y -CONFIG_AEABI=y -# CONFIG_CPU_SW_DOMAIN_PAN is not set # CONFIG_COMPACTION is not set +CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_SECCOMP=y # CONFIG_ATAGS is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_KEXEC=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=y @@ -49,8 +56,14 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_ADVANCED is not set +CONFIG_VLAN_8021Q=y CONFIG_NET_NCSI=y +CONFIG_BPF_STREAM_PARSER=y # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y @@ -60,11 +73,12 @@ CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_PARTITIONED_MASTER=y CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set CONFIG_SPI_ASPEED_SMC=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y -CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_LOOP=y CONFIG_ASPEED_LPC_CTRL=y CONFIG_ASPEED_LPC_SNOOP=y CONFIG_EEPROM_AT24=y @@ -72,18 +86,26 @@ CONFIG_NETDEVICES=y CONFIG_NETCONSOLE=y # CONFIG_NET_VENDOR_ALACRITECH is not set # CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CORTINA is not set # CONFIG_NET_VENDOR_EZCHIP is not set CONFIG_FTGMAC100=y # CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set # CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set # CONFIG_NET_VENDOR_QUALCOMM is not set # CONFIG_NET_VENDOR_RENESAS is not set # CONFIG_NET_VENDOR_ROCKER is not set @@ -91,13 +113,20 @@ CONFIG_FTGMAC100=y # CONFIG_NET_VENDOR_SEEQ is not set # CONFIG_NET_VENDOR_SOLARFLARE is not set # CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_BROADCOM_PHY=y CONFIG_REALTEK_PHY=y +# CONFIG_USB_NET_DRIVERS is not set # CONFIG_WLAN is not set -# CONFIG_INPUT is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set # CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set @@ -110,15 +139,16 @@ CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_ASPEED_VUART=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_ASPEED_KCS_IPMI_BMC=y CONFIG_ASPEED_BT_IPMI_BMC=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y +CONFIG_HW_RANDOM_TIMERIOMEM=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_ASPEED=y +CONFIG_I2C_FSI=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_ASPEED=y @@ -131,19 +161,45 @@ CONFIG_SENSORS_LM75=y CONFIG_SENSORS_NCT7904=y CONFIG_PMBUS=y CONFIG_SENSORS_ADM1275=y +CONFIG_SENSORS_IBM_CFFPS=y +CONFIG_SENSORS_IR35221=y CONFIG_SENSORS_LM25066=y +CONFIG_SENSORS_MAX31785=y CONFIG_SENSORS_UCD9000=y +CONFIG_SENSORS_UCD9200=y CONFIG_SENSORS_TMP421=y +CONFIG_SENSORS_W83773G=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_DRM=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_GADGET=y +CONFIG_U_SERIAL_CONSOLE=y +CONFIG_USB_ASPEED_VHUB=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=y CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=y +CONFIG_LEDS_PCA955X_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y @@ -152,33 +208,56 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_RV8803=y -CONFIG_MAILBOX=y +# CONFIG_VIRTIO_MENU is not set # CONFIG_IOMMU_SUPPORT is not set CONFIG_IIO=y CONFIG_ASPEED_ADC=y +CONFIG_MAX1363=y CONFIG_BMP280=y +CONFIG_FSI=y +CONFIG_FSI_MASTER_GPIO=y +CONFIG_FSI_MASTER_HUB=y +CONFIG_FSI_MASTER_AST_CF=y +CONFIG_FSI_SCOM=y +CONFIG_FSI_SBEFIFO=y CONFIG_FIRMWARE_MEMMAP=y CONFIG_FANOTIFY=y CONFIG_OVERLAY_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +# CONFIG_JFFS2_FS_WRITEBUFFER is not set CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_DEBUG_INFO_DWARF4=y +CONFIG_GDB_SCRIPTS=y CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_FS=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_DETECT_HUNG_TASK is not set CONFIG_WQ_WATCHDOG=y +CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=-1 # CONFIG_SCHED_DEBUG is not set CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_STACKTRACE=y -# CONFIG_FTRACE is not set +CONFIG_FUNCTION_TRACER=y +# CONFIG_TRACING_EVENTS_GPIO is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_DEBUG_WX=y CONFIG_DEBUG_USER=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y # CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_USER_API_HASH=y # CONFIG_CRYPTO_HW is not set # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index e4d188f0a4b4..e9bc88937b1e 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -86,7 +86,7 @@ CONFIG_SPI=y CONFIG_SPI_BCM2835=y CONFIG_SPI_BCM2835AUX=y CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set +CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_THERMAL=y CONFIG_BCM2835_THERMAL=y CONFIG_WATCHDOG=y diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 21b2d7791df4..07b2eadac3dd 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -31,7 +31,6 @@ CONFIG_MACH_MITYOMAPL138=y CONFIG_MACH_OMAPL138_HAWKBOARD=y CONFIG_DAVINCI_MUX_DEBUG=y CONFIG_DAVINCI_MUX_WARNINGS=y -CONFIG_DAVINCI_RESET_CLOCKS=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_CMA=y @@ -54,6 +53,13 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_NETFILTER=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_BNEP=m +CONFIG_BT_HIDP=m +CONFIG_BT_LEDS=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_FW_LOADER=m @@ -113,6 +119,7 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=3 CONFIG_SERIAL_8250_RUNTIME_UARTS=3 CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_DEV_BUS=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y @@ -153,6 +160,7 @@ CONFIG_TINYDRM_ST7586=m CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DA8XX=y +CONFIG_BACKLIGHT_PWM=m CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_SOUND=m @@ -212,6 +220,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_OMAP=m CONFIG_DMADEVICES=y CONFIG_TI_EDMA=y +CONFIG_COMMON_CLK_PWM=m CONFIG_REMOTEPROC=m CONFIG_DA8XX_REMOTEPROC=m CONFIG_MEMORY=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 200ebda47e0c..e2c127608bcc 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -81,7 +81,6 @@ CONFIG_CAN=y CONFIG_CAN_FLEXCAN=y CONFIG_BT=y CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_LL=y CONFIG_CFG80211=y CONFIG_CFG80211_WEXT=y @@ -266,7 +265,8 @@ CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_ETNAVIV=y -CONFIG_FB_MXS=y +CONFIG_DRM_MXSFB=y +CONFIG_FB_MODE_HELPERS=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y @@ -282,7 +282,6 @@ CONFIG_SND_SOC_FSL_ASRC=y CONFIG_SND_IMX_SOC=y CONFIG_SND_SOC_PHYCORE_AC97=y CONFIG_SND_SOC_EUKREA_TLV320=y -CONFIG_SND_SOC_IMX_WM8962=y CONFIG_SND_SOC_IMX_ES8328=y CONFIG_SND_SOC_IMX_SGTL5000=y CONFIG_SND_SOC_IMX_SPDIF=y @@ -371,13 +370,16 @@ CONFIG_DMADEVICES=y CONFIG_FSL_EDMA=y CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y +CONFIG_DMATEST=m CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_IMX_MEDIA=y CONFIG_COMMON_CLK_PWM=y CONFIG_IIO=y +CONFIG_MMA8452=y CONFIG_IMX7D_ADC=y CONFIG_VF610_ADC=y +CONFIG_SENSORS_ISL29018=y CONFIG_MAG3110=y CONFIG_MPL3115=y CONFIG_PWM=y diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index 2536c231eea1..3ded35a07f45 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig @@ -170,7 +170,10 @@ CONFIG_USB_DWC3=y CONFIG_NOP_USB_XCEIV=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_SDHCI_OMAP=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y @@ -235,3 +238,5 @@ CONFIG_INPUT_GPIO_DECODER=m CONFIG_GPIO_PCA953X=m CONFIG_LEDS_TRIGGER_ACTIVITY=y CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_MICREL_PHY=y +CONFIG_DP83867_PHY=y diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index 7c41bee28463..318b76fa26d1 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -1,5 +1,4 @@ CONFIG_SYSVIPC=y -CONFIG_FHANDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=19 @@ -11,12 +10,10 @@ CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_MVEBU=y -CONFIG_MACH_KIRKWOOD=y -CONFIG_ARCH_AT91=y -CONFIG_SOC_AT91SAM9=y CONFIG_ARCH_ASPEED=y CONFIG_MACH_ASPEED_G4=y +CONFIG_ARCH_AT91=y +CONFIG_SOC_AT91SAM9=y CONFIG_ARCH_MXC=y CONFIG_MACH_MX21ADS=y CONFIG_MACH_MX27ADS=y @@ -25,6 +22,8 @@ CONFIG_MACH_IMX27_VISSTRIM_M10=y CONFIG_MACH_PCA100=y CONFIG_MACH_IMX27_DT=y CONFIG_SOC_IMX25=y +CONFIG_ARCH_MVEBU=y +CONFIG_MACH_KIRKWOOD=y CONFIG_ARCH_ORION5X=y CONFIG_MACH_DB88F5281=y CONFIG_MACH_RD88F5182=y @@ -34,7 +33,6 @@ CONFIG_MACH_DNS323=y CONFIG_MACH_TS209=y CONFIG_MACH_TERASTATION_PRO2=y CONFIG_MACH_LINKSTATION_PRO=y -CONFIG_MACH_LINKSTATION_LSCHL=y CONFIG_MACH_LINKSTATION_MINI=y CONFIG_MACH_LINKSTATION_LS_HGL=y CONFIG_MACH_TS409=y @@ -71,7 +69,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_NET_DSA=y -CONFIG_NET_SWITCHDEV=y CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y @@ -93,10 +90,14 @@ CONFIG_MTD_PHYSMAP=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_ASPEED_SMC=y CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_ATMEL_TCLIB=y CONFIG_ATMEL_SSC=m +CONFIG_ASPEED_LPC_CTRL=m +CONFIG_ASPEED_LPC_SNOOP=m CONFIG_EEPROM_AT24=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y @@ -110,10 +111,11 @@ CONFIG_NET_DSA_MV88E6060=y CONFIG_NET_DSA_MV88E6XXX=y CONFIG_MACB=y CONFIG_DM9000=y +CONFIG_FTGMAC100=m CONFIG_MV643XX_ETH=y CONFIG_R8169=y -CONFIG_MARVELL_PHY=y CONFIG_DAVICOM_PHY=y +CONFIG_MARVELL_PHY=y CONFIG_MICREL_PHY=y CONFIG_LIBERTAS=y CONFIG_LIBERTAS_SDIO=y @@ -125,23 +127,26 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m CONFIG_LEGACY_PTY_COUNT=16 -# CONFIG_DEVKMEM is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=6 CONFIG_SERIAL_8250_RUNTIME_UARTS=6 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_ASPEED_VUART=m CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y CONFIG_SERIAL_ATMEL_TTYAT=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_ASPEED_KCS_IPMI_BMC=m +CONFIG_ASPEED_BT_IPMI_BMC=m CONFIG_HW_RANDOM=y -CONFIG_I2C=y +CONFIG_HW_RANDOM_TIMERIOMEM=m # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y +CONFIG_I2C_ASPEED=m CONFIG_I2C_AT91=y CONFIG_I2C_IMX=y CONFIG_I2C_MV64XXX=y @@ -150,10 +155,12 @@ CONFIG_SPI=y CONFIG_SPI_ATMEL=y CONFIG_SPI_IMX=y CONFIG_SPI_ORION=y +CONFIG_GPIO_ASPEED=m CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_QNAP=y CONFIG_SENSORS_ADT7475=y +CONFIG_SENSORS_ASPEED=y CONFIG_SENSORS_G762=y CONFIG_SENSORS_LM63=y CONFIG_SENSORS_LM75=y @@ -172,11 +179,9 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SOC_CAMERA=y CONFIG_VIDEO_ATMEL_ISI=m -CONFIG_SOC_CAMERA_OV2640=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=m CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_FB=y CONFIG_FB_IMX=y CONFIG_FB_ATMEL=y CONFIG_BACKLIGHT_ATMEL_LCDC=y @@ -246,6 +251,7 @@ CONFIG_MV_XOR=y CONFIG_STAGING=y CONFIG_FB_XGI=y CONFIG_IIO=m +CONFIG_ASPEED_ADC=m CONFIG_AT91_ADC=m CONFIG_PWM=y CONFIG_PWM_ATMEL=m diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index be732f382418..fc33444e94f0 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -88,6 +88,7 @@ CONFIG_ARCH_R8A7791=y CONFIG_ARCH_R8A7792=y CONFIG_ARCH_R8A7793=y CONFIG_ARCH_R8A7794=y +CONFIG_ARCH_R9A06G032=y CONFIG_ARCH_SH73A0=y CONFIG_ARCH_SOCFPGA=y CONFIG_PLAT_SPEAR=y @@ -184,6 +185,7 @@ CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_OMAP2=y CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_MTD_NAND_BRCMNAND=y CONFIG_MTD_NAND_VF610_NFC=y @@ -243,6 +245,7 @@ CONFIG_KS8851=y CONFIG_R8169=y CONFIG_SH_ETH=y CONFIG_SMSC911X=y +CONFIG_SNI_AVE=y CONFIG_STMMAC_ETH=y CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_TI_CPSW=y @@ -447,6 +450,7 @@ CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM95245=y CONFIG_SENSORS_NTC_THERMISTOR=m CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_INA2XX=m CONFIG_CPU_THERMAL=y CONFIG_IMX_THERMAL=y @@ -456,6 +460,7 @@ CONFIG_ARMADA_THERMAL=y CONFIG_BCM2835_THERMAL=m CONFIG_BRCMSTB_THERMAL=m CONFIG_ST_THERMAL_MEMMAP=y +CONFIG_UNIPHIER_THERMAL=y CONFIG_WATCHDOG=y CONFIG_DA9063_WATCHDOG=m CONFIG_XILINX_WATCHDOG=y @@ -562,6 +567,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_STM32_DCMI=m CONFIG_SOC_CAMERA=m CONFIG_SOC_CAMERA_PLATFORM=m CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m @@ -825,6 +831,7 @@ CONFIG_RTC_DRV_SUNXI=y CONFIG_RTC_DRV_MV=y CONFIG_RTC_DRV_TEGRA=y CONFIG_RTC_DRV_ST_LPC=y +CONFIG_RTC_DRV_STM32=y CONFIG_RTC_DRV_CPCAP=m CONFIG_DMADEVICES=y CONFIG_AT_HDMAC=y @@ -840,6 +847,9 @@ CONFIG_PL330_DMA=y CONFIG_SIRF_DMA=y CONFIG_STE_DMA40=y CONFIG_ST_FDMA=m +CONFIG_STM32_DMA=y +CONFIG_STM32_DMAMUX=y +CONFIG_STM32_MDMA=y CONFIG_TEGRA20_APB_DMA=y CONFIG_XILINX_DMA=y CONFIG_QCOM_BAM_DMA=y diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index ddaeda4f2e82..55140219ab11 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -1,5 +1,4 @@ CONFIG_SYSVIPC=y -CONFIG_FHANDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y @@ -16,10 +15,8 @@ CONFIG_MACH_ARMADA_39X=y CONFIG_MACH_ARMADA_XP=y CONFIG_MACH_DOVE=y CONFIG_PCI=y -CONFIG_PCI_MSI=y CONFIG_PCI_MVEBU=y CONFIG_SMP=y -CONFIG_AEABI=y CONFIG_HIGHMEM=y # CONFIG_COMPACTION is not set CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -58,7 +55,6 @@ CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_SPI_NOR=y -CONFIG_SRAM=y CONFIG_MTD_UBI=y CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y @@ -67,12 +63,11 @@ CONFIG_SATA_AHCI=y CONFIG_AHCI_MVEBU=y CONFIG_SATA_MV=y CONFIG_NETDEVICES=y -CONFIG_NET_DSA_MV88E6XXX=y CONFIG_MV643XX_ETH=y CONFIG_MVNETA=y CONFIG_MVPP2=y +CONFIG_SFP=y CONFIG_MARVELL_PHY=y -CONFIG_FIXED_PHY=y CONFIG_MWIFIEX=y CONFIG_MWIFIEX_SDIO=y CONFIG_INPUT_EVDEV=y @@ -88,10 +83,11 @@ CONFIG_SPI=y CONFIG_SPI_ORION=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y -CONFIG_POWER_SUPPLY=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_SUPPLY=y CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_PWM_FAN=y CONFIG_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_WATCHDOG=y @@ -135,7 +131,6 @@ CONFIG_MV_XOR=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_MEMORY=y CONFIG_PWM=y -CONFIG_SENSORS_PWM_FAN=y CONFIG_EXT4_FS=y CONFIG_ISO9660_FS=y CONFIG_JOLIET=y @@ -153,10 +148,8 @@ CONFIG_NLS_ISO8859_2=y CONFIG_NLS_UTF8=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y # CONFIG_SCHED_DEBUG is not set -CONFIG_TIMER_STATS=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_USER=y CONFIG_CRYPTO_DEV_MARVELL_CESA=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index a508eb302e7a..148226e36152 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -94,8 +94,9 @@ CONFIG_STMP3XXX_RTC_WATCHDOG=y CONFIG_MFD_MXS_LRADC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_FB=y -CONFIG_FB_MXS=y +CONFIG_DRM=y +CONFIG_DRM_MXSFB=y +CONFIG_FB_MODE_HELPERS=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index dd2a089f939f..6aa7046fb91f 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -57,6 +57,8 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index 09b5a7386414..a077597369f1 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig @@ -1,5 +1,7 @@ +CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_CGROUPS=y CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y @@ -13,28 +15,68 @@ CONFIG_SOLARIS_X86_PARTITION=y CONFIG_ARCH_S5PV210=y CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT=y -CONFIG_AEABI=y +CONFIG_ARM_APPENDED_DTB=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" CONFIG_VFP=y CONFIG_NEON=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y +CONFIG_NETDEVICES=y +CONFIG_BRCMFMAC=m CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set +CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_HW_RANDOM=y +CONFIG_I2C_GPIO=y +CONFIG_POWER_SUPPLY=y +CONFIG_BATTERY_MAX17040=y # CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_MFD_MAX8998=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_MAX8998=y +CONFIG_DRM=y +CONFIG_DRM_EXYNOS=y +CONFIG_DRM_EXYNOS_FIMD=y +CONFIG_DRM_EXYNOS_DPI=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_EXYNOS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_DWC2=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MAX8998=m +CONFIG_PHY_SAMSUNG_USB2=m +CONFIG_PHY_S5PV210_USB2=y CONFIG_EXT2_FS=y +CONFIG_EXT4_FS=y +CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y @@ -44,6 +86,7 @@ CONFIG_ROMFS_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index b49887e86a3d..f8faf3729464 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -22,6 +22,7 @@ CONFIG_ARCH_R8A7791=y CONFIG_ARCH_R8A7792=y CONFIG_ARCH_R8A7793=y CONFIG_ARCH_R8A7794=y +CONFIG_ARCH_R9A06G032=y CONFIG_ARCH_SH73A0=y CONFIG_PL310_ERRATA_588369=y CONFIG_ARM_ERRATA_754322=y @@ -57,7 +58,6 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_CAN=y CONFIG_CAN_RCAR=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DMA_CMA=y @@ -72,22 +72,9 @@ CONFIG_BLK_DEV_SD=y CONFIG_ATA=y CONFIG_SATA_RCAR=y CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_CADENCE is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set CONFIG_SH_ETH=y CONFIG_RAVB=y -# CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMSC911X=y -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_VIA is not set -# CONFIG_NET_VENDOR_WIZNET is not set CONFIG_MICREL_PHY=y CONFIG_SMSC_PHY=y CONFIG_INPUT_EVDEV=y @@ -100,6 +87,7 @@ CONFIG_INPUT_ADXL34X=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_EM=y CONFIG_SERIAL_SH_SCI=y CONFIG_I2C_CHARDEV=y @@ -205,6 +193,7 @@ CONFIG_AK8975=y CONFIG_PWM=y CONFIG_PWM_RCAR=y CONFIG_PWM_RENESAS_TPU=y +CONFIG_RESET_CONTROLLER=y CONFIG_GENERIC_PHY=y CONFIG_PHY_RCAR_GEN2=y # CONFIG_DNOTIFY is not set diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 3fb1b5a1dce9..689e6565abfc 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -31,21 +31,25 @@ static unsigned long cpu_boot_addr; -static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) +static void tf_generic_smc(u32 type, u32 arg1, u32 arg2) { + register u32 r0 asm("r0") = type; + register u32 r1 asm("r1") = arg1; + register u32 r2 asm("r2") = arg2; + asm volatile( ".arch_extension sec\n\t" - "stmfd sp!, {r4 - r11, lr}\n\t" + "stmfd sp!, {r4 - r11}\n\t" __asmeq("%0", "r0") __asmeq("%1", "r1") __asmeq("%2", "r2") "mov r3, #0\n\t" "mov r4, #0\n\t" "smc #0\n\t" - "ldmfd sp!, {r4 - r11, pc}" + "ldmfd sp!, {r4 - r11}\n\t" : - : "r" (type), "r" (arg1), "r" (arg2) - : "memory"); + : "r" (r0), "r" (r1), "r" (r2) + : "memory", "r3", "r12", "lr"); } static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) diff --git a/arch/arm/include/debug/renesas-scif.S b/arch/arm/include/debug/renesas-scif.S index 97820a8df51a..1c5f795587fc 100644 --- a/arch/arm/include/debug/renesas-scif.S +++ b/arch/arm/include/debug/renesas-scif.S @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Renesas SCIF(A) debugging macro include header * @@ -5,10 +6,6 @@ * * Copyright (C) 2012-2013 Renesas Electronics Corporation * Copyright (C) 1994-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #define SCIF_PHYS CONFIG_DEBUG_UART_PHYS diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 849014c01cf4..32fae4dbd63b 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -40,15 +40,16 @@ extern void at91_pinctrl_gpio_resume(void); #endif static const match_table_t pm_modes __initconst = { - { 0, "standby" }, - { AT91_PM_SLOW_CLOCK, "ulp0" }, + { AT91_PM_STANDBY, "standby" }, + { AT91_PM_ULP0, "ulp0" }, + { AT91_PM_ULP1, "ulp1" }, { AT91_PM_BACKUP, "backup" }, { -1, NULL }, }; static struct at91_pm_data pm_data = { - .standby_mode = 0, - .suspend_mode = AT91_PM_SLOW_CLOCK, + .standby_mode = AT91_PM_STANDBY, + .suspend_mode = AT91_PM_ULP0, }; #define at91_ramc_read(id, field) \ @@ -79,6 +80,90 @@ static struct at91_pm_bu { phys_addr_t resume; } *pm_bu; +struct wakeup_source_info { + unsigned int pmc_fsmr_bit; + unsigned int shdwc_mr_bit; + bool set_polarity; +}; + +static const struct wakeup_source_info ws_info[] = { + { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, + { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, + { .pmc_fsmr_bit = AT91_PMC_USBAL }, + { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, +}; + +static const struct of_device_id sama5d2_ws_ids[] = { + { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, + { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, + { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, + { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, + { .compatible = "usb-ohci", .data = &ws_info[2] }, + { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, + { .compatible = "usb-ehci", .data = &ws_info[2] }, + { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, + { /* sentinel */ } +}; + +static int at91_pm_config_ws(unsigned int pm_mode, bool set) +{ + const struct wakeup_source_info *wsi; + const struct of_device_id *match; + struct platform_device *pdev; + struct device_node *np; + unsigned int mode = 0, polarity = 0, val = 0; + + if (pm_mode != AT91_PM_ULP1) + return 0; + + if (!pm_data.pmc || !pm_data.shdwc) + return -EPERM; + + if (!set) { + writel(mode, pm_data.pmc + AT91_PMC_FSMR); + return 0; + } + + /* SHDWC.WUIR */ + val = readl(pm_data.shdwc + 0x0c); + mode |= (val & 0x3ff); + polarity |= ((val >> 16) & 0x3ff); + + /* SHDWC.MR */ + val = readl(pm_data.shdwc + 0x04); + + /* Loop through defined wakeup sources. */ + for_each_matching_node_and_match(np, sama5d2_ws_ids, &match) { + pdev = of_find_device_by_node(np); + if (!pdev) + continue; + + if (device_may_wakeup(&pdev->dev)) { + wsi = match->data; + + /* Check if enabled on SHDWC. */ + if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) + goto put_node; + + mode |= wsi->pmc_fsmr_bit; + if (wsi->set_polarity) + polarity |= wsi->pmc_fsmr_bit; + } + +put_node: + of_node_put(np); + } + + if (mode) { + writel(mode, pm_data.pmc + AT91_PMC_FSMR); + writel(polarity, pm_data.pmc + AT91_PMC_FSPR); + } else { + pr_err("AT91: PM: no ULP1 wakeup sources found!"); + } + + return mode ? 0 : -EPERM; +} + /* * Called after processes are frozen, but before we shutdown devices. */ @@ -97,7 +182,7 @@ static int at91_pm_begin(suspend_state_t state) pm_data.mode = -1; } - return 0; + return at91_pm_config_ws(pm_data.mode, true); } /* @@ -145,7 +230,7 @@ static int at91_pm_verify_clocks(void) */ int at91_suspend_entering_slow_clock(void) { - return (pm_data.mode >= AT91_PM_SLOW_CLOCK); + return (pm_data.mode >= AT91_PM_ULP0); } EXPORT_SYMBOL(at91_suspend_entering_slow_clock); @@ -186,7 +271,7 @@ static void at91_pm_suspend(suspend_state_t state) * event sources; and reduces DRAM power. But otherwise it's identical to * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. * - * AT91_PM_SLOW_CLOCK is like STANDBY plus slow clock mode, so drivers must + * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must * suspend more deeply, the master clock switches to the clk32k and turns off * the main oscillator * @@ -204,7 +289,7 @@ static int at91_pm_enter(suspend_state_t state) /* * Ensure that clocks are in a valid state. */ - if ((pm_data.mode >= AT91_PM_SLOW_CLOCK) && + if (pm_data.mode >= AT91_PM_ULP0 && !at91_pm_verify_clocks()) goto error; @@ -233,6 +318,7 @@ error: */ static void at91_pm_end(void) { + at91_pm_config_ws(pm_data.mode, false); } @@ -478,31 +564,28 @@ static void __init at91_pm_sram_init(void) &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); } -static void __init at91_pm_backup_init(void) +static bool __init at91_is_pm_mode_active(int pm_mode) +{ + return (pm_data.standby_mode == pm_mode || + pm_data.suspend_mode == pm_mode); +} + +static int __init at91_pm_backup_init(void) { struct gen_pool *sram_pool; struct device_node *np; struct platform_device *pdev = NULL; + int ret = -ENODEV; - if ((pm_data.standby_mode != AT91_PM_BACKUP) && - (pm_data.suspend_mode != AT91_PM_BACKUP)) - return; + if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) + return 0; pm_bu = NULL; - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); - if (!np) { - pr_warn("%s: failed to find shdwc!\n", __func__); - return; - } - - pm_data.shdwc = of_iomap(np, 0); - of_node_put(np); - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); if (!np) { pr_warn("%s: failed to find sfrbu!\n", __func__); - goto sfrbu_fail; + return ret; } pm_data.sfrbu = of_iomap(np, 0); @@ -529,6 +612,7 @@ static void __init at91_pm_backup_init(void) pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); if (!pm_bu) { pr_warn("%s: unable to alloc securam!\n", __func__); + ret = -ENOMEM; goto securam_fail; } @@ -536,19 +620,60 @@ static void __init at91_pm_backup_init(void) pm_bu->canary = __pa_symbol(&canary); pm_bu->resume = __pa_symbol(cpu_resume); - return; + return 0; -sfrbu_fail: - iounmap(pm_data.shdwc); - pm_data.shdwc = NULL; securam_fail: iounmap(pm_data.sfrbu); pm_data.sfrbu = NULL; + return ret; +} - if (pm_data.standby_mode == AT91_PM_BACKUP) - pm_data.standby_mode = AT91_PM_SLOW_CLOCK; - if (pm_data.suspend_mode == AT91_PM_BACKUP) - pm_data.suspend_mode = AT91_PM_SLOW_CLOCK; +static void __init at91_pm_use_default_mode(int pm_mode) +{ + if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP) + return; + + if (pm_data.standby_mode == pm_mode) + pm_data.standby_mode = AT91_PM_ULP0; + if (pm_data.suspend_mode == pm_mode) + pm_data.suspend_mode = AT91_PM_ULP0; +} + +static void __init at91_pm_modes_init(void) +{ + struct device_node *np; + int ret; + + if (!at91_is_pm_mode_active(AT91_PM_BACKUP) && + !at91_is_pm_mode_active(AT91_PM_ULP1)) + return; + + np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); + if (!np) { + pr_warn("%s: failed to find shdwc!\n", __func__); + goto ulp1_default; + } + + pm_data.shdwc = of_iomap(np, 0); + of_node_put(np); + + ret = at91_pm_backup_init(); + if (ret) { + if (!at91_is_pm_mode_active(AT91_PM_ULP1)) + goto unmap; + else + goto backup_default; + } + + return; + +unmap: + iounmap(pm_data.shdwc); + pm_data.shdwc = NULL; +ulp1_default: + at91_pm_use_default_mode(AT91_PM_ULP1); +backup_default: + at91_pm_use_default_mode(AT91_PM_BACKUP); } struct pmc_info { @@ -559,15 +684,20 @@ static const struct pmc_info pmc_infos[] __initconst = { { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP }, { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP }, { .uhp_udp_mask = AT91SAM926x_PMC_UHP }, + { .uhp_udp_mask = 0 }, }; static const struct of_device_id atmel_pmc_ids[] __initconst = { { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, + { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, + { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, + { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, + { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, { /* sentinel */ }, }; @@ -644,7 +774,7 @@ void __init sama5d2_pm_init(void) if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) return; - at91_pm_backup_init(); + at91_pm_modes_init(); sama5_pm_init(); } diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index f95d31496f08..9bd4e6ca672a 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -21,8 +21,10 @@ #define AT91_MEMCTRL_SDRAMC 1 #define AT91_MEMCTRL_DDRSDR 2 -#define AT91_PM_SLOW_CLOCK 0x01 -#define AT91_PM_BACKUP 0x02 +#define AT91_PM_STANDBY 0x00 +#define AT91_PM_ULP0 0x01 +#define AT91_PM_ULP1 0x02 +#define AT91_PM_BACKUP 0x03 #ifndef __ASSEMBLY__ struct at91_pm_data { diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index daca91feea6a..a7c6ae13c945 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -42,6 +42,15 @@ tmp2 .req r5 .endm /* + * Wait for main oscillator selection is done + */ + .macro wait_moscsels +1: ldr tmp1, [pmc, #AT91_PMC_SR] + tst tmp1, #AT91_PMC_MOSCSELS + beq 1b + .endm + +/* * Wait until PLLA has locked. */ .macro wait_pllalock @@ -112,19 +121,20 @@ ENTRY(at91_pm_suspend_in_sram) bl at91_sramc_self_refresh ldr r0, .pm_mode - cmp r0, #AT91_PM_SLOW_CLOCK - beq slow_clock + cmp r0, #AT91_PM_STANDBY + beq standby cmp r0, #AT91_PM_BACKUP beq backup_mode + bl at91_ulp_mode + b exit_suspend + +standby: /* Wait for interrupt */ ldr pmc, .pmc_base at91_cpu_idle b exit_suspend -slow_clock: - bl at91_slowck_mode - b exit_suspend backup_mode: bl at91_backup_mode b exit_suspend @@ -151,7 +161,102 @@ ENTRY(at91_backup_mode) str tmp1, [r0, #0] ENDPROC(at91_backup_mode) -ENTRY(at91_slowck_mode) +.macro at91_pm_ulp0_mode + ldr pmc, .pmc_base + + /* Turn off the crystal oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + bic tmp1, tmp1, #AT91_PMC_MOSCEN + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + + /* Wait for interrupt */ + at91_cpu_idle + + /* Turn on the crystal oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + orr tmp1, tmp1, #AT91_PMC_MOSCEN + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + + wait_moscrdy +.endm + +/** + * Note: This procedure only applies on the platform which uses + * the external crystal oscillator as a main clock source. + */ +.macro at91_pm_ulp1_mode + ldr pmc, .pmc_base + + /* Switch the main clock source to 12-MHz RC oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + bic tmp1, tmp1, #AT91_PMC_MOSCSEL + bic tmp1, tmp1, #AT91_PMC_KEY_MASK + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + + wait_moscsels + + /* Disable the crystal oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + bic tmp1, tmp1, #AT91_PMC_MOSCEN + bic tmp1, tmp1, #AT91_PMC_KEY_MASK + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + + /* Switch the master clock source to main clock */ + ldr tmp1, [pmc, #AT91_PMC_MCKR] + bic tmp1, tmp1, #AT91_PMC_CSS + orr tmp1, tmp1, #AT91_PMC_CSS_MAIN + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy + + /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + orr tmp1, tmp1, #AT91_PMC_WAITMODE + bic tmp1, tmp1, #AT91_PMC_KEY_MASK + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + + wait_mckrdy + + /* Enable the crystal oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + orr tmp1, tmp1, #AT91_PMC_MOSCEN + bic tmp1, tmp1, #AT91_PMC_KEY_MASK + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + + wait_moscrdy + + /* Switch the master clock source to slow clock */ + ldr tmp1, [pmc, #AT91_PMC_MCKR] + bic tmp1, tmp1, #AT91_PMC_CSS + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy + + /* Switch main clock source to crystal oscillator */ + ldr tmp1, [pmc, #AT91_CKGR_MOR] + orr tmp1, tmp1, #AT91_PMC_MOSCSEL + bic tmp1, tmp1, #AT91_PMC_KEY_MASK + orr tmp1, tmp1, #AT91_PMC_KEY + str tmp1, [pmc, #AT91_CKGR_MOR] + + wait_moscsels + + /* Switch the master clock source to main clock */ + ldr tmp1, [pmc, #AT91_PMC_MCKR] + bic tmp1, tmp1, #AT91_PMC_CSS + orr tmp1, tmp1, #AT91_PMC_CSS_MAIN + str tmp1, [pmc, #AT91_PMC_MCKR] + + wait_mckrdy +.endm + +ENTRY(at91_ulp_mode) ldr pmc, .pmc_base /* Save Master clock setting */ @@ -174,22 +279,19 @@ ENTRY(at91_slowck_mode) orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ str tmp1, [pmc, #AT91_CKGR_PLLAR] - /* Turn off the main oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] - bic tmp1, tmp1, #AT91_PMC_MOSCEN - orr tmp1, tmp1, #AT91_PMC_KEY - str tmp1, [pmc, #AT91_CKGR_MOR] + ldr r0, .pm_mode + cmp r0, #AT91_PM_ULP1 + beq ulp1_mode - /* Wait for interrupt */ - at91_cpu_idle + at91_pm_ulp0_mode + b ulp_exit - /* Turn on the main oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] - orr tmp1, tmp1, #AT91_PMC_MOSCEN - orr tmp1, tmp1, #AT91_PMC_KEY - str tmp1, [pmc, #AT91_CKGR_MOR] +ulp1_mode: + at91_pm_ulp1_mode + b ulp_exit - wait_moscrdy +ulp_exit: + ldr pmc, .pmc_base /* Restore PLLA setting */ ldr tmp1, .saved_pllar @@ -212,7 +314,7 @@ ENTRY(at91_slowck_mode) wait_mckrdy mov pc, lr -ENDPROC(at91_slowck_mode) +ENDPROC(at91_ulp_mode) /* * void at91_sramc_self_refresh(unsigned int is_active) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 05c3eecf47cb..da8a039d65f9 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -59,6 +59,7 @@ config MACH_DA8XX_DT default y depends on ARCH_DAVINCI_DA850 select PINCTRL + select TIMER_OF help Say y here to include support for TI DaVinci DA850 based using Flattened Device Tree. More information at Documentation/devicetree @@ -231,18 +232,6 @@ config DAVINCI_MUX_WARNINGS to change the pin multiplexing setup. When there are no warnings printed, it's safe to deselect DAVINCI_MUX for your product. -config DAVINCI_RESET_CLOCKS - bool "Reset unused clocks during boot" - depends on ARCH_DAVINCI - help - Say Y if you want to reset unused clocks during boot. - This option saves power, but assumes all drivers are - using the clock framework. Broken drivers that do not - yet use clock framework may not work with this option. - If you are booting from another operating system, you - probably do not want this option enabled until your - device drivers work properly. - endmenu endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 4e8178050027..93d271b4d84b 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,8 +5,8 @@ # # Common objects -obj-y := time.o clock.o serial.o psc.o \ - usb.o common.o sram.o aemif.o +obj-y := time.o serial.o usb.o \ + common.o sram.o obj-$(CONFIG_DAVINCI_MUX) += mux.o diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c deleted file mode 100644 index e4ab3f3a2a1f..000000000000 --- a/arch/arm/mach-davinci/aemif.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * AEMIF support for DaVinci SoCs - * - * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/module.h> -#include <linux/time.h> - -#include <linux/platform_data/mtd-davinci-aemif.h> -#include <linux/platform_data/mtd-davinci.h> - -/* Timing value configuration */ - -#define TA(x) ((x) << 2) -#define RHOLD(x) ((x) << 4) -#define RSTROBE(x) ((x) << 7) -#define RSETUP(x) ((x) << 13) -#define WHOLD(x) ((x) << 17) -#define WSTROBE(x) ((x) << 20) -#define WSETUP(x) ((x) << 26) - -#define TA_MAX 0x3 -#define RHOLD_MAX 0x7 -#define RSTROBE_MAX 0x3f -#define RSETUP_MAX 0xf -#define WHOLD_MAX 0x7 -#define WSTROBE_MAX 0x3f -#define WSETUP_MAX 0xf - -#define TIMING_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX)) - -static inline unsigned int davinci_aemif_readl(void __iomem *base, int offset) -{ - return readl_relaxed(base + offset); -} - -static inline void davinci_aemif_writel(void __iomem *base, - int offset, unsigned long value) -{ - writel_relaxed(value, base + offset); -} - -/* - * aemif_calc_rate - calculate timing data. - * @wanted: The cycle time needed in nanoseconds. - * @clk: The input clock rate in kHz. - * @max: The maximum divider value that can be programmed. - * - * On success, returns the calculated timing value minus 1 for easy - * programming into AEMIF timing registers, else negative errno. - */ -static int aemif_calc_rate(int wanted, unsigned long clk, int max) -{ - int result; - - result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1; - - pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted); - - /* It is generally OK to have a more relaxed timing than requested... */ - if (result < 0) - result = 0; - - /* ... But configuring tighter timings is not an option. */ - else if (result > max) - result = -EINVAL; - - return result; -} - -/** - * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface - * @t: timing values to be progammed - * @base: The virtual base address of the AEMIF interface - * @cs: chip-select to program the timing values for - * @clkrate: the AEMIF clkrate - * - * This function programs the given timing values (in real clock) into the - * AEMIF registers taking the AEMIF clock into account. - * - * This function does not use any locking while programming the AEMIF - * because it is expected that there is only one user of a given - * chip-select. - * - * Returns 0 on success, else negative errno. - */ -static int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, - void __iomem *base, unsigned cs, - unsigned long clkrate) -{ - unsigned set, val; - int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; - unsigned offset = A1CR_OFFSET + cs * 4; - - if (!t) - return 0; /* Nothing to do */ - - clkrate /= 1000; /* turn clock into kHz for ease of use */ - - ta = aemif_calc_rate(t->ta, clkrate, TA_MAX); - rhold = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX); - rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX); - rsetup = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX); - whold = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX); - wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX); - wsetup = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX); - - if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || - whold < 0 || wstrobe < 0 || wsetup < 0) { - pr_err("%s: cannot get suitable timings\n", __func__); - return -EINVAL; - } - - set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | - WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); - - val = __raw_readl(base + offset); - val &= ~TIMING_MASK; - val |= set; - __raw_writel(val, base + offset); - - return 0; -} - -/** - * davinci_aemif_setup - setup AEMIF interface by davinci_nand_pdata - * @pdev - link to platform device to setup settings for - * - * This function does not use any locking while programming the AEMIF - * because it is expected that there is only one user of a given - * chip-select. - * - * Returns 0 on success, else negative errno. - */ -int davinci_aemif_setup(struct platform_device *pdev) -{ - struct davinci_nand_pdata *pdata = dev_get_platdata(&pdev->dev); - uint32_t val; - unsigned long clkrate; - struct resource *res; - void __iomem *base; - struct clk *clk; - int ret = 0; - - clk = clk_get(&pdev->dev, "aemif"); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); - return ret; - } - - ret = clk_prepare_enable(clk); - if (ret < 0) { - dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", - ret); - goto err_put; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!res) { - dev_err(&pdev->dev, "cannot get IORESOURCE_MEM\n"); - ret = -ENOMEM; - goto err; - } - - base = ioremap(res->start, resource_size(res)); - if (!base) { - dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res); - ret = -ENOMEM; - goto err; - } - - /* - * Setup Async configuration register in case we did not boot - * from NAND and so bootloader did not bother to set it up. - */ - val = davinci_aemif_readl(base, A1CR_OFFSET + pdata->core_chipsel * 4); - /* - * Extended Wait is not valid and Select Strobe mode is not - * used - */ - val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK); - if (pdata->options & NAND_BUSWIDTH_16) - val |= 0x1; - - davinci_aemif_writel(base, A1CR_OFFSET + pdata->core_chipsel * 4, val); - - clkrate = clk_get_rate(clk); - - if (pdata->timing) - ret = davinci_aemif_setup_timing(pdata->timing, base, - pdata->core_chipsel, clkrate); - - if (ret < 0) - dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); - - iounmap(base); -err: - clk_disable_unprepare(clk); -err_put: - clk_put(clk); - return ret; -} diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 14a6fc061744..7d8ab36ff83d 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -28,6 +28,7 @@ #include <linux/platform_data/mtd-davinci-aemif.h> #include <linux/platform_data/spi-davinci.h> #include <linux/platform_data/usb-davinci.h> +#include <linux/platform_data/ti-aemif.h> #include <linux/regulator/machine.h> #include <asm/mach-types.h> @@ -110,15 +111,9 @@ static __init void da830_evm_usb_init(void) { int ret; - /* USB_REFCLKIN is not used. */ - ret = da8xx_register_usb20_phy_clk(false); + ret = da8xx_register_usb_phy_clocks(); if (ret) - pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n", - __func__, ret); - - ret = da8xx_register_usb11_phy_clk(false); - if (ret) - pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n", + pr_warn("%s: USB PHY CLK registration failed: %d\n", __func__, ret); ret = da8xx_register_usb_phy(); @@ -339,14 +334,48 @@ static struct resource da830_evm_nand_resources[] = { }, }; -static struct platform_device da830_evm_nand_device = { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &da830_evm_nand_pdata, +static struct platform_device da830_evm_aemif_devices[] = { + { + .name = "davinci_nand", + .id = 1, + .dev = { + .platform_data = &da830_evm_nand_pdata, + }, + .num_resources = ARRAY_SIZE(da830_evm_nand_resources), + .resource = da830_evm_nand_resources, + }, +}; + +static struct resource da830_evm_aemif_resource[] = { + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct aemif_abus_data da830_evm_aemif_abus_data[] = { + { + .cs = 3, }, - .num_resources = ARRAY_SIZE(da830_evm_nand_resources), - .resource = da830_evm_nand_resources, +}; + +static struct aemif_platform_data da830_evm_aemif_pdata = { + .abus_data = da830_evm_aemif_abus_data, + .num_abus_data = ARRAY_SIZE(da830_evm_aemif_abus_data), + .sub_devices = da830_evm_aemif_devices, + .num_sub_devices = ARRAY_SIZE(da830_evm_aemif_devices), + .cs_offset = 2, +}; + +static struct platform_device da830_evm_aemif_device = { + .name = "ti-aemif", + .id = -1, + .dev = { + .platform_data = &da830_evm_aemif_pdata, + }, + .resource = da830_evm_aemif_resource, + .num_resources = ARRAY_SIZE(da830_evm_aemif_resource), }; /* @@ -377,12 +406,9 @@ static inline void da830_evm_init_nand(int mux_mode) if (ret) pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret); - ret = platform_device_register(&da830_evm_nand_device); + ret = platform_device_register(&da830_evm_aemif_device); if (ret) - pr_warn("%s: NAND device not registered\n", __func__); - - if (davinci_aemif_setup(&da830_evm_nand_device)) - pr_warn("%s: Cannot configure AEMIF\n", __func__); + pr_warn("%s: AEMIF device not registered\n", __func__); gpio_direction_output(mux_mode, 1); } @@ -557,6 +583,8 @@ static __init void da830_evm_init(void) struct davinci_soc_info *soc_info = &davinci_soc_info; int ret; + da830_register_clocks(); + ret = da830_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 6d5beb11bd96..e1a949b47306 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -33,6 +33,7 @@ #include <linux/platform_data/gpio-davinci.h> #include <linux/platform_data/mtd-davinci.h> #include <linux/platform_data/mtd-davinci-aemif.h> +#include <linux/platform_data/ti-aemif.h> #include <linux/platform_data/spi-davinci.h> #include <linux/platform_data/uio_pruss.h> #include <linux/regulator/machine.h> @@ -185,16 +186,6 @@ static struct resource da850_evm_norflash_resource[] = { }, }; -static struct platform_device da850_evm_norflash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &da850_evm_norflash_data, - }, - .num_resources = 1, - .resource = da850_evm_norflash_resource, -}; - /* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash * (128K blocks). It may be used instead of the (default) SPI flash * to boot, using TI's tools to install the secondary boot loader @@ -266,37 +257,58 @@ static struct resource da850_evm_nandflash_resource[] = { }, }; -static struct platform_device da850_evm_nandflash_device = { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &da850_evm_nandflash_data, - }, - .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource), - .resource = da850_evm_nandflash_resource, +static struct resource da850_evm_aemif_resource[] = { + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, + .flags = IORESOURCE_MEM, + } }; -static struct platform_device *da850_evm_devices[] = { - &da850_evm_nandflash_device, - &da850_evm_norflash_device, +static struct aemif_abus_data da850_evm_aemif_abus_data[] = { + { + .cs = 3, + } }; -#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10 -#define DA8XX_AEMIF_ASIZE_16BIT 0x1 - -static void __init da850_evm_init_nor(void) -{ - void __iomem *aemif_addr; - - aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K); +static struct platform_device da850_evm_aemif_devices[] = { + { + .name = "davinci_nand", + .id = 1, + .dev = { + .platform_data = &da850_evm_nandflash_data, + }, + .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource), + .resource = da850_evm_nandflash_resource, + }, + { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &da850_evm_norflash_data, + }, + .num_resources = 1, + .resource = da850_evm_norflash_resource, + } +}; - /* Configure data bus width of CS2 to 16 bit */ - writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) | - DA8XX_AEMIF_ASIZE_16BIT, - aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET); +static struct aemif_platform_data da850_evm_aemif_pdata = { + .cs_offset = 2, + .abus_data = da850_evm_aemif_abus_data, + .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data), + .sub_devices = da850_evm_aemif_devices, + .num_sub_devices = ARRAY_SIZE(da850_evm_aemif_devices), +}; - iounmap(aemif_addr); -} +static struct platform_device da850_evm_aemif_device = { + .name = "ti-aemif", + .id = -1, + .dev = { + .platform_data = &da850_evm_aemif_pdata, + }, + .resource = da850_evm_aemif_resource, + .num_resources = ARRAY_SIZE(da850_evm_aemif_resource), +}; static const short da850_evm_nand_pins[] = { DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, @@ -339,13 +351,10 @@ static inline void da850_evm_setup_nor_nand(void) pr_warn("%s: NOR mux setup failed: %d\n", __func__, ret); - da850_evm_init_nor(); - - platform_add_devices(da850_evm_devices, - ARRAY_SIZE(da850_evm_devices)); - - if (davinci_aemif_setup(&da850_evm_nandflash_device)) - pr_warn("%s: Cannot configure AEMIF.\n", __func__); + ret = platform_device_register(&da850_evm_aemif_device); + if (ret) + pr_warn("%s: registering aemif failed: %d\n", + __func__, ret); } } @@ -1340,6 +1349,8 @@ static __init void da850_evm_init(void) { int ret; + da850_register_clocks(); + ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index a3377f959444..f53a461a606f 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -394,6 +394,8 @@ static __init void dm355_evm_init(void) struct clk *aemif; int ret; + dm355_register_clocks(); + ret = dm355_gpio_register(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index 8249a0bf69f0..0fdf1d03eb11 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -234,6 +234,8 @@ static __init void dm355_leopard_init(void) struct clk *aemif; int ret; + dm355_register_clocks(); + ret = dm355_gpio_register(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 435f7ec7d9af..8143756ff38b 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -28,6 +28,7 @@ #include <linux/spi/spi.h> #include <linux/spi/eeprom.h> #include <linux/v4l2-dv-timings.h> +#include <linux/platform_data/ti-aemif.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -159,16 +160,49 @@ static struct resource davinci_nand_resources[] = { }, }; -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - .dev = { - .platform_data = &davinci_nand_data, +static struct platform_device davinci_aemif_devices[] = { + { + .name = "davinci_nand", + .id = 0, + .num_resources = ARRAY_SIZE(davinci_nand_resources), + .resource = davinci_nand_resources, + .dev = { + .platform_data = &davinci_nand_data, + }, + } +}; + +static struct resource davinci_aemif_resources[] = { + { + .start = DM365_ASYNC_EMIF_CONTROL_BASE, + .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, }; +static struct aemif_abus_data da850_evm_aemif_abus_data[] = { + { + .cs = 1, + }, +}; + +static struct aemif_platform_data davinci_aemif_pdata = { + .abus_data = da850_evm_aemif_abus_data, + .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data), + .sub_devices = davinci_aemif_devices, + .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices), +}; + +static struct platform_device davinci_aemif_device = { + .name = "ti-aemif", + .id = -1, + .dev = { + .platform_data = &davinci_aemif_pdata, + }, + .resource = davinci_aemif_resources, + .num_resources = ARRAY_SIZE(davinci_aemif_resources), +}; + static struct at24_platform_data eeprom_info = { .byte_len = (256*1024) / 8, .page_size = 64, @@ -537,10 +571,6 @@ static void __init evm_init_i2c(void) i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); } -static struct platform_device *dm365_evm_nand_devices[] __initdata = { - &davinci_nand_device, -}; - static inline int have_leds(void) { #ifdef CONFIG_LEDS_CLASS @@ -628,6 +658,7 @@ static void __init evm_init_cpld(void) u8 mux, resets; const char *label; struct clk *aemif_clk; + int rc; /* Make sure we can configure the CPLD through CS1. Then * leave it on for later access to MMC and LED registers. @@ -660,8 +691,10 @@ fail: /* external keypad mux */ mux |= BIT(7); - platform_add_devices(dm365_evm_nand_devices, - ARRAY_SIZE(dm365_evm_nand_devices)); + rc = platform_device_register(&davinci_aemif_device); + if (rc) + pr_warn("%s(): error registering the aemif device: %d\n", + __func__, rc); } else { /* no OneNAND support yet */ } @@ -742,6 +775,8 @@ static __init void dm365_evm_init(void) { int ret; + dm365_register_clocks(); + ret = dm365_gpio_register(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 48436f74fd71..e4a8f9225d16 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -42,6 +42,7 @@ #include <linux/platform_data/mmc-davinci.h> #include <linux/platform_data/usb-davinci.h> #include <linux/platform_data/mtd-davinci-aemif.h> +#include <linux/platform_data/ti-aemif.h> #include "davinci.h" @@ -174,14 +175,47 @@ static struct resource davinci_evm_nandflash_resource[] = { }, }; -static struct platform_device davinci_evm_nandflash_device = { - .name = "davinci_nand", - .id = 0, - .dev = { - .platform_data = &davinci_evm_nandflash_data, +static struct resource davinci_evm_aemif_resource[] = { + { + .start = DM644X_ASYNC_EMIF_CONTROL_BASE, + .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct aemif_abus_data davinci_evm_aemif_abus_data[] = { + { + .cs = 1, + }, +}; + +static struct platform_device davinci_evm_nandflash_devices[] = { + { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &davinci_evm_nandflash_data, + }, + .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource), + .resource = davinci_evm_nandflash_resource, + }, +}; + +static struct aemif_platform_data davinci_evm_aemif_pdata = { + .abus_data = davinci_evm_aemif_abus_data, + .num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data), + .sub_devices = davinci_evm_nandflash_devices, + .num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices), +}; + +static struct platform_device davinci_evm_aemif_device = { + .name = "ti-aemif", + .id = -1, + .dev = { + .platform_data = &davinci_evm_aemif_pdata, }, - .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource), - .resource = davinci_evm_nandflash_resource, + .resource = davinci_evm_aemif_resource, + .num_resources = ARRAY_SIZE(davinci_evm_aemif_resource), }; static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); @@ -773,6 +807,8 @@ static __init void davinci_evm_init(void) struct clk *aemif_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; + dm644x_register_clocks(); + dm644x_init_devices(); ret = dm644x_gpio_register(); @@ -793,12 +829,7 @@ static __init void davinci_evm_init(void) /* only one device will be jumpered and detected */ if (HAS_NAND) { - platform_device_register(&davinci_evm_nandflash_device); - - if (davinci_aemif_setup(&davinci_evm_nandflash_device)) - pr_warn("%s: Cannot configure AEMIF\n", - __func__); - + platform_device_register(&davinci_evm_aemif_device); #ifdef CONFIG_I2C evm_leds[7].default_trigger = "nand-disk"; #endif diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 584064fdabf5..3e5ee09ee717 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -24,6 +24,7 @@ #include <linux/i2c.h> #include <linux/platform_data/at24.h> #include <linux/platform_data/pcf857x.h> +#include <linux/platform_data/ti-aemif.h> #include <media/i2c/tvp514x.h> #include <media/i2c/adv7343.h> @@ -106,18 +107,49 @@ static struct resource davinci_nand_resources[] = { }, }; -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, +static struct platform_device davinci_aemif_devices[] = { + { + .name = "davinci_nand", + .id = 0, + .num_resources = ARRAY_SIZE(davinci_nand_resources), + .resource = davinci_nand_resources, + .dev = { + .platform_data = &davinci_nand_data, + }, + }, +}; - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, +static struct resource davinci_aemif_resources[] = { + { + .start = DM646X_ASYNC_EMIF_CONTROL_BASE, + .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; - .dev = { - .platform_data = &davinci_nand_data, +static struct aemif_abus_data davinci_aemif_abus_data[] = { + { + .cs = 1, }, }; +static struct aemif_platform_data davinci_aemif_pdata = { + .abus_data = davinci_aemif_abus_data, + .num_abus_data = ARRAY_SIZE(davinci_aemif_abus_data), + .sub_devices = davinci_aemif_devices, + .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices), +}; + +static struct platform_device davinci_aemif_device = { + .name = "ti-aemif", + .id = -1, + .dev = { + .platform_data = &davinci_aemif_pdata, + }, + .resource = davinci_aemif_resources, + .num_resources = ARRAY_SIZE(davinci_aemif_resources), +}; + #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ IS_ENABLED(CONFIG_PATA_BK3710)) @@ -776,6 +808,8 @@ static __init void evm_init(void) int ret; struct davinci_soc_info *soc_info = &davinci_soc_info; + dm646x_register_clocks(); + ret = dm646x_gpio_register(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); @@ -791,10 +825,8 @@ static __init void evm_init(void) if (machine_is_davinci_dm6467tevm()) davinci_nand_data.timing = &dm6467tevm_nandflash_timing; - platform_device_register(&davinci_nand_device); - - if (davinci_aemif_setup(&davinci_nand_device)) - pr_warn("%s: Cannot configure AEMIF.\n", __func__); + if (platform_device_register(&davinci_aemif_device)) + pr_warn("%s: Cannot register AEMIF device.\n", __func__); dm646x_init_edma(dm646x_edma_rsv); diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 37b3e48a21d1..2933e0c87cfa 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -30,6 +30,7 @@ #include <mach/da8xx.h> #include <linux/platform_data/mtd-davinci.h> #include <linux/platform_data/mtd-davinci-aemif.h> +#include <linux/platform_data/ti-aemif.h> #include <mach/mux.h> #include <linux/platform_data/spi-davinci.h> @@ -422,27 +423,53 @@ static struct resource mityomapl138_nandflash_resource[] = { }, }; -static struct platform_device mityomapl138_nandflash_device = { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &mityomapl138_nandflash_data, +static struct platform_device mityomapl138_aemif_devices[] = { + { + .name = "davinci_nand", + .id = 1, + .dev = { + .platform_data = &mityomapl138_nandflash_data, + }, + .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), + .resource = mityomapl138_nandflash_resource, + }, +}; + +static struct resource mityomapl138_aemif_resources[] = { + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, }, - .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), - .resource = mityomapl138_nandflash_resource, }; -static struct platform_device *mityomapl138_devices[] __initdata = { - &mityomapl138_nandflash_device, +static struct aemif_abus_data mityomapl138_aemif_abus_data[] = { + { + .cs = 1, + }, +}; + +static struct aemif_platform_data mityomapl138_aemif_pdata = { + .abus_data = mityomapl138_aemif_abus_data, + .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data), + .sub_devices = mityomapl138_aemif_devices, + .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices), +}; + +static struct platform_device mityomapl138_aemif_device = { + .name = "ti-aemif", + .id = -1, + .dev = { + .platform_data = &mityomapl138_aemif_pdata, + }, + .resource = mityomapl138_aemif_resources, + .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources), }; static void __init mityomapl138_setup_nand(void) { - platform_add_devices(mityomapl138_devices, - ARRAY_SIZE(mityomapl138_devices)); - - if (davinci_aemif_setup(&mityomapl138_nandflash_device)) - pr_warn("%s: Cannot configure AEMIF\n", __func__); + if (platform_device_register(&mityomapl138_aemif_device)) + pr_warn("%s: Cannot register AEMIF device\n", __func__); } static const short mityomap_mii_pins[] = { @@ -503,6 +530,8 @@ static void __init mityomapl138_init(void) { int ret; + da850_register_clocks(); + /* for now, no special EDMA channels are reserved */ ret = da850_register_edma(NULL); if (ret) diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 25ad9b0612be..353f9e5a1454 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -175,6 +175,8 @@ static __init void davinci_ntosd2_init(void) struct clk *aemif_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; + dm644x_register_clocks(); + dm644x_init_devices(); ret = dm644x_gpio_register(); diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index be8b892a6ea7..8e8d51f4a276 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -15,7 +15,12 @@ #include <linux/interrupt.h> #include <linux/gpio.h> #include <linux/gpio/machine.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/rawnand.h> #include <linux/platform_data/gpio-davinci.h> +#include <linux/platform_data/mtd-davinci.h> +#include <linux/platform_data/mtd-davinci-aemif.h> +#include <linux/platform_data/ti-aemif.h> #include <linux/regulator/machine.h> #include <asm/mach-types.h> @@ -166,6 +171,129 @@ mmc_setup_mmcsd_fail: gpiod_remove_lookup_table(&mmc_gpios_table); } +static struct mtd_partition omapl138_hawk_nandflash_partition[] = { + { + .name = "u-boot env", + .offset = 0, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "u-boot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "free space", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_aemif_timing omapl138_hawk_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + +static struct davinci_nand_pdata omapl138_hawk_nandflash_data = { + .core_chipsel = 1, + .parts = omapl138_hawk_nandflash_partition, + .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .ecc_bits = 4, + .bbt_options = NAND_BBT_USE_FLASH, + .options = NAND_BUSWIDTH_16, + .timing = &omapl138_hawk_nandflash_timing, + .mask_chipsel = 0, + .mask_ale = 0, + .mask_cle = 0, +}; + +static struct resource omapl138_hawk_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_32M, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource omapl138_hawk_aemif_resource[] = { + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, + .flags = IORESOURCE_MEM, + } +}; + +static struct aemif_abus_data omapl138_hawk_aemif_abus_data[] = { + { + .cs = 3, + } +}; + +static struct platform_device omapl138_hawk_aemif_devices[] = { + { + .name = "davinci_nand", + .id = -1, + .dev = { + .platform_data = &omapl138_hawk_nandflash_data, + }, + .resource = omapl138_hawk_nandflash_resource, + .num_resources = ARRAY_SIZE(omapl138_hawk_nandflash_resource), + } +}; + +static struct aemif_platform_data omapl138_hawk_aemif_pdata = { + .cs_offset = 2, + .abus_data = omapl138_hawk_aemif_abus_data, + .num_abus_data = ARRAY_SIZE(omapl138_hawk_aemif_abus_data), + .sub_devices = omapl138_hawk_aemif_devices, + .num_sub_devices = ARRAY_SIZE(omapl138_hawk_aemif_devices), +}; + +static struct platform_device omapl138_hawk_aemif_device = { + .name = "ti-aemif", + .id = -1, + .dev = { + .platform_data = &omapl138_hawk_aemif_pdata, + }, + .resource = omapl138_hawk_aemif_resource, + .num_resources = ARRAY_SIZE(omapl138_hawk_aemif_resource), +}; + +static const short omapl138_hawk_nand_pins[] = { + DA850_EMA_WAIT_1, DA850_NEMA_OE, DA850_NEMA_WE, DA850_NEMA_CS_3, + DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, + DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, + DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, + DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, + DA850_EMA_A_1, DA850_EMA_A_2, + -1 +}; + +static int omapl138_hawk_register_aemif(void) +{ + int ret; + + ret = davinci_cfg_reg_list(omapl138_hawk_nand_pins); + if (ret) + pr_warn("%s: NAND mux setup failed: %d\n", __func__, ret); + + return platform_device_register(&omapl138_hawk_aemif_device); +} + static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id); static da8xx_ocic_handler_t hawk_usb_ocic_handler; @@ -236,14 +364,9 @@ static __init void omapl138_hawk_usb_init(void) return; } - ret = da8xx_register_usb20_phy_clk(false); - if (ret) - pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n", - __func__, ret); - - ret = da8xx_register_usb11_phy_clk(false); + ret = da8xx_register_usb_phy_clocks(); if (ret) - pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n", + pr_warn("%s: USB PHY CLK registration failed: %d\n", __func__, ret); ret = da8xx_register_usb_phy(); @@ -285,6 +408,8 @@ static __init void omapl138_hawk_init(void) { int ret; + da850_register_clocks(); + ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); @@ -301,6 +426,10 @@ static __init void omapl138_hawk_init(void) omapl138_hawk_usb_init(); + ret = omapl138_hawk_register_aemif(); + if (ret) + pr_warn("%s: aemif registration failed: %d\n", __func__, ret); + ret = da8xx_register_watchdog(); if (ret) pr_warn("%s: watchdog registration failed: %d\n", diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index e7c1728b0833..792bb84d5011 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -134,6 +134,8 @@ static __init void davinci_sffsdr_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; + dm644x_register_clocks(); + dm644x_init_devices(); platform_add_devices(davinci_sffsdr_devices, diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c deleted file mode 100644 index f77a4f766050..000000000000 --- a/arch/arm/mach-davinci/clock.c +++ /dev/null @@ -1,745 +0,0 @@ -/* - * Clock and PLL control for DaVinci devices - * - * Copyright (C) 2006-2007 Texas Instruments. - * Copyright (C) 2008-2009 Deep Root Systems, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/mutex.h> -#include <linux/io.h> -#include <linux/delay.h> - -#include <mach/hardware.h> - -#include <mach/clock.h> -#include "psc.h" -#include <mach/cputype.h> -#include "clock.h" - -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -static DEFINE_SPINLOCK(clockfw_lock); - -void davinci_clk_enable(struct clk *clk) -{ - if (clk->parent) - davinci_clk_enable(clk->parent); - if (clk->usecount++ == 0) { - if (clk->flags & CLK_PSC) - davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, - true, clk->flags); - else if (clk->clk_enable) - clk->clk_enable(clk); - } -} - -void davinci_clk_disable(struct clk *clk) -{ - if (WARN_ON(clk->usecount == 0)) - return; - if (--clk->usecount == 0) { - if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC)) - davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, - false, clk->flags); - else if (clk->clk_disable) - clk->clk_disable(clk); - } - if (clk->parent) - davinci_clk_disable(clk->parent); -} - -int davinci_clk_reset(struct clk *clk, bool reset) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->flags & CLK_PSC) - davinci_psc_reset(clk->gpsc, clk->lpsc, reset); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -EXPORT_SYMBOL(davinci_clk_reset); - -int davinci_clk_reset_assert(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk) || !clk->reset) - return -EINVAL; - - return clk->reset(clk, true); -} -EXPORT_SYMBOL(davinci_clk_reset_assert); - -int davinci_clk_reset_deassert(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk) || !clk->reset) - return -EINVAL; - - return clk->reset(clk, false); -} -EXPORT_SYMBOL(davinci_clk_reset_deassert); - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - if (!clk) - return 0; - else if (IS_ERR(clk)) - return -EINVAL; - - spin_lock_irqsave(&clockfw_lock, flags); - davinci_clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - davinci_clk_disable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return 0; - - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk == NULL || IS_ERR(clk)) - return 0; - - if (clk->round_rate) - return clk->round_rate(clk, rate); - - return clk->rate; -} -EXPORT_SYMBOL(clk_round_rate); - -/* Propagate rate to children */ -static void propagate_rate(struct clk *root) -{ - struct clk *clk; - - list_for_each_entry(clk, &root->children, childnode) { - if (clk->recalc) - clk->rate = clk->recalc(clk); - propagate_rate(clk); - } -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (!clk) - return 0; - else if (IS_ERR(clk)) - return -EINVAL; - - if (clk->set_rate) - ret = clk->set_rate(clk, rate); - - spin_lock_irqsave(&clockfw_lock, flags); - if (ret == 0) { - if (clk->recalc) - clk->rate = clk->recalc(clk); - propagate_rate(clk); - } - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - - if (!clk) - return 0; - else if (IS_ERR(clk)) - return -EINVAL; - - /* Cannot change parent on enabled clock */ - if (WARN_ON(clk->usecount)) - return -EINVAL; - - mutex_lock(&clocks_mutex); - if (clk->set_parent) { - int ret = clk->set_parent(clk, parent); - - if (ret) { - mutex_unlock(&clocks_mutex); - return ret; - } - } - clk->parent = parent; - list_del_init(&clk->childnode); - list_add(&clk->childnode, &clk->parent->children); - mutex_unlock(&clocks_mutex); - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->recalc) - clk->rate = clk->recalc(clk); - propagate_rate(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - if (!clk) - return NULL; - - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -int clk_register(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - if (WARN(clk->parent && !clk->parent->rate, - "CLK: %s parent %s has no rate!\n", - clk->name, clk->parent->name)) - return -EINVAL; - - INIT_LIST_HEAD(&clk->children); - - mutex_lock(&clocks_mutex); - list_add_tail(&clk->node, &clocks); - if (clk->parent) { - if (clk->set_parent) { - int ret = clk->set_parent(clk, clk->parent); - - if (ret) { - mutex_unlock(&clocks_mutex); - return ret; - } - } - list_add_tail(&clk->childnode, &clk->parent->children); - } - mutex_unlock(&clocks_mutex); - - /* If rate is already set, use it */ - if (clk->rate) - return 0; - - /* Else, see if there is a way to calculate it */ - if (clk->recalc) - clk->rate = clk->recalc(clk); - - /* Otherwise, default to parent rate */ - else if (clk->parent) - clk->rate = clk->parent->rate; - - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - - mutex_lock(&clocks_mutex); - list_del(&clk->node); - list_del(&clk->childnode); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -#ifdef CONFIG_DAVINCI_RESET_CLOCKS -/* - * Disable any unused clocks left on by the bootloader - */ -int __init davinci_clk_disable_unused(void) -{ - struct clk *ck; - - spin_lock_irq(&clockfw_lock); - list_for_each_entry(ck, &clocks, node) { - if (ck->usecount > 0) - continue; - if (!(ck->flags & CLK_PSC)) - continue; - - /* ignore if in Disabled or SwRstDisable states */ - if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) - continue; - - pr_debug("Clocks: disable unused %s\n", ck->name); - - davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc, - false, ck->flags); - } - spin_unlock_irq(&clockfw_lock); - - return 0; -} -#endif - -static unsigned long clk_sysclk_recalc(struct clk *clk) -{ - u32 v, plldiv; - struct pll_data *pll; - unsigned long rate = clk->rate; - - /* If this is the PLL base clock, no more calculations needed */ - if (clk->pll_data) - return rate; - - if (WARN_ON(!clk->parent)) - return rate; - - rate = clk->parent->rate; - - /* Otherwise, the parent must be a PLL */ - if (WARN_ON(!clk->parent->pll_data)) - return rate; - - pll = clk->parent->pll_data; - - /* If pre-PLL, source clock is before the multiplier and divider(s) */ - if (clk->flags & PRE_PLL) - rate = pll->input_rate; - - if (!clk->div_reg) - return rate; - - v = __raw_readl(pll->base + clk->div_reg); - if (v & PLLDIV_EN) { - plldiv = (v & pll->div_ratio_mask) + 1; - if (plldiv) - rate /= plldiv; - } - - return rate; -} - -int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) -{ - unsigned v; - struct pll_data *pll; - unsigned long input; - unsigned ratio = 0; - - /* If this is the PLL base clock, wrong function to call */ - if (clk->pll_data) - return -EINVAL; - - /* There must be a parent... */ - if (WARN_ON(!clk->parent)) - return -EINVAL; - - /* ... the parent must be a PLL... */ - if (WARN_ON(!clk->parent->pll_data)) - return -EINVAL; - - /* ... and this clock must have a divider. */ - if (WARN_ON(!clk->div_reg)) - return -EINVAL; - - pll = clk->parent->pll_data; - - input = clk->parent->rate; - - /* If pre-PLL, source clock is before the multiplier and divider(s) */ - if (clk->flags & PRE_PLL) - input = pll->input_rate; - - if (input > rate) { - /* - * Can afford to provide an output little higher than requested - * only if maximum rate supported by hardware on this sysclk - * is known. - */ - if (clk->maxrate) { - ratio = DIV_ROUND_CLOSEST(input, rate); - if (input / ratio > clk->maxrate) - ratio = 0; - } - - if (ratio == 0) - ratio = DIV_ROUND_UP(input, rate); - - ratio--; - } - - if (ratio > pll->div_ratio_mask) - return -EINVAL; - - do { - v = __raw_readl(pll->base + PLLSTAT); - } while (v & PLLSTAT_GOSTAT); - - v = __raw_readl(pll->base + clk->div_reg); - v &= ~pll->div_ratio_mask; - v |= ratio | PLLDIV_EN; - __raw_writel(v, pll->base + clk->div_reg); - - v = __raw_readl(pll->base + PLLCMD); - v |= PLLCMD_GOSET; - __raw_writel(v, pll->base + PLLCMD); - - do { - v = __raw_readl(pll->base + PLLSTAT); - } while (v & PLLSTAT_GOSTAT); - - return 0; -} -EXPORT_SYMBOL(davinci_set_sysclk_rate); - -static unsigned long clk_leafclk_recalc(struct clk *clk) -{ - if (WARN_ON(!clk->parent)) - return clk->rate; - - return clk->parent->rate; -} - -int davinci_simple_set_rate(struct clk *clk, unsigned long rate) -{ - clk->rate = rate; - return 0; -} - -static unsigned long clk_pllclk_recalc(struct clk *clk) -{ - u32 ctrl, mult = 1, prediv = 1, postdiv = 1; - u8 bypass; - struct pll_data *pll = clk->pll_data; - unsigned long rate = clk->rate; - - ctrl = __raw_readl(pll->base + PLLCTL); - rate = pll->input_rate = clk->parent->rate; - - if (ctrl & PLLCTL_PLLEN) { - bypass = 0; - mult = __raw_readl(pll->base + PLLM); - if (cpu_is_davinci_dm365()) - mult = 2 * (mult & PLLM_PLLM_MASK); - else - mult = (mult & PLLM_PLLM_MASK) + 1; - } else - bypass = 1; - - if (pll->flags & PLL_HAS_PREDIV) { - prediv = __raw_readl(pll->base + PREDIV); - if (prediv & PLLDIV_EN) - prediv = (prediv & pll->div_ratio_mask) + 1; - else - prediv = 1; - } - - /* pre-divider is fixed, but (some?) chips won't report that */ - if (cpu_is_davinci_dm355() && pll->num == 1) - prediv = 8; - - if (pll->flags & PLL_HAS_POSTDIV) { - postdiv = __raw_readl(pll->base + POSTDIV); - if (postdiv & PLLDIV_EN) - postdiv = (postdiv & pll->div_ratio_mask) + 1; - else - postdiv = 1; - } - - if (!bypass) { - rate /= prediv; - rate *= mult; - rate /= postdiv; - } - - pr_debug("PLL%d: input = %lu MHz [ ", - pll->num, clk->parent->rate / 1000000); - if (bypass) - pr_debug("bypass "); - if (prediv > 1) - pr_debug("/ %d ", prediv); - if (mult > 1) - pr_debug("* %d ", mult); - if (postdiv > 1) - pr_debug("/ %d ", postdiv); - pr_debug("] --> %lu MHz output.\n", rate / 1000000); - - return rate; -} - -/** - * davinci_set_pllrate - set the output rate of a given PLL. - * - * Note: Currently tested to work with OMAP-L138 only. - * - * @pll: pll whose rate needs to be changed. - * @prediv: The pre divider value. Passing 0 disables the pre-divider. - * @pllm: The multiplier value. Passing 0 leads to multiply-by-one. - * @postdiv: The post divider value. Passing 0 disables the post-divider. - */ -int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, - unsigned int mult, unsigned int postdiv) -{ - u32 ctrl; - unsigned int locktime; - unsigned long flags; - - if (pll->base == NULL) - return -EINVAL; - - /* - * PLL lock time required per OMAP-L138 datasheet is - * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm) - * as 4 and OSCIN cycle as 25 MHz. - */ - if (prediv) { - locktime = ((2000 * prediv) / 100); - prediv = (prediv - 1) | PLLDIV_EN; - } else { - locktime = PLL_LOCK_TIME; - } - if (postdiv) - postdiv = (postdiv - 1) | PLLDIV_EN; - if (mult) - mult = mult - 1; - - /* Protect against simultaneous calls to PLL setting seqeunce */ - spin_lock_irqsave(&clockfw_lock, flags); - - ctrl = __raw_readl(pll->base + PLLCTL); - - /* Switch the PLL to bypass mode */ - ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); - __raw_writel(ctrl, pll->base + PLLCTL); - - udelay(PLL_BYPASS_TIME); - - /* Reset and enable PLL */ - ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); - __raw_writel(ctrl, pll->base + PLLCTL); - - if (pll->flags & PLL_HAS_PREDIV) - __raw_writel(prediv, pll->base + PREDIV); - - __raw_writel(mult, pll->base + PLLM); - - if (pll->flags & PLL_HAS_POSTDIV) - __raw_writel(postdiv, pll->base + POSTDIV); - - udelay(PLL_RESET_TIME); - - /* Bring PLL out of reset */ - ctrl |= PLLCTL_PLLRST; - __raw_writel(ctrl, pll->base + PLLCTL); - - udelay(locktime); - - /* Remove PLL from bypass mode */ - ctrl |= PLLCTL_PLLEN; - __raw_writel(ctrl, pll->base + PLLCTL); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -EXPORT_SYMBOL(davinci_set_pllrate); - -/** - * davinci_set_refclk_rate() - Set the reference clock rate - * @rate: The new rate. - * - * Sets the reference clock rate to a given value. This will most likely - * result in the entire clock tree getting updated. - * - * This is used to support boards which use a reference clock different - * than that used by default in <soc>.c file. The reference clock rate - * should be updated early in the boot process; ideally soon after the - * clock tree has been initialized once with the default reference clock - * rate (davinci_clk_init()). - * - * Returns 0 on success, error otherwise. - */ -int davinci_set_refclk_rate(unsigned long rate) -{ - struct clk *refclk; - - refclk = clk_get(NULL, "ref"); - if (IS_ERR(refclk)) { - pr_err("%s: failed to get reference clock\n", __func__); - return PTR_ERR(refclk); - } - - clk_set_rate(refclk, rate); - - clk_put(refclk); - - return 0; -} - -int __init davinci_clk_init(struct clk_lookup *clocks) -{ - struct clk_lookup *c; - struct clk *clk; - size_t num_clocks = 0; - - for (c = clocks; c->clk; c++) { - clk = c->clk; - - if (!clk->recalc) { - - /* Check if clock is a PLL */ - if (clk->pll_data) - clk->recalc = clk_pllclk_recalc; - - /* Else, if it is a PLL-derived clock */ - else if (clk->flags & CLK_PLL) - clk->recalc = clk_sysclk_recalc; - - /* Otherwise, it is a leaf clock (PSC clock) */ - else if (clk->parent) - clk->recalc = clk_leafclk_recalc; - } - - if (clk->pll_data) { - struct pll_data *pll = clk->pll_data; - - if (!pll->div_ratio_mask) - pll->div_ratio_mask = PLLDIV_RATIO_MASK; - - if (pll->phys_base && !pll->base) { - pll->base = ioremap(pll->phys_base, SZ_4K); - WARN_ON(!pll->base); - } - } - - if (clk->recalc) - clk->rate = clk->recalc(clk); - - if (clk->lpsc) - clk->flags |= CLK_PSC; - - if (clk->flags & PSC_LRST) - clk->reset = davinci_clk_reset; - - clk_register(clk); - num_clocks++; - - /* Turn on clocks that Linux doesn't otherwise manage */ - if (clk->flags & ALWAYS_ENABLED) - clk_enable(clk); - } - - clkdev_add_table(clocks, num_clocks); - - return 0; -} - -#ifdef CONFIG_DEBUG_FS - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -#define CLKNAME_MAX 10 /* longest clock name */ -#define NEST_DELTA 2 -#define NEST_MAX 4 - -static void -dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) -{ - char *state; - char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; - struct clk *clk; - unsigned i; - - if (parent->flags & CLK_PLL) - state = "pll"; - else if (parent->flags & CLK_PSC) - state = "psc"; - else - state = ""; - - /* <nest spaces> name <pad to end> */ - memset(buf, ' ', sizeof(buf) - 1); - buf[sizeof(buf) - 1] = 0; - i = strlen(parent->name); - memcpy(buf + nest, parent->name, - min(i, (unsigned)(sizeof(buf) - 1 - nest))); - - seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", - buf, parent->usecount, state, clk_get_rate(parent)); - /* REVISIT show device associations too */ - - /* cost is now small, but not linear... */ - list_for_each_entry(clk, &parent->children, childnode) { - dump_clock(s, nest + NEST_DELTA, clk); - } -} - -static int davinci_ck_show(struct seq_file *m, void *v) -{ - struct clk *clk; - - /* - * Show clock tree; We trust nonzero usecounts equate to PSC enables... - */ - mutex_lock(&clocks_mutex); - list_for_each_entry(clk, &clocks, node) - if (!clk->parent) - dump_clock(m, 0, clk); - mutex_unlock(&clocks_mutex); - - return 0; -} - -static int davinci_ck_open(struct inode *inode, struct file *file) -{ - return single_open(file, davinci_ck_show, NULL); -} - -static const struct file_operations davinci_ck_operations = { - .open = davinci_ck_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init davinci_clk_debugfs_init(void) -{ - debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL, - &davinci_ck_operations); - return 0; - -} -device_initcall(davinci_clk_debugfs_init); -#endif /* CONFIG_DEBUG_FS */ diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index d7894d5aaa25..307383472400 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -12,10 +12,6 @@ #ifndef __ARCH_ARM_DAVINCI_CLOCK_H #define __ARCH_ARM_DAVINCI_CLOCK_H -#define DAVINCI_PLL1_BASE 0x01c40800 -#define DAVINCI_PLL2_BASE 0x01c40c00 -#define MAX_PLL 2 - /* PLL/Reset register offsets */ #define PLLCTL 0x100 #define PLLCTL_PLLEN BIT(0) @@ -65,76 +61,4 @@ */ #define PLL_LOCK_TIME 20 -#ifndef __ASSEMBLER__ - -#include <linux/list.h> -#include <linux/clkdev.h> - -#define PLLSTAT_GOSTAT BIT(0) -#define PLLCMD_GOSET BIT(0) - -struct pll_data { - u32 phys_base; - void __iomem *base; - u32 num; - u32 flags; - u32 input_rate; - u32 div_ratio_mask; -}; -#define PLL_HAS_PREDIV 0x01 -#define PLL_HAS_POSTDIV 0x02 - -struct clk { - struct list_head node; - struct module *owner; - const char *name; - unsigned long rate; - unsigned long maxrate; /* H/W supported max rate */ - u8 usecount; - u8 lpsc; - u8 gpsc; - u8 domain; - u32 flags; - struct clk *parent; - struct list_head children; /* list of children */ - struct list_head childnode; /* parent's child list node */ - struct pll_data *pll_data; - u32 div_reg; - unsigned long (*recalc) (struct clk *); - int (*set_rate) (struct clk *clk, unsigned long rate); - int (*round_rate) (struct clk *clk, unsigned long rate); - int (*reset) (struct clk *clk, bool reset); - void (*clk_enable) (struct clk *clk); - void (*clk_disable) (struct clk *clk); - int (*set_parent) (struct clk *clk, struct clk *parent); -}; - -/* Clock flags: SoC-specific flags start at BIT(16) */ -#define ALWAYS_ENABLED BIT(1) -#define CLK_PSC BIT(2) -#define CLK_PLL BIT(3) /* PLL-derived clock */ -#define PRE_PLL BIT(4) /* source is before PLL mult/div */ -#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ -#define PSC_FORCE BIT(6) /* Force module state transtition */ -#define PSC_LRST BIT(8) /* Use local reset on enable/disable */ - -#define CLK(dev, con, ck) \ - { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - } \ - -int davinci_clk_init(struct clk_lookup *clocks); -int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, - unsigned int mult, unsigned int postdiv); -int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); -int davinci_set_refclk_rate(unsigned long rate); -int davinci_simple_set_rate(struct clk *clk, unsigned long rate); -int davinci_clk_reset(struct clk *clk, bool reset); -void davinci_clk_enable(struct clk *clk); -void davinci_clk_disable(struct clk *clk); - -#endif - #endif diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c index bcb6a7ba84e9..e1d0f0d841ff 100644 --- a/arch/arm/mach-davinci/common.c +++ b/arch/arm/mach-davinci/common.c @@ -20,8 +20,6 @@ #include <mach/common.h> #include <mach/cputype.h> -#include "clock.h" - struct davinci_soc_info davinci_soc_info; EXPORT_SYMBOL(davinci_soc_info); @@ -118,5 +116,4 @@ err: void __init davinci_init_late(void) { davinci_cpufreq_init(); - davinci_clk_disable_unused(); } diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 350d7673aa4d..0bc5bd2665df 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -8,21 +8,20 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ +#include <linux/clk-provider.h> +#include <linux/clk/davinci.h> #include <linux/gpio.h> #include <linux/init.h> -#include <linux/clk.h> #include <linux/platform_data/gpio-davinci.h> #include <asm/mach/map.h> -#include "psc.h" -#include <mach/irqs.h> -#include <mach/cputype.h> #include <mach/common.h> -#include <mach/time.h> +#include <mach/cputype.h> #include <mach/da8xx.h> +#include <mach/irqs.h> +#include <mach/time.h> -#include "clock.h" #include "mux.h" /* Offsets of the 8 compare registers on the da830 */ @@ -37,402 +36,6 @@ #define DA830_REF_FREQ 24000000 -static struct pll_data pll0_data = { - .num = 1, - .phys_base = DA8XX_PLL0_BASE, - .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, -}; - -static struct clk ref_clk = { - .name = "ref_clk", - .rate = DA830_REF_FREQ, -}; - -static struct clk pll0_clk = { - .name = "pll0", - .parent = &ref_clk, - .pll_data = &pll0_data, - .flags = CLK_PLL, -}; - -static struct clk pll0_aux_clk = { - .name = "pll0_aux_clk", - .parent = &pll0_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll0_sysclk2 = { - .name = "pll0_sysclk2", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll0_sysclk3 = { - .name = "pll0_sysclk3", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static struct clk pll0_sysclk4 = { - .name = "pll0_sysclk4", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV4, -}; - -static struct clk pll0_sysclk5 = { - .name = "pll0_sysclk5", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV5, -}; - -static struct clk pll0_sysclk6 = { - .name = "pll0_sysclk6", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV6, -}; - -static struct clk pll0_sysclk7 = { - .name = "pll0_sysclk7", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV7, -}; - -static struct clk i2c0_clk = { - .name = "i2c0", - .parent = &pll0_aux_clk, -}; - -static struct clk timerp64_0_clk = { - .name = "timer0", - .parent = &pll0_aux_clk, -}; - -static struct clk timerp64_1_clk = { - .name = "timer1", - .parent = &pll0_aux_clk, -}; - -static struct clk arm_rom_clk = { - .name = "arm_rom", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, - .flags = ALWAYS_ENABLED, -}; - -static struct clk scr0_ss_clk = { - .name = "scr0_ss", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_SCR0_SS, - .flags = ALWAYS_ENABLED, -}; - -static struct clk scr1_ss_clk = { - .name = "scr1_ss", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_SCR1_SS, - .flags = ALWAYS_ENABLED, -}; - -static struct clk scr2_ss_clk = { - .name = "scr2_ss", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_SCR2_SS, - .flags = ALWAYS_ENABLED, -}; - -static struct clk dmax_clk = { - .name = "dmax", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_PRUSS, - .flags = ALWAYS_ENABLED, -}; - -static struct clk tpcc_clk = { - .name = "tpcc", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_TPCC, - .flags = ALWAYS_ENABLED | CLK_PSC, -}; - -static struct clk tptc0_clk = { - .name = "tptc0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_TPTC0, - .flags = ALWAYS_ENABLED, -}; - -static struct clk tptc1_clk = { - .name = "tptc1", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_TPTC1, - .flags = ALWAYS_ENABLED, -}; - -static struct clk mmcsd_clk = { - .name = "mmcsd", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_MMC_SD, -}; - -static struct clk uart0_clk = { - .name = "uart0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_UART0, -}; - -static struct clk uart1_clk = { - .name = "uart1", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_UART1, - .gpsc = 1, -}; - -static struct clk uart2_clk = { - .name = "uart2", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_UART2, - .gpsc = 1, -}; - -static struct clk spi0_clk = { - .name = "spi0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_SPI0, -}; - -static struct clk spi1_clk = { - .name = "spi1", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_SPI1, - .gpsc = 1, -}; - -static struct clk ecap0_clk = { - .name = "ecap0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_ECAP, - .gpsc = 1, -}; - -static struct clk ecap1_clk = { - .name = "ecap1", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_ECAP, - .gpsc = 1, -}; - -static struct clk ecap2_clk = { - .name = "ecap2", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_ECAP, - .gpsc = 1, -}; - -static struct clk pwm0_clk = { - .name = "pwm0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_PWM, - .gpsc = 1, -}; - -static struct clk pwm1_clk = { - .name = "pwm1", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_PWM, - .gpsc = 1, -}; - -static struct clk pwm2_clk = { - .name = "pwm2", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_PWM, - .gpsc = 1, -}; - -static struct clk eqep0_clk = { - .name = "eqep0", - .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_EQEP, - .gpsc = 1, -}; - -static struct clk eqep1_clk = { - .name = "eqep1", - .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_EQEP, - .gpsc = 1, -}; - -static struct clk lcdc_clk = { - .name = "lcdc", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_LCDC, - .gpsc = 1, -}; - -static struct clk mcasp0_clk = { - .name = "mcasp0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_McASP0, - .gpsc = 1, -}; - -static struct clk mcasp1_clk = { - .name = "mcasp1", - .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_McASP1, - .gpsc = 1, -}; - -static struct clk mcasp2_clk = { - .name = "mcasp2", - .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_McASP2, - .gpsc = 1, -}; - -static struct clk usb20_clk = { - .name = "usb20", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_USB20, - .gpsc = 1, -}; - -static struct clk cppi41_clk = { - .name = "cppi41", - .parent = &usb20_clk, -}; - -static struct clk aemif_clk = { - .name = "aemif", - .parent = &pll0_sysclk3, - .lpsc = DA8XX_LPSC0_EMIF25, - .flags = ALWAYS_ENABLED, -}; - -static struct clk aintc_clk = { - .name = "aintc", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC0_AINTC, - .flags = ALWAYS_ENABLED, -}; - -static struct clk secu_mgr_clk = { - .name = "secu_mgr", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC0_SECU_MGR, - .flags = ALWAYS_ENABLED, -}; - -static struct clk emac_clk = { - .name = "emac", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC1_CPGMAC, - .gpsc = 1, -}; - -static struct clk gpio_clk = { - .name = "gpio", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC1_GPIO, - .gpsc = 1, -}; - -static struct clk i2c1_clk = { - .name = "i2c1", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC1_I2C, - .gpsc = 1, -}; - -static struct clk usb11_clk = { - .name = "usb11", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC1_USB11, - .gpsc = 1, -}; - -static struct clk emif3_clk = { - .name = "emif3", - .parent = &pll0_sysclk5, - .lpsc = DA8XX_LPSC1_EMIF3C, - .gpsc = 1, - .flags = ALWAYS_ENABLED, -}; - -static struct clk arm_clk = { - .name = "arm", - .parent = &pll0_sysclk6, - .lpsc = DA8XX_LPSC0_ARM, - .flags = ALWAYS_ENABLED, -}; - -static struct clk rmii_clk = { - .name = "rmii", - .parent = &pll0_sysclk7, -}; - -static struct clk_lookup da830_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll0", &pll0_clk), - CLK(NULL, "pll0_aux", &pll0_aux_clk), - CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), - CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), - CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), - CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), - CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), - CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), - CLK("i2c_davinci.1", NULL, &i2c0_clk), - CLK(NULL, "timer0", &timerp64_0_clk), - CLK("davinci-wdt", NULL, &timerp64_1_clk), - CLK(NULL, "arm_rom", &arm_rom_clk), - CLK(NULL, "scr0_ss", &scr0_ss_clk), - CLK(NULL, "scr1_ss", &scr1_ss_clk), - CLK(NULL, "scr2_ss", &scr2_ss_clk), - CLK(NULL, "dmax", &dmax_clk), - CLK(NULL, "tpcc", &tpcc_clk), - CLK(NULL, "tptc0", &tptc0_clk), - CLK(NULL, "tptc1", &tptc1_clk), - CLK("da830-mmc.0", NULL, &mmcsd_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK("spi_davinci.0", NULL, &spi0_clk), - CLK("spi_davinci.1", NULL, &spi1_clk), - CLK(NULL, "ecap0", &ecap0_clk), - CLK(NULL, "ecap1", &ecap1_clk), - CLK(NULL, "ecap2", &ecap2_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK("eqep.0", NULL, &eqep0_clk), - CLK("eqep.1", NULL, &eqep1_clk), - CLK("da8xx_lcdc.0", "fck", &lcdc_clk), - CLK("davinci-mcasp.0", NULL, &mcasp0_clk), - CLK("davinci-mcasp.1", NULL, &mcasp1_clk), - CLK("davinci-mcasp.2", NULL, &mcasp2_clk), - CLK("musb-da8xx", NULL, &usb20_clk), - CLK("cppi41-dmaengine", NULL, &cppi41_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "aintc", &aintc_clk), - CLK(NULL, "secu_mgr", &secu_mgr_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK("i2c_davinci.2", NULL, &i2c1_clk), - CLK("ohci-da8xx", NULL, &usb11_clk), - CLK(NULL, "emif3", &emif3_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "rmii", &rmii_clk), - CLK(NULL, NULL, NULL), -}; - /* * Device specific mux setup * @@ -1130,8 +733,6 @@ static struct map_desc da830_io_desc[] = { }, }; -static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; - /* Contents of JTAG ID register used to identify exact cpu type */ static struct davinci_id da830_ids[] = { { @@ -1200,8 +801,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = { .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, .ids = da830_ids, .ids_num = ARRAY_SIZE(da830_ids), - .psc_bases = da830_psc_bases, - .psc_bases_num = ARRAY_SIZE(da830_psc_bases), .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da830_pins, .pinmux_pins_num = ARRAY_SIZE(da830_pins), @@ -1223,6 +822,53 @@ void __init da830_init(void) void __init da830_init_time(void) { - davinci_clk_init(da830_clks); - davinci_timer_init(); + void __iomem *pll; + struct clk *clk; + + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ); + + pll = ioremap(DA8XX_PLL0_BASE, SZ_4K); + + da830_pll_init(NULL, pll, NULL); + + clk = clk_get(NULL, "timer0"); + + davinci_timer_init(clk); +} + +static struct resource da830_psc0_resources[] = { + { + .start = DA8XX_PSC0_BASE, + .end = DA8XX_PSC0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da830_psc0_device = { + .name = "da830-psc0", + .id = -1, + .resource = da830_psc0_resources, + .num_resources = ARRAY_SIZE(da830_psc0_resources), +}; + +static struct resource da830_psc1_resources[] = { + { + .start = DA8XX_PSC1_BASE, + .end = DA8XX_PSC1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da830_psc1_device = { + .name = "da830-psc1", + .id = -1, + .resource = da830_psc1_resources, + .num_resources = ARRAY_SIZE(da830_psc1_resources), +}; + +void __init da830_register_clocks(void) +{ + /* PLL is registered in da830_init_time() */ + platform_device_register(&da830_psc0_device); + platform_device_register(&da830_psc1_device); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 34117e614e08..4528bbf0c861 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -11,27 +11,31 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ + +#include <linux/clk-provider.h> +#include <linux/clk/davinci.h> #include <linux/clkdev.h> +#include <linux/cpufreq.h> #include <linux/gpio.h> #include <linux/init.h> -#include <linux/clk.h> +#include <linux/mfd/da8xx-cfgchip.h> +#include <linux/platform_data/clk-da8xx-cfgchip.h> +#include <linux/platform_data/clk-davinci-pll.h> +#include <linux/platform_data/gpio-davinci.h> #include <linux/platform_device.h> -#include <linux/cpufreq.h> +#include <linux/regmap.h> #include <linux/regulator/consumer.h> -#include <linux/platform_data/gpio-davinci.h> #include <asm/mach/map.h> -#include "psc.h" -#include <mach/irqs.h> -#include <mach/cputype.h> #include <mach/common.h> -#include <mach/time.h> -#include <mach/da8xx.h> #include <mach/cpufreq.h> +#include <mach/cputype.h> +#include <mach/da8xx.h> +#include <mach/irqs.h> #include <mach/pm.h> +#include <mach/time.h> -#include "clock.h" #include "mux.h" #define DA850_PLL1_BASE 0x01e1a000 @@ -40,550 +44,6 @@ #define DA850_REF_FREQ 24000000 -#define CFGCHIP3_ASYNC3_CLKSRC BIT(4) -#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) -#define CFGCHIP0_PLL_MASTER_LOCK BIT(4) - -static int da850_set_armrate(struct clk *clk, unsigned long rate); -static int da850_round_armrate(struct clk *clk, unsigned long rate); -static int da850_set_pll0rate(struct clk *clk, unsigned long armrate); - -static struct pll_data pll0_data = { - .num = 1, - .phys_base = DA8XX_PLL0_BASE, - .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, -}; - -static struct clk ref_clk = { - .name = "ref_clk", - .rate = DA850_REF_FREQ, - .set_rate = davinci_simple_set_rate, -}; - -static struct clk pll0_clk = { - .name = "pll0", - .parent = &ref_clk, - .pll_data = &pll0_data, - .flags = CLK_PLL, - .set_rate = da850_set_pll0rate, -}; - -static struct clk pll0_aux_clk = { - .name = "pll0_aux_clk", - .parent = &pll0_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll0_sysclk1 = { - .name = "pll0_sysclk1", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll0_sysclk2 = { - .name = "pll0_sysclk2", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll0_sysclk3 = { - .name = "pll0_sysclk3", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, - .set_rate = davinci_set_sysclk_rate, - .maxrate = 100000000, -}; - -static struct clk pll0_sysclk4 = { - .name = "pll0_sysclk4", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV4, -}; - -static struct clk pll0_sysclk5 = { - .name = "pll0_sysclk5", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV5, -}; - -static struct clk pll0_sysclk6 = { - .name = "pll0_sysclk6", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV6, -}; - -static struct clk pll0_sysclk7 = { - .name = "pll0_sysclk7", - .parent = &pll0_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV7, -}; - -static struct pll_data pll1_data = { - .num = 2, - .phys_base = DA850_PLL1_BASE, - .flags = PLL_HAS_POSTDIV, -}; - -static struct clk pll1_clk = { - .name = "pll1", - .parent = &ref_clk, - .pll_data = &pll1_data, - .flags = CLK_PLL, -}; - -static struct clk pll1_aux_clk = { - .name = "pll1_aux_clk", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll1_sysclk2 = { - .name = "pll1_sysclk2", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll1_sysclk3 = { - .name = "pll1_sysclk3", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static int da850_async3_set_parent(struct clk *clk, struct clk *parent) -{ - u32 val; - - val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); - - if (parent == &pll0_sysclk2) { - val &= ~CFGCHIP3_ASYNC3_CLKSRC; - } else if (parent == &pll1_sysclk2) { - val |= CFGCHIP3_ASYNC3_CLKSRC; - } else { - pr_err("Bad parent on async3 clock mux\n"); - return -EINVAL; - } - - writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); - - return 0; -} - -static struct clk async3_clk = { - .name = "async3", - .parent = &pll1_sysclk2, - .set_parent = da850_async3_set_parent, -}; - -static struct clk i2c0_clk = { - .name = "i2c0", - .parent = &pll0_aux_clk, -}; - -static struct clk timerp64_0_clk = { - .name = "timer0", - .parent = &pll0_aux_clk, -}; - -static struct clk timerp64_1_clk = { - .name = "timer1", - .parent = &pll0_aux_clk, -}; - -static struct clk arm_rom_clk = { - .name = "arm_rom", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, - .flags = ALWAYS_ENABLED, -}; - -static struct clk tpcc0_clk = { - .name = "tpcc0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_TPCC, - .flags = ALWAYS_ENABLED | CLK_PSC, -}; - -static struct clk tptc0_clk = { - .name = "tptc0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_TPTC0, - .flags = ALWAYS_ENABLED, -}; - -static struct clk tptc1_clk = { - .name = "tptc1", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_TPTC1, - .flags = ALWAYS_ENABLED, -}; - -static struct clk tpcc1_clk = { - .name = "tpcc1", - .parent = &pll0_sysclk2, - .lpsc = DA850_LPSC1_TPCC1, - .gpsc = 1, - .flags = CLK_PSC | ALWAYS_ENABLED, -}; - -static struct clk tptc2_clk = { - .name = "tptc2", - .parent = &pll0_sysclk2, - .lpsc = DA850_LPSC1_TPTC2, - .gpsc = 1, - .flags = ALWAYS_ENABLED, -}; - -static struct clk pruss_clk = { - .name = "pruss", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_PRUSS, -}; - -static struct clk uart0_clk = { - .name = "uart0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_UART0, -}; - -static struct clk uart1_clk = { - .name = "uart1", - .parent = &async3_clk, - .lpsc = DA8XX_LPSC1_UART1, - .gpsc = 1, -}; - -static struct clk uart2_clk = { - .name = "uart2", - .parent = &async3_clk, - .lpsc = DA8XX_LPSC1_UART2, - .gpsc = 1, -}; - -static struct clk aintc_clk = { - .name = "aintc", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC0_AINTC, - .flags = ALWAYS_ENABLED, -}; - -static struct clk gpio_clk = { - .name = "gpio", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC1_GPIO, - .gpsc = 1, -}; - -static struct clk i2c1_clk = { - .name = "i2c1", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC1_I2C, - .gpsc = 1, -}; - -static struct clk emif3_clk = { - .name = "emif3", - .parent = &pll0_sysclk5, - .lpsc = DA8XX_LPSC1_EMIF3C, - .gpsc = 1, - .flags = ALWAYS_ENABLED, -}; - -static struct clk arm_clk = { - .name = "arm", - .parent = &pll0_sysclk6, - .lpsc = DA8XX_LPSC0_ARM, - .flags = ALWAYS_ENABLED, - .set_rate = da850_set_armrate, - .round_rate = da850_round_armrate, -}; - -static struct clk rmii_clk = { - .name = "rmii", - .parent = &pll0_sysclk7, -}; - -static struct clk emac_clk = { - .name = "emac", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC1_CPGMAC, - .gpsc = 1, -}; - -/* - * In order to avoid adding the emac_clk to the clock lookup table twice (and - * screwing up the linked list in the process) create a separate clock for - * mdio inheriting the rate from emac_clk. - */ -static struct clk mdio_clk = { - .name = "mdio", - .parent = &emac_clk, -}; - -static struct clk mcasp_clk = { - .name = "mcasp", - .parent = &async3_clk, - .lpsc = DA8XX_LPSC1_McASP0, - .gpsc = 1, -}; - -static struct clk mcbsp0_clk = { - .name = "mcbsp0", - .parent = &async3_clk, - .lpsc = DA850_LPSC1_McBSP0, - .gpsc = 1, -}; - -static struct clk mcbsp1_clk = { - .name = "mcbsp1", - .parent = &async3_clk, - .lpsc = DA850_LPSC1_McBSP1, - .gpsc = 1, -}; - -static struct clk lcdc_clk = { - .name = "lcdc", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_LCDC, - .gpsc = 1, -}; - -static struct clk mmcsd0_clk = { - .name = "mmcsd0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_MMC_SD, -}; - -static struct clk mmcsd1_clk = { - .name = "mmcsd1", - .parent = &pll0_sysclk2, - .lpsc = DA850_LPSC1_MMC_SD1, - .gpsc = 1, -}; - -static struct clk aemif_clk = { - .name = "aemif", - .parent = &pll0_sysclk3, - .lpsc = DA8XX_LPSC0_EMIF25, - .flags = ALWAYS_ENABLED, -}; - -/* - * In order to avoid adding the aemif_clk to the clock lookup table twice (and - * screwing up the linked list in the process) create a separate clock for - * nand inheriting the rate from aemif_clk. - */ -static struct clk aemif_nand_clk = { - .name = "nand", - .parent = &aemif_clk, -}; - -static struct clk usb11_clk = { - .name = "usb11", - .parent = &pll0_sysclk4, - .lpsc = DA8XX_LPSC1_USB11, - .gpsc = 1, -}; - -static struct clk usb20_clk = { - .name = "usb20", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_USB20, - .gpsc = 1, -}; - -static struct clk cppi41_clk = { - .name = "cppi41", - .parent = &usb20_clk, -}; - -static struct clk spi0_clk = { - .name = "spi0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC0_SPI0, -}; - -static struct clk spi1_clk = { - .name = "spi1", - .parent = &async3_clk, - .lpsc = DA8XX_LPSC1_SPI1, - .gpsc = 1, -}; - -static struct clk vpif_clk = { - .name = "vpif", - .parent = &pll0_sysclk2, - .lpsc = DA850_LPSC1_VPIF, - .gpsc = 1, -}; - -static struct clk sata_clk = { - .name = "sata", - .parent = &pll0_sysclk2, - .lpsc = DA850_LPSC1_SATA, - .gpsc = 1, - .flags = PSC_FORCE, -}; - -static struct clk dsp_clk = { - .name = "dsp", - .parent = &pll0_sysclk1, - .domain = DAVINCI_GPSC_DSPDOMAIN, - .lpsc = DA8XX_LPSC0_GEM, - .flags = PSC_LRST | PSC_FORCE, -}; - -static struct clk ehrpwm_clk = { - .name = "ehrpwm", - .parent = &async3_clk, - .lpsc = DA8XX_LPSC1_PWM, - .gpsc = 1, -}; - -static struct clk ehrpwm0_clk = { - .name = "ehrpwm0", - .parent = &ehrpwm_clk, -}; - -static struct clk ehrpwm1_clk = { - .name = "ehrpwm1", - .parent = &ehrpwm_clk, -}; - -#define DA8XX_EHRPWM_TBCLKSYNC BIT(12) - -static void ehrpwm_tblck_enable(struct clk *clk) -{ - u32 val; - - val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); - val |= DA8XX_EHRPWM_TBCLKSYNC; - writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); -} - -static void ehrpwm_tblck_disable(struct clk *clk) -{ - u32 val; - - val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); - val &= ~DA8XX_EHRPWM_TBCLKSYNC; - writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); -} - -static struct clk ehrpwm_tbclk = { - .name = "ehrpwm_tbclk", - .parent = &ehrpwm_clk, - .clk_enable = ehrpwm_tblck_enable, - .clk_disable = ehrpwm_tblck_disable, -}; - -static struct clk ehrpwm0_tbclk = { - .name = "ehrpwm0_tbclk", - .parent = &ehrpwm_tbclk, -}; - -static struct clk ehrpwm1_tbclk = { - .name = "ehrpwm1_tbclk", - .parent = &ehrpwm_tbclk, -}; - -static struct clk ecap_clk = { - .name = "ecap", - .parent = &async3_clk, - .lpsc = DA8XX_LPSC1_ECAP, - .gpsc = 1, -}; - -static struct clk ecap0_clk = { - .name = "ecap0_clk", - .parent = &ecap_clk, -}; - -static struct clk ecap1_clk = { - .name = "ecap1_clk", - .parent = &ecap_clk, -}; - -static struct clk ecap2_clk = { - .name = "ecap2_clk", - .parent = &ecap_clk, -}; - -static struct clk_lookup da850_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll0", &pll0_clk), - CLK(NULL, "pll0_aux", &pll0_aux_clk), - CLK(NULL, "pll0_sysclk1", &pll0_sysclk1), - CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), - CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), - CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), - CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), - CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), - CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "async3", &async3_clk), - CLK("i2c_davinci.1", NULL, &i2c0_clk), - CLK(NULL, "timer0", &timerp64_0_clk), - CLK("davinci-wdt", NULL, &timerp64_1_clk), - CLK(NULL, "arm_rom", &arm_rom_clk), - CLK(NULL, "tpcc0", &tpcc0_clk), - CLK(NULL, "tptc0", &tptc0_clk), - CLK(NULL, "tptc1", &tptc1_clk), - CLK(NULL, "tpcc1", &tpcc1_clk), - CLK(NULL, "tptc2", &tptc2_clk), - CLK("pruss_uio", "pruss", &pruss_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK(NULL, "aintc", &aintc_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK("i2c_davinci.2", NULL, &i2c1_clk), - CLK(NULL, "emif3", &emif3_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "rmii", &rmii_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &mdio_clk), - CLK("davinci-mcasp.0", NULL, &mcasp_clk), - CLK("davinci-mcbsp.0", NULL, &mcbsp0_clk), - CLK("davinci-mcbsp.1", NULL, &mcbsp1_clk), - CLK("da8xx_lcdc.0", "fck", &lcdc_clk), - CLK("da830-mmc.0", NULL, &mmcsd0_clk), - CLK("da830-mmc.1", NULL, &mmcsd1_clk), - CLK("ti-aemif", NULL, &aemif_clk), - CLK("davinci-nand.0", "aemif", &aemif_nand_clk), - CLK("ohci-da8xx", NULL, &usb11_clk), - CLK("musb-da8xx", NULL, &usb20_clk), - CLK("cppi41-dmaengine", NULL, &cppi41_clk), - CLK("spi_davinci.0", NULL, &spi0_clk), - CLK("spi_davinci.1", NULL, &spi1_clk), - CLK("vpif", NULL, &vpif_clk), - CLK("ahci_da850", "fck", &sata_clk), - CLK("davinci-rproc.0", NULL, &dsp_clk), - CLK(NULL, NULL, &ehrpwm_clk), - CLK("ehrpwm.0", "fck", &ehrpwm0_clk), - CLK("ehrpwm.1", "fck", &ehrpwm1_clk), - CLK(NULL, NULL, &ehrpwm_tbclk), - CLK("ehrpwm.0", "tbclk", &ehrpwm0_tbclk), - CLK("ehrpwm.1", "tbclk", &ehrpwm1_tbclk), - CLK(NULL, NULL, &ecap_clk), - CLK("ecap.0", "fck", &ecap0_clk), - CLK("ecap.1", "fck", &ecap1_clk), - CLK("ecap.2", "fck", &ecap2_clk), - CLK(NULL, NULL, NULL), -}; - /* * Device specific mux setup * @@ -958,8 +418,6 @@ static struct map_desc da850_io_desc[] = { }, }; -static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; - /* Contents of JTAG ID register used to identify exact cpu type */ static struct davinci_id da850_ids[] = { { @@ -1169,89 +627,11 @@ int da850_register_cpufreq(char *async_clk) return platform_device_register(&da850_cpufreq_device); } - -static int da850_round_armrate(struct clk *clk, unsigned long rate) -{ - int ret = 0, diff; - unsigned int best = (unsigned int) -1; - struct cpufreq_frequency_table *table = cpufreq_info.freq_table; - struct cpufreq_frequency_table *pos; - - rate /= 1000; /* convert to kHz */ - - cpufreq_for_each_entry(pos, table) { - diff = pos->frequency - rate; - if (diff < 0) - diff = -diff; - - if (diff < best) { - best = diff; - ret = pos->frequency; - } - } - - return ret * 1000; -} - -static int da850_set_armrate(struct clk *clk, unsigned long index) -{ - struct clk *pllclk = &pll0_clk; - - return clk_set_rate(pllclk, index); -} - -static int da850_set_pll0rate(struct clk *clk, unsigned long rate) -{ - struct pll_data *pll = clk->pll_data; - struct cpufreq_frequency_table *freq; - unsigned int prediv, mult, postdiv; - struct da850_opp *opp = NULL; - int ret; - - rate /= 1000; - - for (freq = da850_freq_table; - freq->frequency != CPUFREQ_TABLE_END; freq++) { - /* rate is in Hz, freq->frequency is in KHz */ - if (freq->frequency == rate) { - opp = (struct da850_opp *)freq->driver_data; - break; - } - } - - if (!opp) - return -EINVAL; - - prediv = opp->prediv; - mult = opp->mult; - postdiv = opp->postdiv; - - ret = davinci_set_pllrate(pll, prediv, mult, postdiv); - if (WARN_ON(ret)) - return ret; - - return 0; -} #else int __init da850_register_cpufreq(char *async_clk) { return 0; } - -static int da850_set_armrate(struct clk *clk, unsigned long rate) -{ - return -EINVAL; -} - -static int da850_set_pll0rate(struct clk *clk, unsigned long armrate) -{ - return -EINVAL; -} - -static int da850_round_armrate(struct clk *clk, unsigned long rate) -{ - return clk->rate; -} #endif /* VPIF resource, platform data */ @@ -1353,8 +733,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, .ids = da850_ids, .ids_num = ARRAY_SIZE(da850_ids), - .psc_bases = da850_psc_bases, - .psc_bases_num = ARRAY_SIZE(da850_psc_bases), .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da850_pins, .pinmux_pins_num = ARRAY_SIZE(da850_pins), @@ -1370,8 +748,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { void __init da850_init(void) { - unsigned int v; - davinci_common_init(&davinci_soc_info_da850); da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); @@ -1379,22 +755,124 @@ void __init da850_init(void) return; da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); - if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) - return; + WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); +} + +void __init da850_init_time(void) +{ + void __iomem *pll0; + struct regmap *cfgchip; + struct clk *clk; - /* Unlock writing to PLL0 registers */ - v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); - v &= ~CFGCHIP0_PLL_MASTER_LOCK; - __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); - /* Unlock writing to PLL1 registers */ - v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); - v &= ~CFGCHIP3_PLL1_MASTER_LOCK; - __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); + cfgchip = da8xx_get_cfgchip(); + + da850_pll0_init(NULL, pll0, cfgchip); + + clk = clk_get(NULL, "timer0"); + + davinci_timer_init(clk); } -void __init da850_init_time(void) +static struct resource da850_pll1_resources[] = { + { + .start = DA850_PLL1_BASE, + .end = DA850_PLL1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct davinci_pll_platform_data da850_pll1_pdata; + +static struct platform_device da850_pll1_device = { + .name = "da850-pll1", + .id = -1, + .resource = da850_pll1_resources, + .num_resources = ARRAY_SIZE(da850_pll1_resources), + .dev = { + .platform_data = &da850_pll1_pdata, + }, +}; + +static struct resource da850_psc0_resources[] = { + { + .start = DA8XX_PSC0_BASE, + .end = DA8XX_PSC0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da850_psc0_device = { + .name = "da850-psc0", + .id = -1, + .resource = da850_psc0_resources, + .num_resources = ARRAY_SIZE(da850_psc0_resources), +}; + +static struct resource da850_psc1_resources[] = { + { + .start = DA8XX_PSC1_BASE, + .end = DA8XX_PSC1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da850_psc1_device = { + .name = "da850-psc1", + .id = -1, + .resource = da850_psc1_resources, + .num_resources = ARRAY_SIZE(da850_psc1_resources), +}; + +static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata; + +static struct platform_device da850_async1_clksrc_device = { + .name = "da850-async1-clksrc", + .id = -1, + .dev = { + .platform_data = &da850_async1_pdata, + }, +}; + +static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata; + +static struct platform_device da850_async3_clksrc_device = { + .name = "da850-async3-clksrc", + .id = -1, + .dev = { + .platform_data = &da850_async3_pdata, + }, +}; + +static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata; + +static struct platform_device da850_tbclksync_device = { + .name = "da830-tbclksync", + .id = -1, + .dev = { + .platform_data = &da850_tbclksync_pdata, + }, +}; + +void __init da850_register_clocks(void) { - davinci_clk_init(da850_clks); - davinci_timer_init(); + /* PLL0 is registered in da850_init_time() */ + + da850_pll1_pdata.cfgchip = da8xx_get_cfgchip(); + platform_device_register(&da850_pll1_device); + + da850_async1_pdata.cfgchip = da8xx_get_cfgchip(); + platform_device_register(&da850_async1_clksrc_device); + + da850_async3_pdata.cfgchip = da8xx_get_cfgchip(); + platform_device_register(&da850_async3_clksrc_device); + + platform_device_register(&da850_psc0_device); + + platform_device_register(&da850_psc1_device); + + da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip(); + platform_device_register(&da850_tbclksync_device); } diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index ab199f4b9ce4..beac80ec4037 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -7,81 +7,16 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <linux/io.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <linux/irqdomain.h> -#include <linux/platform_data/ti-aemif.h> #include <asm/mach/arch.h> #include <mach/common.h> -#include "cp_intc.h" #include <mach/da8xx.h> -static struct of_dev_auxdata da850_aemif_auxdata_lookup[] = { - OF_DEV_AUXDATA("ti,davinci-nand", 0x62000000, "davinci-nand.0", NULL), - {} -}; - -static struct aemif_platform_data aemif_data = { - .dev_lookup = da850_aemif_auxdata_lookup, -}; - -static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL), - OF_DEV_AUXDATA("ti,davinci-i2c", 0x01e28000, "i2c_davinci.2", NULL), - OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL), - OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL), - OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm.0", NULL), - OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm.1", NULL), - OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap.0", NULL), - OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap.1", NULL), - OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap.2", NULL), - OF_DEV_AUXDATA("ti,da830-spi", 0x01c41000, "spi_davinci.0", NULL), - OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL), - OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL), - OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL), - OF_DEV_AUXDATA("ns16550a", 0x01d0d000, "serial8250.2", NULL), - OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL), - OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1", - NULL), - OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL), - OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", &aemif_data), - OF_DEV_AUXDATA("ti,da850-tilcdc", 0x01e13000, "da8xx_lcdc.0", NULL), - OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci-da8xx", NULL), - OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL), - OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL), - OF_DEV_AUXDATA("ti,da850-ahci", 0x01e18000, "ahci_da850", NULL), - OF_DEV_AUXDATA("ti,da850-vpif", 0x01e17000, "vpif", NULL), - OF_DEV_AUXDATA("ti,da850-dsp", 0x11800000, "davinci-rproc.0", NULL), - {} -}; - #ifdef CONFIG_ARCH_DAVINCI_DA850 static void __init da850_init_machine(void) { - /* All existing boards use 100MHz SATA refclkpn */ - static const unsigned long sata_refclkpn = 100 * 1000 * 1000; - - int ret; - - ret = da8xx_register_usb20_phy_clk(false); - if (ret) - pr_warn("%s: registering USB 2.0 PHY clock failed: %d", - __func__, ret); - ret = da8xx_register_usb11_phy_clk(false); - if (ret) - pr_warn("%s: registering USB 1.1 PHY clock failed: %d", - __func__, ret); - - ret = da850_register_sata_refclk(sata_refclkpn); - if (ret) - pr_warn("%s: registering SATA REFCLK failed: %d", - __func__, ret); - - of_platform_default_populate(NULL, da850_auxdata_lookup, NULL); davinci_pm_init(); pdata_quirks_init(); } @@ -96,7 +31,6 @@ static const char *const da850_boards_compat[] __initconst = { DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x") .map_io = da850_init, - .init_time = da850_init_time, .init_machine = da850_init_machine, .dt_compat = da850_boards_compat, .init_late = davinci_init_late, diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 376cdd51ce9d..db4c95ef4d5c 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -35,6 +35,10 @@ #include <media/davinci/vpbe.h> #include <media/davinci/vpbe_osd.h> +#define DAVINCI_PLL1_BASE 0x01c40800 +#define DAVINCI_PLL2_BASE 0x01c40c00 +#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000 + #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000 #define SYSMOD_VDAC_CONFIG 0x2c #define SYSMOD_VIDCLKCTL 0x38 @@ -84,6 +88,7 @@ int davinci_init_wdt(void); /* DM355 function declarations */ void dm355_init(void); void dm355_init_time(void); +void dm355_register_clocks(void); void dm355_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); void dm355_init_asp1(u32 evt_enable); @@ -93,6 +98,7 @@ int dm355_gpio_register(void); /* DM365 function declarations */ void dm365_init(void); void dm365_init_time(void); +void dm365_register_clocks(void); void dm365_init_asp(void); void dm365_init_vc(void); void dm365_init_ks(struct davinci_ks_platform_data *pdata); @@ -106,6 +112,7 @@ int dm365_gpio_register(void); void dm644x_init(void); void dm644x_init_devices(void); void dm644x_init_time(void); +void dm644x_register_clocks(void); void dm644x_init_asp(void); int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); int dm644x_gpio_register(void); @@ -113,6 +120,7 @@ int dm644x_gpio_register(void); /* DM646x function declarations */ void dm646x_init(void); void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate); +void dm646x_register_clocks(void); void dm646x_init_mcasp0(struct snd_platform_data *pdata); void dm646x_init_mcasp1(struct snd_platform_data *pdata); int dm646x_init_edma(struct edma_rsv_info *rsv); diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 78390c64e6ca..1fd3619f6a09 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -10,25 +10,25 @@ * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/dma-contiguous.h> -#include <linux/serial_8250.h> #include <linux/ahci_platform.h> +#include <linux/clk-provider.h> #include <linux/clk.h> -#include <linux/reboot.h> +#include <linux/clkdev.h> +#include <linux/dma-contiguous.h> #include <linux/dmaengine.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/reboot.h> +#include <linux/serial_8250.h> -#include <mach/cputype.h> #include <mach/common.h> -#include <mach/time.h> +#include <mach/cputype.h> #include <mach/da8xx.h> -#include <mach/clock.h> -#include "cpuidle.h" -#include "sram.h" +#include <mach/time.h> -#include "clock.h" #include "asp.h" +#include "cpuidle.h" +#include "sram.h" #define DA8XX_TPCC_BASE 0x01c00000 #define DA8XX_TPTC0_BASE 0x01c08000 @@ -1040,26 +1040,15 @@ int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) } #ifdef CONFIG_ARCH_DAVINCI_DA850 -static struct clk sata_refclk = { - .name = "sata_refclk", - .set_rate = davinci_simple_set_rate, -}; - -static struct clk_lookup sata_refclk_lookup = - CLK("ahci_da850", "refclk", &sata_refclk); - int __init da850_register_sata_refclk(int rate) { - int ret; - - sata_refclk.rate = rate; - ret = clk_register(&sata_refclk); - if (ret) - return ret; + struct clk *clk; - clkdev_add(&sata_refclk_lookup); + clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate); + if (IS_ERR(clk)) + return PTR_ERR(clk); - return 0; + return clk_register_clkdev(clk, "refclk", "ahci_da850"); } static struct resource da850_sata_resources[] = { diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 0edda4093e47..e8dbbb7479ab 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -26,7 +26,6 @@ #include "davinci.h" -#include "clock.h" #define DAVINCI_I2C_BASE 0x01C21000 #define DAVINCI_ATA_BASE 0x01C66000 diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index f29480495c18..9f7d38d12c88 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -8,31 +8,32 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/platform_device.h> + +#include <linux/clk-provider.h> +#include <linux/clk/davinci.h> +#include <linux/clkdev.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> -#include <linux/spi/spi.h> +#include <linux/init.h> #include <linux/platform_data/edma.h> #include <linux/platform_data/gpio-davinci.h> #include <linux/platform_data/spi-davinci.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/spi/spi.h> #include <asm/mach/map.h> +#include <mach/common.h> #include <mach/cputype.h> -#include "psc.h" -#include <mach/mux.h> #include <mach/irqs.h> -#include <mach/time.h> +#include <mach/mux.h> #include <mach/serial.h> -#include <mach/common.h> +#include <mach/time.h> +#include "asp.h" #include "davinci.h" -#include "clock.h" #include "mux.h" -#include "asp.h" #define DM355_UART2_BASE (IO_PHYS + 0x206000) #define DM355_OSD_BASE (IO_PHYS + 0x70200) @@ -43,348 +44,6 @@ */ #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */ -static struct pll_data pll1_data = { - .num = 1, - .phys_base = DAVINCI_PLL1_BASE, - .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, -}; - -static struct pll_data pll2_data = { - .num = 2, - .phys_base = DAVINCI_PLL2_BASE, - .flags = PLL_HAS_PREDIV, -}; - -static struct clk ref_clk = { - .name = "ref_clk", - /* FIXME -- crystal rate is board-specific */ - .rate = DM355_REF_FREQ, -}; - -static struct clk pll1_clk = { - .name = "pll1", - .parent = &ref_clk, - .flags = CLK_PLL, - .pll_data = &pll1_data, -}; - -static struct clk pll1_aux_clk = { - .name = "pll1_aux_clk", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll1_sysclk1 = { - .name = "pll1_sysclk1", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll1_sysclk2 = { - .name = "pll1_sysclk2", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll1_sysclk3 = { - .name = "pll1_sysclk3", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static struct clk pll1_sysclk4 = { - .name = "pll1_sysclk4", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV4, -}; - -static struct clk pll1_sysclkbp = { - .name = "pll1_sysclkbp", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV -}; - -static struct clk vpss_dac_clk = { - .name = "vpss_dac", - .parent = &pll1_sysclk3, - .lpsc = DM355_LPSC_VPSS_DAC, -}; - -static struct clk vpss_master_clk = { - .name = "vpss_master", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_VPSSMSTR, - .flags = CLK_PSC, -}; - -static struct clk vpss_slave_clk = { - .name = "vpss_slave", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_VPSSSLV, -}; - -static struct clk clkout1_clk = { - .name = "clkout1", - .parent = &pll1_aux_clk, - /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */ -}; - -static struct clk clkout2_clk = { - .name = "clkout2", - .parent = &pll1_sysclkbp, -}; - -static struct clk pll2_clk = { - .name = "pll2", - .parent = &ref_clk, - .flags = CLK_PLL, - .pll_data = &pll2_data, -}; - -static struct clk pll2_sysclk1 = { - .name = "pll2_sysclk1", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll2_sysclkbp = { - .name = "pll2_sysclkbp", - .parent = &pll2_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV -}; - -static struct clk clkout3_clk = { - .name = "clkout3", - .parent = &pll2_sysclkbp, - /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */ -}; - -static struct clk arm_clk = { - .name = "arm_clk", - .parent = &pll1_sysclk1, - .lpsc = DAVINCI_LPSC_ARM, - .flags = ALWAYS_ENABLED, -}; - -/* - * NOT LISTED below, and not touched by Linux - * - in SyncReset state by default - * .lpsc = DAVINCI_LPSC_TPCC, - * .lpsc = DAVINCI_LPSC_TPTC0, - * .lpsc = DAVINCI_LPSC_TPTC1, - * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk, - * .lpsc = DAVINCI_LPSC_MEMSTICK, - * - in Enabled state by default - * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS, - * .lpsc = DAVINCI_LPSC_SCR2, // "bus" - * .lpsc = DAVINCI_LPSC_SCR3, // "bus" - * .lpsc = DAVINCI_LPSC_SCR4, // "bus" - * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation" - * .lpsc = DAVINCI_LPSC_CFG27, // "test" - * .lpsc = DAVINCI_LPSC_CFG3, // "test" - * .lpsc = DAVINCI_LPSC_CFG5, // "test" - */ - -static struct clk mjcp_clk = { - .name = "mjcp", - .parent = &pll1_sysclk1, - .lpsc = DAVINCI_LPSC_IMCOP, -}; - -static struct clk uart0_clk = { - .name = "uart0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_UART0, -}; - -static struct clk uart1_clk = { - .name = "uart1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_UART1, -}; - -static struct clk uart2_clk = { - .name = "uart2", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_UART2, -}; - -static struct clk i2c_clk = { - .name = "i2c", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_I2C, -}; - -static struct clk asp0_clk = { - .name = "asp0", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_McBSP, -}; - -static struct clk asp1_clk = { - .name = "asp1", - .parent = &pll1_sysclk2, - .lpsc = DM355_LPSC_McBSP1, -}; - -static struct clk mmcsd0_clk = { - .name = "mmcsd0", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_MMC_SD, -}; - -static struct clk mmcsd1_clk = { - .name = "mmcsd1", - .parent = &pll1_sysclk2, - .lpsc = DM355_LPSC_MMC_SD1, -}; - -static struct clk spi0_clk = { - .name = "spi0", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_SPI, -}; - -static struct clk spi1_clk = { - .name = "spi1", - .parent = &pll1_sysclk2, - .lpsc = DM355_LPSC_SPI1, -}; - -static struct clk spi2_clk = { - .name = "spi2", - .parent = &pll1_sysclk2, - .lpsc = DM355_LPSC_SPI2, -}; - -static struct clk gpio_clk = { - .name = "gpio", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_GPIO, -}; - -static struct clk aemif_clk = { - .name = "aemif", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_AEMIF, -}; - -static struct clk pwm0_clk = { - .name = "pwm0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM0, -}; - -static struct clk pwm1_clk = { - .name = "pwm1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM1, -}; - -static struct clk pwm2_clk = { - .name = "pwm2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM2, -}; - -static struct clk pwm3_clk = { - .name = "pwm3", - .parent = &pll1_aux_clk, - .lpsc = DM355_LPSC_PWM3, -}; - -static struct clk timer0_clk = { - .name = "timer0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER0, -}; - -static struct clk timer1_clk = { - .name = "timer1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER1, -}; - -static struct clk timer2_clk = { - .name = "timer2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why can't this be disabled? */ -}; - -static struct clk timer3_clk = { - .name = "timer3", - .parent = &pll1_aux_clk, - .lpsc = DM355_LPSC_TIMER3, -}; - -static struct clk rto_clk = { - .name = "rto", - .parent = &pll1_aux_clk, - .lpsc = DM355_LPSC_RTO, -}; - -static struct clk usb_clk = { - .name = "usb", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_USB, -}; - -static struct clk_lookup dm355_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), - CLK(NULL, "vpss_dac", &vpss_dac_clk), - CLK("vpss", "master", &vpss_master_clk), - CLK("vpss", "slave", &vpss_slave_clk), - CLK(NULL, "clkout1", &clkout1_clk), - CLK(NULL, "clkout2", &clkout2_clk), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), - CLK(NULL, "clkout3", &clkout3_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "mjcp", &mjcp_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("davinci-mcbsp.0", NULL, &asp0_clk), - CLK("davinci-mcbsp.1", NULL, &asp1_clk), - CLK("dm6441-mmc.0", NULL, &mmcsd0_clk), - CLK("dm6441-mmc.1", NULL, &mmcsd1_clk), - CLK("spi_davinci.0", NULL, &spi0_clk), - CLK("spi_davinci.1", NULL, &spi1_clk), - CLK("spi_davinci.2", NULL, &spi2_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK(NULL, "pwm3", &pwm3_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("davinci-wdt", NULL, &timer2_clk), - CLK(NULL, "timer3", &timer3_clk), - CLK(NULL, "rto", &rto_clk), - CLK(NULL, "usb", &usb_clk), - CLK(NULL, NULL, NULL), -}; - -/*----------------------------------------------------------------------*/ - static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32); static struct resource dm355_spi0_resources[] = { @@ -926,8 +585,6 @@ static struct davinci_id dm355_ids[] = { }, }; -static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; - /* * T0_BOT: Timer 0, bottom: clockevent source for hrtimers * T0_TOP: Timer 0, top : clocksource for generic timekeeping @@ -1012,8 +669,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = { .jtag_id_reg = 0x01c40028, .ids = dm355_ids, .ids_num = ARRAY_SIZE(dm355_ids), - .psc_bases = dm355_psc_bases, - .psc_bases_num = ARRAY_SIZE(dm355_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm355_pins, .pinmux_pins_num = ARRAY_SIZE(dm355_pins), @@ -1046,8 +701,41 @@ void __init dm355_init(void) void __init dm355_init_time(void) { - davinci_clk_init(dm355_clks); - davinci_timer_init(); + void __iomem *pll1, *psc; + struct clk *clk; + + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ); + + pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); + dm355_pll1_init(NULL, pll1, NULL); + + psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); + dm355_psc_init(NULL, psc); + + clk = clk_get(NULL, "timer0"); + + davinci_timer_init(clk); +} + +static struct resource dm355_pll2_resources[] = { + { + .start = DAVINCI_PLL2_BASE, + .end = DAVINCI_PLL2_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm355_pll2_device = { + .name = "dm355-pll2", + .id = -1, + .resource = dm355_pll2_resources, + .num_resources = ARRAY_SIZE(dm355_pll2_resources), +}; + +void __init dm355_register_clocks(void) +{ + /* PLL1 and PSC are registered in dm355_init_time() */ + platform_device_register(&dm355_pll2_device); } int __init dm355_init_video(struct vpfe_config *vpfe_cfg, diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 1e3df9df1e10..abcf2a5ed89b 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -12,32 +12,33 @@ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/platform_device.h> + +#include <linux/clk-provider.h> +#include <linux/clk/davinci.h> +#include <linux/clkdev.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> -#include <linux/spi/spi.h> +#include <linux/init.h> #include <linux/platform_data/edma.h> #include <linux/platform_data/gpio-davinci.h> #include <linux/platform_data/keyscan-davinci.h> #include <linux/platform_data/spi-davinci.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/spi/spi.h> #include <asm/mach/map.h> +#include <mach/common.h> #include <mach/cputype.h> -#include "psc.h" -#include <mach/mux.h> #include <mach/irqs.h> -#include <mach/time.h> +#include <mach/mux.h> #include <mach/serial.h> -#include <mach/common.h> +#include <mach/time.h> +#include "asp.h" #include "davinci.h" -#include "clock.h" #include "mux.h" -#include "asp.h" #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ #define DM365_RTC_BASE 0x01c69000 @@ -54,440 +55,6 @@ #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000 #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000 -static struct pll_data pll1_data = { - .num = 1, - .phys_base = DAVINCI_PLL1_BASE, - .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, -}; - -static struct pll_data pll2_data = { - .num = 2, - .phys_base = DAVINCI_PLL2_BASE, - .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, -}; - -static struct clk ref_clk = { - .name = "ref_clk", - .rate = DM365_REF_FREQ, -}; - -static struct clk pll1_clk = { - .name = "pll1", - .parent = &ref_clk, - .flags = CLK_PLL, - .pll_data = &pll1_data, -}; - -static struct clk pll1_aux_clk = { - .name = "pll1_aux_clk", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll1_sysclkbp = { - .name = "pll1_sysclkbp", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV -}; - -static struct clk clkout0_clk = { - .name = "clkout0", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll1_sysclk1 = { - .name = "pll1_sysclk1", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll1_sysclk2 = { - .name = "pll1_sysclk2", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll1_sysclk3 = { - .name = "pll1_sysclk3", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static struct clk pll1_sysclk4 = { - .name = "pll1_sysclk4", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV4, -}; - -static struct clk pll1_sysclk5 = { - .name = "pll1_sysclk5", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV5, -}; - -static struct clk pll1_sysclk6 = { - .name = "pll1_sysclk6", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV6, -}; - -static struct clk pll1_sysclk7 = { - .name = "pll1_sysclk7", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV7, -}; - -static struct clk pll1_sysclk8 = { - .name = "pll1_sysclk8", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV8, -}; - -static struct clk pll1_sysclk9 = { - .name = "pll1_sysclk9", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV9, -}; - -static struct clk pll2_clk = { - .name = "pll2", - .parent = &ref_clk, - .flags = CLK_PLL, - .pll_data = &pll2_data, -}; - -static struct clk pll2_aux_clk = { - .name = "pll2_aux_clk", - .parent = &pll2_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk clkout1_clk = { - .name = "clkout1", - .parent = &pll2_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll2_sysclk1 = { - .name = "pll2_sysclk1", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll2_sysclk2 = { - .name = "pll2_sysclk2", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll2_sysclk3 = { - .name = "pll2_sysclk3", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static struct clk pll2_sysclk4 = { - .name = "pll2_sysclk4", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV4, -}; - -static struct clk pll2_sysclk5 = { - .name = "pll2_sysclk5", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV5, -}; - -static struct clk pll2_sysclk6 = { - .name = "pll2_sysclk6", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV6, -}; - -static struct clk pll2_sysclk7 = { - .name = "pll2_sysclk7", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV7, -}; - -static struct clk pll2_sysclk8 = { - .name = "pll2_sysclk8", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV8, -}; - -static struct clk pll2_sysclk9 = { - .name = "pll2_sysclk9", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV9, -}; - -static struct clk vpss_dac_clk = { - .name = "vpss_dac", - .parent = &pll1_sysclk3, - .lpsc = DM365_LPSC_DAC_CLK, -}; - -static struct clk vpss_master_clk = { - .name = "vpss_master", - .parent = &pll1_sysclk5, - .lpsc = DM365_LPSC_VPSSMSTR, - .flags = CLK_PSC, -}; - -static struct clk vpss_slave_clk = { - .name = "vpss_slave", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_VPSSSLV, -}; - -static struct clk arm_clk = { - .name = "arm_clk", - .parent = &pll2_sysclk2, - .lpsc = DAVINCI_LPSC_ARM, - .flags = ALWAYS_ENABLED, -}; - -static struct clk uart0_clk = { - .name = "uart0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_UART0, -}; - -static struct clk uart1_clk = { - .name = "uart1", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_UART1, -}; - -static struct clk i2c_clk = { - .name = "i2c", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_I2C, -}; - -static struct clk mmcsd0_clk = { - .name = "mmcsd0", - .parent = &pll1_sysclk8, - .lpsc = DAVINCI_LPSC_MMC_SD, -}; - -static struct clk mmcsd1_clk = { - .name = "mmcsd1", - .parent = &pll1_sysclk4, - .lpsc = DM365_LPSC_MMC_SD1, -}; - -static struct clk spi0_clk = { - .name = "spi0", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_SPI, -}; - -static struct clk spi1_clk = { - .name = "spi1", - .parent = &pll1_sysclk4, - .lpsc = DM365_LPSC_SPI1, -}; - -static struct clk spi2_clk = { - .name = "spi2", - .parent = &pll1_sysclk4, - .lpsc = DM365_LPSC_SPI2, -}; - -static struct clk spi3_clk = { - .name = "spi3", - .parent = &pll1_sysclk4, - .lpsc = DM365_LPSC_SPI3, -}; - -static struct clk spi4_clk = { - .name = "spi4", - .parent = &pll1_aux_clk, - .lpsc = DM365_LPSC_SPI4, -}; - -static struct clk gpio_clk = { - .name = "gpio", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_GPIO, -}; - -static struct clk aemif_clk = { - .name = "aemif", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_AEMIF, -}; - -static struct clk pwm0_clk = { - .name = "pwm0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM0, -}; - -static struct clk pwm1_clk = { - .name = "pwm1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM1, -}; - -static struct clk pwm2_clk = { - .name = "pwm2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM2, -}; - -static struct clk pwm3_clk = { - .name = "pwm3", - .parent = &ref_clk, - .lpsc = DM365_LPSC_PWM3, -}; - -static struct clk timer0_clk = { - .name = "timer0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER0, -}; - -static struct clk timer1_clk = { - .name = "timer1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER1, -}; - -static struct clk timer2_clk = { - .name = "timer2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, -}; - -static struct clk timer3_clk = { - .name = "timer3", - .parent = &pll1_aux_clk, - .lpsc = DM365_LPSC_TIMER3, -}; - -static struct clk usb_clk = { - .name = "usb", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_USB, -}; - -static struct clk emac_clk = { - .name = "emac", - .parent = &pll1_sysclk4, - .lpsc = DM365_LPSC_EMAC, -}; - -static struct clk voicecodec_clk = { - .name = "voice_codec", - .parent = &pll2_sysclk4, - .lpsc = DM365_LPSC_VOICE_CODEC, -}; - -static struct clk asp0_clk = { - .name = "asp0", - .parent = &pll1_sysclk4, - .lpsc = DM365_LPSC_McBSP1, -}; - -static struct clk rto_clk = { - .name = "rto", - .parent = &pll1_sysclk4, - .lpsc = DM365_LPSC_RTO, -}; - -static struct clk mjcp_clk = { - .name = "mjcp", - .parent = &pll1_sysclk3, - .lpsc = DM365_LPSC_MJCP, -}; - -static struct clk_lookup dm365_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), - CLK(NULL, "clkout0", &clkout0_clk), - CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), - CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), - CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), - CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), - CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), - CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_aux", &pll2_aux_clk), - CLK(NULL, "clkout1", &clkout1_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), - CLK(NULL, "pll2_sysclk3", &pll2_sysclk3), - CLK(NULL, "pll2_sysclk4", &pll2_sysclk4), - CLK(NULL, "pll2_sysclk5", &pll2_sysclk5), - CLK(NULL, "pll2_sysclk6", &pll2_sysclk6), - CLK(NULL, "pll2_sysclk7", &pll2_sysclk7), - CLK(NULL, "pll2_sysclk8", &pll2_sysclk8), - CLK(NULL, "pll2_sysclk9", &pll2_sysclk9), - CLK(NULL, "vpss_dac", &vpss_dac_clk), - CLK("vpss", "master", &vpss_master_clk), - CLK("vpss", "slave", &vpss_slave_clk), - CLK(NULL, "arm", &arm_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("da830-mmc.0", NULL, &mmcsd0_clk), - CLK("da830-mmc.1", NULL, &mmcsd1_clk), - CLK("spi_davinci.0", NULL, &spi0_clk), - CLK("spi_davinci.1", NULL, &spi1_clk), - CLK("spi_davinci.2", NULL, &spi2_clk), - CLK("spi_davinci.3", NULL, &spi3_clk), - CLK("spi_davinci.4", NULL, &spi4_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK(NULL, "pwm3", &pwm3_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("davinci-wdt", NULL, &timer2_clk), - CLK(NULL, "timer3", &timer3_clk), - CLK(NULL, "usb", &usb_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), - CLK("davinci_voicecodec", NULL, &voicecodec_clk), - CLK("davinci-mcbsp", NULL, &asp0_clk), - CLK(NULL, "rto", &rto_clk), - CLK(NULL, "mjcp", &mjcp_clk), - CLK(NULL, NULL, NULL), -}; - -/*----------------------------------------------------------------------*/ - #define INTMUX 0x18 #define EVTMUX 0x1c @@ -1054,8 +621,6 @@ static struct davinci_id dm365_ids[] = { }, }; -static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; - static struct davinci_timer_info dm365_timer_info = { .timers = davinci_timer_instance, .clockevent_id = T0_BOT, @@ -1116,8 +681,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = { .jtag_id_reg = 0x01c40028, .ids = dm365_ids, .ids_num = ARRAY_SIZE(dm365_ids), - .psc_bases = dm365_psc_bases, - .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm365_pins, .pinmux_pins_num = ARRAY_SIZE(dm365_pins), @@ -1171,8 +734,28 @@ void __init dm365_init(void) void __init dm365_init_time(void) { - davinci_clk_init(dm365_clks); - davinci_timer_init(); + void __iomem *pll1, *pll2, *psc; + struct clk *clk; + + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ); + + pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); + dm365_pll1_init(NULL, pll1, NULL); + + pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K); + dm365_pll2_init(NULL, pll2, NULL); + + psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); + dm365_psc_init(NULL, psc); + + clk = clk_get(NULL, "timer0"); + + davinci_timer_init(clk); +} + +void __init dm365_register_clocks(void) +{ + /* all clocks are currently registered in dm365_init_time() */ } static struct resource dm365_vpss_resources[] = { diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index a2e8586c8a6d..0720da7809a6 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -8,28 +8,29 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> + +#include <linux/clk-provider.h> +#include <linux/clk/davinci.h> +#include <linux/clkdev.h> #include <linux/dmaengine.h> -#include <linux/platform_device.h> +#include <linux/init.h> #include <linux/platform_data/edma.h> #include <linux/platform_data/gpio-davinci.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> #include <asm/mach/map.h> +#include <mach/common.h> #include <mach/cputype.h> #include <mach/irqs.h> -#include "psc.h" #include <mach/mux.h> -#include <mach/time.h> #include <mach/serial.h> -#include <mach/common.h> +#include <mach/time.h> +#include "asp.h" #include "davinci.h" -#include "clock.h" #include "mux.h" -#include "asp.h" /* * Device specific clocks @@ -43,290 +44,6 @@ #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000 -static struct pll_data pll1_data = { - .num = 1, - .phys_base = DAVINCI_PLL1_BASE, -}; - -static struct pll_data pll2_data = { - .num = 2, - .phys_base = DAVINCI_PLL2_BASE, -}; - -static struct clk ref_clk = { - .name = "ref_clk", - .rate = DM644X_REF_FREQ, -}; - -static struct clk pll1_clk = { - .name = "pll1", - .parent = &ref_clk, - .pll_data = &pll1_data, - .flags = CLK_PLL, -}; - -static struct clk pll1_sysclk1 = { - .name = "pll1_sysclk1", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll1_sysclk2 = { - .name = "pll1_sysclk2", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll1_sysclk3 = { - .name = "pll1_sysclk3", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static struct clk pll1_sysclk5 = { - .name = "pll1_sysclk5", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV5, -}; - -static struct clk pll1_aux_clk = { - .name = "pll1_aux_clk", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll1_sysclkbp = { - .name = "pll1_sysclkbp", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV -}; - -static struct clk pll2_clk = { - .name = "pll2", - .parent = &ref_clk, - .pll_data = &pll2_data, - .flags = CLK_PLL, -}; - -static struct clk pll2_sysclk1 = { - .name = "pll2_sysclk1", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll2_sysclk2 = { - .name = "pll2_sysclk2", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll2_sysclkbp = { - .name = "pll2_sysclkbp", - .parent = &pll2_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV -}; - -static struct clk dsp_clk = { - .name = "dsp", - .parent = &pll1_sysclk1, - .lpsc = DAVINCI_LPSC_GEM, - .domain = DAVINCI_GPSC_DSPDOMAIN, - .usecount = 1, /* REVISIT how to disable? */ -}; - -static struct clk arm_clk = { - .name = "arm", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_ARM, - .flags = ALWAYS_ENABLED, -}; - -static struct clk vicp_clk = { - .name = "vicp", - .parent = &pll1_sysclk2, - .lpsc = DAVINCI_LPSC_IMCOP, - .domain = DAVINCI_GPSC_DSPDOMAIN, - .usecount = 1, /* REVISIT how to disable? */ -}; - -static struct clk vpss_master_clk = { - .name = "vpss_master", - .parent = &pll1_sysclk3, - .lpsc = DAVINCI_LPSC_VPSSMSTR, - .flags = CLK_PSC, -}; - -static struct clk vpss_slave_clk = { - .name = "vpss_slave", - .parent = &pll1_sysclk3, - .lpsc = DAVINCI_LPSC_VPSSSLV, -}; - -static struct clk uart0_clk = { - .name = "uart0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_UART0, -}; - -static struct clk uart1_clk = { - .name = "uart1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_UART1, -}; - -static struct clk uart2_clk = { - .name = "uart2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_UART2, -}; - -static struct clk emac_clk = { - .name = "emac", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, -}; - -static struct clk i2c_clk = { - .name = "i2c", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_I2C, -}; - -static struct clk ide_clk = { - .name = "ide", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_ATA, -}; - -static struct clk asp_clk = { - .name = "asp0", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_McBSP, -}; - -static struct clk mmcsd_clk = { - .name = "mmcsd", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_MMC_SD, -}; - -static struct clk spi_clk = { - .name = "spi", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_SPI, -}; - -static struct clk gpio_clk = { - .name = "gpio", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_GPIO, -}; - -static struct clk usb_clk = { - .name = "usb", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_USB, -}; - -static struct clk vlynq_clk = { - .name = "vlynq", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_VLYNQ, -}; - -static struct clk aemif_clk = { - .name = "aemif", - .parent = &pll1_sysclk5, - .lpsc = DAVINCI_LPSC_AEMIF, -}; - -static struct clk pwm0_clk = { - .name = "pwm0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM0, -}; - -static struct clk pwm1_clk = { - .name = "pwm1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM1, -}; - -static struct clk pwm2_clk = { - .name = "pwm2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_PWM2, -}; - -static struct clk timer0_clk = { - .name = "timer0", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER0, -}; - -static struct clk timer1_clk = { - .name = "timer1", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER1, -}; - -static struct clk timer2_clk = { - .name = "timer2", - .parent = &pll1_aux_clk, - .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why can't this be disabled? */ -}; - -static struct clk_lookup dm644x_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), - CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), - CLK(NULL, "dsp", &dsp_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "vicp", &vicp_clk), - CLK("vpss", "master", &vpss_master_clk), - CLK("vpss", "slave", &vpss_slave_clk), - CLK(NULL, "arm", &arm_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("palm_bk3710", NULL, &ide_clk), - CLK("davinci-mcbsp", NULL, &asp_clk), - CLK("dm6441-mmc.0", NULL, &mmcsd_clk), - CLK(NULL, "spi", &spi_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK(NULL, "usb", &usb_clk), - CLK(NULL, "vlynq", &vlynq_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("davinci-wdt", NULL, &timer2_clk), - CLK(NULL, NULL, NULL), -}; - static struct emac_platform_data dm644x_emac_pdata = { .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, @@ -819,8 +536,6 @@ static struct davinci_id dm644x_ids[] = { }, }; -static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; - /* * T0_BOT: Timer 0, bottom: clockevent source for hrtimers * T0_TOP: Timer 0, top : clocksource for generic timekeeping @@ -905,8 +620,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = { .jtag_id_reg = 0x01c40028, .ids = dm644x_ids, .ids_num = ARRAY_SIZE(dm644x_ids), - .psc_bases = dm644x_psc_bases, - .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm644x_pins, .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), @@ -934,8 +647,41 @@ void __init dm644x_init(void) void __init dm644x_init_time(void) { - davinci_clk_init(dm644x_clks); - davinci_timer_init(); + void __iomem *pll1, *psc; + struct clk *clk; + + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ); + + pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); + dm644x_pll1_init(NULL, pll1, NULL); + + psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); + dm644x_psc_init(NULL, psc); + + clk = clk_get(NULL, "timer0"); + + davinci_timer_init(clk); +} + +static struct resource dm644x_pll2_resources[] = { + { + .start = DAVINCI_PLL2_BASE, + .end = DAVINCI_PLL2_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_pll2_device = { + .name = "dm644x-pll2", + .id = -1, + .resource = dm644x_pll2_resources, + .num_resources = ARRAY_SIZE(dm644x_pll2_resources), +}; + +void __init dm644x_register_clocks(void) +{ + /* PLL1 and PSC are registered in dm644x_init_time() */ + platform_device_register(&dm644x_pll2_device); } int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index c32ca27ab343..6bd2ed069d0d 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -8,29 +8,30 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ + +#include <linux/clk-provider.h> +#include <linux/clk/davinci.h> +#include <linux/clkdev.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/init.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/platform_device.h> #include <linux/platform_data/edma.h> #include <linux/platform_data/gpio-davinci.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> #include <asm/mach/map.h> +#include <mach/common.h> #include <mach/cputype.h> #include <mach/irqs.h> -#include "psc.h" #include <mach/mux.h> -#include <mach/time.h> #include <mach/serial.h> -#include <mach/common.h> +#include <mach/time.h> +#include "asp.h" #include "davinci.h" -#include "clock.h" #include "mux.h" -#include "asp.h" #define DAVINCI_VPIF_BASE (0x01C12000) @@ -46,317 +47,6 @@ #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000 -static struct pll_data pll1_data = { - .num = 1, - .phys_base = DAVINCI_PLL1_BASE, -}; - -static struct pll_data pll2_data = { - .num = 2, - .phys_base = DAVINCI_PLL2_BASE, -}; - -static struct clk ref_clk = { - .name = "ref_clk", - /* rate is initialized in dm646x_init_time() */ -}; - -static struct clk aux_clkin = { - .name = "aux_clkin", - /* rate is initialized in dm646x_init_time() */ -}; - -static struct clk pll1_clk = { - .name = "pll1", - .parent = &ref_clk, - .pll_data = &pll1_data, - .flags = CLK_PLL, -}; - -static struct clk pll1_sysclk1 = { - .name = "pll1_sysclk1", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk pll1_sysclk2 = { - .name = "pll1_sysclk2", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV2, -}; - -static struct clk pll1_sysclk3 = { - .name = "pll1_sysclk3", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV3, -}; - -static struct clk pll1_sysclk4 = { - .name = "pll1_sysclk4", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV4, -}; - -static struct clk pll1_sysclk5 = { - .name = "pll1_sysclk5", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV5, -}; - -static struct clk pll1_sysclk6 = { - .name = "pll1_sysclk6", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV6, -}; - -static struct clk pll1_sysclk8 = { - .name = "pll1_sysclk8", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV8, -}; - -static struct clk pll1_sysclk9 = { - .name = "pll1_sysclk9", - .parent = &pll1_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV9, -}; - -static struct clk pll1_sysclkbp = { - .name = "pll1_sysclkbp", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, - .div_reg = BPDIV, -}; - -static struct clk pll1_aux_clk = { - .name = "pll1_aux_clk", - .parent = &pll1_clk, - .flags = CLK_PLL | PRE_PLL, -}; - -static struct clk pll2_clk = { - .name = "pll2_clk", - .parent = &ref_clk, - .pll_data = &pll2_data, - .flags = CLK_PLL, -}; - -static struct clk pll2_sysclk1 = { - .name = "pll2_sysclk1", - .parent = &pll2_clk, - .flags = CLK_PLL, - .div_reg = PLLDIV1, -}; - -static struct clk dsp_clk = { - .name = "dsp", - .parent = &pll1_sysclk1, - .lpsc = DM646X_LPSC_C64X_CPU, - .usecount = 1, /* REVISIT how to disable? */ -}; - -static struct clk arm_clk = { - .name = "arm", - .parent = &pll1_sysclk2, - .lpsc = DM646X_LPSC_ARM, - .flags = ALWAYS_ENABLED, -}; - -static struct clk edma_cc_clk = { - .name = "edma_cc", - .parent = &pll1_sysclk2, - .lpsc = DM646X_LPSC_TPCC, - .flags = ALWAYS_ENABLED, -}; - -static struct clk edma_tc0_clk = { - .name = "edma_tc0", - .parent = &pll1_sysclk2, - .lpsc = DM646X_LPSC_TPTC0, - .flags = ALWAYS_ENABLED, -}; - -static struct clk edma_tc1_clk = { - .name = "edma_tc1", - .parent = &pll1_sysclk2, - .lpsc = DM646X_LPSC_TPTC1, - .flags = ALWAYS_ENABLED, -}; - -static struct clk edma_tc2_clk = { - .name = "edma_tc2", - .parent = &pll1_sysclk2, - .lpsc = DM646X_LPSC_TPTC2, - .flags = ALWAYS_ENABLED, -}; - -static struct clk edma_tc3_clk = { - .name = "edma_tc3", - .parent = &pll1_sysclk2, - .lpsc = DM646X_LPSC_TPTC3, - .flags = ALWAYS_ENABLED, -}; - -static struct clk uart0_clk = { - .name = "uart0", - .parent = &aux_clkin, - .lpsc = DM646X_LPSC_UART0, -}; - -static struct clk uart1_clk = { - .name = "uart1", - .parent = &aux_clkin, - .lpsc = DM646X_LPSC_UART1, -}; - -static struct clk uart2_clk = { - .name = "uart2", - .parent = &aux_clkin, - .lpsc = DM646X_LPSC_UART2, -}; - -static struct clk i2c_clk = { - .name = "I2CCLK", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_I2C, -}; - -static struct clk gpio_clk = { - .name = "gpio", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_GPIO, -}; - -static struct clk mcasp0_clk = { - .name = "mcasp0", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_McASP0, -}; - -static struct clk mcasp1_clk = { - .name = "mcasp1", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_McASP1, -}; - -static struct clk aemif_clk = { - .name = "aemif", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_AEMIF, - .flags = ALWAYS_ENABLED, -}; - -static struct clk emac_clk = { - .name = "emac", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_EMAC, -}; - -static struct clk pwm0_clk = { - .name = "pwm0", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_PWM0, - .usecount = 1, /* REVIST: disabling hangs system */ -}; - -static struct clk pwm1_clk = { - .name = "pwm1", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_PWM1, - .usecount = 1, /* REVIST: disabling hangs system */ -}; - -static struct clk timer0_clk = { - .name = "timer0", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_TIMER0, -}; - -static struct clk timer1_clk = { - .name = "timer1", - .parent = &pll1_sysclk3, - .lpsc = DM646X_LPSC_TIMER1, -}; - -static struct clk timer2_clk = { - .name = "timer2", - .parent = &pll1_sysclk3, - .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ -}; - - -static struct clk ide_clk = { - .name = "ide", - .parent = &pll1_sysclk4, - .lpsc = DAVINCI_LPSC_ATA, -}; - -static struct clk vpif0_clk = { - .name = "vpif0", - .parent = &ref_clk, - .lpsc = DM646X_LPSC_VPSSMSTR, - .flags = ALWAYS_ENABLED, -}; - -static struct clk vpif1_clk = { - .name = "vpif1", - .parent = &ref_clk, - .lpsc = DM646X_LPSC_VPSSSLV, - .flags = ALWAYS_ENABLED, -}; - -static struct clk_lookup dm646x_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "aux", &aux_clkin), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_sysclk", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk", &pll1_sysclk4), - CLK(NULL, "pll1_sysclk", &pll1_sysclk5), - CLK(NULL, "pll1_sysclk", &pll1_sysclk6), - CLK(NULL, "pll1_sysclk", &pll1_sysclk8), - CLK(NULL, "pll1_sysclk", &pll1_sysclk9), - CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "dsp", &dsp_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "edma_cc", &edma_cc_clk), - CLK(NULL, "edma_tc0", &edma_tc0_clk), - CLK(NULL, "edma_tc1", &edma_tc1_clk), - CLK(NULL, "edma_tc2", &edma_tc2_clk), - CLK(NULL, "edma_tc3", &edma_tc3_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK("davinci-mcasp.0", NULL, &mcasp0_clk), - CLK("davinci-mcasp.1", NULL, &mcasp1_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("davinci-wdt", NULL, &timer2_clk), - CLK("palm_bk3710", NULL, &ide_clk), - CLK(NULL, "vpif0", &vpif0_clk), - CLK(NULL, "vpif1", &vpif1_clk), - CLK(NULL, NULL, NULL), -}; - static struct emac_platform_data dm646x_emac_pdata = { .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, @@ -796,8 +486,6 @@ static struct davinci_id dm646x_ids[] = { }, }; -static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; - /* * T0_BOT: Timer 0, bottom: clockevent source for hrtimers * T0_TOP: Timer 0, top : clocksource for generic timekeeping @@ -882,8 +570,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = { .jtag_id_reg = 0x01c40028, .ids = dm646x_ids, .ids_num = ARRAY_SIZE(dm646x_ids), - .psc_bases = dm646x_psc_bases, - .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, .pinmux_pins = dm646x_pins, .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), @@ -954,10 +640,42 @@ void __init dm646x_init(void) void __init dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate) { - ref_clk.rate = ref_clk_rate; - aux_clkin.rate = aux_clkin_rate; - davinci_clk_init(dm646x_clks); - davinci_timer_init(); + void __iomem *pll1, *psc; + struct clk *clk; + + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); + clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); + + pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); + dm646x_pll1_init(NULL, pll1, NULL); + + psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K); + dm646x_psc_init(NULL, psc); + + clk = clk_get(NULL, "timer0"); + + davinci_timer_init(clk); +} + +static struct resource dm646x_pll2_resources[] = { + { + .start = DAVINCI_PLL2_BASE, + .end = DAVINCI_PLL2_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm646x_pll2_device = { + .name = "dm646x-pll2", + .id = -1, + .resource = dm646x_pll2_resources, + .num_resources = ARRAY_SIZE(dm646x_pll2_resources), +}; + +void __init dm646x_register_clocks(void) +{ + /* PLL1 and PSC are registered in dm646x_init_time() */ + platform_device_register(&dm646x_pll2_device); } static int __init dm646x_init_devices(void) diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h index 3e8af6a0b64c..42ed4f2f5ce4 100644 --- a/arch/arm/mach-davinci/include/mach/clock.h +++ b/arch/arm/mach-davinci/include/mach/clock.h @@ -15,9 +15,6 @@ struct clk; -extern int clk_register(struct clk *clk); -extern void clk_unregister(struct clk *clk); - int davinci_clk_reset_assert(struct clk *c); int davinci_clk_reset_deassert(struct clk *c); diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index f0d5e858f158..b577e13a9c23 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -12,11 +12,12 @@ #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H #define __ARCH_ARM_MACH_DAVINCI_COMMON_H +#include <linux/clk.h> #include <linux/compiler.h> #include <linux/types.h> #include <linux/reboot.h> -extern void davinci_timer_init(void); +void davinci_timer_init(struct clk *clk); extern void davinci_irq_init(void); extern void __iomem *davinci_intc_base; @@ -53,8 +54,6 @@ struct davinci_soc_info { u32 jtag_id_reg; struct davinci_id *ids; unsigned long ids_num; - u32 *psc_bases; - unsigned long psc_bases_num; u32 pinmux_base; const struct mux_config *pinmux_pins; unsigned long pinmux_pins_num; @@ -82,12 +81,6 @@ extern void davinci_common_init(const struct davinci_soc_info *soc_info); extern void davinci_init_ide(void); void davinci_init_late(void); -#ifdef CONFIG_DAVINCI_RESET_CLOCKS -int davinci_clk_disable_unused(void); -#else -static inline int davinci_clk_disable_unused(void) { return 0; } -#endif - #ifdef CONFIG_CPU_FREQ int davinci_cpufreq_init(void); #else diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 9fd6d0125762..ab4a57f433f4 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -89,9 +89,11 @@ extern unsigned int da850_max_speed; void da830_init(void); void da830_init_time(void); +void da830_register_clocks(void); void da850_init(void); void da850_init_time(void); +void da850_register_clocks(void); int da830_register_edma(struct edma_rsv_info *rsv); int da850_register_edma(struct edma_rsv_info *rsv[2]); @@ -101,9 +103,7 @@ int da8xx_register_watchdog(void); int da8xx_register_usb_phy(void); int da8xx_register_usb20(unsigned mA, unsigned potpgt); int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); -int da8xx_register_usb_refclkin(int rate); -int da8xx_register_usb20_phy_clk(bool use_usb_refclkin); -int da8xx_register_usb11_phy_clk(bool use_usb_refclkin); +int da8xx_register_usb_phy_clocks(void); int da850_register_sata_refclk(int rate); int da8xx_register_emac(void); int da8xx_register_uio_pruss(void); diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c index 78eac2c0c146..e251fd593bfd 100644 --- a/arch/arm/mach-davinci/pm_domain.c +++ b/arch/arm/mach-davinci/pm_domain.c @@ -13,6 +13,7 @@ #include <linux/pm_runtime.h> #include <linux/pm_clock.h> #include <linux/platform_device.h> +#include <linux/of.h> static struct dev_pm_domain davinci_pm_domain = { .ops = { @@ -28,6 +29,10 @@ static struct pm_clk_notifier_block platform_bus_notifier = { static int __init davinci_pm_runtime_init(void) { + if (of_have_populated_dt()) + return 0; + + /* Use pm_clk as fallback if we're not using genpd. */ pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); return 0; diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c deleted file mode 100644 index e5dc6bfde5f3..000000000000 --- a/arch/arm/mach-davinci/psc.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * TI DaVinci Power and Sleep Controller (PSC) - * - * Copyright (C) 2006 Texas Instruments. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <mach/cputype.h> -#include "psc.h" - -#include "clock.h" - -/* Return nonzero iff the domain's clock is active */ -int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) -{ - void __iomem *psc_base; - u32 mdstat; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { - pr_warn("PSC: Bad psc data: 0x%x[%d]\n", - (int)soc_info->psc_bases, ctlr); - return 0; - } - - psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); - mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); - iounmap(psc_base); - - /* if clocked, state can be "Enable" or "SyncReset" */ - return mdstat & BIT(12); -} - -/* Control "reset" line associated with PSC domain */ -void davinci_psc_reset(unsigned int ctlr, unsigned int id, bool reset) -{ - u32 mdctl; - void __iomem *psc_base; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { - pr_warn("PSC: Bad psc data: 0x%x[%d]\n", - (int)soc_info->psc_bases, ctlr); - return; - } - - psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); - - mdctl = readl(psc_base + MDCTL + 4 * id); - if (reset) - mdctl &= ~MDCTL_LRST; - else - mdctl |= MDCTL_LRST; - writel(mdctl, psc_base + MDCTL + 4 * id); - - iounmap(psc_base); -} - -/* Enable or disable a PSC domain */ -void davinci_psc_config(unsigned int domain, unsigned int ctlr, - unsigned int id, bool enable, u32 flags) -{ - u32 epcpr, ptcmd, ptstat, pdstat, pdctl, mdstat, mdctl; - void __iomem *psc_base; - struct davinci_soc_info *soc_info = &davinci_soc_info; - u32 next_state = PSC_STATE_ENABLE; - - if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { - pr_warn("PSC: Bad psc data: 0x%x[%d]\n", - (int)soc_info->psc_bases, ctlr); - return; - } - - psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); - - if (!enable) { - if (flags & PSC_SWRSTDISABLE) - next_state = PSC_STATE_SWRSTDISABLE; - else - next_state = PSC_STATE_DISABLE; - } - - mdctl = __raw_readl(psc_base + MDCTL + 4 * id); - mdctl &= ~MDSTAT_STATE_MASK; - mdctl |= next_state; - if (flags & PSC_FORCE) - mdctl |= MDCTL_FORCE; - __raw_writel(mdctl, psc_base + MDCTL + 4 * id); - - pdstat = __raw_readl(psc_base + PDSTAT + 4 * domain); - if ((pdstat & PDSTAT_STATE_MASK) == 0) { - pdctl = __raw_readl(psc_base + PDCTL + 4 * domain); - pdctl |= PDCTL_NEXT; - __raw_writel(pdctl, psc_base + PDCTL + 4 * domain); - - ptcmd = 1 << domain; - __raw_writel(ptcmd, psc_base + PTCMD); - - do { - epcpr = __raw_readl(psc_base + EPCPR); - } while ((((epcpr >> domain) & 1) == 0)); - - pdctl = __raw_readl(psc_base + PDCTL + 4 * domain); - pdctl |= PDCTL_EPCGOOD; - __raw_writel(pdctl, psc_base + PDCTL + 4 * domain); - } else { - ptcmd = 1 << domain; - __raw_writel(ptcmd, psc_base + PTCMD); - } - - do { - ptstat = __raw_readl(psc_base + PTSTAT); - } while (!(((ptstat >> domain) & 1) == 0)); - - do { - mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); - } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); - - iounmap(psc_base); -} diff --git a/arch/arm/mach-davinci/psc.h b/arch/arm/mach-davinci/psc.h index 8af9f09fc10c..68cd9d3fc82b 100644 --- a/arch/arm/mach-davinci/psc.h +++ b/arch/arm/mach-davinci/psc.h @@ -27,8 +27,6 @@ #ifndef __ASM_ARCH_PSC_H #define __ASM_ARCH_PSC_H -#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 - /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_DSPDOMAIN 1 @@ -206,14 +204,4 @@ #define PDCTL_NEXT BIT(0) #define PDCTL_EPCGOOD BIT(8) -#ifndef __ASSEMBLER__ - -extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); -extern void davinci_psc_reset(unsigned int ctlr, unsigned int id, - bool reset); -extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, - unsigned int id, bool enable, u32 flags); - -#endif - #endif /* __ASM_ARCH_PSC_H */ diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 1bb991ad9c1e..5a6de5368ab0 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -17,6 +17,7 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/err.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/sched_clock.h> @@ -27,8 +28,6 @@ #include <mach/hardware.h> #include <mach/time.h> -#include "clock.h" - static struct clock_event_device clockevent_davinci; static unsigned int davinci_clock_tick_rate; @@ -334,10 +333,8 @@ static struct clock_event_device clockevent_davinci = { .set_state_oneshot = davinci_set_oneshot, }; - -void __init davinci_timer_init(void) +void __init davinci_timer_init(struct clk *timer_clk) { - struct clk *timer_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; unsigned int clockevent_id; unsigned int clocksource_id; @@ -373,7 +370,6 @@ void __init davinci_timer_init(void) } } - timer_clk = clk_get(NULL, "timer0"); BUG_ON(IS_ERR(timer_clk)); clk_prepare_enable(timer_clk); @@ -402,3 +398,17 @@ void __init davinci_timer_init(void) for (i=0; i< ARRAY_SIZE(timers); i++) timer32_config(&timers[i]); } + +static int __init of_davinci_timer_init(struct device_node *np) +{ + struct clk *clk; + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + davinci_timer_init(clk); + + return 0; +} +TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_init); diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c index 50445f0e98de..c17ce66a3d95 100644 --- a/arch/arm/mach-davinci/usb-da8xx.c +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -2,29 +2,30 @@ /* * DA8xx USB */ -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/init.h> #include <linux/mfd/da8xx-cfgchip.h> +#include <linux/mfd/syscon.h> #include <linux/phy/phy.h> +#include <linux/platform_data/clk-da8xx-cfgchip.h> #include <linux/platform_data/phy-da8xx-usb.h> #include <linux/platform_data/usb-davinci.h> #include <linux/platform_device.h> #include <linux/usb/musb.h> -#include <mach/clock.h> #include <mach/common.h> #include <mach/cputype.h> #include <mach/da8xx.h> #include <mach/irqs.h> -#include "clock.h" - #define DA8XX_USB0_BASE 0x01e00000 #define DA8XX_USB1_BASE 0x01e25000 +#ifndef CONFIG_COMMON_CLK static struct clk *usb20_clk; +#endif static struct da8xx_usb_phy_platform_data da8xx_usb_phy_pdata; @@ -81,11 +82,6 @@ static struct platform_device da8xx_usb20_dev = { .name = "musb-da8xx", .id = -1, .dev = { - /* - * Setting init_name so that clock lookup will work in - * usb20_phy_clk_enable() even if this device is not registered. - */ - .init_name = "musb-da8xx", .platform_data = &usb_data, .dma_mask = &usb_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), @@ -134,229 +130,17 @@ int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata) return platform_device_register(&da8xx_usb11_device); } -static struct clk usb_refclkin = { - .name = "usb_refclkin", - .set_rate = davinci_simple_set_rate, -}; - -static struct clk_lookup usb_refclkin_lookup = - CLK(NULL, "usb_refclkin", &usb_refclkin); - -/** - * da8xx_register_usb_refclkin - register USB_REFCLKIN clock - * - * @rate: The clock rate in Hz - * - * This clock is only needed if the board provides an external USB_REFCLKIN - * signal, in which case it will be used as the parent of usb20_phy_clk and/or - * usb11_phy_clk. - */ -int __init da8xx_register_usb_refclkin(int rate) -{ - int ret; - - usb_refclkin.rate = rate; - ret = clk_register(&usb_refclkin); - if (ret) - return ret; - - clkdev_add(&usb_refclkin_lookup); - - return 0; -} - -static void usb20_phy_clk_enable(struct clk *clk) -{ - u32 val; - u32 timeout = 500000; /* 500 msec */ - - val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - - /* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */ - davinci_clk_enable(usb20_clk); - - /* - * Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1 - * host may use the PLL clock without USB 2.0 OTG being used. - */ - val &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN); - val |= CFGCHIP2_PHY_PLLON; - - writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - - while (--timeout) { - val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - if (val & CFGCHIP2_PHYCLKGD) - goto done; - udelay(1); - } - - pr_err("Timeout waiting for USB 2.0 PHY clock good\n"); -done: - davinci_clk_disable(usb20_clk); -} - -static void usb20_phy_clk_disable(struct clk *clk) -{ - u32 val; - - val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - val |= CFGCHIP2_PHYPWRDN; - writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); -} - -static int usb20_phy_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 val; - - val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - - /* Set the mux depending on the parent clock. */ - if (parent == &usb_refclkin) { - val &= ~CFGCHIP2_USB2PHYCLKMUX; - } else if (strcmp(parent->name, "pll0_aux_clk") == 0) { - val |= CFGCHIP2_USB2PHYCLKMUX; - } else { - pr_err("Bad parent on USB 2.0 PHY clock\n"); - return -EINVAL; - } - - /* reference frequency also comes from parent clock */ - val &= ~CFGCHIP2_REFFREQ_MASK; - switch (clk_get_rate(parent)) { - case 12000000: - val |= CFGCHIP2_REFFREQ_12MHZ; - break; - case 13000000: - val |= CFGCHIP2_REFFREQ_13MHZ; - break; - case 19200000: - val |= CFGCHIP2_REFFREQ_19_2MHZ; - break; - case 20000000: - val |= CFGCHIP2_REFFREQ_20MHZ; - break; - case 24000000: - val |= CFGCHIP2_REFFREQ_24MHZ; - break; - case 26000000: - val |= CFGCHIP2_REFFREQ_26MHZ; - break; - case 38400000: - val |= CFGCHIP2_REFFREQ_38_4MHZ; - break; - case 40000000: - val |= CFGCHIP2_REFFREQ_40MHZ; - break; - case 48000000: - val |= CFGCHIP2_REFFREQ_48MHZ; - break; - default: - pr_err("Bad parent clock rate on USB 2.0 PHY clock\n"); - return -EINVAL; - } - - writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - - return 0; -} - -static struct clk usb20_phy_clk = { - .name = "usb0_clk48", - .clk_enable = usb20_phy_clk_enable, - .clk_disable = usb20_phy_clk_disable, - .set_parent = usb20_phy_clk_set_parent, -}; - -static struct clk_lookup usb20_phy_clk_lookup = - CLK("da8xx-usb-phy", "usb0_clk48", &usb20_phy_clk); - -/** - * da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock - * - * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true - * or "pll0_aux" if false. - */ -int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin) -{ - struct clk *parent; - int ret; - - usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20"); - ret = PTR_ERR_OR_ZERO(usb20_clk); - if (ret) - return ret; - - parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux"); - ret = PTR_ERR_OR_ZERO(parent); - if (ret) { - clk_put(usb20_clk); - return ret; - } - - usb20_phy_clk.parent = parent; - ret = clk_register(&usb20_phy_clk); - if (!ret) - clkdev_add(&usb20_phy_clk_lookup); - - clk_put(parent); - - return ret; -} - -static int usb11_phy_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 val; - - val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - - /* Set the USB 1.1 PHY clock mux based on the parent clock. */ - if (parent == &usb20_phy_clk) { - val &= ~CFGCHIP2_USB1PHYCLKMUX; - } else if (parent == &usb_refclkin) { - val |= CFGCHIP2_USB1PHYCLKMUX; - } else { - pr_err("Bad parent on USB 1.1 PHY clock\n"); - return -EINVAL; - } - - writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); - - return 0; -} - -static struct clk usb11_phy_clk = { - .name = "usb1_clk48", - .set_parent = usb11_phy_clk_set_parent, +static struct platform_device da8xx_usb_phy_clks_device = { + .name = "da830-usb-phy-clks", + .id = -1, }; -static struct clk_lookup usb11_phy_clk_lookup = - CLK("da8xx-usb-phy", "usb1_clk48", &usb11_phy_clk); - -/** - * da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock - * - * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true - * or "usb0_clk48" if false. - */ -int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin) +int __init da8xx_register_usb_phy_clocks(void) { - struct clk *parent; - int ret = 0; - - if (use_usb_refclkin) - parent = clk_get(NULL, "usb_refclkin"); - else - parent = clk_get(&da8xx_usb_phy.dev, "usb0_clk48"); - if (IS_ERR(parent)) - return PTR_ERR(parent); - - usb11_phy_clk.parent = parent; - ret = clk_register(&usb11_phy_clk); - if (!ret) - clkdev_add(&usb11_phy_clk_lookup); + struct da8xx_cfgchip_clk_platform_data pdata; - clk_put(parent); + pdata.cfgchip = da8xx_get_cfgchip(); + da8xx_usb_phy_clks_device.dev.platform_data = &pdata; - return ret; + return platform_device_register(&da8xx_usb_phy_clks_device); } diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index f4b6c93a7fd0..865dcc4c3181 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -190,8 +190,6 @@ static void __init exynos_dt_fixup(void) } DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") - /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ .l2c_aux_val = 0x3c400001, .l2c_aux_mask = 0xc20fffff, .smp = smp_ops(exynos_smp_ops), diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index f3384e3a675d..7ead3acd6fa4 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -203,6 +203,7 @@ static int __init exynos_pmu_irq_init(struct device_node *node, NULL); if (!domain) { iounmap(pmu_base_addr); + pmu_base_addr = NULL; return -ENOMEM; } diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c index a129aae72602..909bb2493781 100644 --- a/arch/arm/mach-hisi/hotplug.c +++ b/arch/arm/mach-hisi/hotplug.c @@ -148,13 +148,20 @@ static int hi3xxx_hotplug_init(void) struct device_node *node; node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); - if (node) { - ctrl_base = of_iomap(node, 0); - id = HI3620_CTRL; - return 0; + if (!node) { + id = ERROR_CTRL; + return -ENOENT; } - id = ERROR_CTRL; - return -ENOENT; + + ctrl_base = of_iomap(node, 0); + of_node_put(node); + if (!ctrl_base) { + id = ERROR_CTRL; + return -ENOMEM; + } + + id = HI3620_CTRL; + return 0; } void hi3xxx_set_cpu(int cpu, bool enable) @@ -173,11 +180,15 @@ static bool hix5hd2_hotplug_init(void) struct device_node *np; np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl"); - if (np) { - ctrl_base = of_iomap(np, 0); - return true; - } - return false; + if (!np) + return false; + + ctrl_base = of_iomap(np, 0); + of_node_put(np); + if (!ctrl_base) + return false; + + return true; } void hix5hd2_set_cpu(int cpu, bool enable) @@ -219,10 +230,10 @@ void hip01_set_cpu(int cpu, bool enable) if (!ctrl_base) { np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); - if (np) - ctrl_base = of_iomap(np, 0); - else - BUG(); + BUG_ON(!np); + ctrl_base = of_iomap(np, 0); + of_node_put(np); + BUG_ON(!ctrl_base); } if (enable) { diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 6f4232384774..abc337111eff 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -523,18 +523,6 @@ config SOC_IMX6UL help This enables support for Freescale i.MX6 UltraLite processor. -config SOC_IMX7D - bool "i.MX7 Dual support" - select PINCTRL_IMX7D - select ARM_GIC - select HAVE_ARM_ARCH_TIMER - select HAVE_IMX_ANATOP - select HAVE_IMX_MMDC - select HAVE_IMX_SRC - select IMX_GPCV2 - help - This enables support for Freescale i.MX7 Dual processor. - config SOC_LS1021A bool "Freescale LS1021A support" select ARM_GIC @@ -549,6 +537,27 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms" if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M +config SOC_IMX7D_CA7 + bool + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + select HAVE_IMX_ANATOP + select HAVE_IMX_MMDC + select HAVE_IMX_SRC + select IMX_GPCV2 + +config SOC_IMX7D_CM4 + bool + select ARMV7M_SYSTICK + +config SOC_IMX7D + bool "i.MX7 Dual support" + select PINCTRL_IMX7D + select SOC_IMX7D_CA7 if ARCH_MULTI_V7 + select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M + help + This enables support for Freescale i.MX7 Dual processor. + config SOC_VF610 bool "Vybrid Family VF610 support" select ARM_GIC if ARCH_MULTI_V7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 2327e3e876d8..bae179af21f6 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -26,7 +26,7 @@ ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o -obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sl.o +obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sx.o obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o endif @@ -81,7 +81,8 @@ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o -obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o +obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o +obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index c8d68e918b2f..423dd76bb6b8 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -38,7 +38,6 @@ void imx21_soc_init(void); void imx27_soc_init(void); void imx31_soc_init(void); void imx35_soc_init(void); -void epit_timer_init(void __iomem *base, int irq); int mx21_clocks_init(unsigned long lref, unsigned long fref); int mx27_clocks_init(unsigned long fref); int mx31_clocks_init(unsigned long fref); @@ -58,10 +57,12 @@ struct device *imx_soc_device_init(void); void imx6_enable_rbc(bool enable); void imx_gpc_check_dt(void); void imx_gpc_set_arm_power_in_lpm(bool power_off); +void imx_gpc_set_l2_mem_power_in_lpm(bool power_off); void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); void imx25_pm_init(void); void imx27_pm_init(void); +void imx5_pmu_init(void); enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index 4f2d1c772f85..e210bac18840 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c @@ -117,3 +117,48 @@ int mx53_revision(void) return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); + +#define ARM_GPC 0x4 +#define DBGEN BIT(16) + +/* + * This enables the DBGEN bit in ARM_GPC register, which is + * required for accessing some performance counter features. + * Technically it is only required while perf is used, but to + * keep the source code simple we just enable it all the time + * when the kernel configuration allows using the feature. + */ +void __init imx5_pmu_init(void) +{ + void __iomem *tigerp_base; + struct device_node *np; + u32 gpc; + + if (!IS_ENABLED(CONFIG_ARM_PMU)) + return; + + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); + if (!np) + return; + + if (!of_property_read_bool(np, "secure-reg-access")) + goto exit; + + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp"); + if (!np) + return; + + tigerp_base = of_iomap(np, 0); + if (!tigerp_base) + goto exit; + + gpc = readl_relaxed(tigerp_base + ARM_GPC); + gpc |= DBGEN; + writel_relaxed(gpc, tigerp_base + ARM_GPC); + iounmap(tigerp_base); +exit: + of_node_put(np); + +} diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 32969f34486a..c6b1bf97a6c1 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -68,6 +68,7 @@ void __init imx_aips_allow_unprivileged_access( for_each_compatible_node(np, NULL, compat) { aips_base_addr = of_iomap(np, 0); + WARN_ON(!aips_base_addr); imx_set_aips(aips_base_addr); } } diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c index fa8ead145d17..8d866fb674a8 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sl.c +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c @@ -12,7 +12,6 @@ #include "common.h" #include "cpuidle.h" -#include "hardware.h" static int imx6sl_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) @@ -22,11 +21,9 @@ static int imx6sl_enter_wait(struct cpuidle_device *dev, * Software workaround for ERR005311, see function * description for details. */ - if (cpu_is_imx6sl()) - imx6sl_set_wait_clk(true); + imx6sl_set_wait_clk(true); cpu_do_idle(); - if (cpu_is_imx6sl()) - imx6sl_set_wait_clk(false); + imx6sl_set_wait_clk(false); imx6_set_lpm(WAIT_CLOCKED); return index; diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index d0f14b761ff7..243a108a940b 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -103,6 +103,7 @@ int __init imx6sx_cpuidle_init(void) { imx6_set_int_mem_clk_lpm(true); imx6_enable_rbc(false); + imx_gpc_set_l2_mem_power_in_lpm(false); /* * set ARM power up/down timing to the fastest, * sw2iso and sw can be set to one 32K cycle = 31us diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index de535cb679b3..e11159d40fb8 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -20,6 +20,7 @@ #include "common.h" #include "hardware.h" +#define GPC_CNTR 0x0 #define GPC_IMR1 0x008 #define GPC_PGC_CPU_PDN 0x2a0 #define GPC_PGC_CPU_PUPSCR 0x2a4 @@ -27,6 +28,8 @@ #define GPC_PGC_SW2ISO_SHIFT 0x8 #define GPC_PGC_SW_SHIFT 0x0 +#define GPC_CNTR_L2_PGE_SHIFT 22 + #define IMR_NUM 4 #define GPC_MAX_IRQS (IMR_NUM * 32) @@ -51,6 +54,17 @@ void imx_gpc_set_arm_power_in_lpm(bool power_off) writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); } +void imx_gpc_set_l2_mem_power_in_lpm(bool power_off) +{ + u32 val; + + val = readl_relaxed(gpc_base + GPC_CNTR); + val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT); + if (power_off) + val |= 1 << GPC_CNTR_L2_PGE_SHIFT; + writel_relaxed(val, gpc_base + GPC_CNTR); +} + void imx_gpc_pre_suspend(bool arm_power_off) { void __iomem *reg_imr1 = gpc_base + GPC_IMR1; diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index 668d74b72511..9d9640aaf858 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c @@ -9,35 +9,17 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> #include <asm/mach/arch.h> -#include <asm/mach/time.h> - #include "common.h" -#include "mx31.h" static const char * const imx31_dt_board_compat[] __initconst = { "fsl,imx31", NULL }; -/* FIXME: replace with DT binding */ -static const struct resource imx31_rnga_res[] __initconst = { - DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K), -}; - -static void __init imx31_dt_mach_init(void) -{ - platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res, - ARRAY_SIZE(imx31_rnga_res)); -} - DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, - .init_machine = imx31_dt_mach_init, .dt_compat = imx31_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c index 3835b6a3423c..c7169c2f94c4 100644 --- a/arch/arm/mach-imx/mach-imx51.c +++ b/arch/arm/mach-imx/mach-imx51.c @@ -12,6 +12,7 @@ #include <linux/io.h> #include <linux/irq.h> +#include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> @@ -48,11 +49,38 @@ static void __init imx51_ipu_mipi_setup(void) iounmap(hsc_addr); } +static void __init imx51_m4if_setup(void) +{ + void __iomem *m4if_base; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx51-m4if"); + if (!np) + return; + + m4if_base = of_iomap(np, 0); + if (!m4if_base) { + pr_err("Unable to map M4IF registers\n"); + return; + } + + /* + * Configure VPU and IPU with higher priorities + * in order to avoid artifacts during video playback + */ + writel_relaxed(0x00000203, m4if_base + 0x40); + writel_relaxed(0x00000000, m4if_base + 0x44); + writel_relaxed(0x00120125, m4if_base + 0x9c); + writel_relaxed(0x001901A3, m4if_base + 0x48); + iounmap(m4if_base); +} + static void __init imx51_dt_init(void) { imx51_ipu_mipi_setup(); imx_src_init(); - + imx51_m4if_setup(); + imx5_pmu_init(); imx_aips_allow_unprivileged_access("fsl,imx51-aipstz"); } diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 07c2e8dca494..5ec7100737e8 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -31,7 +31,7 @@ static void __init imx53_init_early(void) static void __init imx53_dt_init(void) { imx_src_init(); - + imx5_pmu_init(); imx_aips_allow_unprivileged_access("fsl,imx53-aipstz"); } diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index c7a1ef180dda..99be4225297a 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -42,7 +42,10 @@ static void __init imx6sl_init_late(void) if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); - imx6sl_cpuidle_init(); + if (IS_ENABLED(CONFIG_SOC_IMX6SL) && cpu_is_imx6sl()) + imx6sl_cpuidle_init(); + else if (IS_ENABLED(CONFIG_SOC_IMX6SLL)) + imx6sx_cpuidle_init(); } static void __init imx6sl_init_machine(void) diff --git a/arch/arm/mach-imx/mach-imx7d-cm4.c b/arch/arm/mach-imx/mach-imx7d-cm4.c new file mode 100644 index 000000000000..0800b5891d2a --- /dev/null +++ b/arch/arm/mach-imx/mach-imx7d-cm4.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> + */ + +#include <linux/kernel.h> +#include <asm/v7m.h> +#include <asm/mach/arch.h> + +static const char * const imx7d_cm4_dt_compat[] __initconst = { + "fsl,imx7d-cm4", + NULL, +}; + +DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)") + .dt_compat = imx7d_cm4_dt_compat, + .restart = armv7m_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 017539dd712b..b08e407d8d96 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -130,6 +130,13 @@ static const u32 imx6sl_mmdc_io_offset[] __initconst = { 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ }; +static const u32 imx6sll_mmdc_io_offset[] __initconst = { + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ +}; + static const u32 imx6sx_mmdc_io_offset[] __initconst = { 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ @@ -175,6 +182,16 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { .mmdc_io_offset = imx6sl_mmdc_io_offset, }; +static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sll-mmdc", + .src_compat = "fsl,imx6sll-src", + .iomuxc_compat = "fsl,imx6sll-iomuxc", + .gpc_compat = "fsl,imx6sll-gpc", + .pl310_compat = "arm,pl310-cache", + .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), + .mmdc_io_offset = imx6sll_mmdc_io_offset, +}; + static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { .mmdc_compat = "fsl,imx6sx-mmdc", .src_compat = "fsl,imx6sx-src", @@ -296,7 +313,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) if (cpu_is_imx6sl()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || - cpu_is_imx6ull()) + cpu_is_imx6ull() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; @@ -314,7 +331,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) if (cpu_is_imx6sl() || cpu_is_imx6sx()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || - cpu_is_imx6ull()) + cpu_is_imx6ull() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; @@ -631,7 +648,17 @@ void __init imx6dl_pm_init(void) void __init imx6sl_pm_init(void) { - imx6_pm_common_init(&imx6sl_pm_data); + struct regmap *gpr; + + if (cpu_is_imx6sl()) { + imx6_pm_common_init(&imx6sl_pm_data); + } else { + imx6_pm_common_init(&imx6sll_pm_data); + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0); + } } void __init imx6sx_pm_init(void) diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index 4ffbbd217e82..c130497dc6cc 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -35,6 +35,8 @@ #define AXP_BOOTROM_BASE 0xfff00000 #define AXP_BOOTROM_SIZE 0x100000 +static struct clk *boot_cpu_clk; + static struct clk *get_cpu_clk(int cpu) { struct clk *cpu_clk; @@ -48,30 +50,6 @@ static struct clk *get_cpu_clk(int cpu) return cpu_clk; } -static void set_secondary_cpu_clock(unsigned int cpu) -{ - int thiscpu; - unsigned long rate; - struct clk *cpu_clk; - - thiscpu = get_cpu(); - - cpu_clk = get_cpu_clk(thiscpu); - if (!cpu_clk) - goto out; - clk_prepare_enable(cpu_clk); - rate = clk_get_rate(cpu_clk); - - cpu_clk = get_cpu_clk(cpu); - if (!cpu_clk) - goto out; - clk_set_rate(cpu_clk, rate); - clk_prepare_enable(cpu_clk); - -out: - put_cpu(); -} - static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle) { int ret, hw_cpu; @@ -79,7 +57,6 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle) pr_info("Booting CPU %d\n", cpu); hw_cpu = cpu_logical_map(cpu); - set_secondary_cpu_clock(hw_cpu); mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup); /* @@ -122,6 +99,19 @@ static void __init armada_xp_smp_init_cpus(void) panic("Invalid number of CPUs in DT\n"); } +static int armada_xp_sync_secondary_clk(unsigned int cpu) +{ + struct clk *cpu_clk = get_cpu_clk(cpu); + + if (!cpu_clk || !boot_cpu_clk) + return 0; + + clk_prepare_enable(cpu_clk); + clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk)); + + return 0; +} + static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) { struct device_node *node; @@ -131,6 +121,14 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) flush_cache_all(); set_cpu_coherent(); + boot_cpu_clk = get_cpu_clk(smp_processor_id()); + if (boot_cpu_clk) { + clk_prepare_enable(boot_cpu_clk); + cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS, + "arm/mvebu/sync_clocks:online", + armada_xp_sync_secondary_clk, NULL); + } + /* * In order to boot the secondary CPUs we need to ensure * the bootROM is mapped at the correct address. @@ -223,7 +221,6 @@ static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle) int ret, hw_cpu; hw_cpu = cpu_logical_map(cpu); - set_secondary_cpu_clock(hw_cpu); mv98dx3236_resume_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup); diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 27a78c80e5b1..73d5d72dfc3e 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -116,8 +116,8 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); } -extern unsigned char mvebu_boot_wa_start; -extern unsigned char mvebu_boot_wa_end; +extern unsigned char mvebu_boot_wa_start[]; +extern unsigned char mvebu_boot_wa_end[]; /* * This function sets up the boot address workaround needed for SMP @@ -130,7 +130,7 @@ int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target, phys_addr_t resume_addr_reg) { void __iomem *sram_virt_base; - u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start; + u32 code_len = mvebu_boot_wa_end - mvebu_boot_wa_start; mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE); mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute, diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S index bf608441b357..ddc27638ba2a 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -14,11 +14,12 @@ */ #include <linux/linkage.h> -#include <asm/assembler.h> +#include <linux/platform_data/ams-delta-fiq.h> +#include <asm/assembler.h> #include <mach/board-ams-delta.h> -#include <mach/ams-delta-fiq.h> +#include "ams-delta-fiq.h" #include "iomap.h" #include "soc.h" diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index d7ca9e2b40d2..b0dc7ddf5877 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -13,17 +13,20 @@ * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. */ -#include <linux/gpio.h> +#include <linux/gpio/consumer.h> +#include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/io.h> +#include <linux/platform_data/ams-delta-fiq.h> +#include <linux/platform_device.h> #include <mach/board-ams-delta.h> #include <asm/fiq.h> -#include <mach/ams-delta-fiq.h> +#include "ams-delta-fiq.h" static struct fiq_handler fh = { .name = "ams-delta-fiq" @@ -34,20 +37,24 @@ static struct fiq_handler fh = { * The FIQ and IRQ isrs can both read and write it. * It is structured as a header section several 32bit slots, * followed by the circular buffer where the FIQ isr stores - * keystrokes received from the qwerty keyboard. - * See ams-delta-fiq.h for details of offsets. + * keystrokes received from the qwerty keyboard. See + * <linux/platform_data/ams-delta-fiq.h> for details of offsets. */ -unsigned int fiq_buffer[1024]; -EXPORT_SYMBOL(fiq_buffer); +static unsigned int fiq_buffer[1024]; +static struct irq_chip *irq_chip; +static struct irq_data *irq_data[16]; static unsigned int irq_counter[16]; +static const char *pin_name[16] __initconst = { + [AMS_DELTA_GPIO_PIN_KEYBRD_DATA] = "keybrd_data", + [AMS_DELTA_GPIO_PIN_KEYBRD_CLK] = "keybrd_clk", +}; + static irqreturn_t deferred_fiq(int irq, void *dev_id) { + struct irq_data *d; int gpio, irq_num, fiq_count; - struct irq_chip *irq_chip; - - irq_chip = irq_get_chip(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK)); /* * For each handled GPIO interrupt, keep calling its interrupt handler @@ -55,24 +62,21 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id) */ for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK; gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) { - irq_num = gpio_to_irq(gpio); + d = irq_data[gpio]; + irq_num = d->irq; fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio]; if (irq_counter[gpio] < fiq_count && gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) { - struct irq_data *d = irq_get_irq_data(irq_num); - /* * handle_simple_irq() that OMAP GPIO edge * interrupts default to since commit 80ac93c27441 * requires interrupt already acked and unmasked. */ - if (irq_chip) { - if (irq_chip->irq_ack) - irq_chip->irq_ack(d); - if (irq_chip->irq_unmask) - irq_chip->irq_unmask(d); - } + if (irq_chip->irq_ack) + irq_chip->irq_ack(d); + if (irq_chip->irq_unmask) + irq_chip->irq_unmask(d); } for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++) generic_handle_irq(irq_num); @@ -80,14 +84,56 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id) return IRQ_HANDLED; } -void __init ams_delta_init_fiq(void) +void __init ams_delta_init_fiq(struct gpio_chip *chip, + struct platform_device *serio) { + struct gpio_desc *gpiod, *data = NULL, *clk = NULL; void *fiqhandler_start; unsigned int fiqhandler_length; struct pt_regs FIQ_regs; unsigned long val, offset; int i, retval; + /* Store irq_chip location for IRQ handler use */ + irq_chip = chip->irq.chip; + if (!irq_chip) { + pr_err("%s: GPIO chip %s is missing IRQ function\n", __func__, + chip->label); + return; + } + + for (i = 0; i < ARRAY_SIZE(irq_data); i++) { + gpiod = gpiochip_request_own_desc(chip, i, pin_name[i]); + if (IS_ERR(gpiod)) { + pr_err("%s: failed to get GPIO pin %d (%ld)\n", + __func__, i, PTR_ERR(gpiod)); + return; + } + /* Store irq_data location for IRQ handler use */ + irq_data[i] = irq_get_irq_data(gpiod_to_irq(gpiod)); + + /* + * FIQ handler takes full control over serio data and clk GPIO + * pins. Initiaize them and keep requested so nobody can + * interfere. Fail if any of those two couldn't be requested. + */ + switch (i) { + case AMS_DELTA_GPIO_PIN_KEYBRD_DATA: + data = gpiod; + gpiod_direction_input(data); + break; + case AMS_DELTA_GPIO_PIN_KEYBRD_CLK: + clk = gpiod; + gpiod_direction_input(clk); + break; + default: + gpiochip_free_own_desc(gpiod); + break; + } + } + if (!data || !clk) + goto out_gpio; + fiqhandler_start = &qwerty_fiqin_start; fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start; pr_info("Installing fiq handler from %p, length 0x%x\n", @@ -97,7 +143,7 @@ void __init ams_delta_init_fiq(void) if (retval) { pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n", retval); - return; + goto out_gpio; } retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq, @@ -105,7 +151,7 @@ void __init ams_delta_init_fiq(void) if (retval < 0) { pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval); release_fiq(&fh); - return; + goto out_gpio; } /* * Since no set_type() method is provided by OMAP irq chip, @@ -155,4 +201,29 @@ void __init ams_delta_init_fiq(void) offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4; val = omap_readl(OMAP_IH1_BASE + offset) | 1; omap_writel(val, OMAP_IH1_BASE + offset); + + /* Initialize serio device IRQ resource and platform_data */ + serio->resource[0].start = gpiod_to_irq(clk); + serio->resource[0].end = serio->resource[0].start; + serio->dev.platform_data = fiq_buffer; + + /* + * Since FIQ handler performs handling of GPIO registers for + * "keybrd_clk" IRQ pin, ams_delta_serio driver used to set + * handle_simple_irq() as active IRQ handler for that pin to avoid + * bad interaction with gpio-omap driver. This is no longer needed + * as handle_simple_irq() is now the default handler for OMAP GPIO + * edge interrupts. + * This comment replaces the obsolete code which has been removed + * from the ams_delta_serio driver and stands here only as a reminder + * of that dependency on gpio-omap driver behavior. + */ + + return; + +out_gpio: + if (data) + gpiochip_free_own_desc(data); + if (clk) + gpiochip_free_own_desc(clk); } diff --git a/arch/arm/mach-omap1/ams-delta-fiq.h b/arch/arm/mach-omap1/ams-delta-fiq.h new file mode 100644 index 000000000000..fd76df3cce37 --- /dev/null +++ b/arch/arm/mach-omap1/ams-delta-fiq.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * arch/arm/mach-omap1/ams-delta-fiq.h + * + * Taken from the original Amstrad modifications to fiq.h + * + * Copyright (c) 2004 Amstrad Plc + * Copyright (c) 2006 Matt Callow + * Copyright (c) 2010 Janusz Krzysztofik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __AMS_DELTA_FIQ_H +#define __AMS_DELTA_FIQ_H + +#include <mach/irqs.h> + +/* + * Interrupt number used for passing control from FIQ to IRQ. + * IRQ12, described as reserved, has been selected. + */ +#define INT_DEFERRED_FIQ INT_1510_RES12 +/* + * Base address of an interrupt handler that the INT_DEFERRED_FIQ belongs to. + */ +#if (INT_DEFERRED_FIQ < IH2_BASE) +#define DEFERRED_FIQ_IH_BASE OMAP_IH1_BASE +#else +#define DEFERRED_FIQ_IH_BASE OMAP_IH2_BASE +#endif + +#ifndef __ASSEMBLER__ +extern unsigned char qwerty_fiqin_start, qwerty_fiqin_end; + +extern void __init ams_delta_init_fiq(struct gpio_chip *chip, + struct platform_device *pdev); +#endif + +#endif diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 80f54cb54276..dd28d2614d7f 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -41,10 +41,10 @@ #include <mach/mux.h> #include <mach/hardware.h> -#include <mach/ams-delta-fiq.h> #include "camera.h" #include <mach/usb.h> +#include "ams-delta-fiq.h" #include "iomap.h" #include "common.h" @@ -179,7 +179,10 @@ static struct resource latch1_resources[] = { }, }; +#define LATCH1_LABEL "latch1" + static struct bgpio_pdata latch1_pdata = { + .label = LATCH1_LABEL, .base = LATCH1_GPIO_BASE, .ngpio = LATCH1_NGPIO, }; @@ -194,6 +197,15 @@ static struct platform_device latch1_gpio_device = { }, }; +#define LATCH1_PIN_LED_CAMERA 0 +#define LATCH1_PIN_LED_ADVERT 1 +#define LATCH1_PIN_LED_MAIL 2 +#define LATCH1_PIN_LED_HANDSFREE 3 +#define LATCH1_PIN_LED_VOICEMAIL 4 +#define LATCH1_PIN_LED_VOICE 5 +#define LATCH1_PIN_DOCKIT1 6 +#define LATCH1_PIN_DOCKIT2 7 + static struct resource latch2_resources[] = { [0] = { .name = "dat", @@ -398,38 +410,43 @@ static struct gpiod_lookup_table ams_delta_lcd_gpio_table = { }, }; -static const struct gpio_led gpio_leds[] __initconst = { - { +/* + * Dynamically allocated GPIO numbers must be obtained fromm GPIO device + * before they can be put in the gpio_led table. Before that happens, + * initialize the table with invalid GPIO numbers, not 0. + */ +static struct gpio_led gpio_leds[] __initdata = { + [LATCH1_PIN_LED_CAMERA] = { .name = "camera", - .gpio = LATCH1_GPIO_BASE + 0, + .gpio = -EINVAL, .default_state = LEDS_GPIO_DEFSTATE_OFF, #ifdef CONFIG_LEDS_TRIGGERS .default_trigger = "ams_delta_camera", #endif }, - { + [LATCH1_PIN_LED_ADVERT] = { .name = "advert", - .gpio = LATCH1_GPIO_BASE + 1, + .gpio = -EINVAL, .default_state = LEDS_GPIO_DEFSTATE_OFF, }, - { + [LATCH1_PIN_LED_MAIL] = { .name = "email", - .gpio = LATCH1_GPIO_BASE + 2, + .gpio = -EINVAL, .default_state = LEDS_GPIO_DEFSTATE_OFF, }, - { + [LATCH1_PIN_LED_HANDSFREE] = { .name = "handsfree", - .gpio = LATCH1_GPIO_BASE + 3, + .gpio = -EINVAL, .default_state = LEDS_GPIO_DEFSTATE_OFF, }, - { + [LATCH1_PIN_LED_VOICEMAIL] = { .name = "voicemail", - .gpio = LATCH1_GPIO_BASE + 4, + .gpio = -EINVAL, .default_state = LEDS_GPIO_DEFSTATE_OFF, }, - { + [LATCH1_PIN_LED_VOICE] = { .name = "voice", - .gpio = LATCH1_GPIO_BASE + 5, + .gpio = -EINVAL, .default_state = LEDS_GPIO_DEFSTATE_OFF, }, }; @@ -504,16 +521,70 @@ static struct platform_device cx20442_codec_device = { .id = -1, }; -static struct gpiod_lookup_table ams_delta_serio_gpio_table = { +static struct resource ams_delta_serio_resources[] = { + { + .flags = IORESOURCE_IRQ, + /* + * Initialize IRQ resource with invalid IRQ number. + * It will be replaced with dynamically allocated GPIO IRQ + * obtained from GPIO chip as soon as the chip is available. + */ + .start = -EINVAL, + .end = -EINVAL, + }, +}; + +static struct platform_device ams_delta_serio_device = { + .name = "ams-delta-serio", + .id = PLATFORM_DEVID_NONE, + .dev = { + /* + * Initialize .platform_data explicitly with NULL to + * indicate it is going to be used. It will be replaced + * with FIQ buffer address as soon as FIQ is initialized. + */ + .platform_data = NULL, + }, + .num_resources = ARRAY_SIZE(ams_delta_serio_resources), + .resource = ams_delta_serio_resources, +}; + +static struct regulator_consumer_supply keybrd_pwr_consumers[] = { + /* + * Initialize supply .dev_name with NULL. It will be replaced + * with serio dev_name() as soon as the serio device is registered. + */ + REGULATOR_SUPPLY("vcc", NULL), +}; + +static struct regulator_init_data keybrd_pwr_initdata = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(keybrd_pwr_consumers), + .consumer_supplies = keybrd_pwr_consumers, +}; + +static struct fixed_voltage_config keybrd_pwr_config = { + .supply_name = "keybrd_pwr", + .microvolts = 5000000, + .gpio = AMS_DELTA_GPIO_PIN_KEYBRD_PWR, + .enable_high = 1, + .init_data = &keybrd_pwr_initdata, +}; + +static struct platform_device keybrd_pwr_device = { + .name = "reg-fixed-voltage", + .id = PLATFORM_DEVID_AUTO, + .dev = { + .platform_data = &keybrd_pwr_config, + }, +}; + +static struct gpiod_lookup_table keybrd_pwr_gpio_table = { .table = { - GPIO_LOOKUP(OMAP_GPIO_LABEL, AMS_DELTA_GPIO_PIN_KEYBRD_DATA, - "data", 0), - GPIO_LOOKUP(OMAP_GPIO_LABEL, AMS_DELTA_GPIO_PIN_KEYBRD_CLK, - "clock", 0), - GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_KEYBRD_PWR, - "power", 0), - GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_KEYBRD_DATAOUT, - "dataout", 0), + GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_KEYBRD_PWR, NULL, + GPIO_ACTIVE_HIGH), { }, }, }; @@ -524,9 +595,7 @@ static struct platform_device *ams_delta_devices[] __initdata = { &ams_delta_kp_device, &ams_delta_camera_device, &ams_delta_audio_device, -}; - -static struct platform_device *late_devices[] __initdata = { + &ams_delta_serio_device, &ams_delta_nand_device, &ams_delta_lcd_device, &cx20442_codec_device, @@ -534,14 +603,55 @@ static struct platform_device *late_devices[] __initdata = { static struct gpiod_lookup_table *ams_delta_gpio_tables[] __initdata = { &ams_delta_audio_gpio_table, - &ams_delta_serio_gpio_table, -}; - -static struct gpiod_lookup_table *late_gpio_tables[] __initdata = { + &keybrd_pwr_gpio_table, &ams_delta_lcd_gpio_table, &ams_delta_nand_gpio_table, }; +/* + * Some drivers may not use GPIO lookup tables but need to be provided + * with GPIO numbers. The same applies to GPIO based IRQ lines - some + * drivers may even not use GPIO layer but expect just IRQ numbers. + * We could either define GPIO lookup tables then use them on behalf + * of those devices, or we can use GPIO driver level methods for + * identification of GPIO and IRQ numbers. For the purpose of the latter, + * defina a helper function which identifies GPIO chips by their labels. + */ +static int gpiochip_match_by_label(struct gpio_chip *chip, void *data) +{ + char *label = data; + + return !strcmp(label, chip->label); +} + +static struct gpiod_hog ams_delta_gpio_hogs[] = { + GPIO_HOG(LATCH2_LABEL, LATCH2_PIN_KEYBRD_DATAOUT, "keybrd_dataout", + GPIO_ACTIVE_HIGH, GPIOD_OUT_LOW), + {}, +}; + +/* + * The purpose of this function is to take care of proper initialization of + * devices and data structures which depend on GPIO lines provided by OMAP GPIO + * banks but their drivers don't use GPIO lookup tables or GPIO layer at all. + * The function may be called as soon as OMAP GPIO devices are probed. + * Since that happens at postcore_initcall, it can be called successfully + * from init_machine or later. + * Dependent devices may be registered from within this function or later. + */ +static void __init omap_gpio_deps_init(void) +{ + struct gpio_chip *chip; + + chip = gpiochip_find(OMAP_GPIO_LABEL, gpiochip_match_by_label); + if (!chip) { + pr_err("%s: OMAP GPIO chip not found\n", __func__); + return; + } + + ams_delta_init_fiq(chip, &ams_delta_serio_device); +} + static void __init ams_delta_init(void) { /* mux pins for uarts */ @@ -562,6 +672,9 @@ static void __init ams_delta_init(void) omap_cfg_reg(J19_1610_CAM_D6); omap_cfg_reg(J18_1610_CAM_D7); + omap_gpio_deps_init(); + gpiod_add_hogs(ams_delta_gpio_hogs); + omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); @@ -571,25 +684,38 @@ static void __init ams_delta_init(void) led_trigger_register_simple("ams_delta_camera", &ams_delta_camera_led_trigger); #endif - gpio_led_register_device(-1, &leds_pdata); platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); /* - * As soon as devices have been registered, assign their dev_names - * to respective GPIO lookup tables before they are added. + * As soon as regulator consumers have been registered, assign their + * dev_names to consumer supply entries of respective regulators. + */ + keybrd_pwr_consumers[0].dev_name = + dev_name(&ams_delta_serio_device.dev); + + /* + * Once consumer supply entries are populated with dev_names, + * register regulator devices. At this stage only the keyboard + * power regulator has its consumer supply table fully populated. + */ + platform_device_register(&keybrd_pwr_device); + + /* + * As soon as GPIO consumers have been registered, assign + * their dev_names to respective GPIO lookup tables. */ ams_delta_audio_gpio_table.dev_id = dev_name(&ams_delta_audio_device.dev); + keybrd_pwr_gpio_table.dev_id = dev_name(&keybrd_pwr_device.dev); + ams_delta_nand_gpio_table.dev_id = dev_name(&ams_delta_nand_device.dev); + ams_delta_lcd_gpio_table.dev_id = dev_name(&ams_delta_lcd_device.dev); + /* - * No device name is assigned to GPIO lookup table for serio device - * as long as serio driver is not converted to platform device driver. + * Once GPIO lookup tables are populated with dev_names, register them. */ - gpiod_add_lookup_tables(ams_delta_gpio_tables, ARRAY_SIZE(ams_delta_gpio_tables)); - ams_delta_init_fiq(); - omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); omapfb_set_lcd_config(&ams_delta_lcd_config); @@ -643,35 +769,84 @@ static struct platform_device ams_delta_modem_device = { }, }; -static int __init late_init(void) +/* + * leds-gpio driver doesn't make use of GPIO lookup tables, + * it has to be provided with GPIO numbers over platform data + * if GPIO descriptor info can't be obtained from device tree. + * We could either define GPIO lookup tables and use them on behalf + * of the leds-gpio device, or we can use GPIO driver level methods + * for identification of GPIO numbers as long as we don't support + * device tree. Let's do the latter. + */ +static void __init ams_delta_led_init(struct gpio_chip *chip) +{ + struct gpio_desc *gpiod; + int i; + + for (i = LATCH1_PIN_LED_CAMERA; i < LATCH1_PIN_DOCKIT1; i++) { + gpiod = gpiochip_request_own_desc(chip, i, NULL); + if (IS_ERR(gpiod)) { + pr_warn("%s: %s GPIO %d request failed (%ld)\n", + __func__, LATCH1_LABEL, i, PTR_ERR(gpiod)); + continue; + } + + /* Assign GPIO numbers to LED device. */ + gpio_leds[i].gpio = desc_to_gpio(gpiod); + + gpiochip_free_own_desc(gpiod); + } + + gpio_led_register_device(PLATFORM_DEVID_NONE, &leds_pdata); +} + +/* + * The purpose of this function is to take care of assignment of GPIO numbers + * to platform devices which depend on GPIO lines provided by Amstrad Delta + * latch1 and/or latch2 GPIO devices but don't use GPIO lookup tables. + * The function may be called as soon as latch1/latch2 GPIO devices are + * initilized. Since basic-mmio-gpio driver is not registered before + * device_initcall, this may happen at erliest during device_initcall_sync. + * Dependent devices shouldn't be registered before that, their + * registration may be performed from within this function or later. + */ +static int __init ams_delta_gpio_init(void) { + struct gpio_chip *chip; int err; if (!machine_is_ams_delta()) return -ENODEV; + chip = gpiochip_find(LATCH1_LABEL, gpiochip_match_by_label); + if (!chip) + pr_err("%s: latch1 GPIO chip not found\n", __func__); + else + ams_delta_led_init(chip); + err = gpio_request_array(latch_gpios, ARRAY_SIZE(latch_gpios)); - if (err) { + if (err) pr_err("Couldn't take over latch1/latch2 GPIO pins\n"); - return err; - } - platform_add_devices(late_devices, ARRAY_SIZE(late_devices)); - - /* - * As soon as devices have been registered, assign their dev_names - * to respective GPIO lookup tables before they are added. - */ - ams_delta_lcd_gpio_table.dev_id = dev_name(&ams_delta_lcd_device.dev); - ams_delta_nand_gpio_table.dev_id = dev_name(&ams_delta_nand_device.dev); + return err; +} +device_initcall_sync(ams_delta_gpio_init); - gpiod_add_lookup_tables(late_gpio_tables, ARRAY_SIZE(late_gpio_tables)); +static int __init modem_nreset_init(void) +{ + int err; err = platform_device_register(&modem_nreset_device); - if (err) { + if (err) pr_err("Couldn't register the modem regulator device\n"); - return err; - } + + return err; +} + + +static int __init ams_delta_modem_init(void) +{ + int err; omap_cfg_reg(M14_1510_GPIO2); ams_delta_modem_ports[0].irq = @@ -692,7 +867,22 @@ static int __init late_init(void) err = platform_device_register(&ams_delta_modem_device); if (err) - goto gpio_free; + gpio_free(AMS_DELTA_GPIO_PIN_MODEM_IRQ); + + return err; +} + +static int __init late_init(void) +{ + int err; + + err = modem_nreset_init(); + if (err) + return err; + + err = ams_delta_modem_init(); + if (err) + return err; /* * Once the modem device is registered, the modem_nreset @@ -708,7 +898,6 @@ static int __init late_init(void) unregister: platform_device_unregister(&ams_delta_modem_device); -gpio_free: gpio_free(AMS_DELTA_GPIO_PIN_MODEM_IRQ); return err; } diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index ab51f8554697..9aeb8ad8c327 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -274,7 +274,7 @@ static struct platform_device h2_kp_device = { .resource = h2_kp_resources, }; -static struct gpio_led h2_gpio_led_pins[] = { +static const struct gpio_led h2_gpio_led_pins[] = { { .name = "h2:red", .default_trigger = "heartbeat", diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index ad339f51cc78..2edcd6356f2d 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -326,7 +326,7 @@ static struct spi_board_info h3_spi_board_info[] __initdata = { }, }; -static struct gpio_led h3_gpio_led_pins[] = { +static const struct gpio_led h3_gpio_led_pins[] = { { .name = "h3:red", .default_trigger = "heartbeat", diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index da8f3fc3180f..5733212759d3 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -292,7 +292,7 @@ static struct platform_device herald_gpiokeys_device = { }; /* LEDs for the Herald. These connect to the HTCPLD GPIO device. */ -static struct gpio_led gpio_leds[] = { +static const struct gpio_led gpio_leds[] = { {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 9ffa8d755a59..4df15e693b6e 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -167,7 +167,7 @@ static struct platform_device *osk5912_devices[] __initdata = { &osk5912_cf_device, }; -static struct gpio_led tps_leds[] = { +static const struct gpio_led tps_leds[] = { /* NOTE: D9 and D2 have hardware blink support. * Also, D9 requires non-battery power. */ @@ -385,7 +385,7 @@ static struct platform_device osk5912_lcd_device = { .id = -1, }; -static struct gpio_led mistral_gpio_led_pins[] = { +static const struct gpio_led mistral_gpio_led_pins[] = { { .name = "mistral:red", .default_trigger = "heartbeat", diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c index b68f9c0aff0b..d5ddba00bb73 100644 --- a/arch/arm/mach-omap2/omap_hwmod_reset.c +++ b/arch/arm/mach-omap2/omap_hwmod_reset.c @@ -92,11 +92,13 @@ static void omap_rtc_wait_not_busy(struct omap_hwmod *oh) */ void omap_hwmod_rtc_unlock(struct omap_hwmod *oh) { - local_irq_disable(); + unsigned long flags; + + local_irq_save(flags); omap_rtc_wait_not_busy(oh); omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG); omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG); - local_irq_enable(); + local_irq_restore(flags); } /** @@ -110,9 +112,11 @@ void omap_hwmod_rtc_unlock(struct omap_hwmod *oh) */ void omap_hwmod_rtc_lock(struct omap_hwmod *oh) { - local_irq_disable(); + unsigned long flags; + + local_irq_save(flags); omap_rtc_wait_not_busy(oh); omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG); omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG); - local_irq_enable(); + local_irq_restore(flags); } diff --git a/arch/arm/mach-omap2/pm-asm-offsets.c b/arch/arm/mach-omap2/pm-asm-offsets.c index b9846b19e5e2..d8ae8a85b14b 100644 --- a/arch/arm/mach-omap2/pm-asm-offsets.c +++ b/arch/arm/mach-omap2/pm-asm-offsets.c @@ -27,6 +27,8 @@ int main(void) offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_virt)); DEFINE(AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET, offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_phys)); + DEFINE(AMX3_PM_RTC_BASE_VIRT_OFFSET, + offsetof(struct am33xx_pm_ro_sram_data, rtc_base_virt)); DEFINE(AMX3_PM_RO_SRAM_DATA_SIZE, sizeof(struct am33xx_pm_ro_sram_data)); diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index acb698d5780f..5a8839203958 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -47,11 +47,6 @@ static int pm_dbg_init_done; static int pm_dbg_init(void); -enum { - DEBUG_FILE_COUNTERS = 0, - DEBUG_FILE_TIMERS, -}; - static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = { "OFF", "RET", @@ -141,39 +136,21 @@ static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user) return 0; } -static int pm_dbg_show_counters(struct seq_file *s, void *unused) +static int pm_dbg_counters_show(struct seq_file *s, void *unused) { pwrdm_for_each(pwrdm_dbg_show_counter, s); clkdm_for_each(clkdm_dbg_show_counter, s); return 0; } +DEFINE_SHOW_ATTRIBUTE(pm_dbg_counters); -static int pm_dbg_show_timers(struct seq_file *s, void *unused) +static int pm_dbg_timers_show(struct seq_file *s, void *unused) { pwrdm_for_each(pwrdm_dbg_show_timer, s); return 0; } - -static int pm_dbg_open(struct inode *inode, struct file *file) -{ - switch ((int)inode->i_private) { - case DEBUG_FILE_COUNTERS: - return single_open(file, pm_dbg_show_counters, - &inode->i_private); - case DEBUG_FILE_TIMERS: - default: - return single_open(file, pm_dbg_show_timers, - &inode->i_private); - } -} - -static const struct file_operations debug_fops = { - .open = pm_dbg_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; +DEFINE_SHOW_ATTRIBUTE(pm_dbg_timers); static int pwrdm_suspend_get(void *data, u64 *val) { @@ -259,10 +236,8 @@ static int __init pm_dbg_init(void) if (!d) return -EINVAL; - (void) debugfs_create_file("count", S_IRUGO, - d, (void *)DEBUG_FILE_COUNTERS, &debug_fops); - (void) debugfs_create_file("time", S_IRUGO, - d, (void *)DEBUG_FILE_TIMERS, &debug_fops); + (void) debugfs_create_file("count", 0444, d, NULL, &pm_dbg_counters_fops); + (void) debugfs_create_file("time", 0444, d, NULL, &pm_dbg_timers_fops); pwrdm_for_each(pwrdms_setup, (void *)d); diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c index 9b3755a2e2ec..f4971e4a86b2 100644 --- a/arch/arm/mach-omap2/pm33xx-core.c +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -26,6 +26,7 @@ static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; static struct clockdomain *gfx_l4ls_clkdm; static void __iomem *scu_base; +static struct omap_hwmod *rtc_oh; static int __init am43xx_map_scu(void) { @@ -106,12 +107,13 @@ static void amx3_post_suspend_common(void) pr_err("PM: GFX domain did not transition: %x\n", status); } -static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long)) +static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long), + unsigned long args) { int ret = 0; amx3_pre_suspend_common(); - ret = cpu_suspend(0, fn); + ret = cpu_suspend(args, fn); amx3_post_suspend_common(); /* @@ -128,13 +130,14 @@ static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long)) return ret; } -static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long)) +static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), + unsigned long args) { int ret = 0; amx3_pre_suspend_common(); scu_power_mode(scu_base, SCU_PM_POWEROFF); - ret = cpu_suspend(0, fn); + ret = cpu_suspend(args, fn); scu_power_mode(scu_base, SCU_PM_NORMAL); amx3_post_suspend_common(); @@ -151,16 +154,25 @@ static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void) return NULL; } +void __iomem *am43xx_get_rtc_base_addr(void) +{ + rtc_oh = omap_hwmod_lookup("rtc"); + + return omap_hwmod_get_mpu_rt_va(rtc_oh); +} + static struct am33xx_pm_platform_data am33xx_ops = { .init = am33xx_suspend_init, .soc_suspend = am33xx_suspend, .get_sram_addrs = amx3_get_sram_addrs, + .get_rtc_base_addr = am43xx_get_rtc_base_addr, }; static struct am33xx_pm_platform_data am43xx_ops = { .init = am43xx_suspend_init, .soc_suspend = am43xx_suspend, .get_sram_addrs = amx3_get_sram_addrs, + .get_rtc_base_addr = am43xx_get_rtc_base_addr, }; static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void) diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S index 322b3bb868b4..47a816468cdb 100644 --- a/arch/arm/mach-omap2/sleep33xx.S +++ b/arch/arm/mach-omap2/sleep33xx.S @@ -8,6 +8,7 @@ #include <generated/ti-pm-asm-offsets.h> #include <linux/linkage.h> +#include <linux/platform_data/pm33xx.h> #include <linux/ti-emif-sram.h> #include <asm/assembler.h> #include <asm/memory.h> @@ -19,12 +20,25 @@ #define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003 #define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002 +/* replicated define because linux/bitops.h cannot be included in assembly */ +#define BIT(nr) (1 << (nr)) + .arm .align 3 ENTRY(am33xx_do_wfi) stmfd sp!, {r4 - r11, lr} @ save registers on stack + /* Save wfi_flags arg to data space */ + mov r4, r0 + adr r3, am33xx_pm_ro_sram_data + ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] + str r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET] + + /* Only flush cache is we know we are losing MPU context */ + tst r4, #WFI_FLAG_FLUSH_CACHE + beq cache_skip_flush + /* * Flush all data from the L1 and L2 data cache before disabling * SCTLR.C bit. @@ -48,14 +62,33 @@ ENTRY(am33xx_do_wfi) ldr r1, kernel_flush blx r1 + adr r3, am33xx_pm_ro_sram_data + ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] + ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET] + +cache_skip_flush: + /* Check if we want self refresh */ + tst r4, #WFI_FLAG_SELF_REFRESH + beq emif_skip_enter_sr + adr r9, am33xx_emif_sram_table ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET] blx r3 +emif_skip_enter_sr: + /* Only necessary if PER is losing context */ + tst r4, #WFI_FLAG_SAVE_EMIF + beq emif_skip_save + ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET] blx r3 +emif_skip_save: + /* Only can disable EMIF if we have entered self refresh */ + tst r4, #WFI_FLAG_SELF_REFRESH + beq emif_skip_disable + /* Disable EMIF */ ldr r1, virt_emif_clkctrl ldr r2, [r1] @@ -69,6 +102,10 @@ wait_emif_disable: cmp r2, r3 bne wait_emif_disable +emif_skip_disable: + tst r4, #WFI_FLAG_WAKE_M3 + beq wkup_m3_skip + /* * For the MPU WFI to be registered as an interrupt * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set @@ -79,6 +116,7 @@ wait_emif_disable: bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE str r2, [r1] +wkup_m3_skip: /* * Execute an ISB instruction to ensure that all of the * CP15 register changes have been committed. @@ -132,10 +170,18 @@ wait_emif_enable: cmp r2, r3 bne wait_emif_enable + /* Only necessary if PER is losing context */ + tst r4, #WFI_FLAG_SELF_REFRESH + beq emif_skip_exit_sr_abt + adr r9, am33xx_emif_sram_table ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET] blx r1 +emif_skip_exit_sr_abt: + tst r4, #WFI_FLAG_FLUSH_CACHE + beq cache_skip_restore + /* * Set SCTLR.C bit to allow data cache allocation */ @@ -144,6 +190,7 @@ wait_emif_enable: mcr p15, 0, r0, c1, c0, 0 isb +cache_skip_restore: /* Let the suspend code know about the abort */ mov r0, #1 ldmfd sp!, {r4 - r11, pc} @ restore regs and return @@ -181,8 +228,6 @@ ENDPROC(am33xx_resume_from_deep_sleep) * Local variables */ .align -resume_addr: - .word cpu_resume - PAGE_OFFSET + 0x80000000 kernel_flush: .word v7_flush_dcache_all virt_mpu_clkctrl: @@ -205,6 +250,9 @@ ENTRY(am33xx_pm_sram) .word am33xx_emif_sram_table .word am33xx_pm_ro_sram_data +resume_addr: +.word cpu_resume - PAGE_OFFSET + 0x80000000 + .align 3 ENTRY(am33xx_pm_ro_sram_data) .space AMX3_PM_RO_SRAM_DATA_SIZE diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S index 8903814a6677..5b9343b58fc7 100644 --- a/arch/arm/mach-omap2/sleep43xx.S +++ b/arch/arm/mach-omap2/sleep43xx.S @@ -9,7 +9,7 @@ #include <generated/ti-pm-asm-offsets.h> #include <linux/linkage.h> #include <linux/ti-emif-sram.h> - +#include <linux/platform_data/pm33xx.h> #include <asm/assembler.h> #include <asm/hardware/cache-l2x0.h> #include <asm/memory.h> @@ -22,6 +22,9 @@ #include "prm33xx.h" #include "prcm43xx.h" +/* replicated define because linux/bitops.h cannot be included in assembly */ +#define BIT(nr) (1 << (nr)) + #define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000 #define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003 #define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002 @@ -45,12 +48,25 @@ AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET) #define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030 +#define RTC_SECONDS_REG 0x0 +#define RTC_PMIC_REG 0x98 +#define RTC_PMIC_POWER_EN BIT(16) +#define RTC_PMIC_EXT_WAKEUP_STS BIT(12) +#define RTC_PMIC_EXT_WAKEUP_POL BIT(4) +#define RTC_PMIC_EXT_WAKEUP_EN BIT(0) + .arm .align 3 ENTRY(am43xx_do_wfi) stmfd sp!, {r4 - r11, lr} @ save registers on stack + /* Save wfi_flags arg to data space */ + mov r4, r0 + adr r3, am43xx_pm_ro_sram_data + ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] + str r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET] + #ifdef CONFIG_CACHE_L2X0 /* Retrieve l2 cache virt address BEFORE we shut off EMIF */ ldr r1, get_l2cache_base @@ -58,6 +74,10 @@ ENTRY(am43xx_do_wfi) mov r8, r0 #endif + /* Only flush cache is we know we are losing MPU context */ + tst r4, #WFI_FLAG_FLUSH_CACHE + beq cache_skip_flush + /* * Flush all data from the L1 and L2 data cache before disabling * SCTLR.C bit. @@ -128,13 +148,47 @@ sync: bne sync #endif + /* Restore wfi_flags */ + adr r3, am43xx_pm_ro_sram_data + ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] + ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET] + +cache_skip_flush: + /* + * If we are trying to enter RTC+DDR mode we must perform + * a read from the rtc address space to ensure translation + * presence in the TLB to avoid page table walk after DDR + * is unavailable. + */ + tst r4, #WFI_FLAG_RTC_ONLY + beq skip_rtc_va_refresh + + adr r3, am43xx_pm_ro_sram_data + ldr r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET] + ldr r0, [r1] + +skip_rtc_va_refresh: + /* Check if we want self refresh */ + tst r4, #WFI_FLAG_SELF_REFRESH + beq emif_skip_enter_sr + adr r9, am43xx_emif_sram_table ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET] blx r3 +emif_skip_enter_sr: + /* Only necessary if PER is losing context */ + tst r4, #WFI_FLAG_SAVE_EMIF + beq emif_skip_save + ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET] - blx r3 + blx r3 + +emif_skip_save: + /* Only can disable EMIF if we have entered self refresh */ + tst r4, #WFI_FLAG_SELF_REFRESH + beq emif_skip_disable /* Disable EMIF */ ldr r1, am43xx_virt_emif_clkctrl @@ -148,6 +202,38 @@ wait_emif_disable: cmp r2, r3 bne wait_emif_disable +emif_skip_disable: + tst r4, #WFI_FLAG_RTC_ONLY + beq skip_rtc_only + + adr r3, am43xx_pm_ro_sram_data + ldr r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET] + + ldr r0, [r1, #RTC_PMIC_REG] + orr r0, r0, #RTC_PMIC_POWER_EN + orr r0, r0, #RTC_PMIC_EXT_WAKEUP_STS + orr r0, r0, #RTC_PMIC_EXT_WAKEUP_EN + orr r0, r0, #RTC_PMIC_EXT_WAKEUP_POL + str r0, [r1, #RTC_PMIC_REG] + ldr r0, [r1, #RTC_PMIC_REG] + /* Wait for 2 seconds to lose power */ + mov r3, #2 + ldr r2, [r1, #RTC_SECONDS_REG] +rtc_loop: + ldr r0, [r1, #RTC_SECONDS_REG] + cmp r0, r2 + beq rtc_loop + mov r2, r0 + subs r3, r3, #1 + bne rtc_loop + + b re_enable_emif + +skip_rtc_only: + + tst r4, #WFI_FLAG_WAKE_M3 + beq wkup_m3_skip + /* * For the MPU WFI to be registered as an interrupt * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set @@ -165,6 +251,7 @@ wait_emif_disable: mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP str r2, [r1] +wkup_m3_skip: /* * Execute a barrier instruction to ensure that all cache, * TLB and branch predictor maintenance operations issued @@ -209,6 +296,7 @@ wait_emif_disable: mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE str r2, [r1] +re_enable_emif: /* Re-enable EMIF */ ldr r1, am43xx_virt_emif_clkctrl mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE @@ -218,6 +306,9 @@ wait_emif_enable: cmp r2, r3 bne wait_emif_enable + tst r4, #WFI_FLAG_FLUSH_CACHE + beq cache_skip_restore + /* * Set SCTLR.C bit to allow data cache allocation */ @@ -226,9 +317,16 @@ wait_emif_enable: mcr p15, 0, r0, c1, c0, 0 isb - ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET] - blx r1 +cache_skip_restore: + /* Only necessary if PER is losing context */ + tst r4, #WFI_FLAG_SELF_REFRESH + beq emif_skip_exit_sr_abt + + adr r9, am43xx_emif_sram_table + ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET] + blx r1 +emif_skip_exit_sr_abt: /* Let the suspend code know about the abort */ mov r0, #1 ldmfd sp!, {r4 - r11, pc} @ restore regs and return @@ -333,8 +431,6 @@ ENDPROC(am43xx_resume_from_deep_sleep) * Local variables */ .align -resume_addr: - .word cpu_resume - PAGE_OFFSET + 0x80000000 kernel_flush: .word v7_flush_dcache_all ddr_start: @@ -381,6 +477,8 @@ ENTRY(am43xx_pm_sram) .word am43xx_emif_sram_table .word am43xx_pm_ro_sram_data +resume_addr: + .word cpu_resume - PAGE_OFFSET + 0x80000000 .align 3 ENTRY(am43xx_pm_ro_sram_data) diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 5a16ea74e28a..a24783a03827 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -3,6 +3,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/clkdev.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/spi/pxa2xx_spi.h> @@ -477,6 +478,18 @@ struct platform_device pxa_device_ac97 = { void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops) { + int ret; + + ret = clk_add_alias("ac97_clk", "pxa2xx-ac97:0", "AC97CLK", + &pxa_device_ac97.dev); + if (ret) + pr_err("PXA AC97 clock1 alias error: %d\n", ret); + + ret = clk_add_alias("ac97_clk", "pxa2xx-ac97:1", "AC97CLK", + &pxa_device_ac97.dev); + if (ret) + pr_err("PXA AC97 clock2 alias error: %d\n", ret); + pxa_register_device(&pxa_device_ac97, ops); } diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index e2e7f247a645..b79b757fdd41 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -54,6 +54,7 @@ #include "devices.h" #include "generic.h" +#include "udc.h" /* Physical address space information */ @@ -594,6 +595,8 @@ static struct platform_device gpio_vbus = { }, }; +static struct pxa2xx_udc_mach_info hx4700_udc_info; + /* * Touchscreen - TSC2046 connected to SSP2 */ @@ -891,6 +894,7 @@ static void __init hx4700_init(void) gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 1); mdelay(10); + pxa_set_udc_info(&hx4700_udc_info); regulator_has_full_constraints(); } diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 9b6c7ea45a40..04dc78d0809f 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -677,14 +677,12 @@ MIO_SIMPLE_DEV(mioa701_led, "leds-gpio", &gpio_led_info) MIO_SIMPLE_DEV(pxa2xx_pcm, "pxa2xx-pcm", NULL) MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL) MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL) -MIO_SIMPLE_DEV(wm9713_acodec, "wm9713-codec", NULL); MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", &gpio_vbus_data); static struct platform_device *devices[] __initdata = { &mioa701_gpio_keys, &mioa701_backlight, &mioa701_led, - &wm9713_acodec, &pxa2xx_pcm, &mioa701_sound, &power_dev, diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index d69de312d8d9..52e70a5c1281 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -47,16 +47,6 @@ int wm9713_irq; int lcd_id; int lcd_orientation; -struct platform_device pxa_device_wm9713_audio = { - .name = "wm9713-codec", - .id = -1, -}; - -static void __init zylonite_init_wm9713_audio(void) -{ - platform_device_register(&pxa_device_wm9713_audio); -} - static struct resource smc91x_resources[] = { [0] = { .start = ZYLONITE_ETH_PHYS + 0x300, @@ -428,7 +418,6 @@ static void __init zylonite_init(void) zylonite_init_nand(); zylonite_init_leds(); zylonite_init_ohci(); - zylonite_init_wm9713_audio(); } MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h index b6b32724ace8..4ff83f956cfb 100644 --- a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h +++ b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h @@ -6,7 +6,7 @@ */ #ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H -#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__ +#define __ARCH_ARM_MACH_S3C24XX_S3C2412_H __FILE__ #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) #define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 0b67254eabb2..aeb2eed08598 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -15,6 +15,7 @@ config ARCH_RCAR_GEN1 config ARCH_RCAR_GEN2 bool + select HAVE_ARM_ARCH_TIMER select PM select PM_GENERIC_DOMAINS select RENESAS_IRQC @@ -58,6 +59,7 @@ config ARCH_R8A73A4 bool "R-Mobile APE6 (R8A73A40)" select ARCH_RMOBILE select ARM_ERRATA_798181 if SMP + select HAVE_ARM_ARCH_TIMER select RENESAS_IRQC config ARCH_R8A7740 diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 1939f521579c..b33dc59d8698 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -11,9 +11,7 @@ obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o -obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o -obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o -obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o +obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o @@ -23,17 +21,15 @@ cpu-y := platsmp.o headsmp.o # Shared SoC family objects obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y) CFLAGS_setup-rcar-gen2.o += -march=armv7-a -obj-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o # SMP objects smp-y := $(cpu-y) +smp-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o -smp-$(CONFIG_ARCH_R8A7790) += smp-r8a7790.o -smp-$(CONFIG_ARCH_R8A7791) += smp-r8a7791.o smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o # PM objects diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h index 2109f123bdfb..3ac4b36b5c2b 100644 --- a/arch/arm/mach-shmobile/common.h +++ b/arch/arm/mach-shmobile/common.h @@ -15,7 +15,6 @@ extern void shmobile_smp_sleep(void); extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg); extern bool shmobile_smp_cpu_can_disable(unsigned int cpu); -extern bool shmobile_smp_init_fallback_ops(void); extern void shmobile_boot_apmu(void); extern void shmobile_boot_scu(void); extern void shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys, diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S index d49ab194766a..fabe9cadd12e 100644 --- a/arch/arm/mach-shmobile/headsmp-apmu.S +++ b/arch/arm/mach-shmobile/headsmp-apmu.S @@ -1,19 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * SMP support for APMU based systems with Cortex A7/A15 * * Copyright (C) 2014 Renesas Electronics Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/linkage.h> #include <asm/assembler.h> -#ifdef CONFIG_SMP ENTRY(shmobile_boot_apmu) bl secure_cntvoff_init b secondary_startup ENDPROC(shmobile_boot_apmu) -#endif diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index ba732effc90b..96330ef25641 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SMP support for SoCs with APMU * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/cpu_pm.h> #include <linux/delay.h> @@ -23,7 +20,6 @@ #include <asm/smp_plat.h> #include <asm/suspend.h> #include "common.h" -#include "platsmp-apmu.h" #include "rcar-gen2.h" static struct { @@ -87,6 +83,104 @@ static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu) return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL; } +#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND) +/* nicked from arch/arm/mach-exynos/hotplug.c */ +static inline void cpu_enter_lowpower_a15(void) +{ + unsigned int v; + + asm volatile( + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "Ir" (CR_C) + : "cc"); + + flush_cache_louis(); + + asm volatile( + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (0x40) + : "cc"); + + isb(); + dsb(); +} + +static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu) +{ + + /* Select next sleep mode using the APMU */ + apmu_wrap(cpu, apmu_power_off); + + /* Do ARM specific CPU shutdown */ + cpu_enter_lowpower_a15(); +} +#endif + +#if defined(CONFIG_HOTPLUG_CPU) +static void shmobile_smp_apmu_cpu_die(unsigned int cpu) +{ + /* For this particular CPU deregister boot vector */ + shmobile_smp_hook(cpu, 0, 0); + + /* Shutdown CPU core */ + shmobile_smp_apmu_cpu_shutdown(cpu); + + /* jump to shared mach-shmobile sleep / reset code */ + shmobile_smp_sleep(); +} + +static int shmobile_smp_apmu_cpu_kill(unsigned int cpu) +{ + return apmu_wrap(cpu, apmu_power_off_poll); +} +#endif + +#if defined(CONFIG_SUSPEND) +static int shmobile_smp_apmu_do_suspend(unsigned long cpu) +{ + shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0); + shmobile_smp_apmu_cpu_shutdown(cpu); + cpu_do_idle(); /* WFI selects Core Standby */ + return 1; +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile("mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + +static int shmobile_smp_apmu_enter_suspend(suspend_state_t state) +{ + cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend); + cpu_leave_lowpower(); + return 0; +} + +void __init shmobile_smp_apmu_suspend_init(void) +{ + shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend; +} +#endif + #ifdef CONFIG_SMP static void apmu_init_cpu(struct resource *res, int cpu, int bit) { @@ -106,38 +200,6 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit) writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS); } -static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit), - struct rcar_apmu_config *apmu_config, int num) -{ - int id; - int k; - int bit, index; - bool is_allowed; - - for (k = 0; k < num; k++) { - /* only enable the cluster that includes the boot CPU */ - is_allowed = false; - for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { - id = apmu_config[k].cpus[bit]; - if (id >= 0) { - if (id == cpu_logical_map(0)) - is_allowed = true; - } - } - if (!is_allowed) - continue; - - for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { - id = apmu_config[k].cpus[bit]; - if (id >= 0) { - index = get_logical_index(id); - if (index >= 0) - fn(&apmu_config[k].iomem, index, bit); - } - } - } -} - static const struct of_device_id apmu_ids[] = { { .compatible = "renesas,apmu" }, { /*sentinel*/ } @@ -194,15 +256,8 @@ static void __init shmobile_smp_apmu_setup_boot(void) shmobile_boot_fn_gen2 = shmobile_boot_fn; } -void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, - struct rcar_apmu_config *apmu_config, - int num) -{ - shmobile_smp_apmu_setup_boot(); - apmu_parse_cfg(apmu_init_cpu, apmu_config, num); -} - -int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int shmobile_smp_apmu_boot_secondary(unsigned int cpu, + struct task_struct *idle) { /* For this particular CPU register boot vector */ shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0); @@ -229,101 +284,3 @@ static struct smp_operations apmu_smp_ops __initdata = { CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops); #endif /* CONFIG_SMP */ - -#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND) -/* nicked from arch/arm/mach-exynos/hotplug.c */ -static inline void cpu_enter_lowpower_a15(void) -{ - unsigned int v; - - asm volatile( - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); - - flush_cache_louis(); - - asm volatile( - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (0x40) - : "cc"); - - isb(); - dsb(); -} - -static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu) -{ - - /* Select next sleep mode using the APMU */ - apmu_wrap(cpu, apmu_power_off); - - /* Do ARM specific CPU shutdown */ - cpu_enter_lowpower_a15(); -} - -static inline void cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile("mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C), "Ir" (0x40) - : "cc"); -} -#endif - -#if defined(CONFIG_HOTPLUG_CPU) -void shmobile_smp_apmu_cpu_die(unsigned int cpu) -{ - /* For this particular CPU deregister boot vector */ - shmobile_smp_hook(cpu, 0, 0); - - /* Shutdown CPU core */ - shmobile_smp_apmu_cpu_shutdown(cpu); - - /* jump to shared mach-shmobile sleep / reset code */ - shmobile_smp_sleep(); -} - -int shmobile_smp_apmu_cpu_kill(unsigned int cpu) -{ - return apmu_wrap(cpu, apmu_power_off_poll); -} -#endif - -#if defined(CONFIG_SUSPEND) -static int shmobile_smp_apmu_do_suspend(unsigned long cpu) -{ - shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0); - shmobile_smp_apmu_cpu_shutdown(cpu); - cpu_do_idle(); /* WFI selects Core Standby */ - return 1; -} - -static int shmobile_smp_apmu_enter_suspend(suspend_state_t state) -{ - cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend); - cpu_leave_lowpower(); - return 0; -} - -void __init shmobile_smp_apmu_suspend_init(void) -{ - shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend; -} -#endif diff --git a/arch/arm/mach-shmobile/platsmp-apmu.h b/arch/arm/mach-shmobile/platsmp-apmu.h deleted file mode 100644 index 76512c9a2545..000000000000 --- a/arch/arm/mach-shmobile/platsmp-apmu.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * rmobile apmu definition - * - * Copyright (C) 2014 Renesas Electronics Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PLATSMP_APMU_H -#define PLATSMP_APMU_H - -struct rcar_apmu_config { - struct resource iomem; - int cpus[4]; -}; - -extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, - struct rcar_apmu_config *apmu_config, - int num); -extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu, - struct task_struct *idle); -extern void shmobile_smp_apmu_cpu_die(unsigned int cpu); -extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu); - -#endif /* PLATSMP_APMU_H */ diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index 02e21bceb085..b23378f3d7e1 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -36,12 +36,3 @@ bool shmobile_smp_cpu_can_disable(unsigned int cpu) return true; /* Hotplug of any CPU is supported */ } #endif - -bool __init shmobile_smp_init_fallback_ops(void) -{ - /* fallback on PSCI/smp_ops if no other DT based method is detected */ - if (!IS_ENABLED(CONFIG_SMP)) - return false; - - return platform_can_secondary_boot() ? true : false; -} diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c deleted file mode 100644 index 5c9a93f5e650..000000000000 --- a/arch/arm/mach-shmobile/pm-r8a7779.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * r8a7779 Power management support - * - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Magnus Damm - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include <linux/soc/renesas/rcar-sysc.h> - -#include <asm/io.h> - -#include "r8a7779.h" - -/* SYSC */ -#define SYSCIER 0x0c -#define SYSCIMR 0x10 - -#if defined(CONFIG_PM) || defined(CONFIG_SMP) - -static void __init r8a7779_sysc_init(void) -{ - rcar_sysc_init(0xffd85000, 0x0131000e); -} - -#else /* CONFIG_PM || CONFIG_SMP */ - -static inline void r8a7779_sysc_init(void) {} - -#endif /* CONFIG_PM || CONFIG_SMP */ - -void __init r8a7779_pm_init(void) -{ - static int once; - - if (!once++) - r8a7779_sysc_init(); -} diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c index 5a798b406af0..345af3ebcc3a 100644 --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c @@ -15,7 +15,6 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/smp.h> -#include <linux/soc/renesas/rcar-sysc.h> #include <asm/io.h> #include <asm/cputype.h> #include "common.h" @@ -46,23 +45,6 @@ static inline u32 phys_to_sbar(phys_addr_t addr) return (addr >> 8) & 0xfffffc00; } -/* SYSC */ -#define SYSCIER 0x0c -#define SYSCIMR 0x10 - -#if defined(CONFIG_SMP) - -static void __init rcar_gen2_sysc_init(u32 syscier) -{ - rcar_sysc_init(0xe6180000, syscier); -} - -#else /* CONFIG_SMP */ - -static inline void rcar_gen2_sysc_init(u32 syscier) {} - -#endif /* CONFIG_SMP */ - void __init rcar_gen2_pm_init(void) { void __iomem *p; @@ -72,7 +54,6 @@ void __init rcar_gen2_pm_init(void) bool has_a7 = false; bool has_a15 = false; struct resource res; - u32 syscier = 0; int error; if (once++) @@ -89,11 +70,6 @@ void __init rcar_gen2_pm_init(void) has_a7 = true; } - if (of_machine_is_compatible("renesas,r8a7790")) - syscier = 0x013111ef; - else if (of_machine_is_compatible("renesas,r8a7791")) - syscier = 0x00111003; - np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram"); if (!np) { /* No smp-sram in DT, fall back to hardcoded address */ @@ -155,6 +131,5 @@ map: } iounmap(p); - rcar_gen2_sysc_init(syscier); shmobile_smp_apmu_suspend_init(); } diff --git a/arch/arm/mach-shmobile/r8a7779.h b/arch/arm/mach-shmobile/r8a7779.h index 30668aa6acc3..ca9db8fde2f7 100644 --- a/arch/arm/mach-shmobile/r8a7779.h +++ b/arch/arm/mach-shmobile/r8a7779.h @@ -2,8 +2,6 @@ #ifndef __ASM_R8A7779_H__ #define __ASM_R8A7779_H__ -extern void r8a7779_pm_init(void); - extern const struct smp_operations r8a7779_smp_ops; #endif /* __ASM_R8A7779_H__ */ diff --git a/arch/arm/mach-shmobile/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h deleted file mode 100644 index 669c8cd09e07..000000000000 --- a/arch/arm/mach-shmobile/r8a7790.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_R8A7790_H__ -#define __ASM_R8A7790_H__ - -extern const struct smp_operations r8a7790_smp_ops; - -#endif /* __ASM_R8A7790_H__ */ diff --git a/arch/arm/mach-shmobile/r8a7791.h b/arch/arm/mach-shmobile/r8a7791.h deleted file mode 100644 index 8c794aace938..000000000000 --- a/arch/arm/mach-shmobile/r8a7791.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_R8A7791_H__ -#define __ASM_R8A7791_H__ - -extern const struct smp_operations r8a7791_smp_ops; - -#endif /* __ASM_R8A7791_H__ */ diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c index 93f628acfd94..21ebc7678ffd 100644 --- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c +++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * R-Car Generation 2 da9063/da9210 regulator quirk * @@ -16,15 +17,6 @@ * been initialized, but before the i2c slave drivers are initialized. * * Copyright (C) 2015 Glider bvba - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/device.h> diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index 3c99aaf65325..a328d2f52678 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Emma Mobile EV2 processor support * * Copyright (C) 2012 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/init.h> diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index 319ca9508ec6..14867226f8f4 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * r7s72100 processor support * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 20173c4f415d..23a29a0ea9c9 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * r8a73a4 processor support * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/init.h> @@ -26,7 +18,6 @@ static const char *const r8a73a4_boards_compat_dt[] __initconst = { }; DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") - .init_early = shmobile_init_delay, .init_late = shmobile_init_late, .dt_compat = r8a73a4_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 3849eef0d3a7..787d039b5a07 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * R8A7740 processor support * * Copyright (C) 2011 Renesas Solutions Corp. * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/init.h> diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 7fa4a0b5f654..ce51794f64c7 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -1,18 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * r8a7778 processor support * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> * Copyright (C) 2013 Cogent Embedded, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/io.h> diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 0686112f2435..d589326099e0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -1,18 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * r8a7779 processor support * * Copyright (C) 2011, 2013 Renesas Solutions Corp. * Copyright (C) 2011 Magnus Damm * Copyright (C) 2013 Cogent Embedded, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/init.h> #include <linux/irq.h> diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c deleted file mode 100644 index 78d3e859bd64..000000000000 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * r8a7790 processor support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/init.h> - -#include <asm/mach/arch.h> - -#include "common.h" -#include "r8a7790.h" -#include "rcar-gen2.h" - -static const char * const r8a7790_boards_compat_dt[] __initconst = { - "renesas,r8a7790", - NULL, -}; - -DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") - .smp_init = smp_init_ops(shmobile_smp_init_fallback_ops), - .smp = smp_ops(r8a7790_smp_ops), - .init_early = shmobile_init_delay, - .init_time = rcar_gen2_timer_init, - .init_late = shmobile_init_late, - .reserve = rcar_gen2_reserve, - .dt_compat = r8a7790_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c deleted file mode 100644 index 26e2d181a190..000000000000 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * r8a7791 processor support - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/init.h> - -#include <asm/mach/arch.h> - -#include "common.h" -#include "r8a7791.h" -#include "rcar-gen2.h" - -static const char *const r8a7791_boards_compat_dt[] __initconst = { - "renesas,r8a7791", - NULL, -}; - -DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)") - .smp_init = smp_init_ops(shmobile_smp_init_fallback_ops), - .smp = smp_ops(r8a7791_smp_ops), - .init_early = shmobile_init_delay, - .init_time = rcar_gen2_timer_init, - .init_late = shmobile_init_late, - .reserve = rcar_gen2_reserve, - .dt_compat = r8a7791_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 88fdc1801d90..013acc97795c 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -1,18 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * R-Car Generation 2 support * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Magnus Damm * Copyright (C) 2014 Ulrich Hecht - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/clk-provider.h> @@ -67,7 +59,6 @@ static unsigned int __init get_extal_freq(void) void __init rcar_gen2_timer_init(void) { -#ifdef CONFIG_ARM_ARCH_TIMER void __iomem *base; u32 freq; @@ -109,7 +100,6 @@ void __init rcar_gen2_timer_init(void) } iounmap(base); -#endif /* CONFIG_ARM_ARCH_TIMER */ of_clk_init(NULL); timer_probe(); @@ -186,10 +176,8 @@ void __init rcar_gen2_reserve(void) } static const char * const rcar_gen2_boards_compat_dt[] __initconst = { - /* - * R8A7790 and R8A7791 can't be handled here as long as they need SMP - * initialization fallback. - */ + "renesas,r8a7790", + "renesas,r8a7791", "renesas,r8a7792", "renesas,r8a7793", "renesas,r8a7794", @@ -197,7 +185,6 @@ static const char * const rcar_gen2_boards_compat_dt[] __initconst = { }; DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)") - .init_early = shmobile_init_delay, .init_late = shmobile_init_late, .init_time = rcar_gen2_timer_init, .reserve = rcar_gen2_reserve, @@ -212,7 +199,6 @@ static const char * const rz_g1_boards_compat_dt[] __initconst = { }; DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)") - .init_early = shmobile_init_delay, .init_late = shmobile_init_late, .init_time = rcar_gen2_timer_init, .reserve = rcar_gen2_reserve, diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index a25ff188e403..cc08aa752244 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -1,18 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * sh73a0 processor support * * Copyright (C) 2010 Takashi Yoshii * Copyright (C) 2010 Magnus Damm * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/init.h> diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 3a732199cf5e..3853ecea44ca 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SMP support for Emma Mobile EV2 * * Copyright (C) 2012 Renesas Solutions Corp. * Copyright (C) 2012 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/init.h> diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index c6951ee24588..0ed73b650c14 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SMP support for R-Mobile / SH-Mobile - r8a7779 portion * * Copyright (C) 2011 Renesas Solutions Corp. * Copyright (C) 2011 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/init.h> @@ -31,59 +23,13 @@ #define AVECR IOMEM(0xfe700040) #define R8A7779_SCU_BASE 0xf0000000 -static const struct rcar_sysc_ch r8a7779_ch_cpu1 = { - .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ - .chan_bit = 1, /* ARM1 */ - .isr_bit = 1, /* ARM1 */ -}; - -static const struct rcar_sysc_ch r8a7779_ch_cpu2 = { - .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ - .chan_bit = 2, /* ARM2 */ - .isr_bit = 2, /* ARM2 */ -}; - -static const struct rcar_sysc_ch r8a7779_ch_cpu3 = { - .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ - .chan_bit = 3, /* ARM3 */ - .isr_bit = 3, /* ARM3 */ -}; - -static const struct rcar_sysc_ch * const r8a7779_ch_cpu[4] = { - [1] = &r8a7779_ch_cpu1, - [2] = &r8a7779_ch_cpu2, - [3] = &r8a7779_ch_cpu3, -}; - -static int r8a7779_platform_cpu_kill(unsigned int cpu) +static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { - const struct rcar_sysc_ch *ch = NULL; int ret = -EIO; cpu = cpu_logical_map(cpu); - - if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) - ch = r8a7779_ch_cpu[cpu]; - - if (ch) - ret = rcar_sysc_power_down(ch); - - return ret ? ret : 1; -} - -static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - const struct rcar_sysc_ch *ch = NULL; - unsigned int lcpu = cpu_logical_map(cpu); - int ret; - - if (lcpu < ARRAY_SIZE(r8a7779_ch_cpu)) - ch = r8a7779_ch_cpu[lcpu]; - - if (ch) - ret = rcar_sysc_power_up(ch); - else - ret = -EIO; + if (cpu) + ret = rcar_sysc_power_up_cpu(cpu); return ret; } @@ -95,16 +41,20 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) /* setup r8a7779 specific SCU bits */ shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus); +} - r8a7779_pm_init(); +#ifdef CONFIG_HOTPLUG_CPU +static int r8a7779_platform_cpu_kill(unsigned int cpu) +{ + int ret = -EIO; - /* power off secondary CPUs */ - r8a7779_platform_cpu_kill(1); - r8a7779_platform_cpu_kill(2); - r8a7779_platform_cpu_kill(3); + cpu = cpu_logical_map(cpu); + if (cpu) + ret = rcar_sysc_power_down_cpu(cpu); + + return ret ? ret : 1; } -#ifdef CONFIG_HOTPLUG_CPU static int r8a7779_cpu_kill(unsigned int cpu) { if (shmobile_smp_scu_cpu_kill(cpu)) diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c deleted file mode 100644 index 28f26d5362d8..000000000000 --- a/arch/arm/mach-shmobile/smp-r8a7790.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * SMP support for r8a7790 - * - * Copyright (C) 2012-2013 Renesas Solutions Corp. - * Copyright (C) 2012 Takashi Yoshii <takashi.yoshii.ze@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/io.h> -#include <linux/soc/renesas/rcar-sysc.h> - -#include <asm/smp_plat.h> - -#include "common.h" -#include "platsmp-apmu.h" -#include "rcar-gen2.h" -#include "r8a7790.h" - -static const struct rcar_sysc_ch r8a7790_ca15_scu = { - .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */ - .isr_bit = 12, /* CA15-SCU */ -}; - -static const struct rcar_sysc_ch r8a7790_ca7_scu = { - .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */ - .isr_bit = 21, /* CA7-SCU */ -}; - -static struct rcar_apmu_config r8a7790_apmu_config[] = { - { - .iomem = DEFINE_RES_MEM(0xe6152000, 0x188), - .cpus = { 0, 1, 2, 3 }, - }, - { - .iomem = DEFINE_RES_MEM(0xe6151000, 0x188), - .cpus = { 0x100, 0x0101, 0x102, 0x103 }, - } -}; - -static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus) -{ - /* let APMU code install data related to shmobile_boot_vector */ - shmobile_smp_apmu_prepare_cpus(max_cpus, - r8a7790_apmu_config, - ARRAY_SIZE(r8a7790_apmu_config)); - - /* turn on power to SCU */ - rcar_gen2_pm_init(); - rcar_sysc_power_up(&r8a7790_ca15_scu); - rcar_sysc_power_up(&r8a7790_ca7_scu); -} - -const struct smp_operations r8a7790_smp_ops __initconst = { - .smp_prepare_cpus = r8a7790_smp_prepare_cpus, - .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_can_disable = shmobile_smp_cpu_can_disable, - .cpu_die = shmobile_smp_apmu_cpu_die, - .cpu_kill = shmobile_smp_apmu_cpu_kill, -#endif -}; diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c deleted file mode 100644 index 2948c22cfc53..000000000000 --- a/arch/arm/mach-shmobile/smp-r8a7791.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * SMP support for r8a7791 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/io.h> - -#include <asm/smp_plat.h> - -#include "common.h" -#include "platsmp-apmu.h" -#include "r8a7791.h" -#include "rcar-gen2.h" - -static struct rcar_apmu_config r8a7791_apmu_config[] = { - { - .iomem = DEFINE_RES_MEM(0xe6152000, 0x188), - .cpus = { 0, 1 }, - } -}; - -static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus) -{ - /* let APMU code install data related to shmobile_boot_vector */ - shmobile_smp_apmu_prepare_cpus(max_cpus, - r8a7791_apmu_config, - ARRAY_SIZE(r8a7791_apmu_config)); - - rcar_gen2_pm_init(); -} - -const struct smp_operations r8a7791_smp_ops __initconst = { - .smp_prepare_cpus = r8a7791_smp_prepare_cpus, - .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_can_disable = shmobile_smp_cpu_can_disable, - .cpu_die = shmobile_smp_apmu_cpu_die, - .cpu_kill = shmobile_smp_apmu_cpu_kill, -#endif -}; diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 6196a6380385..828e8aea037e 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -32,14 +32,6 @@ void __init shmobile_init_delay(void) for_each_child_of_node(cpus, np) { u32 freq; - if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER) && - (of_device_is_compatible(np, "arm,cortex-a7") || - of_device_is_compatible(np, "arm,cortex-a15"))) { - of_node_put(np); - of_node_put(cpus); - return; - } - if (!of_property_read_u32(np, "clock-frequency", &freq)) max_freq = max(max_freq, freq); } diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 779235a9147d..e661d2626675 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -9,6 +9,7 @@ config ARCH_UNIPHIER select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP select PINCTRL + select RESET_CONTROLLER help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index d5aeac351fc3..35f2e6e1be23 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -71,6 +71,13 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_K3 + bool "Texas Instruments Inc. K3 multicore SoC architecture" + select PM_GENERIC_DOMAINS if PM + help + This enables support for Texas Instruments' K3 multicore SoC + architecture. + config ARCH_LAYERSCAPE bool "ARMv8 based Freescale Layerscape SoC family" select EDAC_SUPPORT @@ -261,6 +268,7 @@ config ARCH_UNIPHIER bool "Socionext UniPhier SoC Family" select ARCH_HAS_RESET_CONTROLLER select PINCTRL + select RESET_CONTROLLER help This enables support for Socionext UniPhier SoC family. diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 3543bc324553..4690364d584b 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -23,5 +23,6 @@ subdir-y += rockchip subdir-y += socionext subdir-y += sprd subdir-y += synaptics +subdir-y += ti subdir-y += xilinx subdir-y += zte diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index c31f90a49481..9ffa7a038791 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -1,9 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-amarula-relic.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts new file mode 100644 index 000000000000..eac4793c8502 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Amarula A64-Relic"; + compatible = "amarula,a64-relic", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dcdc1>; + /* + * Schematic shows both dldo4 and eldo1 connected for vcc-io-wifi, but + * dldo4 connection shows DNP(Do Not Populate) and eldo1 connected with + * 0Ohm register to vcc-io-wifi so eldo1 is used. + */ + vqmmc-supply = <®_eldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ + }; +}; + +#include "axp803.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi-dsi-sensor"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "dovdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_eldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus-supply = <®_drivevbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 0716b1441187..094cfed13df9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -296,6 +296,10 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index e2dce48fa29a..98dbff19f5cc 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -195,6 +195,10 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index 3b3081b10ecb..3f531393eaee 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -214,6 +214,10 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index bf42690a3361..1221764f5719 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -191,6 +191,10 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index a75825798a71..1b9b92e541d2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -229,6 +229,10 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + /* On Euler connector */ &spdif { status = "disabled"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts new file mode 100644 index 000000000000..897e60cbe38d --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz> + * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com> + * + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Pinebook"; + compatible = "pine64,pinebook", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + ethernet0 = &rtl8723cs; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 0>; + brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; + default-brightness-level = <2>; + enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + + framebuffer-lcd { + panel-supply = <®_dc1sw>; + dvdd25-supply = <®_dldo2>; + dvdd12-supply = <®_fldo1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + lid_switch { + label = "Lid Switch"; + gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + wakeup-source; + }; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; +}; + +&ehci0 { + phys = <&usbphy 0>; + phy-names = "usb"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo4>; + vqmmc-supply = <®_eldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723cs: wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_eldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + status = "okay"; +}; + +&ohci0 { + phys = <&usbphy 0>; + phy-names = "usb"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* The ANX6345 eDP-bridge is on r_i2c */ +&r_i2c { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins_a>; + status = "okay"; +}; + +#include "axp803.dtsi" + +®_aldo1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-csi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi"; +}; + +®_dldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-edp"; +}; + +®_dldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_eldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd-1v8-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; + +&usbphy { + usb0_vbus-supply = <®_ldo_io0>; + usb1_vbus-supply = <®_ldo_io0>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index abe179de35d7..c21f2331add6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -134,6 +134,10 @@ regulator-name = "vcc-wifi"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi index 43418bd881d8..6723b8695e0b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi @@ -45,6 +45,8 @@ #include "sun50i-a64.dtsi" +#include <dt-bindings/gpio/gpio.h> + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -52,6 +54,7 @@ non-removable; disable-wp; bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; @@ -66,6 +69,18 @@ }; }; +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + #include "axp803.dtsi" ®_aldo2 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index d9baab3dc96b..81f8e0098699 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -38,6 +38,7 @@ gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ linux,input-type = <EV_SW>; linux,code = <SW_LID>; + wakeup-source; }; }; @@ -210,7 +211,7 @@ ®_dldo3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-name = "eDP12"; + regulator-name = "vdd-edp"; }; ®_dldo4 { @@ -253,6 +254,10 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1b2ef28c42bd..d3daf90a8715 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -43,9 +43,12 @@ */ #include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/sun50i-a64-ccu.h> +#include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/reset/sun8i-r-ccu.h> / { interrupt-parent = <&gic>; @@ -57,17 +60,21 @@ #size-cells = <1>; ranges; -/* - * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU. - * However there is no support for this clock on A64 yet, so we depend - * on the upstream clocks here to keep them (and thus CLK_MIXER0) up. - */ simplefb_lcd: framebuffer-lcd { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "mixer0-lcd0"; clocks = <&ccu CLK_TCON0>, - <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; + <&display_clocks CLK_MIXER0>; + status = "disabled"; + }; + + simplefb_hdmi: framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-hdmi"; + clocks = <&display_clocks CLK_MIXER1>, + <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; status = "disabled"; }; }; @@ -168,10 +175,46 @@ #size-cells = <1>; ranges; + de2@1000000 { + compatible = "allwinner,sun50i-a64-de2"; + reg = <0x1000000 0x400000>; + allwinner,sram = <&de2_sram 1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000000 0x400000>; + + display_clocks: clock@0 { + compatible = "allwinner,sun50i-a64-de2-clk"; + reg = <0x0 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + syscon: syscon@1c00000 { - compatible = "allwinner,sun50i-a64-system-controller", - "syscon"; + compatible = "allwinner,sun50i-a64-system-control"; reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@18000 { + compatible = "mmio-sram"; + reg = <0x00018000 0x28000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00018000 0x28000>; + + de2_sram: sram-section@0 { + compatible = "allwinner,sun50i-a64-sram-c"; + reg = <0x0000 0x28000>; + }; + }; }; dma: dma-controller@1c02000 { @@ -364,6 +407,11 @@ bias-pull-up; }; + pwm_pin: pwm_pin { + pins = "PD22"; + function = "pwm"; + }; + rmii_pins: rmii_pins { pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; @@ -608,8 +656,6 @@ clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; mdio: mdio { compatible = "snps,dwmac-mdio"; @@ -629,11 +675,25 @@ #interrupt-cells = <3>; }; + pwm: pwm@1c21400 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01c21400 0x400>; + clocks = <&osc24M>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; + clocks = <&osc32k>; + #clock-cells = <1>; }; r_intc: interrupt-controller@1f00c00 { @@ -655,6 +715,29 @@ #reset-cells = <1>; }; + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun50i-a64-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_APB0_I2C>; + resets = <&r_ccu RST_APB0_I2C>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01f03800 0x400>; + clocks = <&osc24M>; + pinctrl-names = "default"; + pinctrl-0 = <&r_pwm_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -666,6 +749,16 @@ interrupt-controller; #interrupt-cells = <3>; + r_i2c_pins_a: i2c-a { + pins = "PL8", "PL9"; + function = "s_i2c"; + }; + + r_pwm_pin: pwm { + pins = "PL10"; + function = "s_pwm"; + }; + r_rsb_pins: rsb { pins = "PL0", "PL1"; function = "s_rsb"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 98862c7c7258..3e0d5a9c096d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -207,6 +207,18 @@ status = "okay"; }; +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index b6f2d6b2ecae..ceffc40810ee 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -20,11 +20,157 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + label = "pine-h64:green:heartbeat"; + gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; + + link { + label = "pine-h64:white:link"; + gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */ + }; + + status { + label = "pine-h64:blue:status"; + gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + }; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; }; &r_i2c { status = "okay"; + axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + }; + + reg_aldo3: aldo3 { + /* This regulator is connected with CLDO1 */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-1"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + /* This regulator is connected with ALDO3 */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-2"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; + pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index c72da8cd9ef5..cfa5fffcf62b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -5,7 +5,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun50i-h6-ccu.h> +#include <dt-bindings/clock/sun50i-h6-r-ccu.h> #include <dt-bindings/reset/sun50i-h6-ccu.h> +#include <dt-bindings/reset/sun50i-h6-r-ccu.h> / { interrupt-parent = <&gic>; @@ -124,12 +126,71 @@ interrupt-controller; #interrupt-cells = <3>; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC1", "PC4", "PC5", "PC6", + "PC7", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + uart0_ph_pins: uart0-ph { pins = "PH0", "PH1"; function = "uart0"; }; }; + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-h6-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun50i-h6-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x04021000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun50i-h6-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x04022000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + uart0: serial@5000000 { compatible = "snps,dw-apb-uart"; reg = <0x05000000 0x400>; @@ -198,7 +259,7 @@ reg = <0x07022000 0x400>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu 2>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -215,8 +276,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07081400 0x400>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu 8>; - resets = <&r_ccu 4>; + clocks = <&r_ccu CLK_R_APB2_I2C>; + resets = <&r_ccu RST_R_APB2_I2C>; pinctrl-names = "default"; pinctrl-0 = <&r_i2c_pins>; status = "disabled"; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 67dac595dc72..d033da401c26 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -119,6 +119,12 @@ #clock-cells = <0>; compatible = "fixed-clock"; }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; gmac0: ethernet@ff800000 { @@ -127,8 +133,8 @@ interrupts = <0 90 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; clocks = <&clkmgr STRATIX10_EMAC0_CLK>; clock-names = "stmmaceth"; status = "disabled"; @@ -140,8 +146,8 @@ interrupts = <0 91 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; clocks = <&clkmgr STRATIX10_EMAC1_CLK>; clock-names = "stmmaceth"; status = "disabled"; @@ -153,8 +159,8 @@ interrupts = <0 92 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; clocks = <&clkmgr STRATIX10_EMAC2_CLK>; clock-names = "stmmaceth"; status = "disabled"; @@ -310,6 +316,7 @@ resets = <&rst SPIM0_RESET>; reg-io-width = <4>; num-cs = <4>; + clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; status = "disabled"; }; @@ -322,6 +329,7 @@ resets = <&rst SPIM1_RESET>; reg-io-width = <4>; num-cs = <4>; + clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; status = "disabled"; }; @@ -407,6 +415,7 @@ phy-names = "usb2-phy"; resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr STRATIX10_USB_CLK>; status = "disabled"; }; @@ -418,6 +427,7 @@ phy-names = "usb2-phy"; resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr STRATIX10_USB_CLK>; status = "disabled"; }; @@ -426,6 +436,7 @@ reg = <0xffd00200 0x100>; interrupts = <0 117 4>; resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; status = "disabled"; }; @@ -434,6 +445,7 @@ reg = <0xffd00300 0x100>; interrupts = <0 118 4>; resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; status = "disabled"; }; @@ -442,6 +454,7 @@ reg = <0xffd00400 0x100>; interrupts = <0 125 4>; resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; status = "disabled"; }; @@ -450,6 +463,7 @@ reg = <0xffd00500 0x100>; interrupts = <0 126 4>; resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; status = "disabled"; }; @@ -464,5 +478,20 @@ interrupts = <16 4>, <48 4>; }; }; + + qspi: spi@ff8d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff8d2000 0x100>, + <0xff900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index f9b1ef12db48..6edc4fa9fd42 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -147,3 +147,38 @@ reg = <0x68>; }; }; + +&qspi { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00a"; + reg = <0>; + spi-max-frequency = <50000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x4000000>; + }; + + qspi_rootfs: partition@4000000 { + label = "Root Filesystem - JFFS2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 34dd0e9b5cbb..a97c0e2d7bc6 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -17,6 +17,9 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index dff9b15eb3c0..d5c01427a5ca 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -6,21 +6,75 @@ /dts-v1/; #include "meson-axg.dtsi" +#include <dt-bindings/input/input.h> / { compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; model = "Amlogic Meson AXG S400 Development Board"; + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-next { + label = "Next"; + linux,code = <KEY_NEXT>; + press-threshold-microvolt = <1116000>; /* 62% */ + }; + + button-prev { + label = "Previous"; + linux,code = <KEY_PREVIOUS>; + press-threshold-microvolt = <900000>; /* 50% */ + }; + + button-wifi { + label = "Wifi"; + linux,code = <KEY_WLAN>; + press-threshold-microvolt = <684000>; /* 38% */ + }; + + button-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <468000>; /* 26% */ + }; + + button-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <252000>; /* 14% */ + }; + + button-voice { + label = "Voice"; + linux,code = <KEY_VOICECOMMAND>; + press-threshold-microvolt = <0>; /* 0% */ + }; + }; + aliases { serial0 = &uart_AO; serial1 = &uart_A; }; + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; }; vddao_3v3: regulator-vddao_3v3 { @@ -28,6 +82,8 @@ regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; }; vddio_ao18: regulator-vddio_ao18 { @@ -35,6 +91,8 @@ regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; }; vcc_3v3: regulator-vcc_3v3 { @@ -42,6 +100,30 @@ regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_pwr: regulator-usb_pwr { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + enable-active-high; }; emmc_pwrseq: emmc-pwrseq { @@ -62,6 +144,66 @@ clock-frequency = <32768>; pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ }; + + speaker-leds { + compatible = "gpio-leds"; + + aled1 { + label = "speaker:aled1"; + gpios = <&gpio_speaker 7 0>; + }; + + aled2 { + label = "speaker:aled2"; + gpios = <&gpio_speaker 6 0>; + }; + + aled3 { + label = "speaker:aled3"; + gpios = <&gpio_speaker 5 0>; + }; + + aled4 { + label = "speaker:aled4"; + gpios = <&gpio_speaker 4 0>; + }; + + aled5 { + label = "speaker:aled5"; + gpios = <&gpio_speaker 3 0>; + }; + + aled6 { + label = "speaker:aled6"; + gpios = <&gpio_speaker 2 0>; + }; + }; + + linein: audio-codec@0 { + #sound-dai-cells = <0>; + compatible = "everest,es7241"; + VDDA-supply = <&vcc_3v3>; + VDDP-supply = <&vcc_3v3>; + VDDD-supply = <&vcc_3v3>; + status = "okay"; + sound-name-prefix = "Linein"; + }; + + lineout: audio-codec@1 { + #sound-dai-cells = <0>; + compatible = "everest,es7154"; + VDD-supply = <&vcc_3v3>; + PVDD-supply = <&vcc_5v>; + status = "okay"; + sound-name-prefix = "Lineout"; + }; + + spdif_dit: audio-codec@2 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; }; ðmac { @@ -106,12 +248,33 @@ status = "okay"; pinctrl-0 = <&i2c1_z_pins>; pinctrl-names = "default"; + + speaker_amp1: audio-codec@1b { + compatible = "ti,tas5707"; + reg = <0x1b>; + reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + AVDD-supply = <&vcc_3v3>; + DVDD-supply = <&vcc_3v3>; + PVDD_A-supply = <&main_12v>; + PVDD_B-supply = <&main_12v>; + PVDD_C-supply = <&main_12v>; + PVDD_D-supply = <&main_12v>; + }; }; &i2c_AO { status = "okay"; pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; pinctrl-names = "default"; + + gpio_speaker: gpio-controller@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vddao_3v3>; + }; }; &pwm_ab { @@ -166,3 +329,8 @@ compatible = "brcm,bcm4329-fmac"; }; }; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 67d7115e4eff..c518130e5ce7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/axg-audio-clkc.h> #include <dt-bindings/clock/axg-clkc.h> #include <dt-bindings/clock/axg-aoclkc.h> #include <dt-bindings/gpio/meson-axg-gpio.h> @@ -91,6 +92,39 @@ method = "smc"; }; + tdmif_a: audio-controller@0 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_A"; + clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, + <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_b: audio-controller@1 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_B"; + clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, + <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_c: audio-controller@2 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_C"; + clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, + <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 @@ -155,6 +189,157 @@ }; }; + audio: bus@ff642000 { + compatible = "simple-bus"; + reg = <0x0 0xff642000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; + + clkc_audio: clock-controller@0 { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets = <&reset RESET_AUDIO>; + }; + + arb: reset-controller@280 { + compatible = "amlogic,meson-axg-audio-arb"; + reg = <0x0 0x280 0x0 0x4>; + #reset-cells = <1>; + clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; + }; + + tdmin_a: audio-controller@300 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x300 0x0 0x40>; + sound-name-prefix = "TDMIN_A"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_b: audio-controller@340 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x340 0x0 0x40>; + sound-name-prefix = "TDMIN_B"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_c: audio-controller@380 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x380 0x0 0x40>; + sound-name-prefix = "TDMIN_C"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_lb: audio-controller@3c0 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x3c0 0x0 0x40>; + sound-name-prefix = "TDMIN_LB"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifout: audio-controller@480 { + compatible = "amlogic,axg-spdifout"; + reg = <0x0 0x480 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tdmout_a: audio-controller@500 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x500 0x0 0x40>; + sound-name-prefix = "TDMOUT_A"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_b: audio-controller@540 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x540 0x0 0x40>; + sound-name-prefix = "TDMOUT_B"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_c: audio-controller@580 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x580 0x0 0x40>; + sound-name-prefix = "TDMOUT_C"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + }; + cbus: bus@ffd00000 { compatible = "simple-bus"; reg = <0x0 0xffd00000 0x0 0x25000>; @@ -477,6 +662,48 @@ }; }; + pdm_dclk_a14_pins: pdm_dclk_a14 { + mux { + groups = "pdm_dclk_a14"; + function = "pdm"; + }; + }; + + pdm_dclk_a19_pins: pdm_dclk_a19 { + mux { + groups = "pdm_dclk_a19"; + function = "pdm"; + }; + }; + + pdm_din0_pins: pdm_din0 { + mux { + groups = "pdm_din0"; + function = "pdm"; + }; + }; + + pdm_din1_pins: pdm_din1 { + mux { + groups = "pdm_din1"; + function = "pdm"; + }; + }; + + pdm_din2_pins: pdm_din2 { + mux { + groups = "pdm_din2"; + function = "pdm"; + }; + }; + + pdm_din3_pins: pdm_din3 { + mux { + groups = "pdm_din3"; + function = "pdm"; + }; + }; + pwm_a_a_pins: pwm_a_a { mux { groups = "pwm_a_a"; @@ -561,6 +788,76 @@ }; }; + spdif_in_z_pins: spdif_in_z { + mux { + groups = "spdif_in_z"; + function = "spdif_in"; + }; + }; + + spdif_in_a1_pins: spdif_in_a1 { + mux { + groups = "spdif_in_a1"; + function = "spdif_in"; + }; + }; + + spdif_in_a7_pins: spdif_in_a7 { + mux { + groups = "spdif_in_a7"; + function = "spdif_in"; + }; + }; + + spdif_in_a19_pins: spdif_in_a19 { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + spdif_in_a20_pins: spdif_in_a20 { + mux { + groups = "spdif_in_a20"; + function = "spdif_in"; + }; + }; + + spdif_out_z_pins: spdif_out_z { + mux { + groups = "spdif_out_z"; + function = "spdif_out"; + }; + }; + + spdif_out_a1_pins: spdif_out_a1 { + mux { + groups = "spdif_out_a1"; + function = "spdif_out"; + }; + }; + + spdif_out_a11_pins: spdif_out_a11 { + mux { + groups = "spdif_out_a11"; + function = "spdif_out"; + }; + }; + + spdif_out_a19_pins: spdif_out_a19 { + mux { + groups = "spdif_out_a19"; + function = "spdif_out"; + }; + }; + + spdif_out_a20_pins: spdif_out_a20 { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + spi0_pins: spi0 { mux { groups = "spi0_miso", @@ -1194,6 +1491,20 @@ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; + + saradc: adc@9000 { + compatible = "amlogic,meson-axg-saradc", + "amlogic,meson-saradc"; + reg = <0x0 0x9000 0x0 0x38>; + #io-channel-cells = <1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_SAR_ADC>, + <&clkc_AO CLKID_AO_SAR_ADC_CLK>, + <&clkc_AO CLKID_AO_SAR_ADC_SEL>; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index 88e712ea757a..765247bc4f24 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -35,6 +35,13 @@ regulator-always-on; }; + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; @@ -140,6 +147,11 @@ clock-names = "clkin0"; }; +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + /* Wireless SDIO Module */ &sd_emmc_a { status = "okay"; @@ -160,11 +172,6 @@ vmmc-supply = <&vddao_3v3>; vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; }; /* SD card */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 7d5709c37e95..cbe99bd4e06d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -106,6 +106,42 @@ compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; + + /* CVBS is available on CON1 pin 36, disabled by default */ + cvbs-connector { + compatible = "composite-video-connector"; + status = "disabled"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; }; ðmac { @@ -137,6 +173,18 @@ }; }; +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts new file mode 100644 index 000000000000..70433e023fda --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * Author: Jerome Brunet <jbrunet@baylibre.com> + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl"; + model = "Amlogic Meson GXL (S805X) P241 Development Board"; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +ðmac { + status = "okay"; +}; + +&internal_phy { + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +/* This is connected to the Bluetooth module: */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index a9f9bb90a877..15014faa2ab2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -41,13 +41,6 @@ }; }; - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - hdmi-connector { compatible = "hdmi-connector"; type = "a"; @@ -108,7 +101,9 @@ }; }; -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts index 80a231476b80..92c425d0259c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts @@ -19,3 +19,10 @@ phy-mode = "rmii"; phy-handle = <&internal_phy>; }; + +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts new file mode 100644 index 000000000000..6509c4950950 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gxl-s905d-p231.dts: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + */ + +/dts-v1/; + +#include "meson-gxl-s905x.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl"; + model = "Amlogic Meson GXL (S905W) P281 Development Board"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts new file mode 100644 index 000000000000..789c819c99c4 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gxl-s905d-p231.dts: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + */ + +/dts-v1/; + +#include "meson-gxl-s905x.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl"; + model = "Oranth Tanix TX3 Mini"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */ + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 0868da476e41..313f88f8759e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -209,10 +209,34 @@ #cooling-cells = <2>; }; +&cpu1 { + #cooling-cells = <2>; +}; + +&cpu2 { + #cooling-cells = <2>; +}; + +&cpu3 { + #cooling-cells = <2>; +}; + &cpu4 { #cooling-cells = <2>; }; +&cpu5 { + #cooling-cells = <2>; +}; + +&cpu6 { + #cooling-cells = <2>; +}; + +&cpu7 { + #cooling-cells = <2>; +}; + ðmac { pinctrl-0 = <ð_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts index 101417298a1d..73d656e4aade 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts @@ -40,13 +40,6 @@ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; }; }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; }; /* Q200 has exclusive choice between internal or external PHY */ @@ -79,7 +72,9 @@ }; }; -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts index 8d132b17514a..d02b80d77378 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts @@ -19,3 +19,10 @@ phy-mode = "rmii"; phy-handle = <&internal_phy>; }; + +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/Makefile b/arch/arm64/boot/dts/broadcom/stingray/Makefile index c4d06cffcb11..20c7d0aa6cb7 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/Makefile +++ b/arch/arm64/boot/dts/broadcom/stingray/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb + +dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958802a802x.dtb diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi index 8862ec907fd8..bc299c3d9068 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -30,20 +30,9 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "stingray.dtsi" +#include "stingray-board-base.dtsi" / { - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart1; - serial1 = &uart0; - serial2 = &uart2; - serial3 = &uart3; - }; - sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl { compatible = "regulator-gpio"; regulator-name = "sdio0_vddo_ctrl_reg"; @@ -67,11 +56,6 @@ }; }; -&memory { /* Default DRAM banks */ - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */ -}; - &sata0 { status = "okay"; }; @@ -136,18 +120,6 @@ status = "okay"; }; -&mdio_mux_iproc { - mdio@10 { - gphy0: eth-phy@10 { - reg = <0x10>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - &pwm { status = "okay"; }; @@ -175,8 +147,6 @@ }; &enet { - phy-mode = "rgmii-id"; - phy-handle = <&gphy0>; status = "okay"; }; @@ -197,13 +167,10 @@ &sdio0 { vqmmc-supply = <&sdio0_vddo_ctrl_reg>; - non-removable; - full-pwr-cycle; status = "okay"; }; &sdio1 { vqmmc-supply = <&sdio1_vddo_ctrl_reg>; - full-pwr-cycle; status = "okay"; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts new file mode 100644 index 000000000000..a41facd7d79b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +/* + *Copyright(c) 2018 Broadcom + */ + +/dts-v1/; + +#include "stingray-board-base.dtsi" + +/ { + compatible = "brcm,bcm958802a802x", "brcm,stingray"; + model = "Stingray PS225xx (BCM958802A802x)"; +}; + +&enet { + status = "disabled"; +}; + +&sdio0 { + no-1-8-v; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi new file mode 100644 index 000000000000..82a24711d0d8 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +/* + * Copyright(c) 2016-2018 Broadcom + */ + +#include "stingray.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart0; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&memory { /* Default DRAM banks */ + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */ +}; + +&enet { + phy-mode = "rgmii-id"; + phy-handle = <&gphy0>; +}; + +&uart1 { + status = "okay"; +}; + +&sdio0 { + non-removable; + full-pwr-cycle; +}; + +&sdio1 { + full-pwr-cycle; +}; + +&mdio_mux_iproc { + mdio@10 { + gphy0: eth-phy@10 { + reg = <0x10>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi index 3a4d4524b5ed..10a106aca229 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi @@ -52,12 +52,24 @@ reg = <0x0001d104 0x32>, <0x0001c854 0x4>; clocks = <&osc>; - clock-output-names = "genpll0", "clk_125", "clk_scr", + clock-output-names = "genpll0", "clk_125m", "clk_scr", "clk_250", "clk_pcie_axi", "clk_paxc_axi_x2", "clk_paxc_axi"; }; + genpll2: genpll2@1d1ac { + #clock-cells = <1>; + compatible = "brcm,sr-genpll2"; + reg = <0x0001d1ac 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll2", "clk_nic", + "clk_ts_500_ref", "clk_125_nitro", + "clk_chimp", "clk_nic_flash", + "clk_fs"; + }; + genpll3: genpll3@1d1e0 { #clock-cells = <1>; compatible = "brcm,sr-genpll3"; @@ -75,8 +87,8 @@ <0x0001c854 0x4>; clocks = <&osc>; clock-output-names = "genpll4", "clk_ccn", - "clk_tpiu_pll", "noc_clk", - "pll_chclk_fs4", + "clk_tpiu_pll", "clk_noc", + "clk_chclk_fs4", "clk_bridge_fscpu"; }; @@ -86,8 +98,8 @@ reg = <0x0001d248 0x32>, <0x0001c870 0x4>; clocks = <&osc>; - clock-output-names = "genpll5", "fs4_hf_clk", - "crypto_ae_clk", "raid_ae_clk"; + clock-output-names = "genpll5", "clk_fs4_hf", + "clk_crypto_ae", "clk_raid_ae"; }; lcpll0: lcpll0@1d0c4 { @@ -107,9 +119,9 @@ reg = <0x0001d138 0x3c>, <0x0001c870 0x4>; clocks = <&osc>; - clock-output-names = "lcpll1", "clk_wanpn", + clock-output-names = "lcpll1", "clk_wan", "clk_usb_ref", - "timesync_evt_clk"; + "clk_crmu_ts"; }; hsls_clk: hsls_clk { diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi new file mode 100644 index 000000000000..33a472ab17e8 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +/* + *Copyright(c) 2018 Broadcom + */ + +pcie8: pcie@60400000 { + compatible = "brcm,iproc-pcie-paxc-v2"; + reg = <0 0x60400000 0 0x1000>; + linux,pci-domain = <8>; + + bus-range = <0x0 0x1>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; + + dma-coherent; + + msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */ + <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */ + <0x101 &gic_its 0x2080 0x1>, /* PF1 */ + <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */ + <0x102 &gic_its 0x2100 0x1>, /* PF2 */ + <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */ + <0x103 &gic_its 0x2180 0x1>, /* PF3 */ + <0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */ + <0x104 &gic_its 0x2200 0x1>, /* PF4 */ + <0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */ + <0x105 &gic_its 0x2280 0x1>, /* PF5 */ + <0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */ + <0x106 &gic_its 0x2300 0x1>, /* PF6 */ + <0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */ + <0x107 &gic_its 0x2380 0x1>, /* PF7 */ + <0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */ + + phys = <&pcie_phy 8>; + phy-names = "pcie-phy"; +}; + +pcie-ss { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40000000 0x800>; + + pcie_phy: phy@0 { + compatible = "brcm,sr-pcie-phy"; + reg = <0x0 0x200>; + brcm,sr-cdru = <&cdru>; + brcm,sr-mhb = <&mhb>; + #phy-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index a70e8ddbd66f..e283480bfc7e 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -146,6 +146,11 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + mhb: syscon@60401000 { + compatible = "brcm,sr-mhb", "syscon"; + reg = <0 0x60401000 0 0x38c>; + }; + scr { compatible = "simple-bus"; #address-cells = <1>; @@ -258,6 +263,18 @@ #include "stingray-clock.dtsi" + otp: otp@1c400 { + compatible = "brcm,ocotp-v2"; + reg = <0x0001c400 0x68>; + brcm,ocotp-size = <2048>; + status = "okay"; + }; + + cdru: syscon@1d000 { + compatible = "brcm,sr-cdru", "syscon"; + reg = <0x0001d000 0x400>; + }; + gpio_crmu: gpio@24800 { compatible = "brcm,iproc-gpio"; reg = <0x00024800 0x4c>; @@ -269,6 +286,7 @@ #include "stingray-fs4.dtsi" #include "stingray-sata.dtsi" + #include "stingray-pcie.dtsi" hsls { compatible = "simple-bus"; @@ -420,6 +438,7 @@ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; clock-names = "wdogclk", "apb_pclk"; + timeout-sec = <60>; }; gpio_hsls: gpio@d0000 { diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi deleted file mode 100644 index f0803575fd9f..000000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos5433 TMU sensor configuration - * - * Copyright (c) 2016 Jonghwa Lee <jonghwa3.lee@samsung.com> - */ - -#include <dt-bindings/thermal/thermal_exynos.h> - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <23>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <75>; -samsung,tmu_min_efuse_value = <40>; -samsung,tmu_max_efuse_value = <150>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_mux_addr = <6>; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi deleted file mode 100644 index cccae662228a..000000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos5433 TMU sensor configuration - * - * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com> - */ - -#include <dt-bindings/thermal/thermal_exynos.h> - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <8>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <75>; -samsung,tmu_min_efuse_value = <40>; -samsung,tmu_max_efuse_value = <150>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 038c99792ccb..2131f12364cb 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -630,7 +630,7 @@ clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, <&cmu_peris CLK_SCLK_TMU0>; clock-names = "tmu_apbif", "tmu_sclk"; - #include "exynos5433-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; status = "disabled"; }; @@ -641,7 +641,7 @@ clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, <&cmu_peris CLK_SCLK_TMU0>; clock-names = "tmu_apbif", "tmu_sclk"; - #include "exynos5433-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; status = "disabled"; }; @@ -652,7 +652,7 @@ clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; - #include "exynos5433-tmu-g3d-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; status = "disabled"; }; @@ -663,7 +663,7 @@ clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; - #include "exynos5433-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; status = "disabled"; }; @@ -674,7 +674,7 @@ clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; - #include "exynos5433-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; status = "disabled"; }; @@ -1171,7 +1171,7 @@ power-domains = <&pd_gscl>; }; - sysmmu_scaler_0: sysmmu@0x15040000 { + sysmmu_scaler_0: sysmmu@15040000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15040000 0x1000>; interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; @@ -1182,7 +1182,7 @@ power-domains = <&pd_mscl>; }; - sysmmu_scaler_1: sysmmu@0x15050000 { + sysmmu_scaler_1: sysmmu@15050000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15050000 0x1000>; interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/exynos/exynos7-tmu-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos7-tmu-sensor-conf.dtsi deleted file mode 100644 index 48494710b7b2..000000000000 --- a/arch/arm64/boot/dts/exynos/exynos7-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos7 TMU sensor configuration - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include <dt-bindings/thermal/thermal_exynos.h> - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <9>; -samsung,tmu_reference_voltage = <17>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <75>; -samsung,tmu_min_efuse_value = <15>; -samsung,tmu_max_efuse_value = <100>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <85>; -samsung,tmu_default_temp_offset = <50>; -samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 93a84338938a..75ad724c487e 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -589,7 +589,7 @@ clocks = <&clock_peris PCLK_TMU>, <&clock_peris SCLK_TMU>; clock-names = "tmu_apbif", "tmu_sclk"; - #include "exynos7-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; thermal-zones { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts index 7286b1ebfd7a..f90c040fd5e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts @@ -1,45 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS1012A Freedom Board. * * Copyright 2016 Freescale Semiconductor, Inc. * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts index cdc4aee75227..2fb1cb1f7d8f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts @@ -1,45 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS1012A QDS Board. * * Copyright 2016 Freescale Semiconductor, Inc. * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts index c1a119effa61..5edb1e137a52 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts @@ -1,45 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS1012A RDB Board. * * Copyright 2016 Freescale Semiconductor, Inc. * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 205f0f4c5df0..4c558a2133e2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -1,45 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1012A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi index 169e171407a6..6082ae022136 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 device tree nodes for ls1043 * * Copyright 2015-2016 Freescale Semiconductor Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ &soc { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts index 6341281485cf..c7b8d2c009cd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1043A family SoC. * * Copyright 2014-2015 Freescale Semiconductor, Inc. * * Mingkai Hu <Mingkai.hu@freescale.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index 3dc0c8e9663d..7b01ba8d3b7e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1043A family SoC. * * Copyright 2014-2015 Freescale Semiconductor, Inc. * * Mingkai Hu <Mingkai.hu@freescale.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 1109f22bda5e..b9f5d2ff4ff2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1043A family SoC. * * Copyright 2014-2015 Freescale Semiconductor, Inc. * * Mingkai Hu <Mingkai.hu@freescale.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/thermal/thermal.h> @@ -80,8 +43,8 @@ reg = <0x0>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; - #cooling-cells = <2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -91,6 +54,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -100,6 +64,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -109,6 +74,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; l2: l2-cache { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi index f5017dba0f17..d6caaea57d90 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 device tree nodes for ls1046 * * Copyright 2015-2016 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ &soc { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index 434383bade0e..e69306e6b0b1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. * * Shaohui Xie <Shaohui.Xie@nxp.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 5dc2782e2a58..440e111651d5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. * * Mingkai Hu <mingkai.hu@nxp.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 136ebfa9b333..65ce1c3cb568 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. * * Mingkai Hu <mingkai.hu@nxp.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -87,6 +50,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -96,6 +60,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -105,6 +70,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; l2: l2-cache { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts index 30128051d0c0..6f48d21b97c0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for NXP LS1088A QDS Board. * @@ -5,43 +6,6 @@ * * Harninder Rai <harninder.rai@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 4f17601b919c..8e925df6c01c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for NXP LS1088A RDB Board. * @@ -5,43 +6,6 @@ * * Harninder Rai <harninder.rai@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 1c6556bcfddf..a07f612ab56b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for NXP Layerscape-1088A family SoC. * @@ -5,43 +6,6 @@ * * Harninder Rai <harninder.rai@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> @@ -76,6 +40,7 @@ reg = <0x1>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -84,6 +49,7 @@ reg = <0x2>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -92,6 +58,7 @@ reg = <0x3>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu4: cpu@100 { @@ -109,6 +76,7 @@ reg = <0x101>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu6: cpu@102 { @@ -117,6 +85,7 @@ reg = <0x102>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu7: cpu@103 { @@ -125,6 +94,7 @@ reg = <0x103>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; CPU_PH20: cpu-ph20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts index 3c99608b9b45..f6c3ee78ace0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS2080a QDS Board. * @@ -7,43 +8,6 @@ * Abhimanyu Saini <abhimanyu.saini@nxp.com> * Bhupesh Sharma <bhupesh.sharma@freescale.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts index a4e7de9f70d8..44894356059c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS2080a RDB Board. * @@ -7,43 +8,6 @@ * Abhimanyu Saini <abhimanyu.saini@nxp.com> * Bhupesh Sharma <bhupesh.sharma@freescale.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts index fbbb73e571c0..5517305039a4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS2080a software Simulator model * @@ -5,43 +6,6 @@ * * Bhupesh Sharma <bhupesh.sharma@freescale.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 8d739301e7b8..f9c1d30cf4a7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-2080A family SoC. * @@ -6,43 +7,6 @@ * Abhimanyu Saini <abhimanyu.saini@nxp.com> * Bhupesh Sharma <bhupesh.sharma@freescale.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "fsl-ls208xa.dtsi" @@ -65,6 +29,7 @@ clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; }; cpu2: cpu@100 { @@ -84,6 +49,7 @@ clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; }; cpu4: cpu@200 { @@ -103,6 +69,7 @@ clocks = <&clockgen 1 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; + #cooling-cells = <2>; }; cpu6: cpu@300 { @@ -122,6 +89,7 @@ clocks = <&clockgen 1 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts index eaee5b1c3a44..7c17b1bd4529 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS2088A QDS Board. * @@ -6,43 +7,6 @@ * * Abhimanyu Saini <abhimanyu.saini@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index c411442cac62..f6b4d75a258b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS2088A RDB Board. * @@ -6,43 +7,6 @@ * * Abhimanyu Saini <abhimanyu.saini@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 0884e1a77901..7c882da3f6b0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-2088A family SoC. * @@ -6,43 +7,6 @@ * * Abhimanyu Saini <abhimanyu.saini@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "fsl-ls208xa.dtsi" @@ -65,6 +29,7 @@ clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; }; cpu2: cpu@100 { @@ -84,6 +49,7 @@ clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; }; cpu4: cpu@200 { @@ -103,6 +69,7 @@ clocks = <&clockgen 1 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; + #cooling-cells = <2>; }; cpu6: cpu@300 { @@ -122,6 +89,7 @@ clocks = <&clockgen 1 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi index 1de618801c73..c11f52e7ae9a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS2080A QDS Board. * @@ -6,43 +7,6 @@ * * Abhimanyu Saini <abhimanyu.saini@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ &esdhc { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi index 061647bd97b8..6fd7f63085c9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Freescale LS2080A RDB Board. * @@ -6,43 +7,6 @@ * * Abhimanyu Saini <abhimanyu.saini@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ &esdhc { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 137ef4dfc3e9..8cb78dd99672 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Freescale Layerscape-2080A family SoC. * @@ -6,43 +7,6 @@ * * Abhimanyu Saini <abhimanyu.saini@nxp.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPLv2 or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi index ae15307f6e8b..ff1aba5fae7f 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ BMan Portals device tree * * Copyright 2011-2016 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ &bportals { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi index ecdffe731b98..dbd2fc3ba790 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 10g port #0 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi index a7f6af56b6a5..6fc5d2560057 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 10g port #1 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi index d600786719fb..4e02276fcf99 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 1g port #0 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi index 3c0b76d43043..0312fa43fa77 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 1g port #1 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi index 89633afca26a..af2df07971dd 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 1g port #2 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi index 87c2b705b1f9..4ac98dc8b227 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 1g port #3 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi index 8f4d74b96b67..bd932d8b0160 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 1g port #4 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi index d534f770f729..7de1c5203f3e 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 1g port #5 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi index 4664c33e0763..263b972a6d1e 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ FMan v3 device tree * * Copyright 2012-2015 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ fman0: fman@1a00000 { diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi index 6a93a4a9be0e..e3bec08b110d 100644 --- a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi +++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi @@ -1,9 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * QorIQ QMan Portals device tree * * Copyright 2011-2016 Freescale Semiconductor Inc. * - * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ &qportals { diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 68c5a6c819ae..c98bcbc8dfba 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -574,21 +574,35 @@ }; &dwmmc1 { + bus-width = <0x4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + disable-wp; + cd-inverted; + cd-gpios = <&gpio25 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pmx_func + &sd_clk_cfg_func + &sd_cfg_func>; vmmc-supply = <&ldo16>; vqmmc-supply = <&ldo9>; status = "okay"; }; &dwmmc2 { /* WIFI */ + bus-width = <0x4>; + non-removable; broken-cd; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pmx_func + &sdio_clk_cfg_func + &sdio_cfg_func>; /* WL_EN */ vmmc-supply = <&wlan_en>; - ti,non-removable; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - #address-cells = <0x1>; - #size-cells = <0x0>; status = "ok"; wlcore: wlcore@2 { diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 851190a719ea..f432b0a88c65 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -61,7 +61,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; @@ -75,7 +75,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; @@ -87,7 +87,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; @@ -99,7 +99,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; @@ -111,7 +111,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; @@ -125,7 +125,7 @@ reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; @@ -137,7 +137,7 @@ reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; @@ -149,7 +149,7 @@ reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; @@ -158,31 +158,40 @@ idle-states { entry-method = "psci"; - CPU_SLEEP: cpu-sleep { + CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <40>; - exit-latency-us = <70>; - min-residency-us = <3000>; + entry-latency-us = <400>; + exit-latency-us = <650>; + min-residency-us = <1500>; }; - CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x1010000>; entry-latency-us = <500>; - exit-latency-us = <5000>; - min-residency-us = <20000>; + exit-latency-us = <1600>; + min-residency-us = <3500>; + }; + + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <400>; + exit-latency-us = <550>; + min-residency-us = <1500>; }; CLUSTER_SLEEP_1: cluster-sleep-1 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <1000>; - exit-latency-us = <5000>; - min-residency-us = <20000>; + entry-latency-us = <800>; + exit-latency-us = <2900>; + min-residency-us = <3500>; }; }; @@ -1020,16 +1029,10 @@ /* SD */ dwmmc1: dwmmc1@ff37f000 { - #address-cells = <1>; - #size-cells = <0>; - cd-inverted; compatible = "hisilicon,hi3660-dw-mshc"; - bus-width = <0x4>; - disable-wp; - cap-sd-highspeed; - supports-highspeed; - card-detect-delay = <200>; reg = <0x0 0xff37f000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, <&crg_ctrl HI3660_HCLK_GATE_SD>; @@ -1037,29 +1040,17 @@ clock-frequency = <3200000>; resets = <&crg_rst 0x94 18>; reset-names = "reset"; - cd-gpios = <&gpio25 3 0>; hisilicon,peripheral-syscon = <&sctrl>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pmx_func - &sd_clk_cfg_func - &sd_cfg_func>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; + card-detect-delay = <200>; status = "disabled"; - - slot@0 { - reg = <0x0>; - bus-width = <4>; - disable-wp; - }; }; /* SDIO */ dwmmc2: dwmmc2@ff3ff000 { compatible = "hisilicon,hi3660-dw-mshc"; reg = <0x0 0xff3ff000 0x0 0x1000>; + #address-cells = <0x1>; + #size-cells = <0x0>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; @@ -1067,12 +1058,6 @@ resets = <&crg_rst 0x94 20>; reset-names = "reset"; card-detect-delay = <200>; - supports-highspeed; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pmx_func - &sdio_clk_cfg_func - &sdio_cfg_func>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 7f12624f6c8e..f4964bee6a1a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -323,7 +323,6 @@ bus-width = <0x4>; non-removable; cap-power-off-card; - keep-power-in-suspend; vmmc-supply = <®_vdd_3v3>; mmc-pwrseq = <&wl1835_pwrseq>; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 586b281cd531..247024df714f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -88,8 +88,8 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; }; @@ -101,6 +101,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu2: cpu@2 { @@ -111,6 +113,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu3: cpu@3 { @@ -121,6 +125,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu4: cpu@100 { @@ -131,6 +137,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu5: cpu@101 { @@ -141,6 +149,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu6: cpu@102 { @@ -151,6 +161,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu7: cpu@103 { @@ -161,6 +173,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; CLUSTER0_L2: l2-cache0 { diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 3353252d78a0..d9531e242eb4 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -22,6 +22,21 @@ serial1 = &uart1; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The PSCI firmware region depicted below is the default one + * and should be updated by the bootloader. + */ + psci-area@4000000 { + reg = <0 0x4000000 0 0x200000>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -98,6 +113,12 @@ status = "disabled"; }; + avs: avs@11500 { + compatible = "marvell,armada-3700-avs", + "syscon"; + reg = <0x11500 0x40>; + }; + uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; reg = <0x12000 0x200>; @@ -287,7 +308,7 @@ }; crypto: crypto@90000 { - compatible = "inside-secure,safexcel-eip97"; + compatible = "inside-secure,safexcel-eip97ies"; reg = <0x90000 0x20000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index a66958ff4de6..56fa44860909 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -91,7 +91,7 @@ }; sfp_eth3: sfp-eth3 { - /* CON3,4 - CPS lane 5 */ + /* CON13,14 - CPS lane 5 */ compatible = "sff,sfp"; i2c-bus = <&sfp_1g_i2c>; los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index 1c6ff8197a88..840c8454d03e 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -398,7 +398,7 @@ }; CP110_LABEL(crypto): crypto@800000 { - compatible = "inside-secure,safexcel-eip197"; + compatible = "inside-secure,safexcel-eip197b"; reg = <0x800000 0x200000>; interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index ac17f60f998c..5b7fd6ad96e4 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts new file mode 100644 index 000000000000..742938a1a548 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for MediaTek X20 Development Board + * + * Copyright (C) 2018, Linaro Ltd. + * + */ + +/dts-v1/; + +#include "mt6797.dtsi" + +/ { + model = "Mediatek X20 Development Board"; + compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; + + aliases { + serial0 = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index b7837642c33a..a747b7bf132d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -18,7 +18,7 @@ compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; chosen { - bootargs = "console=ttyS0,115200n1 swiotlb=512"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; }; cpus { @@ -34,7 +34,7 @@ }; gpio-keys { - compatible = "gpio-keys-polled"; + compatible = "gpio-keys"; poll-interval = <100>; factory { diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 9213c966c224..de2c47bdbe64 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -89,6 +89,7 @@ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; enable-method = "psci"; clock-frequency = <1300000000>; }; @@ -286,9 +287,16 @@ pio: pinctrl@10211000 { compatible = "mediatek,mt7622-pinctrl"; - reg = <0 0x10211000 0 0x1000>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10005000 0 0x1000>; + reg-names = "base", "eint"; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 103>; + interrupt-controller; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; }; watchdog: watchdog@10212000 { @@ -331,7 +339,7 @@ reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; + <&pericfg CLK_PERI_UART0_PD>; clock-names = "baud", "bus"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 94597e33c806..abd2f15a544b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -168,6 +168,7 @@ reg = <0x001>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + #cooling-cells = <2>; clocks = <&infracfg CLK_INFRA_CA53SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; @@ -193,6 +194,7 @@ reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + #cooling-cells = <2>; clocks = <&infracfg CLK_INFRA_CA57SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index ecb034177fc2..57d3f00464ce 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -27,15 +27,33 @@ }; cbb { + ethernet@2490000 { + status = "okay"; + + phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; + phy-mode = "rgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA194_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + serial@3110000 { status = "okay"; }; /* SDMMC1 (SD/MMC) */ sdhci@3400000 { -/* cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; -*/ }; /* SDMMC4 (eMMC) */ diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 6322ef265c2f..a4dfcd19b9e8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -18,6 +18,45 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; + gpio: gpio@2200000 { + compatible = "nvidia,tegra194-gpio"; + reg-names = "security", "gpio"; + reg = <0x2200000 0x10000>, + <0x2210000 0x10000>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + + ethernet@2490000 { + compatible = "nvidia,tegra186-eqos", + "snps,dwc-qos-ethernet-4.10"; + reg = <0x02490000 0x10000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, + <&bpmp TEGRA194_CLK_EQOS_AXI>, + <&bpmp TEGRA194_CLK_EQOS_RX>, + <&bpmp TEGRA194_CLK_EQOS_TX>, + <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; + clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; + resets = <&bpmp TEGRA194_RESET_EQOS>; + reset-names = "eqos"; + status = "disabled"; + + snps,write-requests = <1>; + snps,read-requests = <3>; + snps,burst-map = <0x7>; + snps,txpbl = <16>; + snps,rxpbl = <8>; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>; @@ -329,6 +368,73 @@ }; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "nvidia,tegra194-carmel", "arm,armv8"; + device_type = "cpu"; + reg = <0x10000>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "nvidia,tegra194-carmel", "arm,armv8"; + device_type = "cpu"; + reg = <0x10001>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "nvidia,tegra194-carmel", "arm,armv8"; + device_type = "cpu"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "nvidia,tegra194-carmel", "arm,armv8"; + device_type = "cpu"; + reg = <0x101>; + enable-method = "psci"; + }; + + cpu@4 { + compatible = "nvidia,tegra194-carmel", "arm,armv8"; + device_type = "cpu"; + reg = <0x200>; + enable-method = "psci"; + }; + + cpu@5 { + compatible = "nvidia,tegra194-carmel", "arm,armv8"; + device_type = "cpu"; + reg = <0x201>; + enable-method = "psci"; + }; + + cpu@6 { + compatible = "nvidia,tegra194-carmel", "arm,armv8"; + device_type = "cpu"; + reg = <0x10300>; + enable-method = "psci"; + }; + + cpu@7 { + compatible = "nvidia,tegra194-carmel", "arm,armv8"; + device_type = "cpu"; + reg = <0x10301>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + status = "okay"; + method = "smc"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 9ff848792712..78ce3979ef09 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -338,7 +338,7 @@ led@6 { label = "apq8016-sbc:blue:bt"; gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bt"; + linux,default-trigger = "bluetooth-power"; default-state = "off"; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 4d5ef01f43a3..0ef90c6554a9 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -19,6 +19,33 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * P HSEC = Primary High Speed External Connector + * S HSEC = Secondary High Speed External Connector + * J14 = Camera Connector + * TP = Test Points + * + * Line names are taken from the schematic "DragonBoard 820c", + * drawing no: LM25-P2751-1 + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + / { aliases { serial0 = &blsp2_uart1; @@ -130,6 +157,218 @@ status = "okay"; }; + pinctrl@1010000 { + gpio-line-names = + "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ + "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ + "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */ + "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */ + "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */ + "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */ + "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */ + "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */ + "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */ + "TP93", /* GPIO_9 */ + "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */ + "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */ + "NC", /* GPIO_12 */ + "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ + "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ + "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ + "TP99", /* GPIO_16 */ + "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ + "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ + "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ + "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ + "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ + "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ + "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */ + "GPIO-D", /* GPIO_24, LSEC pin 26 */ + "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */ + "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */ + "BLSP6_I2C_SDA", /* GPIO_27 */ + "BLSP6_I2C_SCL", /* GPIO_28 */ + "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */ + "GPIO30", /* GPIO_30, S HSEC pin 4 */ + "HDMI_CEC", /* GPIO_31 */ + "HDMI_DDC_CLOCK", /* GPIO_32 */ + "HDMI_DDC_DATA", /* GPIO_33 */ + "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ + "PCIE0_RST_N", /* GPIO_35 */ + "PCIE0_CLKREQ_N", /* GPIO_36 */ + "PCIE0_WAKE", /* GPIO_37 */ + "SD_CARD_DET_N", /* GPIO_38 */ + "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ + "W_DISABLE_N", /* GPIO_40 */ + "[BLSP9_UART_TX]", /* GPIO_41 */ + "[BLSP9_UART_RX]", /* GPIO_42 */ + "[BLSP2_UART_CTS_N]", /* GPIO_43 */ + "[BLSP2_UART_RFR_N]", /* GPIO_44 */ + "[BLSP3_UART_TX]", /* GPIO_45 */ + "[BLSP3_UART_RX]", /* GPIO_46 */ + "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */ + "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */ + "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */ + "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */ + "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */ + "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */ + "[CODEC_INT1_N]", /* GPIO_53 */ + "[CODEC_INT2_N]", /* GPIO_54 */ + "[BLSP7_I2C_SDA]", /* GPIO_55 */ + "[BLSP7_I2C_SCL]", /* GPIO_56 */ + "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ + "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */ + "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */ + "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */ + "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */ + "GPIO-E", /* GPIO_62, LSEC pin 27 */ + "TP87", /* GPIO_63 */ + "[CODEC_RST_N]", /* GPIO_64 */ + "[PCM1_CLK]", /* GPIO_65 */ + "[PCM1_SYNC]", /* GPIO_66 */ + "[PCM1_DIN]", /* GPIO_67 */ + "[PCM1_DOUT]", /* GPIO_68 */ + "AUDIO_REF_CLK", /* GPIO_69 */ + "SLIMBUS_CLK", /* GPIO_70 */ + "SLIMBUS_DATA0", /* GPIO_71 */ + "SLIMBUS_DATA1", /* GPIO_72 */ + "NC", /* GPIO_73 */ + "NC", /* GPIO_74 */ + "NC", /* GPIO_75 */ + "NC", /* GPIO_76 */ + "TP94", /* GPIO_77 */ + "NC", /* GPIO_78 */ + "TP95", /* GPIO_79 */ + "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */ + "TP88", /* GPIO_81 */ + "TP89", /* GPIO_82 */ + "TP90", /* GPIO_83 */ + "TP91", /* GPIO_84 */ + "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ + "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ + "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ + "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */ + "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ + "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ + "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ + "NC", /* GPIO_92 */ + "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ + "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ + "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ + "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ + "NC", /* GPIO_97 */ + "CAM1_STANDBY_N", /* GPIO_98 */ + "NC", /* GPIO_99 */ + "NC", /* GPIO_100 */ + "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ + "BOOT_CONFIG1", /* GPIO_102 */ + "USB_HUB_RESET", /* GPIO_103 */ + "CAM1_RST_N", /* GPIO_104 */ + "NC", /* GPIO_105 */ + "NC", /* GPIO_106 */ + "NC", /* GPIO_107 */ + "NC", /* GPIO_108 */ + "NC", /* GPIO_109 */ + "NC", /* GPIO_110 */ + "NC", /* GPIO_111 */ + "NC", /* GPIO_112 */ + "PMI8994_BUA", /* GPIO_113 */ + "PCIE2_RST_N", /* GPIO_114 */ + "PCIE2_CLKREQ_N", /* GPIO_115 */ + "PCIE2_WAKE", /* GPIO_116 */ + "SSC_IRQ_0", /* GPIO_117 */ + "SSC_IRQ_1", /* GPIO_118 */ + "SSC_IRQ_2", /* GPIO_119 */ + "NC", /* GPIO_120 */ + "GPIO121", /* GPIO_121, S HSEC pin 2 */ + "NC", /* GPIO_122 */ + "SSC_IRQ_6", /* GPIO_123 */ + "SSC_IRQ_7", /* GPIO_124 */ + "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */ + "BOOT_CONFIG5", /* GPIO_126 */ + "NC", /* GPIO_127 */ + "NC", /* GPIO_128 */ + "BOOT_CONFIG7", /* GPIO_129 */ + "PCIE1_RST_N", /* GPIO_130 */ + "PCIE1_CLKREQ_N", /* GPIO_131 */ + "PCIE1_WAKE", /* GPIO_132 */ + "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */ + "NC", /* GPIO_134 */ + "NC", /* GPIO_135 */ + "BOOT_CONFIG8", /* GPIO_136 */ + "NC", /* GPIO_137 */ + "NC", /* GPIO_138 */ + "GPS_SSBI2", /* GPIO_139 */ + "GPS_SSBI1", /* GPIO_140 */ + "NC", /* GPIO_141 */ + "NC", /* GPIO_142 */ + "NC", /* GPIO_143 */ + "BOOT_CONFIG6", /* GPIO_144 */ + "NC", /* GPIO_145 */ + "NC", /* GPIO_146 */ + "NC", /* GPIO_147 */ + "NC", /* GPIO_148 */ + "NC"; /* GPIO_149 */ + }; + + qcom,spmi@400f000 { + pmic@0 { + gpios@c000 { + gpio-line-names = + "NC", + "KEY_VOLP_N", + "NC", + "BL1_PWM", + "GPIO-F", /* BL0_PWM, LSEC pin 28 */ + "BL1_EN", + "NC", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "DIVCLK1", + "DIVCLK2", + "DIVCLK3", + "DIVCLK4", + "BT_EN", + "PMIC_SLB", + "PMIC_BUA", + "USB_VBUS_DET"; + }; + + mpps@a000 { + gpio-line-names = + "VDDPX_BIAS", + "WIFI_LED", + "NC", + "BT_LED", + "PM_MPP05", + "PM_MPP06", + "PM_MPP07", + "NC"; + }; + }; + + pmic@2 { + gpios@c000 { + gpio-line-names = + "NC", + "SPKR_AMP_EN1", + "SPKR_AMP_EN2", + "TP61", + "NC", + "USB2_VBUS_DET", + "NC", + "NC", + "NC", + "NC"; + }; + }; + }; + phy@34000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c2625d15a8c0..7b32b8990d62 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -858,9 +858,9 @@ clocks = <&gcc GCC_MDSS_AHB_CLK>, <&gcc GCC_MDSS_AXI_CLK>, <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface_clk", - "bus_clk", - "vsync_clk"; + clock-names = "iface", + "bus", + "vsync"; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; @@ -883,10 +883,10 @@ <&gcc GCC_MDSS_AXI_CLK>, <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface_clk", - "bus_clk", - "core_clk", - "vsync_clk"; + clock-names = "iface", + "bus", + "core", + "vsync"; iommus = <&apps_iommu 4>; @@ -922,12 +922,12 @@ <&gcc GCC_MDSS_BYTE0_CLK>, <&gcc GCC_MDSS_PCLK0_CLK>, <&gcc GCC_MDSS_ESC0_CLK>; - clock-names = "mdp_core_clk", - "iface_clk", - "bus_clk", - "byte_clk", - "pixel_clk", - "core_clk"; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; phys = <&dsi_phy0>; phy-names = "dsi-phy"; @@ -963,7 +963,7 @@ #phy-cells = <0>; clocks = <&gcc GCC_MDSS_AHB_CLK>; - clock-names = "iface_clk"; + clock-names = "iface"; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8c7f9ca25b53..cd3865e7a270 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -377,6 +377,22 @@ reg = <0x740000 0x20000>; }; + tsens0: thermal-sensor@4a9000 { + compatible = "qcom,msm8996-tsens"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + #qcom,sensors = <13>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@4ad000 { + compatible = "qcom,msm8996-tsens"; + reg = <0x4ad000 0x1000>, /* TM */ + <0x4ac000 0x1000>; /* SROT */ + #qcom,sensors = <8>; + #thermal-sensor-cells = <1>; + }; + tcsr: syscon@7a0000 { compatible = "qcom,tcsr-msm8996", "syscon"; reg = <0x7a0000 0x18000>; @@ -459,12 +475,6 @@ status = "disabled"; }; - tsens0: thermal-sensor@4a8000 { - compatible = "qcom,msm8996-tsens"; - reg = <0x4a8000 0x2000>; - #thermal-sensor-cells = <1>; - }; - blsp2_uart1: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x75b0000 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi new file mode 100644 index 000000000000..4d5aca3eeb69 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* Copyright 2018 Google LLC. */ + +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/interrupt-controller/irq.h> + +&spmi_bus { + pm8005_lsid0: pmic@4 { + compatible = "qcom,pm8005", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8005_gpio: gpios@c000 { + compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>; + }; + + }; + + pm8005_lsid1: pmic@5 { + compatible = "qcom,pm8005", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi new file mode 100644 index 000000000000..92bed1e7d4bb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* Copyright 2018 Google LLC. */ + +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/interrupt-controller/irq.h> + +&spmi_bus { + pm8998_lsid0: pmic@0 { + compatible = "qcom,pm8998", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8998_gpio: gpios@c000 { + compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>, + <0 0xca 0 IRQ_TYPE_NONE>, + <0 0xcb 0 IRQ_TYPE_NONE>, + <0 0xcc 0 IRQ_TYPE_NONE>, + <0 0xcd 0 IRQ_TYPE_NONE>, + <0 0xce 0 IRQ_TYPE_NONE>, + <0 0xcf 0 IRQ_TYPE_NONE>, + <0 0xd0 0 IRQ_TYPE_NONE>, + <0 0xd1 0 IRQ_TYPE_NONE>, + <0 0xd2 0 IRQ_TYPE_NONE>, + <0 0xd3 0 IRQ_TYPE_NONE>, + <0 0xd4 0 IRQ_TYPE_NONE>, + <0 0xd5 0 IRQ_TYPE_NONE>, + <0 0xd6 0 IRQ_TYPE_NONE>, + <0 0xd7 0 IRQ_TYPE_NONE>, + <0 0xd8 0 IRQ_TYPE_NONE>, + <0 0xd9 0 IRQ_TYPE_NONE>; + }; + + }; + + pm8998_lsid1: pmic@1 { + compatible = "qcom,pm8998", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 979ab49913f1..6d651f314193 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -12,4 +12,49 @@ / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; compatible = "qcom,sdm845-mtp"; + + aliases { + serial0 = &uart9; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&i2c10 { + status = "okay"; + clock-frequency = <400000>; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&uart9 { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&qup_i2c10_default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_uart9_default { + pinconf-tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cdaabeb3c995..0c9a2aa6a1b5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5,7 +5,10 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/clock/qcom,gcc-sdm845.h> +#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> / { interrupt-parent = <&intc>; @@ -13,6 +16,41 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; + spi6 = &spi6; + spi7 = &spi7; + spi8 = &spi8; + spi9 = &spi9; + spi10 = &spi10; + spi11 = &spi11; + spi12 = &spi12; + spi13 = &spi13; + spi14 = &spi14; + spi15 = &spi15; + }; + chosen { }; memory@80000000 { @@ -152,6 +190,11 @@ }; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, @@ -206,6 +249,457 @@ #power-domain-cells = <1>; }; + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x884000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x884000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x888000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x888000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_default>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x88c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_default>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x88c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_default>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x890000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x890000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x894000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x894000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_default>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x898000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x898000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_default>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0x89c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0x89c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi7_default>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0xa80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0xa80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_default>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_default>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart9: serial@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart9_default>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0xa88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0xa88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0xa8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_default>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0xa8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_default>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0xa90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_default>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0xa90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_default>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0xa94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_default>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0xa94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_default>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0xa98000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0xa98000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi14_default>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0xa9c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_default>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0xa9c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_default>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x40000>; @@ -219,6 +713,269 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + qup_i2c0_default: qup-i2c0-default { + pinmux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + }; + + qup_i2c1_default: qup-i2c1-default { + pinmux { + pins = "gpio17", "gpio18"; + function = "qup1"; + }; + }; + + qup_i2c2_default: qup-i2c2-default { + pinmux { + pins = "gpio27", "gpio28"; + function = "qup2"; + }; + }; + + qup_i2c3_default: qup-i2c3-default { + pinmux { + pins = "gpio41", "gpio42"; + function = "qup3"; + }; + }; + + qup_i2c4_default: qup-i2c4-default { + pinmux { + pins = "gpio89", "gpio90"; + function = "qup4"; + }; + }; + + qup_i2c5_default: qup-i2c5-default { + pinmux { + pins = "gpio85", "gpio86"; + function = "qup5"; + }; + }; + + qup_i2c6_default: qup-i2c6-default { + pinmux { + pins = "gpio45", "gpio46"; + function = "qup6"; + }; + }; + + qup_i2c7_default: qup-i2c7-default { + pinmux { + pins = "gpio93", "gpio94"; + function = "qup7"; + }; + }; + + qup_i2c8_default: qup-i2c8-default { + pinmux { + pins = "gpio65", "gpio66"; + function = "qup8"; + }; + }; + + qup_i2c9_default: qup-i2c9-default { + pinmux { + pins = "gpio6", "gpio7"; + function = "qup9"; + }; + }; + + qup_i2c10_default: qup-i2c10-default { + pinmux { + pins = "gpio55", "gpio56"; + function = "qup10"; + }; + }; + + qup_i2c11_default: qup-i2c11-default { + pinmux { + pins = "gpio31", "gpio32"; + function = "qup11"; + }; + }; + + qup_i2c12_default: qup-i2c12-default { + pinmux { + pins = "gpio49", "gpio50"; + function = "qup12"; + }; + }; + + qup_i2c13_default: qup-i2c13-default { + pinmux { + pins = "gpio105", "gpio106"; + function = "qup13"; + }; + }; + + qup_i2c14_default: qup-i2c14-default { + pinmux { + pins = "gpio33", "gpio34"; + function = "qup14"; + }; + }; + + qup_i2c15_default: qup-i2c15-default { + pinmux { + pins = "gpio81", "gpio82"; + function = "qup15"; + }; + }; + + qup_spi0_default: qup-spi0-default { + pinmux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup0"; + }; + }; + + qup_spi1_default: qup-spi1-default { + pinmux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "qup1"; + }; + }; + + qup_spi2_default: qup-spi2-default { + pinmux { + pins = "gpio27", "gpio28", + "gpio29", "gpio30"; + function = "qup2"; + }; + }; + + qup_spi3_default: qup-spi3-default { + pinmux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "qup3"; + }; + }; + + qup_spi4_default: qup-spi4-default { + pinmux { + pins = "gpio89", "gpio90", + "gpio91", "gpio92"; + function = "qup4"; + }; + }; + + qup_spi5_default: qup-spi5-default { + pinmux { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + function = "qup5"; + }; + }; + + qup_spi6_default: qup-spi6-default { + pinmux { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + function = "qup6"; + }; + }; + + qup_spi7_default: qup-spi7-default { + pinmux { + pins = "gpio93", "gpio94", + "gpio95", "gpio96"; + function = "qup7"; + }; + }; + + qup_spi8_default: qup-spi8-default { + pinmux { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "qup8"; + }; + }; + + qup_spi9_default: qup-spi9-default { + pinmux { + pins = "gpio6", "gpio7", + "gpio4", "gpio5"; + function = "qup9"; + }; + }; + + qup_spi10_default: qup-spi10-default { + pinmux { + pins = "gpio55", "gpio56", + "gpio53", "gpio54"; + function = "qup10"; + }; + }; + + qup_spi11_default: qup-spi11-default { + pinmux { + pins = "gpio31", "gpio32", + "gpio33", "gpio34"; + function = "qup11"; + }; + }; + + qup_spi12_default: qup-spi12-default { + pinmux { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + function = "qup12"; + }; + }; + + qup_spi13_default: qup-spi13-default { + pinmux { + pins = "gpio105", "gpio106", + "gpio107", "gpio108"; + function = "qup13"; + }; + }; + + qup_spi14_default: qup-spi14-default { + pinmux { + pins = "gpio33", "gpio34", + "gpio31", "gpio32"; + function = "qup14"; + }; + }; + + qup_spi15_default: qup-spi15-default { + pinmux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "qup15"; + }; + }; + + qup_uart9_default: qup-uart9-default { + pinmux { + pins = "gpio4", "gpio5"; + function = "qup9"; + }; + }; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0xc263000 0x1ff>, /* TM */ + <0xc222000 0x1ff>; /* SROT */ + #qcom,sensors = <13>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0xc265000 0x1ff>, /* TM */ + <0xc223000 0x1ff>; /* SROT */ + #qcom,sensors = <8>; + #thermal-sensor-cells = <1>; }; spmi_bus: spmi@c440000 { @@ -246,6 +1003,29 @@ #mbox-cells = <1>; }; + apps_rsc: rsc@179c0000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x179c0000 0x10000>, + <0x179d0000 0x10000>, + <0x179e0000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 1>; + + rpmhcc: clock-controller { + compatible = "qcom,sdm845-rpmh-clk"; + #clock-cells = <1>; + }; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts index 009cb1cb0dde..2f24dfc45617 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the H3ULCB Kingfisher board * * Copyright (C) 2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7795-es1-h3ulcb.dts" diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts index dd4f9b6a4254..598b98168559 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts index 3f46345a4644..6b5fa91f1d5d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x * * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index e19dcd6cb767..7b2fbaec9aef 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7795 ES1.x SoC * * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7795.dtsi" @@ -80,7 +77,7 @@ vspd3: vsp@fea38000 { compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x8000>; + reg = <0 0xfea38000 0 0x5000>; interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 620>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts index 4403227c0f97..80791ed27539 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the H3ULCB Kingfisher board * * Copyright (C) 2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7795-h3ulcb.dts" diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 0afe777973de..df50bf46406e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 0efbef5ea9b7..446822f5751c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0 * * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts index e231b5a7cbab..8ded64d0a4d5 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0 * * Copyright (C) 2015-2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index d842940b2f43..fb9d08ad7659 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7795 SoC * * Copyright (C) 2015 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7795-cpg-mssr.h> @@ -291,7 +288,7 @@ #size-cells = <2>; ranges; - wdt0: watchdog@e6020000 { + rwdt: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; @@ -528,6 +525,15 @@ status = "disabled"; }; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + i2c3: i2c@e66d0000 { #address-cells = <1>; #size-cells = <0>; @@ -2530,7 +2536,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2541,7 +2547,7 @@ vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; + reg = <0 0xfea28000 0 0x5000>; interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2552,7 +2558,7 @@ vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x8000>; + reg = <0 0xfea30000 0 0x5000>; interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts index de2390f009e7..2df50eb11f16 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the M3ULCB Kingfisher board * * Copyright (C) 2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "r8a7796-m3ulcb.dts" diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index daee1f1a3f68..cbd8acbf537e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 90cca09b9a5e..052d72acc862 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X board with R-Car M3-W * * Copyright (C) 2016 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts index ddf35d4cd5e5..8860be65342e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W * * Copyright (C) 2015-2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 7c25be6b5af3..cbd35c00b4af 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7796 SoC * - * Copyright (C) 2016 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2016-2017 Renesas Electronics Corp. */ #include <dt-bindings/clock/r8a7796-cpg-mssr.h> @@ -269,7 +266,7 @@ #size-cells = <2>; ranges; - wdt0: watchdog@e6020000 { + rwdt: watchdog@e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; @@ -2108,13 +2105,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; imr-lx4@fe860000 { @@ -2212,7 +2253,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -2223,7 +2264,7 @@ vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; + reg = <0 0xfea28000 0 0x5000>; interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -2234,7 +2275,7 @@ vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x8000>; + reg = <0 0xfea30000 0 0x5000>; interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 486aecacb22a..0cd44461a0bd 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -138,9 +138,14 @@ #size-cells = <2>; ranges; - wdt0: watchdog@e6020000 { + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77965-wdt", + "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; - /* placeholder */ + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; }; gpio0: gpio@e6050000 { @@ -451,6 +456,94 @@ status = "disabled"; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a7796", "renesas,rcar-gen3-usbhs"; @@ -611,6 +704,95 @@ dma-channels = <16>; }; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A77965_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77965_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A77965_PD_A3VP>; + #iommu-cells = <1>; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77965", "renesas,etheravb-rcar-gen3"; @@ -732,7 +914,7 @@ reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE 20>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x51>, <&dmac1 0x50>, @@ -749,7 +931,7 @@ reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE 20>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x53>, <&dmac1 0x52>, @@ -766,7 +948,7 @@ reg = <0 0xe6e88000 0 64>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE 20>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -780,7 +962,7 @@ reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE 20>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>; @@ -796,7 +978,7 @@ reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE 20>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>; @@ -812,7 +994,7 @@ reg = <0 0xe6f30000 0 64>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE 20>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, @@ -1176,6 +1358,9 @@ port@0 { reg = <0>; }; + port@1 { + reg = <1>; + }; }; }; @@ -1340,13 +1525,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a77965", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a77965", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; fcpf0: fcp@fe950000 { @@ -1397,7 +1626,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -1416,7 +1645,7 @@ vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; + reg = <0 0xfea28000 0 0x5000>; interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 21f9cf5c6e84..b6d53321576b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Eagle board * * Copyright (C) 2016-2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 9fce031a596f..8eac8ca6550b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the V3M Starter Kit board * * Copyright (C) 2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 98a2317a16c4..954168858fed 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a77970 SoC * * Copyright (C) 2016-2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a77970-cpg-mssr.h> @@ -776,7 +773,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 0b93a7d76585..9f25c407dfd7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -59,6 +59,8 @@ phy0: ethernet-phy@0 { rxc-skew-ps = <1500>; reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; }; }; @@ -80,6 +82,28 @@ clock-frequency = <32768>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander0: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander1: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &mmc0 { pinctrl-0 = <&mmc_pins>; pinctrl-1 = <&mmc_pins_uhs>; @@ -104,6 +128,11 @@ function = "canfd0"; }; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + mmc_pins: mmc { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index c9680994555d..9dac42f8f804 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -15,6 +15,7 @@ aliases { serial0 = &scif0; + ethernet0 = &gether; }; chosen { @@ -36,7 +37,29 @@ clock-frequency = <32768>; }; +&gether { + pinctrl-0 = <&gether_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + phy-handle = <&phy0>; + renesas,no-ether-link; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &pfc { + gether_pins: gether { + groups = "gether_mdio_a", "gether_rgmii", + "gether_txcrefclk", "gether_txcrefclk_mega"; + function = "gether"; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 4c40f9f0ebc9..b8c9a56562f2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -16,6 +16,15 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -30,6 +39,36 @@ enable-method = "psci"; }; + a53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; + power-domains = <&sysc R8A77980_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <2>; + clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; + power-domains = <&sysc R8A77980_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <3>; + clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; + power-domains = <&sysc R8A77980_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller { compatible = "cache"; power-domains = <&sysc R8A77980_PD_CA53_SCU>; @@ -79,6 +118,96 @@ #size-cells = <2>; ranges; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77980", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 22>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77980", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77980", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77980", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77980", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 25>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77980", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77980"; reg = <0 0xe6060000 0 0x50c>; @@ -105,6 +234,118 @@ #power-domain-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a77980", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a77980", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a77980", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a77980", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a77980", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a77980", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, + <&dmac2 0x9b>, <&dmac2 0x9a>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a77980", "renesas,rcar-gen3-hscif", @@ -202,6 +443,69 @@ }; }; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77980"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vip0: mmu@e7b00000 { + compatible = "renesas,ipmmu-r8a77980"; + reg = <0 0xe7b00000 0 0x1000>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vip1: mmu@e7960000 { + compatible = "renesas,ipmmu-r8a77980"; + reg = <0 0xe7960000 0 0x1000>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a77980"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A77980_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77980"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77980"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77980"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77980"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77980", "renesas,etheravb-rcar-gen3"; @@ -387,6 +691,18 @@ dma-channels = <16>; }; + gether: ethernet@e7400000 { + compatible = "renesas,gether-r8a77980"; + reg = <0 0xe7400000 0 0x1000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 813>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mmc0: mmc@ee140000 { compatible = "renesas,sdhi-r8a77980", "renesas,rcar-gen3-sdhi"; @@ -408,7 +724,7 @@ <0x0 0xf1020000 0 0x20000>, <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; @@ -416,6 +732,83 @@ resets = <&cpg 408>; }; + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a77980", + "renesas,du-r8a77970"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>; + clock-names = "du.0"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 724>; + vsps = <&vspd0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds-encoder@feb90000 { + compatible = "renesas,r8a77980-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = + <&du_out_lvds0>; + }; + }; + + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; @@ -424,13 +817,13 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 7a09d0524f9b..2bc3a4884b00 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -47,10 +47,18 @@ }; }; +&ehci0 { + status = "okay"; +}; + &extal_clk { clock-frequency = <48000000>; }; +&ohci0 { + status = "okay"; +}; + &pfc { avb_pins: avb { mux { @@ -58,8 +66,37 @@ function = "avb"; }; }; + + usb0_pins: usb { + groups = "usb0_b"; + function = "usb0"; + }; + + usb30_pins: usb30 { + groups = "usb30"; + function = "usb30"; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; }; &scif2 { status = "okay"; }; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index be4f519711a1..ae89260baad9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/renesas-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a77990-sysc.h> / { compatible = "renesas,r8a77990"; @@ -17,16 +18,24 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a53_0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x0>; + reg = <0>; device_type = "cpu"; power-domains = <&sysc 5>; next-level-cache = <&L2_CA53>; enable-method = "psci"; }; + a53_1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + device_type = "cpu"; + power-domains = <&sysc 6>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller-0 { compatible = "cache"; power-domains = <&sysc 21>; @@ -44,8 +53,9 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>; }; psci { @@ -60,6 +70,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77990-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc 32>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77990", "renesas,rcar-gen3-gpio"; @@ -191,10 +211,91 @@ #power-domain-cells = <1>; }; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77990_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77990", "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + reg = <0 0xe6800000 0 0x800>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, @@ -248,6 +349,54 @@ status = "disabled"; }; + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77990", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77990", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -258,7 +407,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc 32>; @@ -273,9 +422,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 9d73de8bc94d..a8e8f2669d4c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Draak board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Glider bvba - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /dts-v1/; @@ -59,6 +56,27 @@ }; }; + composite-in { + compatible = "composite-video-connector"; + + port { + composite_con_in: endpoint { + remote-endpoint = <&adv7180_in>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -82,6 +100,12 @@ regulator-boot-on; regulator-always-on; }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; }; &extal_clk { @@ -142,6 +166,11 @@ groups = "usb0"; function = "usb0"; }; + + vin4_pins_cvbs: vin4 { + groups = "vin4_data8", "vin4_sync", "vin4_clk"; + function = "vin4"; + }; }; &i2c0 { @@ -154,6 +183,77 @@ reg = <0x50>; pagesize = <8>; }; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + + /* + * The VIN4 video input path is shared between + * CVBS and HDMI inputs through SW[49-53] + * switches. + * + * CVBS is the default selection, link it to + * VIN4 here. + */ + adv7180_out: endpoint { + remote-endpoint = <&vin4_in>; + }; + }; + }; + + }; + + hdmi-decoder@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + + /* + * The VIN4 video input path is shared between + * CVBS and HDMI inputs through SW[49-53] + * switches. + * + * CVBS is the default selection, leave HDMI + * not connected here. + */ + adv7612_out: endpoint { + pclk-sample = <0>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; + }; }; &i2c1 { @@ -167,6 +267,11 @@ pinctrl-names = "default"; status = "okay"; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&x12_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + ports { port@0 { endpoint { @@ -246,3 +351,23 @@ timeout-sec = <60>; status = "okay"; }; + +&vin4 { + pinctrl-0 = <&vin4_pins_cvbs>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vin4_in: endpoint { + remote-endpoint = <&adv7180_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 2506f46293e8..fe77bc43c447 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a77995 SoC * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Glider bvba - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a77995-cpg-mssr.h> @@ -88,8 +85,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -104,8 +100,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -120,8 +115,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -136,8 +130,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -152,8 +145,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -168,8 +160,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -184,8 +175,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -224,6 +214,18 @@ #power-domain-cells = <1>; }; + thermal: thermal@e6190000 { + compatible = "renesas,thermal-r8a77995"; + reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; #interrupt-cells = <2>; @@ -240,6 +242,41 @@ resets = <&cpg 407>; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77995", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77995", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; @@ -408,6 +445,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -415,6 +453,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -422,6 +461,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -430,6 +470,7 @@ reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -437,6 +478,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -444,6 +486,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -451,6 +494,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -458,6 +502,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -465,6 +510,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -472,6 +518,7 @@ compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -593,6 +640,40 @@ status = "disabled"; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a77995", "renesas,rcar-gen3-scif", "renesas,scif"; @@ -610,6 +691,117 @@ status = "disabled"; }; + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x64>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x64>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x64>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x64>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + vin4: video@e6ef4000 { compatible = "renesas,vin-r8a77995"; reg = <0 0xe6ef4000 0 0x1000>; @@ -699,7 +891,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -709,7 +901,7 @@ vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; + reg = <0 0xfea28000 0 0x5000>; interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -785,6 +977,25 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 9256fbaaab7f..7d3d866a0063 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for common parts of Salvator-X board variants * * Copyright (C) 2015-2016 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* @@ -36,7 +33,7 @@ / { aliases { serial0 = &scif2; - serial1 = &scif1; + serial1 = &hscif1; ethernet0 = &avb; }; @@ -341,6 +338,15 @@ clock-frequency = <32768>; }; +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + status = "okay"; +}; + &hsusb { dr_mode = "otg"; status = "okay"; @@ -440,7 +446,7 @@ }; }; - port@10 { + port@a { reg = <10>; adv7482_txa: endpoint { @@ -450,7 +456,7 @@ }; }; - port@11 { + port@b { reg = <11>; adv7482_txb: endpoint { @@ -546,6 +552,11 @@ function = "du"; }; + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + i2c2_pins: i2c2 { groups = "i2c2_a"; function = "i2c2"; @@ -589,13 +600,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <3300>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -711,7 +722,8 @@ pinctrl-names = "default"; uart-has-rtscts; - status = "okay"; + /* Please only enable hscif1 or scif1 */ + /* status = "okay"; */ }; &scif2 { @@ -838,7 +850,7 @@ status = "okay"; }; -&wdt0 { +&rwdt { timeout-sec = <60>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-x.dtsi b/arch/arm64/boot/dts/renesas/salvator-x.dtsi index 468868c8ed9f..ddee50e64632 100644 --- a/arch/arm64/boot/dts/renesas/salvator-x.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-x.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X board * * Copyright (C) 2015-2016 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "salvator-common.dtsi" @@ -20,6 +17,8 @@ }; &i2c4 { + clock-frequency = <400000>; + versaclock5: clock-generator@6a { compatible = "idt,5p49v5923"; reg = <0x6a>; diff --git a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi index bf4d200fb546..717d42758cbc 100644 --- a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X 2nd version board * * Copyright (C) 2015-2017 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "salvator-common.dtsi" @@ -20,6 +17,8 @@ }; &i2c4 { + clock-frequency = <400000>; + versaclock6: clock-generator@6a { compatible = "idt,5p49v6901"; reg = <0x6a>; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index a4e715cbde87..8bf3091a899c 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Kingfisher (ULCB extension) board * * Copyright (C) 2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ / { diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 0edb16e6b372..0ead552d7eae 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the R-Car Gen3 ULCB board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/gpio/gpio.h> @@ -330,13 +327,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <3300>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -447,7 +444,7 @@ status = "okay"; }; -&wdt0 { +&rwdt { timeout-sec = <60>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 48a83f882947..b0092d95b574 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -9,7 +9,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts index 3d551e3e6c23..8302d86d35c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 28257724a56e..5272e887a434 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 PINE64 - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index b8e9da15e00c..3f5a2944300f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/rk3328-cru.h> @@ -89,6 +52,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; @@ -100,6 +64,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; @@ -111,6 +76,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; @@ -331,7 +297,7 @@ reg = <0x0 0xff120000 0x0 0x100>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "sclk_uart", "pclk_uart"; + clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 4>, <&dmac 5>; dma-names = "tx", "rx"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts b/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts index 8a5275f0539b..160f2c7e9559 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2015 Caesar Wang <wxt@rock-chips.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi index a37220a9387c..4de089149c50 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2015 Caesar Wang <wxt@rock-chips.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/input/input.h> diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts index 5e4d3a7015f5..6b9b1ac1994c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index d3f6c8e0d206..96147d93dd1d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Matthias Brugger <mbrugger@suse.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts index 13a9e22f5d2d..fc1bf078a41f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index b3510d56517a..7452bedf1a7e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index ad91ced78649..9c24de1ba43c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/rk3368-cru.h> @@ -113,7 +76,6 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ }; @@ -122,6 +84,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_l2: cpu@2 { @@ -129,6 +92,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_l3: cpu@3 { @@ -136,6 +100,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_b0: cpu@100 { @@ -143,7 +108,6 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ }; @@ -152,6 +116,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_b2: cpu@102 { @@ -159,6 +124,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; cpu_b3: cpu@103 { @@ -166,6 +132,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts index 56533c344ef2..959ddc3c7df5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts new file mode 100644 index 000000000000..8978d924eb83 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts @@ -0,0 +1,599 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + * + * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "96boards RK3399 Ficus"; + compatible = "vamrs,ficus", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 0>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_sys>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + status = "okay"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { + rockchip,pins = + <3 15 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 17 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + clock-frequency = <100000000>; + clock-freq-min-max = <100000 100000000>; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + card-detect-delay = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index 2a352763c848..38336ab57cc4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -1,46 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -109,6 +73,39 @@ regulator-max-microvolt = <12000000>; }; + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + + work-led { + label = "work"; + default-state = "on"; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + }; + + diy-led { + label = "diy"; + default-state = "off"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + }; + rt5640-sound { compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,rt5640-codec"; @@ -529,19 +526,16 @@ &i2s0 { rockchip,playback-channels = <8>; rockchip,capture-channels = <8>; - #sound-dai-cells = <0>; status = "okay"; }; &i2s1 { rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; status = "okay"; }; &i2s2 { - #sound-dai-cells = <0>; status = "okay"; }; @@ -627,6 +621,16 @@ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + leds { + work_led_gpio: work_led-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_gpio: diy_led-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts new file mode 100644 index 000000000000..1ee0dc0d9f10 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Bob Rev 4+ board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; +#include "rk3399-gru-chromebook.dtsi" + +/ { + model = "Google Bob"; + compatible = "google,bob-rev13", "google,bob-rev12", + "google,bob-rev11", "google,bob-rev10", + "google,bob-rev9", "google,bob-rev8", + "google,bob-rev7", "google,bob-rev6", + "google,bob-rev5", "google,bob-rev4", + "google,bob", "google,gru", "rockchip,rk3399"; + + edp_panel: edp-panel { + compatible = "boe,nv101wxmn51", "simple-panel"; + backlight = <&backlight>; + power-supply = <&pp3300_disp>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; +}; + +&ap_i2c_ts { + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l &touch_reset_l>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; +}; + +&ap_i2c_tp { + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + wakeup-source; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&spi0 { + status = "okay"; +}; + +&pinctrl { + tpm { + h1_int_od_l: h1-int-od-l { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi new file mode 100644 index 000000000000..ff81dfda3b95 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Chromebook shared properties + * + * Copyright 2018 Google, Inc + */ + +#include "rk3399-gru.dtsi" + +/ { + pp900_ap: pp900-ap { + compatible = "regulator-fixed"; + regulator-name = "pp900_ap"; + + /* EC turns on w/ pp900_ap_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + /* EC turns on w/ pp900_usb_en */ + pp900_usb: pp900-ap { + }; + + /* EC turns on w/ pp900_pcie_en */ + pp900_pcie: pp900-ap { + }; + + pp3000: pp3000 { + compatible = "regulator-fixed"; + regulator-name = "pp3000"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3000_en>; + + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_centerlogic_pwm"; + + pwms = <&pwm3 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + }; + + ppvar_centerlogic: ppvar-centerlogic { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_centerlogic"; + + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + + ctrl-supply = <&ppvar_centerlogic_pwm>; + ctrl-voltage-range = <799434 1049925>; + + regulator-settling-time-up-us = <378>; + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; + }; + + /* Schematics call this PPVAR even though it's fixed */ + ppvar_logic: ppvar-logic { + compatible = "regulator-fixed"; + regulator-name = "ppvar_logic"; + + /* EC turns on w/ ppvar_logic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1800_audio: pp1800-audio { + compatible = "regulator-fixed"; + regulator-name = "pp1800_audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_audio_en>; + + enable-active-high; + gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp1800>; + }; + + /* gpio is shared with pp3300_wifi_bt */ + pp1800_pcie: pp1800-pcie { + compatible = "regulator-fixed"; + regulator-name = "pp1800_pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_pd_l>; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + /* + * Need to wait 1ms + ramp-up time before we can power on WiFi. + * This has been approximated as 8ms total. + */ + regulator-enable-ramp-delay = <8000>; + + vin-supply = <&pp1800>; + }; + + /* Always on; plain and simple */ + pp3000_ap: pp3000_emmc: pp3000 { + }; + + pp1500_ap_io: pp1500-ap-io { + compatible = "regulator-fixed"; + regulator-name = "pp1500_ap_io"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1500_en>; + + enable-active-high; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&pp1800>; + }; + + pp3300_disp: pp3300-disp { + compatible = "regulator-fixed"; + regulator-name = "pp3300_disp"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_disp_en>; + + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <2000>; + vin-supply = <&pp3300>; + }; + + /* EC turns on w/ pp3300_usb_en_l */ + pp3300_usb: pp3300 { + }; + + /* gpio is shared with pp1800_pcie and pinctrl is set there */ + pp3300_wifi_bt: pp3300-wifi-bt { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wifi_bt"; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp3300>; + }; + + /* + * This is a bit of a hack. The WiFi module should be reset at least + * 1ms after its regulators have ramped up (max rampup time is ~7ms). + * With some stretching of the imagination, we can call the 1.8V + * regulator a supply. + */ + wlan_pd_n: wlan-pd-n { + compatible = "regulator-fixed"; + regulator-name = "wlan_pd_n"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_reset_l>; + + enable-active-high; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp1800_pcie>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 + 45 46 47 48 49 50 51 52 53 54 55 56 57 58 + 59 60 61 62 63 64 65 66 67 68 69 70 71 72 + 73 74 75 76 77 78 79 80 81 82 83 84 85 86 + 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; + default-brightness-level = <51>; + enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + power-supply = <&pp3300_disp>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwm-delay-us = <10000>; + }; +}; + +&ppvar_bigcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_litcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_gpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&cdn_dp { + extcon = <&usbc_extcon0>, <&usbc_extcon1>; +}; + +&edp { + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +ap_i2c_mic: &i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + headsetcodec: rt5514@57 { + compatible = "realtek,rt5514"; + reg = <0x57>; + realtek,dmic-init-delay-ms = <20>; + }; +}; + +ap_i2c_tp: &i2c5 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + /* + * Note strange pullup enable. Apparently this avoids leakage but + * still allows us to get nice 4.7K pullups for high speed i2c + * transfers. Basically we want the pullup on whenever the ap is + * alive, so the "en" pin just gets set to output high. + */ + pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; +}; + +&cros_ec { + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + usbc_extcon1: extcon@1 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <1>; + + #extcon-cells = <0>; + }; +}; + +&sound { + rockchip,codec = <&max98357a &headsetcodec + &codec &wacky_spi_audio &cdn_dp>; +}; + +&spi2 { + wacky_spi_audio: spi2@0 { + compatible = "realtek,rt5514"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mic_int>; + /* May run faster once verified. */ + spi-max-frequency = <10000000>; + wakeup-source; + }; +}; + +&pci_rootport { + mvl_wifi: wifi@0,0 { + compatible = "pci1b4b,2b42"; + reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 + 0x83010000 0x0 0x00100000 0x0 0x00100000>; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_host_wake_l>; + wakeup-source; + }; +}; + +&tcphy1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&u2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&pinctrl { + discrete-regulators { + pp1500_en: pp1500-en { + rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp1800_audio_en: pp1800-audio-en { + rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + + pp3000_en: pp3000-en { + rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp3300_disp_en: pp3300-disp-en { + rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + wlan_module_pd_l: wlan-module-pd-l { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + }; +}; + +&wifi { + wifi_perst_l: wifi-perst-l { + rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_host_wake_l: wlan-host-wake-l { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index 82179125bfb7..2cc7c47d6a85 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -1,49 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Gru-Kevin Rev 6+ board device tree source * * Copyright 2016-2017 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; -#include "rk3399-gru.dtsi" +#include "rk3399-gru-chromebook.dtsi" #include <dt-bindings/input/linux-event-codes.h> /* @@ -75,24 +38,6 @@ vin-supply = <&pp3300>; }; - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 1>; - brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - 45 46 47 48 49 50 51 52 53 54 55 56 57 58 - 59 60 61 62 63 64 65 66 67 68 69 70 71 72 - 73 74 75 76 77 78 79 80 81 82 83 84 85 86 - 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; - default-brightness-level = <51>; - enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - power-supply = <&pp3300_disp>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwm-delay-us = <10000>; - }; - edp_panel: edp-panel { compatible = "sharp,lq123p1jx31", "simple-panel"; backlight = <&backlight>; @@ -124,6 +69,10 @@ }; }; +&backlight { + pwms = <&cros_ec_pwm 1>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; @@ -280,23 +229,6 @@ ap_i2c_dig: &i2c2 { }; }; -&edp { - status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - &ppvar_bigcpu_pwm { regulator-min-microvolt = <798674>; regulator-max-microvolt = <1302172>; @@ -374,10 +306,4 @@ ap_i2c_dig: &i2c2 { rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>; }; }; - - wifi { - wlan_host_wake_l: wlan-host-wake-l { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index f49bfab75dd0..ca07f6032200 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Google Gru (and derivatives) board device tree source * * Copyright 2016-2017 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/input/input.h> @@ -82,19 +45,6 @@ regulator-boot-on; }; - pp900_ap: pp900-ap { - compatible = "regulator-fixed"; - regulator-name = "pp900_ap"; - - /* EC turns on w/ pp900_ap_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&ppvar_sys>; - }; - pp1200_lpddr: pp1200-lpddr { compatible = "regulator-fixed"; regulator-name = "pp1200_lpddr"; @@ -121,23 +71,6 @@ vin-supply = <&ppvar_sys>; }; - pp3000: pp3000 { - compatible = "regulator-fixed"; - regulator-name = "pp3000"; - pinctrl-names = "default"; - pinctrl-0 = <&pp3000_en>; - - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - vin-supply = <&ppvar_sys>; - }; - pp3300: pp3300 { compatible = "regulator-fixed"; regulator-name = "pp3300"; @@ -191,8 +124,6 @@ ctrl-voltage-range = <800107 1302232>; regulator-settling-time-up-us = <322>; - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; }; ppvar_litcpu_pwm: ppvar-litcpu-pwm { @@ -222,8 +153,6 @@ ctrl-voltage-range = <797743 1307837>; regulator-settling-time-up-us = <384>; - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; }; ppvar_gpu_pwm: ppvar-gpu-pwm { @@ -253,63 +182,12 @@ ctrl-voltage-range = <786384 1217747>; regulator-settling-time-up-us = <390>; - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; - }; - - ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_centerlogic_pwm"; - - pwms = <&pwm3 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <799434>; - regulator-max-microvolt = <1049925>; - }; - - ppvar_centerlogic: ppvar-centerlogic { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_centerlogic"; - - regulator-min-microvolt = <799434>; - regulator-max-microvolt = <1049925>; - - ctrl-supply = <&ppvar_centerlogic_pwm>; - ctrl-voltage-range = <799434 1049925>; - - regulator-settling-time-up-us = <378>; - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; - }; - - /* Schematics call this PPVAR even though it's fixed */ - ppvar_logic: ppvar-logic { - compatible = "regulator-fixed"; - regulator-name = "ppvar_logic"; - - /* EC turns on w/ ppvar_logic_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&ppvar_sys>; }; /* EC turns on w/ pp900_ddrpll_en */ pp900_ddrpll: pp900-ap { }; - /* EC turns on w/ pp900_pcie_en */ - pp900_pcie: pp900-ap { - }; - /* EC turns on w/ pp900_pll_en */ pp900_pll: pp900-ap { }; @@ -318,10 +196,6 @@ pp900_pmu: pp900-ap { }; - /* EC turns on w/ pp900_usb_en */ - pp900_usb: pp900-ap { - }; - /* EC turns on w/ pp1800_s0_en_l */ pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { }; @@ -346,79 +220,6 @@ pp1800_usb: pp1800 { }; - pp1500_ap_io: pp1500-ap-io { - compatible = "regulator-fixed"; - regulator-name = "pp1500_ap_io"; - pinctrl-names = "default"; - pinctrl-0 = <&pp1500_en>; - - enable-active-high; - gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - vin-supply = <&pp1800>; - }; - - pp1800_audio: pp1800-audio { - compatible = "regulator-fixed"; - regulator-name = "pp1800_audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pp1800_audio_en>; - - enable-active-high; - gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&pp1800>; - }; - - /* gpio is shared with pp3300_wifi_bt */ - pp1800_pcie: pp1800-pcie { - compatible = "regulator-fixed"; - regulator-name = "pp1800_pcie"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_module_pd_l>; - - enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - - /* - * Need to wait 1ms + ramp-up time before we can power on WiFi. - * This has been approximated as 8ms total. - */ - regulator-enable-ramp-delay = <8000>; - - vin-supply = <&pp1800>; - }; - - /* - * This is a bit of a hack. The WiFi module should be reset at least - * 1ms after its regulators have ramped up (max rampup time is ~7ms). - * With some stretching of the imagination, we can call the 1.8V - * regulator a supply. - */ - wlan_pd_n: wlan-pd-n { - compatible = "regulator-fixed"; - regulator-name = "wlan_pd_n"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_module_reset_l>; - - enable-active-high; - gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - - vin-supply = <&pp1800_pcie>; - }; - - /* Always on; plain and simple */ - pp3000_ap: pp3000_emmc: pp3000 { - }; - pp3000_sd_slot: pp3000-sd-slot { compatible = "regulator-fixed"; regulator-name = "pp3000_sd_slot"; @@ -457,34 +258,6 @@ pp3300_trackpad: pp3300-trackpad { }; - /* EC turns on w/ pp3300_usb_en_l */ - pp3300_usb: pp3300 { - }; - - pp3300_disp: pp3300-disp { - compatible = "regulator-fixed"; - regulator-name = "pp3300_disp"; - pinctrl-names = "default"; - pinctrl-0 = <&pp3300_disp_en>; - - enable-active-high; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - - startup-delay-us = <2000>; - vin-supply = <&pp3300>; - }; - - /* gpio is shared with pp1800_pcie and pinctrl is set there */ - pp3300_wifi_bt: pp3300-wifi-bt { - compatible = "regulator-fixed"; - regulator-name = "pp3300_wifi_bt"; - - enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - - vin-supply = <&pp3300>; - }; - /* EC turns on w/ usb_a_en */ pp5000_usb_a_vbus: pp5000 { }; @@ -494,7 +267,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>; - wake-on-bt { + wake_on_bt: wake-on-bt { label = "Wake-on-Bluetooth"; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; @@ -512,17 +285,14 @@ status = "okay"; }; - sound { + sound: sound { compatible = "rockchip,rk3399-gru-sound"; rockchip,cpu = <&i2s0 &i2s2>; - rockchip,codec = <&max98357a &headsetcodec - &codec &wacky_spi_audio &cdn_dp>; }; }; &cdn_dp { status = "okay"; - extcon = <&usbc_extcon0>, <&usbc_extcon1>; }; /* @@ -613,22 +383,6 @@ status = "okay"; }; -ap_i2c_mic: &i2c1 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - headsetcodec: rt5514@57 { - compatible = "realtek,rt5514"; - reg = <0x57>; - realtek,dmic-init-delay-ms = <20>; - }; -}; - ap_i2c_ts: &i2c3 { status = "okay"; @@ -639,24 +393,6 @@ ap_i2c_ts: &i2c3 { i2c-scl-rising-time-ns = <300>; }; -ap_i2c_tp: &i2c5 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - /* - * Note strange pullup enable. Apparently this avoids leakage but - * still allows us to get nice 4.7K pullups for high speed i2c - * transfers. Basically we want the pullup on whenever the ap is - * alive, so the "en" pin just gets set to output high. - */ - pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; -}; - ap_i2c_audio: &i2c8 { status = "okay"; @@ -730,17 +466,6 @@ ap_i2c_audio: &i2c8 { #address-cells = <3>; #size-cells = <2>; ranges; - - mvl_wifi: wifi@0,0 { - compatible = "pci1b4b,2b42"; - reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 - 0x83010000 0x0 0x00100000 0x0 0x00100000>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_host_wake_l>; - wakeup-source; - }; }; }; @@ -830,18 +555,6 @@ ap_i2c_audio: &i2c8 { &spi2 { status = "okay"; - - wacky_spi_audio: spi2@0 { - compatible = "realtek,rt5514"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mic_int>; - /* May run faster once verified. */ - spi-max-frequency = <10000000>; - wakeup-source; - }; }; &spi5 { @@ -863,24 +576,12 @@ ap_i2c_audio: &i2c8 { #size-cells = <0>; }; - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - usbc_extcon0: extcon@0 { compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <0>; #extcon-cells = <0>; }; - - usbc_extcon1: extcon@1 { - compatible = "google,extcon-usbc-cros-ec"; - google,usb-port-id = <1>; - - #extcon-cells = <0>; - }; }; }; @@ -896,19 +597,10 @@ ap_i2c_audio: &i2c8 { extcon = <&usbc_extcon0>; }; -&tcphy1 { - status = "okay"; - extcon = <&usbc_extcon1>; -}; - &u2phy0 { status = "okay"; }; -&u2phy1 { - status = "okay"; -}; - &u2phy0_host { status = "okay"; }; @@ -929,22 +621,10 @@ ap_i2c_audio: &i2c8 { status = "okay"; }; -&usb_host0_ehci { - status = "okay"; -}; - &usb_host0_ohci { status = "okay"; }; -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - &usbdrd3_0 { status = "okay"; extcon = <&usbc_extcon0>; @@ -955,16 +635,6 @@ ap_i2c_audio: &i2c8 { dr_mode = "host"; }; -&usbdrd3_1 { - status = "okay"; - extcon = <&usbc_extcon1>; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - &vopb { status = "okay"; }; @@ -1023,26 +693,6 @@ ap_i2c_audio: &i2c8 { }; discrete-regulators { - pp1500_en: pp1500-en { - rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - pp1800_audio_en: pp1800-audio-en { - rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO - &pcfg_pull_down>; - }; - - pp3300_disp_en: pp3300-disp-en { - rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - pp3000_en: pp3000-en { - rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - sd_io_pwr_en: sd-io-pwr-en { rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -1057,11 +707,6 @@ ap_i2c_audio: &i2c8 { rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO &pcfg_pull_none>; }; - - wlan_module_pd_l: wlan-module-pd-l { - rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO - &pcfg_pull_down>; - }; }; codec { @@ -1168,11 +813,7 @@ ap_i2c_audio: &i2c8 { }; }; - wifi { - wifi_perst_l: wifi-perst-l { - rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; - }; - + wifi: wifi { wlan_module_reset_l: wlan-module-reset-l { rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi index d8a120f945c8..69cc9b05baa5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ / { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi index 81617bcf2522..d6f1095abb04 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ / { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index e0afdd8b62bd..e0d64f862322 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index 14a0f1998639..0130b9f98c9d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/pwm/pwm.h> @@ -439,7 +402,6 @@ pinctrl-0 = <&i2s0_2ch_bus>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index ad7548d3b93d..fef2c0608999 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -186,7 +149,6 @@ &i2s0 { rockchip,playback-channels = <8>; rockchip,capture-channels = <8>; - #sound-dai-cells = <0>; status = "okay"; }; @@ -235,6 +197,5 @@ &spdif { i2c-scl-rising-time-ns = <450>; i2c-scl-falling-time-ns = <15>; - #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 941b627094d7..36b60791c156 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "dt-bindings/pwm/pwm.h" @@ -227,6 +190,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -458,7 +425,6 @@ }; &i2s2 { - #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e0040b648f43..c88e603396f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/rk3399-cru.h> @@ -108,8 +71,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -119,6 +82,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -128,6 +92,7 @@ reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -137,6 +102,7 @@ reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -145,8 +111,8 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; }; @@ -156,6 +122,7 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; }; }; @@ -1446,10 +1413,6 @@ <&cru SRST_P_UPHY0_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; rockchip,grf = <&grf>; - rockchip,typec-conn-dir = <0xe580 0 16>; - rockchip,usb3tousb2-en = <0xe580 3 19>; - rockchip,external-psm = <0xe588 14 30>; - rockchip,pipe-status = <0xe5c0 0 0>; status = "disabled"; tcphy0_dp: dp-port { @@ -1475,10 +1438,6 @@ <&cru SRST_P_UPHY1_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; rockchip,grf = <&grf>; - rockchip,typec-conn-dir = <0xe58c 0 16>; - rockchip,usb3tousb2-en = <0xe58c 3 19>; - rockchip,external-psm = <0xe594 14 30>; - rockchip,pipe-status = <0xe5c0 16 16>; status = "disabled"; tcphy1_dp: dp-port { @@ -1516,6 +1475,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spdif_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -1531,6 +1491,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s0_8ch_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -1545,6 +1506,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s1_2ch_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -1557,6 +1519,7 @@ clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -1698,6 +1661,21 @@ status = "disabled"; }; + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "hdmi-sound"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + hdmi: hdmi@ff940000 { compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; @@ -1711,6 +1689,7 @@ power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { @@ -1936,19 +1915,49 @@ drive-strength = <12>; }; + pcfg_pull_none_13ma: pcfg-pull-none-13ma { + bias-disable; + drive-strength = <13>; + }; + + pcfg_pull_none_18ma: pcfg-pull-none-18ma { + bias-disable; + drive-strength = <18>; + }; + + pcfg_pull_none_20ma: pcfg-pull-none-20ma { + bias-disable; + drive-strength = <20>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + pcfg_pull_up_8ma: pcfg-pull-up-8ma { bias-pull-up; drive-strength = <8>; }; + pcfg_pull_up_18ma: pcfg-pull-up-18ma { + bias-pull-up; + drive-strength = <18>; + }; + + pcfg_pull_up_20ma: pcfg-pull-up-20ma { + bias-pull-up; + drive-strength = <20>; + }; + pcfg_pull_down_4ma: pcfg-pull-down-4ma { bias-pull-down; drive-strength = <4>; }; - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; + pcfg_pull_down_8ma: pcfg-pull-down-8ma { + bias-pull-down; + drive-strength = <8>; }; pcfg_pull_down_12ma: pcfg-pull-down-12ma { @@ -1956,9 +1965,22 @@ drive-strength = <12>; }; - pcfg_pull_none_13ma: pcfg-pull-none-13ma { - bias-disable; - drive-strength = <13>; + pcfg_pull_down_18ma: pcfg-pull-down-18ma { + bias-pull-down; + drive-strength = <18>; + }; + + pcfg_pull_down_20ma: pcfg-pull-down-20ma { + bias-pull-down; + drive-strength = <20>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; }; clock { @@ -2481,45 +2503,60 @@ pwm0 { pwm0_pin: pwm0-pin { rockchip,pins = - <4 18 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; + }; + + pwm0_pin_pull_down: pwm0-pin-pull-down { + rockchip,pins = + <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>; }; vop0_pwm_pin: vop0-pwm-pin { rockchip,pins = - <4 18 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + }; + + vop1_pwm_pin: vop1-pwm-pin { + rockchip,pins = + <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { rockchip,pins = - <4 22 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; }; - vop1_pwm_pin: vop1-pwm-pin { + pwm1_pin_pull_down: pwm1-pin-pull-down { rockchip,pins = - <4 18 RK_FUNC_3 &pcfg_pull_none>; + <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>; }; }; pwm2 { pwm2_pin: pwm2-pin { rockchip,pins = - <1 19 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; + }; + + pwm2_pin_pull_down: pwm2-pin-pull-down { + rockchip,pins = + <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; }; }; pwm3a { pwm3a_pin: pwm3a-pin { rockchip,pins = - <0 6 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; }; }; pwm3b { pwm3b_pin: pwm3b-pin { rockchip,pins = - <1 14 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts index ae3b5adf32df..7968d524351b 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts @@ -60,6 +60,7 @@ &i2s_port4 &spdif_port0 &comp_spdif_port0>; + hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>; }; spdif-out { diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index 7919233c9ce2..1a5e7c24b901 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -60,6 +60,7 @@ &i2s_port4 &spdif_port0 &comp_spdif_port0>; + hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>; }; spdif-out { diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 0298bd0d0e1a..caf112629caa 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -58,6 +58,7 @@ clocks = <&sys_clk 32>; enable-method = "psci"; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu2: cpu@100 { @@ -77,6 +78,7 @@ clocks = <&sys_clk 33>; enable-method = "psci"; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi index 98d3b4fdb9ad..82bd642d770b 100644 --- a/arch/arm64/boot/dts/sprd/sc2731.dtsi +++ b/arch/arm64/boot/dts/sprd/sc2731.dtsi @@ -17,6 +17,28 @@ #address-cells = <1>; #size-cells = <0>; + led-controller@200 { + compatible = "sprd,sc27xx-bltc", "sprd,sc2731-bltc"; + reg = <0x200>; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + label = "red"; + reg = <0x0>; + }; + + led@1 { + label = "green"; + reg = <0x1>; + }; + + led@2 { + label = "blue"; + reg = <0x2>; + }; + }; + rtc@280 { compatible = "sprd,sc27xx-rtc", "sprd,sc2731-rtc"; reg = <0x280>; @@ -35,6 +57,28 @@ #interrupt-cells = <2>; }; + efuse@380 { + compatible = "sprd,sc27xx-efuse", "sprd,sc2731-efuse"; + reg = <0x380>; + #address-cells = <1>; + #size-cells = <1>; + hwlocks = <&hwlock 12>; + }; + + pmic_adc: adc@480 { + compatible = "sprd,sc27xx-adc", "sprd,sc2731-adc"; + reg = <0x480>; + interrupt-parent = <&sc2731_pmic>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + hwlocks = <&hwlock 4>; + }; + + vibrator@ec8 { + compatible = "sprd,sc27xx-vibrator", "sprd,sc2731-vibrator"; + reg = <0xec8>; + }; + regulators { compatible = "sprd,sc27xx-regulator"; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index e9db9108f3c0..eb6be5675f79 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -146,6 +146,12 @@ clocks = <&ext_32k>; }; + timer@40050020 { + compatible = "sprd,sc9860-suspend-timer"; + reg = <0 0x40050020 0 0x20>; + clocks = <&ext_32k>; + }; + hwlock: hwspinlock@40500000 { compatible = "sprd,hwspinlock-r3p0"; reg = <0 0x40500000 0 0x1000>; diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile new file mode 100644 index 000000000000..63e619d0b5b8 --- /dev/null +++ b/arch/arm64/boot/dts/ti/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Make file to build device tree binaries for boards based on +# Texas Instruments Inc processors +# +# Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ +# + +dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi new file mode 100644 index 000000000000..2409344df4fa --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family Main Domain peripherals + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x01800000 0x10000>, /* GICD */ + <0x01880000 0x90000>; /* GICR */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: gic-its@18200000 { + compatible = "arm,gic-v3-its"; + reg = <0x01820000 0x10000>; + msi-controller; + #msi-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi new file mode 100644 index 000000000000..cede1fa0983c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Texas Instruments K3 AM654 SoC"; + compatible = "ti,am654"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + cbass_main: interconnect@100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */ + <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */ + <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */ + <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */ + <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */ + /* MCUSS Range */ + <0x28380000 0x00 0x28380000 0x03880000>, + <0x40200000 0x00 0x40200000 0x00900100>, + <0x42040000 0x00 0x42040000 0x03ac2400>, + <0x45100000 0x00 0x45100000 0x00c24000>, + <0x46000000 0x00 0x46000000 0x00200000>, + <0x47000000 0x00 0x47000000 0x00068400>; + + cbass_mcu: interconnect@28380000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/ + <0x40200000 0x40200000 0x00900100>, /* First peripheral window */ + <0x42040000 0x42040000 0x03ac2400>, /* WKUP */ + <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x46000000 0x46000000 0x00200000>, /* CPSW */ + <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */ + + cbass_wakeup: interconnect@42040000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* WKUP Basic peripherals */ + ranges = <0x42040000 0x42040000 0x03ac2400>; + }; + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am65-main.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts new file mode 100644 index 000000000000..af6956fdc13f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am654.dtsi" + +/ { + compatible = "ti,am654-evm", "ti,am654"; + model = "Texas Instruments AM654 Base Board"; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + secure_ddr: secure_ddr@9e800000 { + reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi new file mode 100644 index 000000000000..2affa6f6617e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC family in Quad core configuration + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "k3-am65.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + + cpu3: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + L2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index c2a0c00272e2..60f5443f3ef4 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts new file mode 100644 index 000000000000..88aa06fa78a8 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Avnet Ultra96 rev1 + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp-zcu100-revC.dts" + +/ { + model = "Avnet Ultra96 Rev1"; + compatible = "avnet,ultra96-rev1", "avnet,ultra96", + "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", + "xlnx,zynqmp"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi deleted file mode 100644 index 9f5eedbc2139..000000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * clock specification for Xilinx ZynqMP ep108 development board - * - * (C) Copyright 2015, Xilinx, Inc. - * - * Michal Simek <michal.simek@xilinx.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/ { - misc_clk: misc_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - i2c_clk: i2c_clk { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <111111111>; - }; - - sata_clk: sata_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <75000000>; - }; - - clk100: clk100 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - clk600: clk600 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - }; -}; - -&can0 { - clocks = <&misc_clk &misc_clk>; -}; - -&can1 { - clocks = <&misc_clk &misc_clk>; -}; - -&fpd_dma_chan1 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan2 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan3 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan4 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan5 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan6 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan7 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan8 { - clocks = <&clk600>, <&clk100>; -}; - -&gem0 { - clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; -}; - -&gpio { - clocks = <&misc_clk>; -}; - -&i2c0 { - clocks = <&i2c_clk>; -}; - -&i2c1 { - clocks = <&i2c_clk>; -}; - -&sata { - clocks = <&sata_clk>; -}; - -&sdhci0 { - clocks = <&misc_clk>, <&misc_clk>; -}; - -&sdhci1 { - clocks = <&misc_clk>, <&misc_clk>; -}; - -&spi0 { - clocks = <&misc_clk &misc_clk>; -}; - -&spi1 { - clocks = <&misc_clk &misc_clk>; -}; - -&uart0 { - clocks = <&misc_clk &misc_clk>; -}; - -&usb0 { - clocks = <&misc_clk>, <&misc_clk>; -}; - -&usb1 { - clocks = <&misc_clk>, <&misc_clk>; -}; - -&watchdog0 { - clocks= <&misc_clk>; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts deleted file mode 100644 index 4b0684911626..000000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ep108 development board - * - * (C) Copyright 2014 - 2015, Xilinx, Inc. - * - * Michal Simek <michal.simek@xilinx.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-ep108-clk.dtsi" - -/ { - model = "ZynqMP EP108"; - - aliases { - mmc0 = &sdhci0; - mmc1 = &sdhci1; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: phy@0 { - reg = <0>; - max-speed = <100>; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - eeprom@55 { - compatible = "atmel,24c64"; - reg = <0x55>; - }; -}; - -&sata { - status = "okay"; - ceva,broken-gen2; - /* SATA Phy OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; - ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; - ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; - ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; - ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; - ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; -}; - -&sdhci0 { - status = "okay"; - bus-width = <8>; -}; - -&sdhci1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - num-cs = <1>; - spi0_flash0: spi0_flash0@0 { - compatible = "m25p80"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - spi0_flash0@0 { - label = "spi0_flash0"; - reg = <0x0 0x100000>; - }; - }; -}; - -&spi1 { - status = "okay"; - num-cs = <1>; - spi1_flash0: spi1_flash0@0 { - compatible = "m25p80"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - spi1_flash0@0 { - label = "spi1_flash0"; - reg = <0x0 0x100000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; - maximum-speed = "high-speed"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; - maximum-speed = "high-speed"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 3e862a9faf26..eb5e8bddb610 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -44,8 +44,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw4 { label = "sw4"; @@ -89,12 +87,6 @@ gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - - bt_power { - label = "bt_power"; - gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { @@ -267,6 +259,10 @@ &uart0 { status = "okay"; + bluetooth { + compatible = "ti,wl1831-st"; + enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; }; &uart1 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 5b4ffe646a9b..25dd57485323 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -41,8 +41,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw19 { label = "sw19"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 668f7f26716a..259f21b0c001 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -41,8 +41,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw19 { label = "sw19"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 9a9dd6a0142b..a61b3cc6f4c9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -41,8 +41,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw19 { label = "sw19"; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 514787d45dee..f67e8d5e93ad 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -179,6 +179,7 @@ CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_MARVELL=y +CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m @@ -295,6 +296,8 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_SERIAL_MVEBU_UART=y CONFIG_SERIAL_DEV_BUS=y CONFIG_VIRTIO_CONSOLE=y +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y @@ -349,10 +352,12 @@ CONFIG_POWER_RESET_MSM=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_SBS=m CONFIG_BATTERY_BQ27XXX=y CONFIG_SENSORS_ARM_SCPI=y CONFIG_SENSORS_LM90=m CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_THERMAL_EMULATION=y @@ -365,12 +370,14 @@ CONFIG_TEGRA_BPMP_THERMAL=m CONFIG_QCOM_TSENS=y CONFIG_UNIPHIER_THERMAL=y CONFIG_WATCHDOG=y +CONFIG_ARM_SP805_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_WATCHDOG=m CONFIG_RENESAS_WDT=y CONFIG_UNIPHIER_WATCHDOG=y CONFIG_BCM2835_WDT=y +CONFIG_MFD_BD9571MWV=y CONFIG_MFD_AXP20X_RSB=y CONFIG_MFD_CROS_EC=y CONFIG_CROS_EC_I2C=y @@ -385,6 +392,7 @@ CONFIG_MFD_RK808=y CONFIG_MFD_SEC_CORE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BD9571MWV=y CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_HI6421V530=y @@ -395,6 +403,7 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_VCTRL=m CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y CONFIG_RC_DEVICES=y @@ -407,6 +416,8 @@ CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_DVB_NET is not set CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m @@ -448,9 +459,20 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_SOC_ROCKCHIP=m +CONFIG_SND_SOC_ROCKCHIP_I2S=m +CONFIG_SND_SOC_ROCKCHIP_SPDIF=m +CONFIG_SND_SOC_ROCKCHIP_RT5645=m +CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_DA7219=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RT5514=m +CONFIG_SND_SOC_RT5514_SPI=m +CONFIG_SND_SOC_RT5645=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD=m CONFIG_I2C_HID=m @@ -617,6 +639,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_PCIE=m CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_TEGRA_XUSB=y +CONFIG_HISI_PMU=y CONFIG_QCOM_L2_PMU=y CONFIG_QCOM_L3_PMU=y CONFIG_QCOM_QFPROM=y diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h index 0ad1cf233470..a3233167be60 100644 --- a/arch/arm64/include/asm/tlb.h +++ b/arch/arm64/include/asm/tlb.h @@ -33,6 +33,8 @@ static inline void __tlb_remove_table(void *_table) #define tlb_remove_entry(tlb, entry) tlb_remove_page(tlb, entry) #endif /* CONFIG_HAVE_RCU_TABLE_FREE */ +static void tlb_flush(struct mmu_gather *tlb); + #include <asm-generic/tlb.h> static inline void tlb_flush(struct mmu_gather *tlb) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2af13b162e5e..35511999156a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -33,6 +33,7 @@ config MIPS select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL select HANDLE_DOMAIN_IRQ + select HAVE_ARCH_COMPILER_H select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_KGDB select HAVE_ARCH_MMAP_RND_BITS if MMU diff --git a/arch/mips/include/asm/asm-prototypes.h b/arch/mips/include/asm/asm-prototypes.h index 576f1a62dea9..f901ed043c71 100644 --- a/arch/mips/include/asm/asm-prototypes.h +++ b/arch/mips/include/asm/asm-prototypes.h @@ -5,3 +5,4 @@ #include <asm-generic/asm-prototypes.h> #include <linux/uaccess.h> #include <asm/ftrace.h> +#include <asm/mmu_context.h> diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 0269b3de8b51..d4ea7a5b60cf 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -122,8 +122,8 @@ static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \ " " #asm_op " %0, %1, %3 \n" \ " sc %0, %2 \n" \ "\t" __scbeqz " %0, 1b \n" \ - " move %0, %1 \n" \ " .set mips0 \n" \ + " move %0, %1 \n" \ : "=&r" (result), "=&r" (temp), \ "+" GCC_OFF_SMALL_ASM() (v->counter) \ : "Ir" (i)); \ @@ -190,9 +190,11 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) __asm__ __volatile__( " .set "MIPS_ISA_LEVEL" \n" "1: ll %1, %2 # atomic_sub_if_positive\n" + " .set mips0 \n" " subu %0, %1, %3 \n" " move %1, %0 \n" " bltz %0, 1f \n" + " .set "MIPS_ISA_LEVEL" \n" " sc %1, %2 \n" "\t" __scbeqz " %1, 1b \n" "1: \n" diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h index e081a265f422..cc2eb1b06050 100644 --- a/arch/mips/include/asm/compiler.h +++ b/arch/mips/include/asm/compiler.h @@ -8,6 +8,41 @@ #ifndef _ASM_COMPILER_H #define _ASM_COMPILER_H +/* + * With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the + * compiler that a particular code path will never be hit. This allows it to be + * optimised out of the generated binary. + * + * Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug + * that can lead to instructions from beyond an unreachable statement being + * incorrectly reordered into earlier delay slots if the unreachable statement + * is the only content of a case in a switch statement. This can lead to + * seemingly random behaviour, such as invalid memory accesses from incorrectly + * reordered loads or stores. See this potential GCC fix for details: + * + * https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html + * + * It is unclear whether GCC 8 onwards suffer from the same issue - nothing + * relevant is mentioned in GCC 8 release notes and nothing obviously relevant + * stands out in GCC commit logs, but these newer GCC versions generate very + * different code for the testcase which doesn't exhibit the bug. + * + * GCC also handles stack allocation suboptimally when calling noreturn + * functions or calling __builtin_unreachable(): + * + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365 + * + * We work around both of these issues by placing a volatile asm statement, + * which GCC is prevented from reordering past, prior to __builtin_unreachable + * calls. + * + * The .insn statement is required to ensure that any branches to the + * statement, which sadly must be kept due to the asm statement, are known to + * be branches to code and satisfy linker requirements for microMIPS kernels. + */ +#undef barrier_before_unreachable +#define barrier_before_unreachable() asm volatile(".insn") + #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) #define GCC_IMM_ASM() "n" #define GCC_REG_ACCUM "$0" diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index b509371a6b0c..94414561de0e 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -32,6 +32,7 @@ do { \ } while (0) extern void tlbmiss_handler_setup_pgd(unsigned long); +extern char tlbmiss_handler_setup_pgd_end[]; /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */ #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ diff --git a/arch/mips/include/asm/tlbex.h b/arch/mips/include/asm/tlbex.h index 4ed7ebed3bf1..6d97e23f30ab 100644 --- a/arch/mips/include/asm/tlbex.h +++ b/arch/mips/include/asm/tlbex.h @@ -24,4 +24,13 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l, struct uasm_reloc **r, enum tlb_write_entry wmode); +extern void handle_tlbl(void); +extern char handle_tlbl_end[]; + +extern void handle_tlbs(void); +extern char handle_tlbs_end[]; + +extern void handle_tlbm(void); +extern char handle_tlbm_end[]; + #endif /* __ASM_TLBEX_H */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f8871d5b7eb3..9dab0ed1b227 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -67,14 +67,12 @@ #include <asm/mmu_context.h> #include <asm/types.h> #include <asm/stacktrace.h> +#include <asm/tlbex.h> #include <asm/uasm.h> extern void check_wait(void); extern asmlinkage void rollback_handle_int(void); extern asmlinkage void handle_int(void); -extern u32 handle_tlbl[]; -extern u32 handle_tlbs[]; -extern u32 handle_tlbm[]; extern asmlinkage void handle_adel(void); extern asmlinkage void handle_ades(void); extern asmlinkage void handle_ibe(void); diff --git a/arch/mips/lib/multi3.c b/arch/mips/lib/multi3.c index 111ad475aa0c..4c2483f410c2 100644 --- a/arch/mips/lib/multi3.c +++ b/arch/mips/lib/multi3.c @@ -4,12 +4,12 @@ #include "libgcc.h" /* - * GCC 7 suboptimally generates __multi3 calls for mips64r6, so for that - * specific case only we'll implement it here. + * GCC 7 & older can suboptimally generate __multi3 calls for mips64r6, so for + * that specific case only we implement that intrinsic here. * * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82981 */ -#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPSR6) && (__GNUC__ == 7) +#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPSR6) && (__GNUC__ < 8) /* multiply 64-bit values, low 64-bits returned */ static inline long long notrace dmulu(long long a, long long b) diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S index a5427c6e9757..00fef578c8cd 100644 --- a/arch/mips/mm/tlb-funcs.S +++ b/arch/mips/mm/tlb-funcs.S @@ -12,16 +12,17 @@ * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> */ #include <asm/asm.h> +#include <asm/export.h> #include <asm/regdef.h> #define FASTPATH_SIZE 128 -EXPORT(tlbmiss_handler_setup_pgd_start) LEAF(tlbmiss_handler_setup_pgd) 1: j 1b /* Dummy, will be replaced. */ .space 64 END(tlbmiss_handler_setup_pgd) EXPORT(tlbmiss_handler_setup_pgd_end) +EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd) LEAF(handle_tlbm) .space FASTPATH_SIZE * 4 diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 49312a14cd17..067714291643 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -31,6 +31,7 @@ #include <asm/cacheflush.h> #include <asm/cpu-type.h> +#include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/war.h> #include <asm/uasm.h> @@ -253,8 +254,10 @@ static void output_pgtable_bits_defines(void) pr_debug("\n"); } -static inline void dump_handler(const char *symbol, const u32 *handler, int count) +static inline void dump_handler(const char *symbol, const void *start, const void *end) { + unsigned int count = (end - start) / sizeof(u32); + const u32 *handler = start; int i; pr_debug("LEAF(%s)\n", symbol); @@ -402,12 +405,6 @@ static void build_restore_work_registers(u32 **p) * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, * we cannot do r3000 under these circumstances. * - * Declare pgd_current here instead of including mmu_context.h to avoid type - * conflicts for tlbmiss_handler_setup_pgd - */ -extern unsigned long pgd_current[]; - -/* * The R3000 TLB handler is simple. */ static void build_r3000_tlb_refill_handler(void) @@ -444,8 +441,7 @@ static void build_r3000_tlb_refill_handler(void) memcpy((void *)ebase, tlb_handler, 0x80); local_flush_icache_range(ebase, ebase + 0x80); - - dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); + dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80)); } #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ @@ -1465,8 +1461,7 @@ static void build_r4000_tlb_refill_handler(void) memcpy((void *)ebase, final_handler, 0x100); local_flush_icache_range(ebase, ebase + 0x100); - - dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); + dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100)); } static void setup_pw(void) @@ -1568,31 +1563,21 @@ static void build_loongson3_tlb_refill_handler(void) uasm_resolve_relocs(relocs, labels); memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); local_flush_icache_range(ebase + 0x80, ebase + 0x100); - dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32); + dump_handler("loongson3_tlb_refill", + (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100)); } -extern u32 handle_tlbl[], handle_tlbl_end[]; -extern u32 handle_tlbs[], handle_tlbs_end[]; -extern u32 handle_tlbm[], handle_tlbm_end[]; -extern u32 tlbmiss_handler_setup_pgd_start[]; -extern u32 tlbmiss_handler_setup_pgd[]; -EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd); -extern u32 tlbmiss_handler_setup_pgd_end[]; - static void build_setup_pgd(void) { const int a0 = 4; const int __maybe_unused a1 = 5; const int __maybe_unused a2 = 6; - u32 *p = tlbmiss_handler_setup_pgd_start; - const int tlbmiss_handler_setup_pgd_size = - tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; + u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd); #ifndef CONFIG_MIPS_PGD_C0_CONTEXT long pgdc = (long)pgd_current; #endif - memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * - sizeof(tlbmiss_handler_setup_pgd[0])); + memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); pgd_reg = allocate_kscratch(); @@ -1645,15 +1630,15 @@ static void build_setup_pgd(void) else uasm_i_nop(&p); #endif - if (p >= tlbmiss_handler_setup_pgd_end) + if (p >= (u32 *)tlbmiss_handler_setup_pgd_end) panic("tlbmiss_handler_setup_pgd space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", - (unsigned int)(p - tlbmiss_handler_setup_pgd)); + (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd)); dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, - tlbmiss_handler_setup_pgd_size); + tlbmiss_handler_setup_pgd_end); } static void @@ -1922,12 +1907,11 @@ build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, static void build_r3000_tlb_load_handler(void) { - u32 *p = handle_tlbl; - const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; + u32 *p = (u32 *)handle_tlbl; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; - memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); + memset(p, 0, handle_tlbl_end - (char *)p); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -1941,24 +1925,23 @@ static void build_r3000_tlb_load_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); uasm_i_nop(&p); - if (p >= handle_tlbl_end) + if (p >= (u32 *)handle_tlbl_end) panic("TLB load handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", - (unsigned int)(p - handle_tlbl)); + (unsigned int)(p - (u32 *)handle_tlbl)); - dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); + dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end); } static void build_r3000_tlb_store_handler(void) { - u32 *p = handle_tlbs; - const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; + u32 *p = (u32 *)handle_tlbs; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; - memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); + memset(p, 0, handle_tlbs_end - (char *)p); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -1972,24 +1955,23 @@ static void build_r3000_tlb_store_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if (p >= handle_tlbs_end) + if (p >= (u32 *)handle_tlbs_end) panic("TLB store handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", - (unsigned int)(p - handle_tlbs)); + (unsigned int)(p - (u32 *)handle_tlbs)); - dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); + dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end); } static void build_r3000_tlb_modify_handler(void) { - u32 *p = handle_tlbm; - const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; + u32 *p = (u32 *)handle_tlbm; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; - memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); + memset(p, 0, handle_tlbm_end - (char *)p); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -2003,14 +1985,14 @@ static void build_r3000_tlb_modify_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if (p >= handle_tlbm_end) + if (p >= (u32 *)handle_tlbm_end) panic("TLB modify handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", - (unsigned int)(p - handle_tlbm)); + (unsigned int)(p - (u32 *)handle_tlbm)); - dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); + dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end); } #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ @@ -2102,12 +2084,11 @@ build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, static void build_r4000_tlb_load_handler(void) { u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); - const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; struct work_registers wr; - memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); + memset(p, 0, handle_tlbl_end - (char *)p); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -2288,25 +2269,24 @@ static void build_r4000_tlb_load_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); uasm_i_nop(&p); - if (p >= handle_tlbl_end) + if (p >= (u32 *)handle_tlbl_end) panic("TLB load handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", - (unsigned int)(p - handle_tlbl)); + (unsigned int)(p - (u32 *)handle_tlbl)); - dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); + dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end); } static void build_r4000_tlb_store_handler(void) { u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); - const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; struct work_registers wr; - memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); + memset(p, 0, handle_tlbs_end - (char *)p); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -2343,25 +2323,24 @@ static void build_r4000_tlb_store_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if (p >= handle_tlbs_end) + if (p >= (u32 *)handle_tlbs_end) panic("TLB store handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", - (unsigned int)(p - handle_tlbs)); + (unsigned int)(p - (u32 *)handle_tlbs)); - dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); + dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end); } static void build_r4000_tlb_modify_handler(void) { u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); - const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; struct uasm_label *l = labels; struct uasm_reloc *r = relocs; struct work_registers wr; - memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); + memset(p, 0, handle_tlbm_end - (char *)p); memset(labels, 0, sizeof(labels)); memset(relocs, 0, sizeof(relocs)); @@ -2399,14 +2378,14 @@ static void build_r4000_tlb_modify_handler(void) uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); uasm_i_nop(&p); - if (p >= handle_tlbm_end) + if (p >= (u32 *)handle_tlbm_end) panic("TLB modify handler fastpath space exceeded"); uasm_resolve_relocs(relocs, labels); pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", - (unsigned int)(p - handle_tlbm)); + (unsigned int)(p - (u32 *)handle_tlbm)); - dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); + dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end); } static void flush_tlb_handlers(void) diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index ed5f32d8fbd8..e0081e734827 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -6,6 +6,8 @@ config OPENRISC def_bool y + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select DMA_NONCOHERENT_OPS select OF select OF_EARLY_FLATTREE select IRQ_DOMAIN diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild index 65964d390b10..eb87cd8327c8 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -7,6 +7,7 @@ generic-y += current.h generic-y += device.h generic-y += div64.h generic-y += dma.h +generic-y += dma-mapping.h generic-y += emergency-restart.h generic-y += exec.h generic-y += extable.h diff --git a/arch/openrisc/include/asm/dma-mapping.h b/arch/openrisc/include/asm/dma-mapping.h deleted file mode 100644 index e212a1f0b6d2..000000000000 --- a/arch/openrisc/include/asm/dma-mapping.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * OpenRISC Linux - * - * Linux architectural port borrowing liberally from similar works of - * others. All original copyrights apply as per the original source - * declaration. - * - * OpenRISC implementation: - * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __ASM_OPENRISC_DMA_MAPPING_H -#define __ASM_OPENRISC_DMA_MAPPING_H - -/* - * See Documentation/DMA-API-HOWTO.txt and - * Documentation/DMA-API.txt for documentation. - */ - -#include <linux/dma-debug.h> -#include <linux/dma-mapping.h> - -extern const struct dma_map_ops or1k_dma_map_ops; - -static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) -{ - return &or1k_dma_map_ops; -} - -#endif /* __ASM_OPENRISC_DMA_MAPPING_H */ diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c index ec7fd45704d2..159336adfa2f 100644 --- a/arch/openrisc/kernel/dma.c +++ b/arch/openrisc/kernel/dma.c @@ -19,9 +19,7 @@ * the only thing implemented properly. The rest need looking into... */ -#include <linux/dma-mapping.h> -#include <linux/dma-debug.h> -#include <linux/export.h> +#include <linux/dma-noncoherent.h> #include <asm/cpuinfo.h> #include <asm/spr_defs.h> @@ -80,10 +78,9 @@ page_clear_nocache(pte_t *pte, unsigned long addr, * is being ignored for now; uncached but write-combined memory is a * missing feature of the OR1K. */ -static void * -or1k_dma_alloc(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp, - unsigned long attrs) +void * +arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, + gfp_t gfp, unsigned long attrs) { unsigned long va; void *page; @@ -115,9 +112,9 @@ or1k_dma_alloc(struct device *dev, size_t size, return (void *)va; } -static void -or1k_dma_free(struct device *dev, size_t size, void *vaddr, - dma_addr_t dma_handle, unsigned long attrs) +void +arch_dma_free(struct device *dev, size_t size, void *vaddr, + dma_addr_t dma_handle, unsigned long attrs) { unsigned long va = (unsigned long)vaddr; struct mm_walk walk = { @@ -133,19 +130,12 @@ or1k_dma_free(struct device *dev, size_t size, void *vaddr, free_pages_exact(vaddr, size); } -static dma_addr_t -or1k_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, - enum dma_data_direction dir, - unsigned long attrs) +void arch_sync_dma_for_device(struct device *dev, phys_addr_t addr, size_t size, + enum dma_data_direction dir) { unsigned long cl; - dma_addr_t addr = page_to_phys(page) + offset; struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; - if (attrs & DMA_ATTR_SKIP_CPU_SYNC) - return addr; - switch (dir) { case DMA_TO_DEVICE: /* Flush the dcache for the requested range */ @@ -167,83 +157,4 @@ or1k_map_page(struct device *dev, struct page *page, */ break; } - - return addr; -} - -static void -or1k_unmap_page(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction dir, - unsigned long attrs) -{ - /* Nothing special to do here... */ -} - -static int -or1k_map_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir, - unsigned long attrs) -{ - struct scatterlist *s; - int i; - - for_each_sg(sg, s, nents, i) { - s->dma_address = or1k_map_page(dev, sg_page(s), s->offset, - s->length, dir, 0); - } - - return nents; } - -static void -or1k_unmap_sg(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir, - unsigned long attrs) -{ - struct scatterlist *s; - int i; - - for_each_sg(sg, s, nents, i) { - or1k_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, 0); - } -} - -static void -or1k_sync_single_for_cpu(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir) -{ - unsigned long cl; - dma_addr_t addr = dma_handle; - struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; - - /* Invalidate the dcache for the requested range */ - for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size) - mtspr(SPR_DCBIR, cl); -} - -static void -or1k_sync_single_for_device(struct device *dev, - dma_addr_t dma_handle, size_t size, - enum dma_data_direction dir) -{ - unsigned long cl; - dma_addr_t addr = dma_handle; - struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; - - /* Flush the dcache for the requested range */ - for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size) - mtspr(SPR_DCBFR, cl); -} - -const struct dma_map_ops or1k_dma_map_ops = { - .alloc = or1k_dma_alloc, - .free = or1k_dma_free, - .map_page = or1k_map_page, - .unmap_page = or1k_unmap_page, - .map_sg = or1k_map_sg, - .unmap_sg = or1k_unmap_sg, - .sync_single_for_cpu = or1k_sync_single_for_cpu, - .sync_single_for_device = or1k_sync_single_for_device, -}; -EXPORT_SYMBOL(or1k_dma_map_ops); diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 576ffdca06ba..efdbe311e936 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -1,6 +1,7 @@ generic-y += bugs.h generic-y += cacheflush.h generic-y += checksum.h +generic-y += compat.h generic-y += cputime.h generic-y += device.h generic-y += div64.h diff --git a/arch/riscv/include/asm/compat.h b/arch/riscv/include/asm/compat.h deleted file mode 100644 index 044aecff8854..000000000000 --- a/arch/riscv/include/asm/compat.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2012 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ -#ifndef __ASM_COMPAT_H -#define __ASM_COMPAT_H -#ifdef CONFIG_COMPAT - -#if defined(CONFIG_64BIT) -#define COMPAT_UTS_MACHINE "riscv64\0\0" -#elif defined(CONFIG_32BIT) -#define COMPAT_UTS_MACHINE "riscv32\0\0" -#else -#error "Unknown RISC-V base ISA" -#endif - -#endif /*CONFIG_COMPAT*/ -#endif /*__ASM_COMPAT_H*/ diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h index 080fb28061de..0caea01d5cca 100644 --- a/arch/riscv/include/asm/unistd.h +++ b/arch/riscv/include/asm/unistd.h @@ -11,6 +11,11 @@ * GNU General Public License for more details. */ +/* + * There is explicitly no include guard here because this file is expected to + * be included multiple times. See uapi/asm/syscalls.h for more info. + */ + #define __ARCH_WANT_SYS_CLONE #include <uapi/asm/unistd.h> #include <uapi/asm/syscalls.h> diff --git a/arch/riscv/include/asm/vdso.h b/arch/riscv/include/asm/vdso.h index 541544d64c33..ec6180a4b55d 100644 --- a/arch/riscv/include/asm/vdso.h +++ b/arch/riscv/include/asm/vdso.h @@ -38,8 +38,6 @@ struct vdso_data { (void __user *)((unsigned long)(base) + __vdso_##name); \ }) -#ifdef CONFIG_SMP asmlinkage long sys_riscv_flush_icache(uintptr_t, uintptr_t, uintptr_t); -#endif #endif /* _ASM_RISCV_VDSO_H */ diff --git a/arch/riscv/include/uapi/asm/syscalls.h b/arch/riscv/include/uapi/asm/syscalls.h index 818655b0d535..206dc4b0f6ea 100644 --- a/arch/riscv/include/uapi/asm/syscalls.h +++ b/arch/riscv/include/uapi/asm/syscalls.h @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2017 SiFive + * Copyright (C) 2017-2018 SiFive */ -#ifndef _ASM__UAPI__SYSCALLS_H -#define _ASM__UAPI__SYSCALLS_H +/* + * There is explicitly no include guard here because this file is expected to + * be included multiple times in order to define the syscall macros via + * __SYSCALL. + */ /* * Allows the instruction cache to be flushed from userspace. Despite RISC-V @@ -20,7 +23,7 @@ * caller. We don't currently do anything with the address range, that's just * in there for forwards compatibility. */ +#ifndef __NR_riscv_flush_icache #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) -__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) - #endif +__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index f7181ed8aafc..568026ccf6e8 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -48,7 +48,6 @@ SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, } #endif /* !CONFIG_64BIT */ -#ifdef CONFIG_SMP /* * Allows the instruction cache to be flushed from userspace. Despite RISC-V * having a direct 'fence.i' instruction available to userspace (which we @@ -66,15 +65,24 @@ SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, uintptr_t, flags) { +#ifdef CONFIG_SMP struct mm_struct *mm = current->mm; bool local = (flags & SYS_RISCV_FLUSH_ICACHE_LOCAL) != 0; +#endif /* Check the reserved flags. */ if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL)) return -EINVAL; + /* + * Without CONFIG_SMP flush_icache_mm is a just a flush_icache_all(), + * which generates unused variable warnings all over this function. + */ +#ifdef CONFIG_SMP flush_icache_mm(mm, local); +#else + flush_icache_all(); +#endif return 0; } -#endif diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 512003f16889..c5ff296bc5d1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -180,7 +180,8 @@ config X86 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP - select HAVE_RCU_TABLE_FREE + select HAVE_RCU_TABLE_FREE if PARAVIRT + select HAVE_RCU_TABLE_INVALIDATE if HAVE_RCU_TABLE_FREE select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RELIABLE_STACKTRACE if X86_64 && (UNWINDER_FRAME_POINTER || UNWINDER_ORC) && STACK_VALIDATION select HAVE_STACKPROTECTOR if CC_HAS_SANE_STACKPROTECTOR diff --git a/arch/x86/hyperv/mmu.c b/arch/x86/hyperv/mmu.c index 1147e1fed7ff..ef5f29f913d7 100644 --- a/arch/x86/hyperv/mmu.c +++ b/arch/x86/hyperv/mmu.c @@ -9,6 +9,7 @@ #include <asm/mshyperv.h> #include <asm/msr.h> #include <asm/tlbflush.h> +#include <asm/tlb.h> #define CREATE_TRACE_POINTS #include <asm/trace/hyperv.h> @@ -231,4 +232,5 @@ void hyperv_setup_mmu_ops(void) pr_info("Using hypercall for remote TLB flush\n"); pv_mmu_ops.flush_tlb_others = hyperv_flush_tlb_others; + pv_mmu_ops.tlb_remove_table = tlb_remove_table; } diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index d49bbf4bb5c8..e375d4266b53 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -309,6 +309,11 @@ static inline void flush_tlb_others(const struct cpumask *cpumask, PVOP_VCALL2(pv_mmu_ops.flush_tlb_others, cpumask, info); } +static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) +{ + PVOP_VCALL2(pv_mmu_ops.tlb_remove_table, tlb, table); +} + static inline int paravirt_pgd_alloc(struct mm_struct *mm) { return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm); diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 180bc0bff0fb..4b75acc23b30 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -54,6 +54,7 @@ struct desc_struct; struct task_struct; struct cpumask; struct flush_tlb_info; +struct mmu_gather; /* * Wrapper type for pointers to code which uses the non-standard @@ -222,6 +223,8 @@ struct pv_mmu_ops { void (*flush_tlb_others)(const struct cpumask *cpus, const struct flush_tlb_info *info); + void (*tlb_remove_table)(struct mmu_gather *tlb, void *table); + /* Hooks for allocating and freeing a pagetable top-level */ int (*pgd_alloc)(struct mm_struct *mm); void (*pgd_free)(struct mm_struct *mm, pgd_t *pgd); diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 511bf5fae8b8..29c9da6c62fc 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -148,6 +148,22 @@ static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid) #define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr) #endif +static inline bool tlb_defer_switch_to_init_mm(void) +{ + /* + * If we have PCID, then switching to init_mm is reasonably + * fast. If we don't have PCID, then switching to init_mm is + * quite slow, so we try to defer it in the hopes that we can + * avoid it entirely. The latter approach runs the risk of + * receiving otherwise unnecessary IPIs. + * + * This choice is just a heuristic. The tlb code can handle this + * function returning true or false regardless of whether we have + * PCID. + */ + return !static_cpu_has(X86_FEATURE_PCID); +} + struct tlb_context { u64 ctx_id; u64 tlb_gen; @@ -536,11 +552,9 @@ extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); #ifndef CONFIG_PARAVIRT #define flush_tlb_others(mask, info) \ native_flush_tlb_others(mask, info) -#endif -extern void tlb_flush_remove_tables(struct mm_struct *mm); -extern void tlb_flush_remove_tables_local(void *arg); - -#define HAVE_TLB_FLUSH_REMOVE_TABLES +#define paravirt_tlb_remove_table(tlb, page) \ + tlb_remove_page(tlb, (void *)(page)) +#endif #endif /* _ASM_X86_TLBFLUSH_H */ diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h index 6b2f90a0b149..ef05bea7010d 100644 --- a/arch/x86/include/asm/xen/hypercall.h +++ b/arch/x86/include/asm/xen/hypercall.h @@ -197,17 +197,6 @@ extern struct { char _entry[32]; } hypercall_page[]; (type)__res; \ }) -#define _hypercall5(type, name, a1, a2, a3, a4, a5) \ -({ \ - __HYPERCALL_DECLS; \ - __HYPERCALL_5ARG(a1, a2, a3, a4, a5); \ - asm volatile (__HYPERCALL \ - : __HYPERCALL_5PARAM \ - : __HYPERCALL_ENTRY(name) \ - : __HYPERCALL_CLOBBER5); \ - (type)__res; \ -}) - static inline long xen_single_call(unsigned int call, unsigned long a1, unsigned long a2, @@ -267,47 +256,12 @@ HYPERVISOR_set_gdt(unsigned long *frame_list, int entries) } static inline int -HYPERVISOR_stack_switch(unsigned long ss, unsigned long esp) -{ - return _hypercall2(int, stack_switch, ss, esp); -} - -#ifdef CONFIG_X86_32 -static inline int -HYPERVISOR_set_callbacks(unsigned long event_selector, - unsigned long event_address, - unsigned long failsafe_selector, - unsigned long failsafe_address) -{ - return _hypercall4(int, set_callbacks, - event_selector, event_address, - failsafe_selector, failsafe_address); -} -#else /* CONFIG_X86_64 */ -static inline int -HYPERVISOR_set_callbacks(unsigned long event_address, - unsigned long failsafe_address, - unsigned long syscall_address) -{ - return _hypercall3(int, set_callbacks, - event_address, failsafe_address, - syscall_address); -} -#endif /* CONFIG_X86_{32,64} */ - -static inline int HYPERVISOR_callback_op(int cmd, void *arg) { return _hypercall2(int, callback_op, cmd, arg); } static inline int -HYPERVISOR_fpu_taskswitch(int set) -{ - return _hypercall1(int, fpu_taskswitch, set); -} - -static inline int HYPERVISOR_sched_op(int cmd, void *arg) { return _hypercall2(int, sched_op, cmd, arg); @@ -419,19 +373,6 @@ HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count) } static inline int -HYPERVISOR_update_va_mapping_otherdomain(unsigned long va, pte_t new_val, - unsigned long flags, domid_t domid) -{ - if (sizeof(new_val) == sizeof(long)) - return _hypercall4(int, update_va_mapping_otherdomain, va, - new_val.pte, flags, domid); - else - return _hypercall5(int, update_va_mapping_otherdomain, va, - new_val.pte, new_val.pte >> 32, - flags, domid); -} - -static inline int HYPERVISOR_vm_assist(unsigned int cmd, unsigned int type) { return _hypercall2(int, vm_assist, cmd, type); @@ -465,12 +406,6 @@ HYPERVISOR_suspend(unsigned long start_info_mfn) return _hypercall3(int, sched_op, SCHEDOP_shutdown, &r, start_info_mfn); } -static inline int -HYPERVISOR_nmi_op(unsigned long op, unsigned long arg) -{ - return _hypercall2(int, nmi_op, op, arg); -} - static inline unsigned long __must_check HYPERVISOR_hvm_op(int op, void *arg) { @@ -529,39 +464,6 @@ MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va, } static inline void -MULTI_grant_table_op(struct multicall_entry *mcl, unsigned int cmd, - void *uop, unsigned int count) -{ - mcl->op = __HYPERVISOR_grant_table_op; - mcl->args[0] = cmd; - mcl->args[1] = (unsigned long)uop; - mcl->args[2] = count; - - trace_xen_mc_entry(mcl, 3); -} - -static inline void -MULTI_update_va_mapping_otherdomain(struct multicall_entry *mcl, unsigned long va, - pte_t new_val, unsigned long flags, - domid_t domid) -{ - mcl->op = __HYPERVISOR_update_va_mapping_otherdomain; - mcl->args[0] = va; - if (sizeof(new_val) == sizeof(long)) { - mcl->args[1] = new_val.pte; - mcl->args[2] = flags; - mcl->args[3] = domid; - } else { - mcl->args[1] = new_val.pte; - mcl->args[2] = new_val.pte >> 32; - mcl->args[3] = flags; - mcl->args[4] = domid; - } - - trace_xen_mc_entry(mcl, sizeof(new_val) == sizeof(long) ? 4 : 5); -} - -static inline void MULTI_update_descriptor(struct multicall_entry *mcl, u64 maddr, struct desc_struct desc) { @@ -582,16 +484,6 @@ MULTI_update_descriptor(struct multicall_entry *mcl, u64 maddr, } static inline void -MULTI_memory_op(struct multicall_entry *mcl, unsigned int cmd, void *arg) -{ - mcl->op = __HYPERVISOR_memory_op; - mcl->args[0] = cmd; - mcl->args[1] = (unsigned long)arg; - - trace_xen_mc_entry(mcl, 2); -} - -static inline void MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req, int count, int *success_count, domid_t domid) { @@ -618,16 +510,6 @@ MULTI_mmuext_op(struct multicall_entry *mcl, struct mmuext_op *op, int count, } static inline void -MULTI_set_gdt(struct multicall_entry *mcl, unsigned long *frames, int entries) -{ - mcl->op = __HYPERVISOR_set_gdt; - mcl->args[0] = (unsigned long)frames; - mcl->args[1] = entries; - - trace_xen_mc_entry(mcl, 2); -} - -static inline void MULTI_stack_switch(struct multicall_entry *mcl, unsigned long ss, unsigned long esp) { diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 0f471bd93417..d9b71924c23c 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -45,6 +45,7 @@ #include <asm/apic.h> #include <asm/apicdef.h> #include <asm/hypervisor.h> +#include <asm/tlb.h> static int kvmapf = 1; @@ -636,8 +637,10 @@ static void __init kvm_guest_init(void) if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH) && !kvm_para_has_hint(KVM_HINTS_REALTIME) && - kvm_para_has_feature(KVM_FEATURE_STEAL_TIME)) + kvm_para_has_feature(KVM_FEATURE_STEAL_TIME)) { pv_mmu_ops.flush_tlb_others = kvm_flush_tlb_others; + pv_mmu_ops.tlb_remove_table = tlb_remove_table; + } if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) apic_set_eoi_write(kvm_guest_apic_eoi_write); diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 930c88341e4e..afdb303285f8 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -41,6 +41,7 @@ #include <asm/tlbflush.h> #include <asm/timer.h> #include <asm/special_insns.h> +#include <asm/tlb.h> /* * nop stub, which must not clobber anything *including the stack* to @@ -409,6 +410,7 @@ struct pv_mmu_ops pv_mmu_ops __ro_after_init = { .flush_tlb_kernel = native_flush_tlb_global, .flush_tlb_one_user = native_flush_tlb_one_user, .flush_tlb_others = native_flush_tlb_others, + .tlb_remove_table = (void (*)(struct mmu_gather *, void *))tlb_remove_page, .pgd_alloc = __paravirt_pgd_alloc, .pgd_free = paravirt_nop, diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index acfab322fbe0..5c32a7665492 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -99,15 +99,22 @@ __ref void *alloc_low_pages(unsigned int num) } if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { - unsigned long ret; - if (min_pfn_mapped >= max_pfn_mapped) - panic("alloc_low_pages: ran out of memory"); - ret = memblock_find_in_range(min_pfn_mapped << PAGE_SHIFT, + unsigned long ret = 0; + + if (min_pfn_mapped < max_pfn_mapped) { + ret = memblock_find_in_range( + min_pfn_mapped << PAGE_SHIFT, max_pfn_mapped << PAGE_SHIFT, PAGE_SIZE * num , PAGE_SIZE); + } + if (ret) + memblock_reserve(ret, PAGE_SIZE * num); + else if (can_use_brk_pgt) + ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE)); + if (!ret) panic("alloc_low_pages: can not alloc memory"); - memblock_reserve(ret, PAGE_SIZE * num); + pfn = ret >> PAGE_SHIFT; } else { pfn = pgt_buf_end; diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 3ef095c70ae3..e848a4811785 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -63,7 +63,7 @@ void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) { pgtable_page_dtor(pte); paravirt_release_pte(page_to_pfn(pte)); - tlb_remove_table(tlb, pte); + paravirt_tlb_remove_table(tlb, pte); } #if CONFIG_PGTABLE_LEVELS > 2 @@ -79,21 +79,21 @@ void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) tlb->need_flush_all = 1; #endif pgtable_pmd_page_dtor(page); - tlb_remove_table(tlb, page); + paravirt_tlb_remove_table(tlb, page); } #if CONFIG_PGTABLE_LEVELS > 3 void ___pud_free_tlb(struct mmu_gather *tlb, pud_t *pud) { paravirt_release_pud(__pa(pud) >> PAGE_SHIFT); - tlb_remove_table(tlb, virt_to_page(pud)); + paravirt_tlb_remove_table(tlb, virt_to_page(pud)); } #if CONFIG_PGTABLE_LEVELS > 4 void ___p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d) { paravirt_release_p4d(__pa(p4d) >> PAGE_SHIFT); - tlb_remove_table(tlb, virt_to_page(p4d)); + paravirt_tlb_remove_table(tlb, virt_to_page(p4d)); } #endif /* CONFIG_PGTABLE_LEVELS > 4 */ #endif /* CONFIG_PGTABLE_LEVELS > 3 */ diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 752dbf4e0e50..9517d1b2a281 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -7,7 +7,6 @@ #include <linux/export.h> #include <linux/cpu.h> #include <linux/debugfs.h> -#include <linux/gfp.h> #include <asm/tlbflush.h> #include <asm/mmu_context.h> @@ -186,11 +185,8 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, { struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm); u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); - bool was_lazy = this_cpu_read(cpu_tlbstate.is_lazy); unsigned cpu = smp_processor_id(); u64 next_tlb_gen; - bool need_flush; - u16 new_asid; /* * NB: The scheduler will call us with prev == next when switching @@ -244,41 +240,20 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, next->context.ctx_id); /* - * Even in lazy TLB mode, the CPU should stay set in the - * mm_cpumask. The TLB shootdown code can figure out from - * from cpu_tlbstate.is_lazy whether or not to send an IPI. + * We don't currently support having a real mm loaded without + * our cpu set in mm_cpumask(). We have all the bookkeeping + * in place to figure out whether we would need to flush + * if our cpu were cleared in mm_cpumask(), but we don't + * currently use it. */ if (WARN_ON_ONCE(real_prev != &init_mm && !cpumask_test_cpu(cpu, mm_cpumask(next)))) cpumask_set_cpu(cpu, mm_cpumask(next)); - /* - * If the CPU is not in lazy TLB mode, we are just switching - * from one thread in a process to another thread in the same - * process. No TLB flush required. - */ - if (!was_lazy) - return; - - /* - * Read the tlb_gen to check whether a flush is needed. - * If the TLB is up to date, just use it. - * The barrier synchronizes with the tlb_gen increment in - * the TLB shootdown code. - */ - smp_mb(); - next_tlb_gen = atomic64_read(&next->context.tlb_gen); - if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) == - next_tlb_gen) - return; - - /* - * TLB contents went out of date while we were in lazy - * mode. Fall through to the TLB switching code below. - */ - new_asid = prev_asid; - need_flush = true; + return; } else { + u16 new_asid; + bool need_flush; u64 last_ctx_id = this_cpu_read(cpu_tlbstate.last_ctx_id); /* @@ -329,41 +304,41 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, next_tlb_gen = atomic64_read(&next->context.tlb_gen); choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); - } - if (need_flush) { - this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); - this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); - load_new_mm_cr3(next->pgd, new_asid, true); + if (need_flush) { + this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); + this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); + load_new_mm_cr3(next->pgd, new_asid, true); + + /* + * NB: This gets called via leave_mm() in the idle path + * where RCU functions differently. Tracing normally + * uses RCU, so we need to use the _rcuidle variant. + * + * (There is no good reason for this. The idle code should + * be rearranged to call this before rcu_idle_enter().) + */ + trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); + } else { + /* The new ASID is already up to date. */ + load_new_mm_cr3(next->pgd, new_asid, false); + + /* See above wrt _rcuidle. */ + trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0); + } /* - * NB: This gets called via leave_mm() in the idle path - * where RCU functions differently. Tracing normally - * uses RCU, so we need to use the _rcuidle variant. - * - * (There is no good reason for this. The idle code should - * be rearranged to call this before rcu_idle_enter().) + * Record last user mm's context id, so we can avoid + * flushing branch buffer with IBPB if we switch back + * to the same user. */ - trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); - } else { - /* The new ASID is already up to date. */ - load_new_mm_cr3(next->pgd, new_asid, false); + if (next != &init_mm) + this_cpu_write(cpu_tlbstate.last_ctx_id, next->context.ctx_id); - /* See above wrt _rcuidle. */ - trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0); + this_cpu_write(cpu_tlbstate.loaded_mm, next); + this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid); } - /* - * Record last user mm's context id, so we can avoid - * flushing branch buffer with IBPB if we switch back - * to the same user. - */ - if (next != &init_mm) - this_cpu_write(cpu_tlbstate.last_ctx_id, next->context.ctx_id); - - this_cpu_write(cpu_tlbstate.loaded_mm, next); - this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid); - load_mm_cr4(next); switch_ldt(real_prev, next); } @@ -386,7 +361,20 @@ void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) return; - this_cpu_write(cpu_tlbstate.is_lazy, true); + if (tlb_defer_switch_to_init_mm()) { + /* + * There's a significant optimization that may be possible + * here. We have accurate enough TLB flush tracking that we + * don't need to maintain coherence of TLB per se when we're + * lazy. We do, however, need to maintain coherence of + * paging-structure caches. We could, in principle, leave our + * old mm loaded and only switch to init_mm when + * tlb_remove_page() happens. + */ + this_cpu_write(cpu_tlbstate.is_lazy, true); + } else { + switch_mm(NULL, &init_mm, NULL); + } } /* @@ -473,9 +461,6 @@ static void flush_tlb_func_common(const struct flush_tlb_info *f, * paging-structure cache to avoid speculatively reading * garbage into our TLB. Since switching to init_mm is barely * slower than a minimal flush, just switch to init_mm. - * - * This should be rare, with native_flush_tlb_others skipping - * IPIs to lazy TLB mode CPUs. */ switch_mm_irqs_off(NULL, &init_mm, NULL); return; @@ -582,9 +567,6 @@ static void flush_tlb_func_remote(void *info) void native_flush_tlb_others(const struct cpumask *cpumask, const struct flush_tlb_info *info) { - cpumask_var_t lazymask; - unsigned int cpu; - count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); if (info->end == TLB_FLUSH_ALL) trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL); @@ -608,6 +590,8 @@ void native_flush_tlb_others(const struct cpumask *cpumask, * that UV should be updated so that smp_call_function_many(), * etc, are optimal on UV. */ + unsigned int cpu; + cpu = smp_processor_id(); cpumask = uv_flush_tlb_others(cpumask, info); if (cpumask) @@ -615,29 +599,8 @@ void native_flush_tlb_others(const struct cpumask *cpumask, (void *)info, 1); return; } - - /* - * A temporary cpumask is used in order to skip sending IPIs - * to CPUs in lazy TLB state, while keeping them in mm_cpumask(mm). - * If the allocation fails, simply IPI every CPU in mm_cpumask. - */ - if (!alloc_cpumask_var(&lazymask, GFP_ATOMIC)) { - smp_call_function_many(cpumask, flush_tlb_func_remote, - (void *)info, 1); - return; - } - - cpumask_copy(lazymask, cpumask); - - for_each_cpu(cpu, lazymask) { - if (per_cpu(cpu_tlbstate.is_lazy, cpu)) - cpumask_clear_cpu(cpu, lazymask); - } - - smp_call_function_many(lazymask, flush_tlb_func_remote, + smp_call_function_many(cpumask, flush_tlb_func_remote, (void *)info, 1); - - free_cpumask_var(lazymask); } /* @@ -690,68 +653,6 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, put_cpu(); } -void tlb_flush_remove_tables_local(void *arg) -{ - struct mm_struct *mm = arg; - - if (this_cpu_read(cpu_tlbstate.loaded_mm) == mm && - this_cpu_read(cpu_tlbstate.is_lazy)) { - /* - * We're in lazy mode. We need to at least flush our - * paging-structure cache to avoid speculatively reading - * garbage into our TLB. Since switching to init_mm is barely - * slower than a minimal flush, just switch to init_mm. - */ - switch_mm_irqs_off(NULL, &init_mm, NULL); - } -} - -static void mm_fill_lazy_tlb_cpu_mask(struct mm_struct *mm, - struct cpumask *lazy_cpus) -{ - int cpu; - - for_each_cpu(cpu, mm_cpumask(mm)) { - if (!per_cpu(cpu_tlbstate.is_lazy, cpu)) - cpumask_set_cpu(cpu, lazy_cpus); - } -} - -void tlb_flush_remove_tables(struct mm_struct *mm) -{ - int cpu = get_cpu(); - cpumask_var_t lazy_cpus; - - if (cpumask_any_but(mm_cpumask(mm), cpu) >= nr_cpu_ids) { - put_cpu(); - return; - } - - if (!zalloc_cpumask_var(&lazy_cpus, GFP_ATOMIC)) { - /* - * If the cpumask allocation fails, do a brute force flush - * on all the CPUs that have this mm loaded. - */ - smp_call_function_many(mm_cpumask(mm), - tlb_flush_remove_tables_local, (void *)mm, 1); - put_cpu(); - return; - } - - /* - * CPUs with !is_lazy either received a TLB flush IPI while the user - * pages in this address range were unmapped, or have context switched - * and reloaded %CR3 since then. - * - * Shootdown IPIs at page table freeing time only need to be sent to - * CPUs that may have out of date TLB contents. - */ - mm_fill_lazy_tlb_cpu_mask(mm, lazy_cpus); - smp_call_function_many(lazy_cpus, - tlb_flush_remove_tables_local, (void *)mm, 1); - free_cpumask_var(lazy_cpus); - put_cpu(); -} static void do_flush_tlb_all(void *info) { diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index ee3b00c7acda..52a7c3faee0c 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -122,6 +122,8 @@ static void __init xen_banner(void) static void __init xen_pv_init_platform(void) { + populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); + set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); @@ -1170,13 +1172,13 @@ static void __init xen_boot_params_init_edd(void) * we do this, we have to be careful not to call any stack-protected * function, which is most of the kernel. */ -static void xen_setup_gdt(int cpu) +static void __init xen_setup_gdt(int cpu) { pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry_boot; pv_cpu_ops.load_gdt = xen_load_gdt_boot; - setup_stack_canary_segment(0); - switch_to_new_gdt(0); + setup_stack_canary_segment(cpu); + switch_to_new_gdt(cpu); pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry; pv_cpu_ops.load_gdt = xen_load_gdt; @@ -1385,8 +1387,11 @@ asmlinkage __visible void __init xen_start_kernel(void) xen_boot_params_init_edd(); } - add_preferred_console("tty", 0, NULL); + if (!boot_params.screen_info.orig_video_isVGA) + add_preferred_console("tty", 0, NULL); add_preferred_console("hvc", 0, NULL); + if (boot_params.screen_info.orig_video_isVGA) + add_preferred_console("tty", 0, NULL); #ifdef CONFIG_PCI /* PCI BIOS service won't work from a PV guest. */ diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c index 52206ad81e4b..45b700ac5fe7 100644 --- a/arch/x86/xen/mmu_pv.c +++ b/arch/x86/xen/mmu_pv.c @@ -67,6 +67,7 @@ #include <asm/init.h> #include <asm/pat.h> #include <asm/smp.h> +#include <asm/tlb.h> #include <asm/xen/hypercall.h> #include <asm/xen/hypervisor.h> @@ -2171,6 +2172,8 @@ void __init xen_relocate_p2m(void) #else /* !CONFIG_X86_64 */ static RESERVE_BRK_ARRAY(pmd_t, initial_kernel_pmd, PTRS_PER_PMD); static RESERVE_BRK_ARRAY(pmd_t, swapper_kernel_pmd, PTRS_PER_PMD); +RESERVE_BRK(fixup_kernel_pmd, PAGE_SIZE); +RESERVE_BRK(fixup_kernel_pte, PAGE_SIZE); static void __init xen_write_cr3_init(unsigned long cr3) { @@ -2397,6 +2400,7 @@ static const struct pv_mmu_ops xen_mmu_ops __initconst = { .flush_tlb_kernel = xen_flush_tlb, .flush_tlb_one_user = xen_flush_tlb_one_user, .flush_tlb_others = xen_flush_tlb_others, + .tlb_remove_table = tlb_remove_table, .pgd_alloc = xen_pgd_alloc, .pgd_free = xen_pgd_free, diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index 6e0d2086eacb..1163e33121fb 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -906,37 +906,6 @@ char * __init xen_memory_setup(void) } /* - * Machine specific memory setup for auto-translated guests. - */ -char * __init xen_auto_xlated_memory_setup(void) -{ - struct xen_memory_map memmap; - int i; - int rc; - - memmap.nr_entries = ARRAY_SIZE(xen_e820_table.entries); - set_xen_guest_handle(memmap.buffer, xen_e820_table.entries); - - rc = HYPERVISOR_memory_op(XENMEM_memory_map, &memmap); - if (rc < 0) - panic("No memory map (%d)\n", rc); - - xen_e820_table.nr_entries = memmap.nr_entries; - - e820__update_table(&xen_e820_table); - - for (i = 0; i < xen_e820_table.nr_entries; i++) - e820__range_add(xen_e820_table.entries[i].addr, xen_e820_table.entries[i].size, xen_e820_table.entries[i].type); - - /* Remove p2m info, it is not needed. */ - xen_start_info->mfn_list = 0; - xen_start_info->first_p2m_pfn = 0; - xen_start_info->nr_p2m_frames = 0; - - return "Xen"; -} - -/* * Set the bit indicating "nosegneg" library variants should be used. * We only need to bother in pure 32-bit mode; compat 32-bit processes * can have un-truncated segments, so wrapping around is allowed. diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h index e78684597f57..0e60bd918695 100644 --- a/arch/x86/xen/xen-ops.h +++ b/arch/x86/xen/xen-ops.h @@ -50,7 +50,6 @@ void __init xen_inv_extra_mem(void); void __init xen_remap_memory(void); phys_addr_t __init xen_find_free_area(phys_addr_t size); char * __init xen_memory_setup(void); -char * xen_auto_xlated_memory_setup(void); void __init xen_arch_setup(void); void xen_enable_sysenter(void); void xen_enable_syscall(void); diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index b933061b6b60..8c0a54d50d0e 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -205,6 +205,7 @@ phys_cpuid_t acpi_get_phys_id(acpi_handle handle, int type, u32 acpi_id) return phys_id; } +EXPORT_SYMBOL_GPL(acpi_get_phys_id); int acpi_map_cpuid(phys_cpuid_t phys_id, u32 acpi_id) { diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c index 99f9a895a459..564570ea3e27 100644 --- a/drivers/ata/ahci_platform.c +++ b/drivers/ata/ahci_platform.c @@ -75,7 +75,6 @@ static const struct of_device_id ahci_of_match[] = { { .compatible = "generic-ahci", }, /* Keep the following compatibles for device tree compatibility */ { .compatible = "snps,spear-ahci", }, - { .compatible = "snps,exynos5440-ahci", }, { .compatible = "ibm,476gtr-ahci", }, { .compatible = "snps,dwc-ahci", }, { .compatible = "hisilicon,hisi-ahci", }, diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index d1c0b60e9326..1851112ccc29 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -103,6 +103,16 @@ config SIMPLE_PM_BUS Controller (BSC, sometimes called "LBSC within Bus Bridge", or "External Bus Interface") as found on several Renesas ARM SoCs. +config SUN50I_DE2_BUS + bool "Allwinner A64 DE2 Bus Driver" + default ARM64 + depends on ARCH_SUNXI + select SUNXI_SRAM + help + Say y here to enable support for Allwinner A64 DE2 bus driver. It's + mostly transparent, but a SRAM region needs to be claimed in the SRAM + controller to make the all blocks in the DE2 part accessible. + config SUNXI_RSB tristate "Allwinner sunXi Reduced Serial Bus Driver" default MACH_SUN8I || MACH_SUN9I || ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index b8f036cca7ff..ca300b1914ce 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o +obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o diff --git a/drivers/bus/sun50i-de2.c b/drivers/bus/sun50i-de2.c new file mode 100644 index 000000000000..672518741f86 --- /dev/null +++ b/drivers/bus/sun50i-de2.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner A64 Display Engine 2.0 Bus Driver + * + * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io> + */ + +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/soc/sunxi/sunxi_sram.h> + +static int sun50i_de2_bus_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + int ret; + + ret = sunxi_sram_claim(&pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Error couldn't map SRAM to device\n"); + return ret; + } + + of_platform_populate(np, NULL, NULL, &pdev->dev); + + return 0; +} + +static int sun50i_de2_bus_remove(struct platform_device *pdev) +{ + sunxi_sram_release(&pdev->dev); + return 0; +} + +static const struct of_device_id sun50i_de2_bus_of_match[] = { + { .compatible = "allwinner,sun50i-a64-de2", }, + { /* sentinel */ } +}; + +static struct platform_driver sun50i_de2_bus_driver = { + .probe = sun50i_de2_bus_probe, + .remove = sun50i_de2_bus_remove, + .driver = { + .name = "sun50i-de2-bus", + .of_match_table = sun50i_de2_bus_of_match, + }, +}; + +builtin_platform_driver(sun50i_de2_bus_driver); diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 80d60f43db56..c9bac9dc4637 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -23,11 +23,14 @@ #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/slab.h> +#include <linux/iopoll.h> #include <linux/platform_data/ti-sysc.h> #include <dt-bindings/bus/ti-sysc.h> +#define MAX_MODULE_SOFTRESET_WAIT 10000 + static const char * const reg_names[] = { "rev", "sysc", "syss", }; enum sysc_clocks { @@ -88,6 +91,11 @@ struct sysc { struct delayed_work idle_work; }; +void sysc_write(struct sysc *ddata, int offset, u32 value) +{ + writel_relaxed(value, ddata->module_va + offset); +} + static u32 sysc_read(struct sysc *ddata, int offset) { if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { @@ -943,6 +951,36 @@ static void sysc_init_revision_quirks(struct sysc *ddata) } } +static int sysc_reset(struct sysc *ddata) +{ + int offset = ddata->offsets[SYSC_SYSCONFIG]; + int val; + + if (ddata->legacy_mode || offset < 0 || + ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) + return 0; + + /* + * Currently only support reset status in sysstatus. + * Warn and return error in all other cases + */ + if (!ddata->cfg.syss_mask) { + dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n"); + return -EINVAL; + } + + val = sysc_read(ddata, offset); + val |= (0x1 << ddata->cap->regbits->srst_shift); + sysc_write(ddata, offset, val); + + /* Poll on reset status */ + offset = ddata->offsets[SYSC_SYSSTATUS]; + + return readl_poll_timeout(ddata->module_va + offset, val, + (val & ddata->cfg.syss_mask) == 0x0, + 100, MAX_MODULE_SOFTRESET_WAIT); +} + /* At this point the module is configured enough to read the revision */ static int sysc_init_module(struct sysc *ddata) { @@ -960,6 +998,14 @@ static int sysc_init_module(struct sysc *ddata) return 0; } + error = sysc_reset(ddata); + if (error) { + dev_err(ddata->dev, "Reset failed with %d\n", error); + pm_runtime_put_sync(ddata->dev); + + return error; + } + ddata->revision = sysc_read_revision(ddata); pm_runtime_put_sync(ddata->dev); @@ -1552,6 +1598,23 @@ static const struct sysc_capabilities sysc_omap4_usb_host_fs = { .regbits = &sysc_regbits_omap4_usb_host_fs, }; +static const struct sysc_regbits sysc_regbits_dra7_mcan = { + .dmadisable_shift = -ENODEV, + .midle_shift = -ENODEV, + .sidle_shift = -ENODEV, + .clkact_shift = -ENODEV, + .enwkup_shift = 4, + .srst_shift = 0, + .emufree_shift = -ENODEV, + .autoidle_shift = -ENODEV, +}; + +static const struct sysc_capabilities sysc_dra7_mcan = { + .type = TI_SYSC_DRA7_MCAN, + .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, + .regbits = &sysc_regbits_dra7_mcan, +}; + static int sysc_init_pdata(struct sysc *ddata) { struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); @@ -1743,6 +1806,7 @@ static const struct of_device_id sysc_match[] = { { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, { .compatible = "ti,sysc-usb-host-fs", .data = &sysc_omap4_usb_host_fs, }, + { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, { }, }; MODULE_DEVICE_TABLE(of, sysc_match); diff --git a/drivers/clk/davinci/psc-da830.c b/drivers/clk/davinci/psc-da830.c index 081b039fcb02..6481337382a6 100644 --- a/drivers/clk/davinci/psc-da830.c +++ b/drivers/clk/davinci/psc-da830.c @@ -14,6 +14,7 @@ #include "psc.h" +LPSC_CLKDEV1(aemif_clkdev, NULL, "ti-aemif"); LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0"); LPSC_CLKDEV1(mmcsd_clkdev, NULL, "da830-mmc.0"); LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); @@ -22,7 +23,7 @@ static const struct davinci_lpsc_clk_info da830_psc0_info[] = { LPSC(0, 0, tpcc, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(3, 0, aemif, pll0_sysclk3, NULL, LPSC_ALWAYS_ENABLED), + LPSC(3, 0, aemif, pll0_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED), LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0), LPSC(5, 0, mmcsd, pll0_sysclk2, mmcsd_clkdev, 0), LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), diff --git a/drivers/clk/davinci/psc-da850.c b/drivers/clk/davinci/psc-da850.c index d196dcbed560..5a18bca464cd 100644 --- a/drivers/clk/davinci/psc-da850.c +++ b/drivers/clk/davinci/psc-da850.c @@ -16,8 +16,7 @@ #include "psc.h" -LPSC_CLKDEV2(emifa_clkdev, NULL, "ti-aemif", - "aemif", "davinci_nand.0"); +LPSC_CLKDEV1(emifa_clkdev, NULL, "ti-aemif"); LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0"); LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0"); LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); diff --git a/drivers/clk/davinci/psc-dm365.c b/drivers/clk/davinci/psc-dm365.c index 8c73086cc676..c75424f4ea3b 100644 --- a/drivers/clk/davinci/psc-dm365.c +++ b/drivers/clk/davinci/psc-dm365.c @@ -21,7 +21,8 @@ LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1"); LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp"); LPSC_CLKDEV1(usb_clkdev, "usb", NULL); LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2"); -LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL); +LPSC_CLKDEV2(aemif_clkdev, "aemif", NULL, + NULL, "ti-aemif"); LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0"); LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1"); LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); diff --git a/drivers/clk/davinci/psc-dm644x.c b/drivers/clk/davinci/psc-dm644x.c index fc0230e3a3d6..0cea6e0bd5f0 100644 --- a/drivers/clk/davinci/psc-dm644x.c +++ b/drivers/clk/davinci/psc-dm644x.c @@ -21,7 +21,8 @@ LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1", "fck", "davinci_mdio.0"); LPSC_CLKDEV1(usb_clkdev, "usb", NULL); LPSC_CLKDEV1(ide_clkdev, NULL, "palm_bk3710"); -LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL); +LPSC_CLKDEV2(aemif_clkdev, "aemif", NULL, + NULL, "ti-aemif"); LPSC_CLKDEV1(mmcsd_clkdev, NULL, "dm6441-mmc.0"); LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp"); LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1"); diff --git a/drivers/clk/davinci/psc-dm646x.c b/drivers/clk/davinci/psc-dm646x.c index c3f82ed70a80..20012dc7471a 100644 --- a/drivers/clk/davinci/psc-dm646x.c +++ b/drivers/clk/davinci/psc-dm646x.c @@ -18,7 +18,8 @@ LPSC_CLKDEV1(ide_clkdev, NULL, "palm_bk3710"); LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1", "fck", "davinci_mdio.0"); -LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL); +LPSC_CLKDEV2(aemif_clkdev, "aemif", NULL, + NULL, "ti-aemif"); LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0"); LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1"); LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 513826393158..1a4e6b787978 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5-subcmu.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o -obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c deleted file mode 100644 index b08bd54c5e76..000000000000 --- a/drivers/clk/samsung/clk-exynos5440.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Thomas Abraham <thomas.ab@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Common Clock Framework support for Exynos5440 SoC. -*/ - -#include <dt-bindings/clock/exynos5440.h> -#include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/notifier.h> -#include <linux/reboot.h> - -#include "clk.h" -#include "clk-pll.h" - -#define CLKEN_OV_VAL 0xf8 -#define CPU_CLK_STATUS 0xfc -#define MISC_DOUT1 0x558 - -static void __iomem *reg_base; - -/* parent clock name list */ -PNAME(mout_armclk_p) = { "cplla", "cpllb" }; -PNAME(mout_spi_p) = { "div125", "div200" }; - -/* fixed rate clocks generated outside the soc */ -static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { - FRATE(0, "xtal", NULL, 0, 0), -}; - -/* fixed rate clocks */ -static const struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initconst = { - FRATE(0, "ppll", NULL, 0, 1000000000), - FRATE(0, "usb_phy0", NULL, 0, 60000000), - FRATE(0, "usb_phy1", NULL, 0, 60000000), - FRATE(0, "usb_ohci12", NULL, 0, 12000000), - FRATE(0, "usb_ohci48", NULL, 0, 48000000), -}; - -/* fixed factor clocks */ -static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initconst = { - FFACTOR(0, "div250", "ppll", 1, 4, 0), - FFACTOR(0, "div200", "ppll", 1, 5, 0), - FFACTOR(0, "div125", "div250", 1, 2, 0), -}; - -/* mux clocks */ -static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = { - MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), - MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1), -}; - -/* divider clocks */ -static const struct samsung_div_clock exynos5440_div_clks[] __initconst = { - DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), -}; - -/* gate clocks */ -static const struct samsung_gate_clock exynos5440_gate_clks[] __initconst = { - GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), - GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), - GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), - GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0), - GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0), - GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0), - GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0), - GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0), - GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0), - GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0), - GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0), - GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0), - GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0), - GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0), - GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0), - GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0), - GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0), - GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0), - GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0), - GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), -}; - -static const struct of_device_id ext_clk_match[] __initconst = { - { .compatible = "samsung,clock-xtal", .data = (void *)0, }, - {}, -}; - -static int exynos5440_clk_restart_notify(struct notifier_block *this, - unsigned long code, void *unused) -{ - u32 val, status; - - status = readl_relaxed(reg_base + 0xbc); - val = readl_relaxed(reg_base + 0xcc); - val = (val & 0xffff0000) | (status & 0xffff); - writel_relaxed(val, reg_base + 0xcc); - - return NOTIFY_DONE; -} - -/* - * Exynos5440 Clock restart notifier, handles restart functionality - */ -static struct notifier_block exynos5440_clk_restart_handler = { - .notifier_call = exynos5440_clk_restart_notify, - .priority = 128, -}; - -static const struct samsung_pll_clock exynos5440_plls[] __initconst = { - PLL(pll_2550x, CLK_CPLLA, "cplla", "xtal", 0, 0x4c, NULL), - PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL), -}; - -/* - * Clock aliases for legacy clkdev look-up. - */ -static const struct samsung_clock_alias exynos5440_aliases[] __initconst = { - ALIAS(CLK_ARM_CLK, NULL, "armclk"), -}; - -/* register exynos5440 clocks */ -static void __init exynos5440_clk_init(struct device_node *np) -{ - struct samsung_clk_provider *ctx; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: failed to map clock controller registers," - " aborting clock initialization\n", __func__); - return; - } - - ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); - - samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks, - ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); - - samsung_clk_register_pll(ctx, exynos5440_plls, - ARRAY_SIZE(exynos5440_plls), ctx->reg_base); - - samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks, - ARRAY_SIZE(exynos5440_fixed_rate_clks)); - samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks, - ARRAY_SIZE(exynos5440_fixed_factor_clks)); - samsung_clk_register_mux(ctx, exynos5440_mux_clks, - ARRAY_SIZE(exynos5440_mux_clks)); - samsung_clk_register_div(ctx, exynos5440_div_clks, - ARRAY_SIZE(exynos5440_div_clks)); - samsung_clk_register_gate(ctx, exynos5440_gate_clks, - ARRAY_SIZE(exynos5440_gate_clks)); - samsung_clk_register_alias(ctx, exynos5440_aliases, - ARRAY_SIZE(exynos5440_aliases)); - - samsung_clk_of_add_provider(np, ctx); - - if (register_restart_handler(&exynos5440_clk_restart_handler)) - pr_warn("exynos5440 clock can't register restart handler\n"); - - pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); - pr_info("exynos5440 clock initialization complete\n"); -} -CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init); diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index fb249a1637a5..71a122b2dc67 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -708,6 +708,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" }, { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" }, + { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"}, { 0 }, }; diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 52f5f1a2040c..0cd8eb76ad59 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -71,20 +71,6 @@ config ARM_BRCMSTB_AVS_CPUFREQ Say Y, if you have a Broadcom SoC with AVS support for DFS or DVFS. -config ARM_EXYNOS5440_CPUFREQ - tristate "SAMSUNG EXYNOS5440" - depends on SOC_EXYNOS5440 - depends on HAVE_CLK && OF - select PM_OPP - default y - help - This adds the CPUFreq driver for Samsung EXYNOS5440 - SoC. The nature of exynos5440 clock controller is - different than previous exynos controllers so not using - the common exynos framework. - - If in doubt, say N. - config ARM_HIGHBANK_CPUFREQ tristate "Calxeda Highbank-based" depends on ARCH_HIGHBANK && CPUFREQ_DT && REGULATOR diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index fb4a2ecac43b..c1ffeabe4ecf 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -56,7 +56,6 @@ obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c deleted file mode 100644 index 932caa386ece..000000000000 --- a/drivers/cpufreq/exynos5440-cpufreq.c +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Amit Daniel Kachhap <amit.daniel@samsung.com> - * - * EXYNOS5440 - CPU frequency scaling support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/clk.h> -#include <linux/cpu.h> -#include <linux/cpufreq.h> -#include <linux/err.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/pm_opp.h> -#include <linux/platform_device.h> -#include <linux/slab.h> - -/* Register definitions */ -#define XMU_DVFS_CTRL 0x0060 -#define XMU_PMU_P0_7 0x0064 -#define XMU_C0_3_PSTATE 0x0090 -#define XMU_P_LIMIT 0x00a0 -#define XMU_P_STATUS 0x00a4 -#define XMU_PMUEVTEN 0x00d0 -#define XMU_PMUIRQEN 0x00d4 -#define XMU_PMUIRQ 0x00d8 - -/* PMU mask and shift definations */ -#define P_VALUE_MASK 0x7 - -#define XMU_DVFS_CTRL_EN_SHIFT 0 - -#define P0_7_CPUCLKDEV_SHIFT 21 -#define P0_7_CPUCLKDEV_MASK 0x7 -#define P0_7_ATBCLKDEV_SHIFT 18 -#define P0_7_ATBCLKDEV_MASK 0x7 -#define P0_7_CSCLKDEV_SHIFT 15 -#define P0_7_CSCLKDEV_MASK 0x7 -#define P0_7_CPUEMA_SHIFT 28 -#define P0_7_CPUEMA_MASK 0xf -#define P0_7_L2EMA_SHIFT 24 -#define P0_7_L2EMA_MASK 0xf -#define P0_7_VDD_SHIFT 8 -#define P0_7_VDD_MASK 0x7f -#define P0_7_FREQ_SHIFT 0 -#define P0_7_FREQ_MASK 0xff - -#define C0_3_PSTATE_VALID_SHIFT 8 -#define C0_3_PSTATE_CURR_SHIFT 4 -#define C0_3_PSTATE_NEW_SHIFT 0 - -#define PSTATE_CHANGED_EVTEN_SHIFT 0 - -#define PSTATE_CHANGED_IRQEN_SHIFT 0 - -#define PSTATE_CHANGED_SHIFT 0 - -/* some constant values for clock divider calculation */ -#define CPU_DIV_FREQ_MAX 500 -#define CPU_DBG_FREQ_MAX 375 -#define CPU_ATB_FREQ_MAX 500 - -#define PMIC_LOW_VOLT 0x30 -#define PMIC_HIGH_VOLT 0x28 - -#define CPUEMA_HIGH 0x2 -#define CPUEMA_MID 0x4 -#define CPUEMA_LOW 0x7 - -#define L2EMA_HIGH 0x1 -#define L2EMA_MID 0x3 -#define L2EMA_LOW 0x4 - -#define DIV_TAB_MAX 2 -/* frequency unit is 20MHZ */ -#define FREQ_UNIT 20 -#define MAX_VOLTAGE 1550000 /* In microvolt */ -#define VOLTAGE_STEP 12500 /* In microvolt */ - -#define CPUFREQ_NAME "exynos5440_dvfs" -#define DEF_TRANS_LATENCY 100000 - -enum cpufreq_level_index { - L0, L1, L2, L3, L4, - L5, L6, L7, L8, L9, -}; -#define CPUFREQ_LEVEL_END (L7 + 1) - -struct exynos_dvfs_data { - void __iomem *base; - struct resource *mem; - int irq; - struct clk *cpu_clk; - unsigned int latency; - struct cpufreq_frequency_table *freq_table; - unsigned int freq_count; - struct device *dev; - bool dvfs_enabled; - struct work_struct irq_work; -}; - -static struct exynos_dvfs_data *dvfs_info; -static DEFINE_MUTEX(cpufreq_lock); -static struct cpufreq_freqs freqs; - -static int init_div_table(void) -{ - struct cpufreq_frequency_table *pos, *freq_tbl = dvfs_info->freq_table; - unsigned int tmp, clk_div, ema_div, freq, volt_id, idx; - struct dev_pm_opp *opp; - - cpufreq_for_each_entry_idx(pos, freq_tbl, idx) { - opp = dev_pm_opp_find_freq_exact(dvfs_info->dev, - pos->frequency * 1000, true); - if (IS_ERR(opp)) { - dev_err(dvfs_info->dev, - "failed to find valid OPP for %u KHZ\n", - pos->frequency); - return PTR_ERR(opp); - } - - freq = pos->frequency / 1000; /* In MHZ */ - clk_div = ((freq / CPU_DIV_FREQ_MAX) & P0_7_CPUCLKDEV_MASK) - << P0_7_CPUCLKDEV_SHIFT; - clk_div |= ((freq / CPU_ATB_FREQ_MAX) & P0_7_ATBCLKDEV_MASK) - << P0_7_ATBCLKDEV_SHIFT; - clk_div |= ((freq / CPU_DBG_FREQ_MAX) & P0_7_CSCLKDEV_MASK) - << P0_7_CSCLKDEV_SHIFT; - - /* Calculate EMA */ - volt_id = dev_pm_opp_get_voltage(opp); - - volt_id = (MAX_VOLTAGE - volt_id) / VOLTAGE_STEP; - if (volt_id < PMIC_HIGH_VOLT) { - ema_div = (CPUEMA_HIGH << P0_7_CPUEMA_SHIFT) | - (L2EMA_HIGH << P0_7_L2EMA_SHIFT); - } else if (volt_id > PMIC_LOW_VOLT) { - ema_div = (CPUEMA_LOW << P0_7_CPUEMA_SHIFT) | - (L2EMA_LOW << P0_7_L2EMA_SHIFT); - } else { - ema_div = (CPUEMA_MID << P0_7_CPUEMA_SHIFT) | - (L2EMA_MID << P0_7_L2EMA_SHIFT); - } - - tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT) - | ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT)); - - __raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * idx); - dev_pm_opp_put(opp); - } - - return 0; -} - -static void exynos_enable_dvfs(unsigned int cur_frequency) -{ - unsigned int tmp, cpu; - struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table; - struct cpufreq_frequency_table *pos; - /* Disable DVFS */ - __raw_writel(0, dvfs_info->base + XMU_DVFS_CTRL); - - /* Enable PSTATE Change Event */ - tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN); - tmp |= (1 << PSTATE_CHANGED_EVTEN_SHIFT); - __raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN); - - /* Enable PSTATE Change IRQ */ - tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN); - tmp |= (1 << PSTATE_CHANGED_IRQEN_SHIFT); - __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN); - - /* Set initial performance index */ - cpufreq_for_each_entry(pos, freq_table) - if (pos->frequency == cur_frequency) - break; - - if (pos->frequency == CPUFREQ_TABLE_END) { - dev_crit(dvfs_info->dev, "Boot up frequency not supported\n"); - /* Assign the highest frequency */ - pos = freq_table; - cur_frequency = pos->frequency; - } - - dev_info(dvfs_info->dev, "Setting dvfs initial frequency = %uKHZ", - cur_frequency); - - for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) { - tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4); - tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT); - tmp |= ((pos - freq_table) << C0_3_PSTATE_NEW_SHIFT); - __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4); - } - - /* Enable DVFS */ - __raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT, - dvfs_info->base + XMU_DVFS_CTRL); -} - -static int exynos_target(struct cpufreq_policy *policy, unsigned int index) -{ - unsigned int tmp; - int i; - struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table; - - mutex_lock(&cpufreq_lock); - - freqs.old = policy->cur; - freqs.new = freq_table[index].frequency; - - cpufreq_freq_transition_begin(policy, &freqs); - - /* Set the target frequency in all C0_3_PSTATE register */ - for_each_cpu(i, policy->cpus) { - tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4); - tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT); - tmp |= (index << C0_3_PSTATE_NEW_SHIFT); - - __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4); - } - mutex_unlock(&cpufreq_lock); - return 0; -} - -static void exynos_cpufreq_work(struct work_struct *work) -{ - unsigned int cur_pstate, index; - struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */ - struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table; - - /* Ensure we can access cpufreq structures */ - if (unlikely(dvfs_info->dvfs_enabled == false)) - goto skip_work; - - mutex_lock(&cpufreq_lock); - freqs.old = policy->cur; - - cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS); - if (cur_pstate >> C0_3_PSTATE_VALID_SHIFT & 0x1) - index = (cur_pstate >> C0_3_PSTATE_CURR_SHIFT) & P_VALUE_MASK; - else - index = (cur_pstate >> C0_3_PSTATE_NEW_SHIFT) & P_VALUE_MASK; - - if (likely(index < dvfs_info->freq_count)) { - freqs.new = freq_table[index].frequency; - } else { - dev_crit(dvfs_info->dev, "New frequency out of range\n"); - freqs.new = freqs.old; - } - cpufreq_freq_transition_end(policy, &freqs, 0); - - cpufreq_cpu_put(policy); - mutex_unlock(&cpufreq_lock); -skip_work: - enable_irq(dvfs_info->irq); -} - -static irqreturn_t exynos_cpufreq_irq(int irq, void *id) -{ - unsigned int tmp; - - tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ); - if (tmp >> PSTATE_CHANGED_SHIFT & 0x1) { - __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ); - disable_irq_nosync(irq); - schedule_work(&dvfs_info->irq_work); - } - return IRQ_HANDLED; -} - -static void exynos_sort_descend_freq_table(void) -{ - struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table; - int i = 0, index; - unsigned int tmp_freq; - /* - * Exynos5440 clock controller state logic expects the cpufreq table to - * be in descending order. But the OPP library constructs the table in - * ascending order. So to make the table descending we just need to - * swap the i element with the N - i element. - */ - for (i = 0; i < dvfs_info->freq_count / 2; i++) { - index = dvfs_info->freq_count - i - 1; - tmp_freq = freq_tbl[i].frequency; - freq_tbl[i].frequency = freq_tbl[index].frequency; - freq_tbl[index].frequency = tmp_freq; - } -} - -static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) -{ - policy->clk = dvfs_info->cpu_clk; - return cpufreq_generic_init(policy, dvfs_info->freq_table, - dvfs_info->latency); -} - -static struct cpufreq_driver exynos_driver = { - .flags = CPUFREQ_STICKY | CPUFREQ_ASYNC_NOTIFICATION | - CPUFREQ_NEED_INITIAL_FREQ_CHECK, - .verify = cpufreq_generic_frequency_table_verify, - .target_index = exynos_target, - .get = cpufreq_generic_get, - .init = exynos_cpufreq_cpu_init, - .name = CPUFREQ_NAME, - .attr = cpufreq_generic_attr, -}; - -static const struct of_device_id exynos_cpufreq_match[] = { - { - .compatible = "samsung,exynos5440-cpufreq", - }, - {}, -}; -MODULE_DEVICE_TABLE(of, exynos_cpufreq_match); - -static int exynos_cpufreq_probe(struct platform_device *pdev) -{ - int ret = -EINVAL; - struct device_node *np; - struct resource res; - unsigned int cur_frequency; - - np = pdev->dev.of_node; - if (!np) - return -ENODEV; - - dvfs_info = devm_kzalloc(&pdev->dev, sizeof(*dvfs_info), GFP_KERNEL); - if (!dvfs_info) { - ret = -ENOMEM; - goto err_put_node; - } - - dvfs_info->dev = &pdev->dev; - - ret = of_address_to_resource(np, 0, &res); - if (ret) - goto err_put_node; - - dvfs_info->base = devm_ioremap_resource(dvfs_info->dev, &res); - if (IS_ERR(dvfs_info->base)) { - ret = PTR_ERR(dvfs_info->base); - goto err_put_node; - } - - dvfs_info->irq = irq_of_parse_and_map(np, 0); - if (!dvfs_info->irq) { - dev_err(dvfs_info->dev, "No cpufreq irq found\n"); - ret = -ENODEV; - goto err_put_node; - } - - ret = dev_pm_opp_of_add_table(dvfs_info->dev); - if (ret) { - dev_err(dvfs_info->dev, "failed to init OPP table: %d\n", ret); - goto err_put_node; - } - - ret = dev_pm_opp_init_cpufreq_table(dvfs_info->dev, - &dvfs_info->freq_table); - if (ret) { - dev_err(dvfs_info->dev, - "failed to init cpufreq table: %d\n", ret); - goto err_free_opp; - } - dvfs_info->freq_count = dev_pm_opp_get_opp_count(dvfs_info->dev); - exynos_sort_descend_freq_table(); - - if (of_property_read_u32(np, "clock-latency", &dvfs_info->latency)) - dvfs_info->latency = DEF_TRANS_LATENCY; - - dvfs_info->cpu_clk = devm_clk_get(dvfs_info->dev, "armclk"); - if (IS_ERR(dvfs_info->cpu_clk)) { - dev_err(dvfs_info->dev, "Failed to get cpu clock\n"); - ret = PTR_ERR(dvfs_info->cpu_clk); - goto err_free_table; - } - - cur_frequency = clk_get_rate(dvfs_info->cpu_clk); - if (!cur_frequency) { - dev_err(dvfs_info->dev, "Failed to get clock rate\n"); - ret = -EINVAL; - goto err_free_table; - } - cur_frequency /= 1000; - - INIT_WORK(&dvfs_info->irq_work, exynos_cpufreq_work); - ret = devm_request_irq(dvfs_info->dev, dvfs_info->irq, - exynos_cpufreq_irq, IRQF_TRIGGER_NONE, - CPUFREQ_NAME, dvfs_info); - if (ret) { - dev_err(dvfs_info->dev, "Failed to register IRQ\n"); - goto err_free_table; - } - - ret = init_div_table(); - if (ret) { - dev_err(dvfs_info->dev, "Failed to initialise div table\n"); - goto err_free_table; - } - - exynos_enable_dvfs(cur_frequency); - ret = cpufreq_register_driver(&exynos_driver); - if (ret) { - dev_err(dvfs_info->dev, - "%s: failed to register cpufreq driver\n", __func__); - goto err_free_table; - } - - of_node_put(np); - dvfs_info->dvfs_enabled = true; - return 0; - -err_free_table: - dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table); -err_free_opp: - dev_pm_opp_of_remove_table(dvfs_info->dev); -err_put_node: - of_node_put(np); - dev_err(&pdev->dev, "%s: failed initialization\n", __func__); - return ret; -} - -static int exynos_cpufreq_remove(struct platform_device *pdev) -{ - cpufreq_unregister_driver(&exynos_driver); - dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table); - dev_pm_opp_of_remove_table(dvfs_info->dev); - return 0; -} - -static struct platform_driver exynos_cpufreq_platdrv = { - .driver = { - .name = "exynos5440-cpufreq", - .of_match_table = exynos_cpufreq_match, - }, - .probe = exynos_cpufreq_probe, - .remove = exynos_cpufreq_remove, -}; -module_platform_driver(exynos_cpufreq_platdrv); - -MODULE_AUTHOR("Amit Daniel Kachhap <amit.daniel@samsung.com>"); -MODULE_DESCRIPTION("Exynos5440 cpufreq driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/crypto/caam/sg_sw_qm2.h b/drivers/crypto/caam/sg_sw_qm2.h index 31b440757146..b5b4c12179df 100644 --- a/drivers/crypto/caam/sg_sw_qm2.h +++ b/drivers/crypto/caam/sg_sw_qm2.h @@ -35,7 +35,7 @@ #ifndef _SG_SW_QM2_H_ #define _SG_SW_QM2_H_ -#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h" +#include <soc/fsl/dpaa2-fd.h> static inline void dma_to_qm_sg_one(struct dpaa2_sg_entry *qm_sg_ptr, dma_addr_t dma, u32 len, u16 offset) diff --git a/drivers/crypto/caam/sg_sw_sec4.h b/drivers/crypto/caam/sg_sw_sec4.h index e586ffab8358..dbfa9fce33e0 100644 --- a/drivers/crypto/caam/sg_sw_sec4.h +++ b/drivers/crypto/caam/sg_sw_sec4.h @@ -12,7 +12,7 @@ #include "ctrl.h" #include "regs.h" #include "sg_sw_qm2.h" -#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h" +#include <soc/fsl/dpaa2-fd.h> struct sec4_sg_entry { u64 ptr; diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c index 2a219b1261b1..721e6c57beae 100644 --- a/drivers/firmware/arm_scmi/perf.c +++ b/drivers/firmware/arm_scmi/perf.c @@ -363,8 +363,6 @@ static int scmi_dvfs_device_opps_add(const struct scmi_handle *handle, return domain; dom = pi->dom_info + domain; - if (!dom) - return -EIO; for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { freq = opp->perf * dom->mult_factor; @@ -394,9 +392,6 @@ static int scmi_dvfs_transition_latency_get(const struct scmi_handle *handle, return domain; dom = pi->dom_info + domain; - if (!dom) - return -EIO; - /* uS to nS */ return dom->opp[dom->opp_count - 1].trans_latency_us * 1000; } diff --git a/drivers/firmware/efi/efi-bgrt.c b/drivers/firmware/efi/efi-bgrt.c index 50793fda7819..b22ccfb0c991 100644 --- a/drivers/firmware/efi/efi-bgrt.c +++ b/drivers/firmware/efi/efi-bgrt.c @@ -20,7 +20,7 @@ #include <linux/efi-bgrt.h> struct acpi_table_bgrt bgrt_tab; -size_t __initdata bgrt_image_size; +size_t bgrt_image_size; struct bmp_header { u16 id; diff --git a/drivers/firmware/psci_checker.c b/drivers/firmware/psci_checker.c index bb1c068bff19..346943657962 100644 --- a/drivers/firmware/psci_checker.c +++ b/drivers/firmware/psci_checker.c @@ -77,28 +77,6 @@ static int psci_ops_check(void) return 0; } -static int find_cpu_groups(const struct cpumask *cpus, - const struct cpumask **cpu_groups) -{ - unsigned int nb = 0; - cpumask_var_t tmp; - - if (!alloc_cpumask_var(&tmp, GFP_KERNEL)) - return -ENOMEM; - cpumask_copy(tmp, cpus); - - while (!cpumask_empty(tmp)) { - const struct cpumask *cpu_group = - topology_core_cpumask(cpumask_any(tmp)); - - cpu_groups[nb++] = cpu_group; - cpumask_andnot(tmp, tmp, cpu_group); - } - - free_cpumask_var(tmp); - return nb; -} - /* * offlined_cpus is a temporary array but passing it as an argument avoids * multiple allocations. @@ -166,29 +144,66 @@ static unsigned int down_and_up_cpus(const struct cpumask *cpus, return err; } +static void free_cpu_groups(int num, cpumask_var_t **pcpu_groups) +{ + int i; + cpumask_var_t *cpu_groups = *pcpu_groups; + + for (i = 0; i < num; ++i) + free_cpumask_var(cpu_groups[i]); + kfree(cpu_groups); +} + +static int alloc_init_cpu_groups(cpumask_var_t **pcpu_groups) +{ + int num_groups = 0; + cpumask_var_t tmp, *cpu_groups; + + if (!alloc_cpumask_var(&tmp, GFP_KERNEL)) + return -ENOMEM; + + cpu_groups = kcalloc(nb_available_cpus, sizeof(cpu_groups), + GFP_KERNEL); + if (!cpu_groups) + return -ENOMEM; + + cpumask_copy(tmp, cpu_online_mask); + + while (!cpumask_empty(tmp)) { + const struct cpumask *cpu_group = + topology_core_cpumask(cpumask_any(tmp)); + + if (!alloc_cpumask_var(&cpu_groups[num_groups], GFP_KERNEL)) { + free_cpu_groups(num_groups, &cpu_groups); + return -ENOMEM; + } + cpumask_copy(cpu_groups[num_groups++], cpu_group); + cpumask_andnot(tmp, tmp, cpu_group); + } + + free_cpumask_var(tmp); + *pcpu_groups = cpu_groups; + + return num_groups; +} + static int hotplug_tests(void) { - int err; - cpumask_var_t offlined_cpus; - int i, nb_cpu_group; - const struct cpumask **cpu_groups; + int i, nb_cpu_group, err = -ENOMEM; + cpumask_var_t offlined_cpus, *cpu_groups; char *page_buf; - err = -ENOMEM; if (!alloc_cpumask_var(&offlined_cpus, GFP_KERNEL)) return err; - /* We may have up to nb_available_cpus cpu_groups. */ - cpu_groups = kmalloc_array(nb_available_cpus, sizeof(*cpu_groups), - GFP_KERNEL); - if (!cpu_groups) + + nb_cpu_group = alloc_init_cpu_groups(&cpu_groups); + if (nb_cpu_group < 0) goto out_free_cpus; page_buf = (char *)__get_free_page(GFP_KERNEL); if (!page_buf) goto out_free_cpu_groups; err = 0; - nb_cpu_group = find_cpu_groups(cpu_online_mask, cpu_groups); - /* * Of course the last CPU cannot be powered down and cpu_down() should * refuse doing that. @@ -212,7 +227,7 @@ static int hotplug_tests(void) free_page((unsigned long)page_buf); out_free_cpu_groups: - kfree(cpu_groups); + free_cpu_groups(nb_cpu_group, &cpu_groups); out_free_cpus: free_cpumask_var(offlined_cpus); return err; diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c index 6692888f04cf..a200a2174611 100644 --- a/drivers/firmware/raspberrypi.c +++ b/drivers/firmware/raspberrypi.c @@ -21,6 +21,10 @@ #define MBOX_DATA28(msg) ((msg) & ~0xf) #define MBOX_CHAN_PROPERTY 8 +#define MAX_RPI_FW_PROP_BUF_SIZE 32 + +static struct platform_device *rpi_hwmon; + struct rpi_firmware { struct mbox_client cl; struct mbox_chan *chan; /* The property channel. */ @@ -143,18 +147,22 @@ int rpi_firmware_property(struct rpi_firmware *fw, /* Single tags are very small (generally 8 bytes), so the * stack should be safe. */ - u8 data[buf_size + sizeof(struct rpi_firmware_property_tag_header)]; + u8 data[sizeof(struct rpi_firmware_property_tag_header) + + MAX_RPI_FW_PROP_BUF_SIZE]; struct rpi_firmware_property_tag_header *header = (struct rpi_firmware_property_tag_header *)data; int ret; + if (WARN_ON(buf_size > sizeof(data) - sizeof(*header))) + return -EINVAL; + header->tag = tag; header->buf_size = buf_size; header->req_resp_size = 0; memcpy(data + sizeof(struct rpi_firmware_property_tag_header), tag_data, buf_size); - ret = rpi_firmware_property_list(fw, &data, sizeof(data)); + ret = rpi_firmware_property_list(fw, &data, buf_size + sizeof(*header)); memcpy(tag_data, data + sizeof(struct rpi_firmware_property_tag_header), buf_size); @@ -183,6 +191,20 @@ rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) } } +static void +rpi_register_hwmon_driver(struct device *dev, struct rpi_firmware *fw) +{ + u32 packet; + int ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_THROTTLED, + &packet, sizeof(packet)); + + if (ret) + return; + + rpi_hwmon = platform_device_register_data(dev, "raspberrypi-hwmon", + -1, NULL, 0); +} + static int rpi_firmware_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -209,6 +231,7 @@ static int rpi_firmware_probe(struct platform_device *pdev) platform_set_drvdata(pdev, fw); rpi_firmware_print_firmware_revision(fw); + rpi_register_hwmon_driver(dev, fw); return 0; } @@ -217,6 +240,8 @@ static int rpi_firmware_remove(struct platform_device *pdev) { struct rpi_firmware *fw = platform_get_drvdata(pdev); + platform_device_unregister(rpi_hwmon); + rpi_hwmon = NULL; mbox_free_channel(fw->chan); return 0; diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index ccf42663a908..81da17a42dc9 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1320,6 +1320,16 @@ config SENSORS_PWM_FAN This driver can also be built as a module. If so, the module will be called pwm-fan. +config SENSORS_RASPBERRYPI_HWMON + tristate "Raspberry Pi voltage monitor" + depends on RASPBERRYPI_FIRMWARE || (COMPILE_TEST && !RASPBERRYPI_FIRMWARE) + help + If you say yes here you get support for voltage sensor on the + Raspberry Pi. + + This driver can also be built as a module. If so, the module + will be called raspberrypi-hwmon. + config SENSORS_SHT15 tristate "Sensiron humidity and temperature sensors. SHT15 and compat." depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 842c92f83ce6..93f7f41ea4ad 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -143,6 +143,7 @@ obj-$(CONFIG_SENSORS_PC87427) += pc87427.o obj-$(CONFIG_SENSORS_PCF8591) += pcf8591.o obj-$(CONFIG_SENSORS_POWR1220) += powr1220.o obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o +obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o obj-$(CONFIG_SENSORS_S3C) += s3c-hwmon.o obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o obj-$(CONFIG_SENSORS_SCH5627) += sch5627.o diff --git a/drivers/hwmon/raspberrypi-hwmon.c b/drivers/hwmon/raspberrypi-hwmon.c new file mode 100644 index 000000000000..fb4e4a6bb1f6 --- /dev/null +++ b/drivers/hwmon/raspberrypi-hwmon.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Raspberry Pi voltage sensor driver + * + * Based on firmware/raspberrypi.c by Noralf Trønnes + * + * Copyright (C) 2018 Stefan Wahren <stefan.wahren@i2se.com> + */ +#include <linux/device.h> +#include <linux/err.h> +#include <linux/hwmon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/workqueue.h> +#include <soc/bcm2835/raspberrypi-firmware.h> + +#define UNDERVOLTAGE_STICKY_BIT BIT(16) + +struct rpi_hwmon_data { + struct device *hwmon_dev; + struct rpi_firmware *fw; + u32 last_throttled; + struct delayed_work get_values_poll_work; +}; + +static void rpi_firmware_get_throttled(struct rpi_hwmon_data *data) +{ + u32 new_uv, old_uv, value; + int ret; + + /* Request firmware to clear sticky bits */ + value = 0xffff; + + ret = rpi_firmware_property(data->fw, RPI_FIRMWARE_GET_THROTTLED, + &value, sizeof(value)); + if (ret) { + dev_err_once(data->hwmon_dev, "Failed to get throttled (%d)\n", + ret); + return; + } + + new_uv = value & UNDERVOLTAGE_STICKY_BIT; + old_uv = data->last_throttled & UNDERVOLTAGE_STICKY_BIT; + data->last_throttled = value; + + if (new_uv == old_uv) + return; + + if (new_uv) + dev_crit(data->hwmon_dev, "Undervoltage detected!\n"); + else + dev_info(data->hwmon_dev, "Voltage normalised\n"); + + sysfs_notify(&data->hwmon_dev->kobj, NULL, "in0_lcrit_alarm"); +} + +static void get_values_poll(struct work_struct *work) +{ + struct rpi_hwmon_data *data; + + data = container_of(work, struct rpi_hwmon_data, + get_values_poll_work.work); + + rpi_firmware_get_throttled(data); + + /* + * We can't run faster than the sticky shift (100ms) since we get + * flipping in the sticky bits that are cleared. + */ + schedule_delayed_work(&data->get_values_poll_work, 2 * HZ); +} + +static int rpi_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct rpi_hwmon_data *data = dev_get_drvdata(dev); + + *val = !!(data->last_throttled & UNDERVOLTAGE_STICKY_BIT); + return 0; +} + +static umode_t rpi_is_visible(const void *_data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + return 0444; +} + +static const u32 rpi_in_config[] = { + HWMON_I_LCRIT_ALARM, + 0 +}; + +static const struct hwmon_channel_info rpi_in = { + .type = hwmon_in, + .config = rpi_in_config, +}; + +static const struct hwmon_channel_info *rpi_info[] = { + &rpi_in, + NULL +}; + +static const struct hwmon_ops rpi_hwmon_ops = { + .is_visible = rpi_is_visible, + .read = rpi_read, +}; + +static const struct hwmon_chip_info rpi_chip_info = { + .ops = &rpi_hwmon_ops, + .info = rpi_info, +}; + +static int rpi_hwmon_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rpi_hwmon_data *data; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + /* Parent driver assure that firmware is correct */ + data->fw = dev_get_drvdata(dev->parent); + + /* Init throttled */ + ret = rpi_firmware_property(data->fw, RPI_FIRMWARE_GET_THROTTLED, + &data->last_throttled, + sizeof(data->last_throttled)); + + data->hwmon_dev = devm_hwmon_device_register_with_info(dev, "rpi_volt", + data, + &rpi_chip_info, + NULL); + + INIT_DELAYED_WORK(&data->get_values_poll_work, get_values_poll); + platform_set_drvdata(pdev, data); + + if (!PTR_ERR_OR_ZERO(data->hwmon_dev)) + schedule_delayed_work(&data->get_values_poll_work, 2 * HZ); + + return PTR_ERR_OR_ZERO(data->hwmon_dev); +} + +static int rpi_hwmon_remove(struct platform_device *pdev) +{ + struct rpi_hwmon_data *data = platform_get_drvdata(pdev); + + cancel_delayed_work_sync(&data->get_values_poll_work); + + return 0; +} + +static struct platform_driver rpi_hwmon_driver = { + .probe = rpi_hwmon_probe, + .remove = rpi_hwmon_remove, + .driver = { + .name = "raspberrypi-hwmon", + }, +}; +module_platform_driver(rpi_hwmon_driver); + +MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>"); +MODULE_DESCRIPTION("Raspberry Pi voltage sensor driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig index d160d2d1f3a3..abb6660c099c 100644 --- a/drivers/infiniband/Kconfig +++ b/drivers/infiniband/Kconfig @@ -36,7 +36,7 @@ config INFINIBAND_USER_ACCESS rdma-core <https://github.com/linux-rdma/rdma-core>. config INFINIBAND_USER_ACCESS_UCM - bool "Userspace CM (UCM, DEPRECATED)" + tristate "Userspace CM (UCM, DEPRECATED)" depends on BROKEN || COMPILE_TEST depends on INFINIBAND_USER_ACCESS help diff --git a/drivers/infiniband/hw/hfi1/affinity.c b/drivers/infiniband/hw/hfi1/affinity.c index fbe7198a715a..bedd5fba33b0 100644 --- a/drivers/infiniband/hw/hfi1/affinity.c +++ b/drivers/infiniband/hw/hfi1/affinity.c @@ -198,7 +198,7 @@ int node_affinity_init(void) while ((dev = pci_get_device(ids->vendor, ids->device, dev))) { node = pcibus_to_node(dev->bus); if (node < 0) - node = numa_node_id(); + goto out; hfi1_per_node_cntr[node]++; } @@ -206,6 +206,18 @@ int node_affinity_init(void) } return 0; + +out: + /* + * Invalid PCI NUMA node information found, note it, and populate + * our database 1:1. + */ + pr_err("HFI: Invalid PCI NUMA node. Performance may be affected\n"); + pr_err("HFI: System BIOS may need to be upgraded\n"); + for (node = 0; node < node_affinity.num_possible_nodes; node++) + hfi1_per_node_cntr[node] = 1; + + return 0; } static void node_affinity_destroy(struct hfi1_affinity_node *entry) @@ -622,8 +634,14 @@ int hfi1_dev_affinity_init(struct hfi1_devdata *dd) int curr_cpu, possible, i, ret; bool new_entry = false; - if (node < 0) - node = numa_node_id(); + /* + * If the BIOS does not have the NUMA node information set, select + * NUMA 0 so we get consistent performance. + */ + if (node < 0) { + dd_dev_err(dd, "Invalid PCI NUMA node. Performance may be affected\n"); + node = 0; + } dd->node = node; local_mask = cpumask_of_node(dd->node); diff --git a/drivers/input/serio/ams_delta_serio.c b/drivers/input/serio/ams_delta_serio.c index 3df501c3421b..f8663d7891f2 100644 --- a/drivers/input/serio/ams_delta_serio.c +++ b/drivers/input/serio/ams_delta_serio.c @@ -20,32 +20,33 @@ * However, when used with the E3 mailboard that producecs non-standard * scancodes, a custom key table must be prepared and loaded from userspace. */ -#include <linux/gpio.h> #include <linux/irq.h> +#include <linux/platform_data/ams-delta-fiq.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> #include <linux/serio.h> #include <linux/slab.h> #include <linux/module.h> -#include <asm/mach-types.h> -#include <mach/board-ams-delta.h> - -#include <mach/ams-delta-fiq.h> +#define DRIVER_NAME "ams-delta-serio" MODULE_AUTHOR("Matt Callow"); MODULE_DESCRIPTION("AMS Delta (E3) keyboard port driver"); MODULE_LICENSE("GPL"); -static struct serio *ams_delta_serio; +struct ams_delta_serio { + struct serio *serio; + struct regulator *vcc; + unsigned int *fiq_buffer; +}; -static int check_data(int data) +static int check_data(struct serio *serio, int data) { int i, parity = 0; /* check valid stop bit */ if (!(data & 0x400)) { - dev_warn(&ams_delta_serio->dev, - "invalid stop bit, data=0x%X\n", - data); + dev_warn(&serio->dev, "invalid stop bit, data=0x%X\n", data); return SERIO_FRAME; } /* calculate the parity */ @@ -55,9 +56,9 @@ static int check_data(int data) } /* it should be odd */ if (!(parity & 0x01)) { - dev_warn(&ams_delta_serio->dev, - "parity check failed, data=0x%X parity=0x%X\n", - data, parity); + dev_warn(&serio->dev, + "parity check failed, data=0x%X parity=0x%X\n", data, + parity); return SERIO_PARITY; } return 0; @@ -65,127 +66,130 @@ static int check_data(int data) static irqreturn_t ams_delta_serio_interrupt(int irq, void *dev_id) { - int *circ_buff = &fiq_buffer[FIQ_CIRC_BUFF]; + struct ams_delta_serio *priv = dev_id; + int *circ_buff = &priv->fiq_buffer[FIQ_CIRC_BUFF]; int data, dfl; u8 scancode; - fiq_buffer[FIQ_IRQ_PEND] = 0; + priv->fiq_buffer[FIQ_IRQ_PEND] = 0; /* * Read data from the circular buffer, check it * and then pass it on the serio */ - while (fiq_buffer[FIQ_KEYS_CNT] > 0) { + while (priv->fiq_buffer[FIQ_KEYS_CNT] > 0) { - data = circ_buff[fiq_buffer[FIQ_HEAD_OFFSET]++]; - fiq_buffer[FIQ_KEYS_CNT]--; - if (fiq_buffer[FIQ_HEAD_OFFSET] == fiq_buffer[FIQ_BUF_LEN]) - fiq_buffer[FIQ_HEAD_OFFSET] = 0; + data = circ_buff[priv->fiq_buffer[FIQ_HEAD_OFFSET]++]; + priv->fiq_buffer[FIQ_KEYS_CNT]--; + if (priv->fiq_buffer[FIQ_HEAD_OFFSET] == + priv->fiq_buffer[FIQ_BUF_LEN]) + priv->fiq_buffer[FIQ_HEAD_OFFSET] = 0; - dfl = check_data(data); + dfl = check_data(priv->serio, data); scancode = (u8) (data >> 1) & 0xFF; - serio_interrupt(ams_delta_serio, scancode, dfl); + serio_interrupt(priv->serio, scancode, dfl); } return IRQ_HANDLED; } static int ams_delta_serio_open(struct serio *serio) { - /* enable keyboard */ - gpio_set_value(AMS_DELTA_GPIO_PIN_KEYBRD_PWR, 1); + struct ams_delta_serio *priv = serio->port_data; - return 0; + /* enable keyboard */ + return regulator_enable(priv->vcc); } static void ams_delta_serio_close(struct serio *serio) { + struct ams_delta_serio *priv = serio->port_data; + /* disable keyboard */ - gpio_set_value(AMS_DELTA_GPIO_PIN_KEYBRD_PWR, 0); + regulator_disable(priv->vcc); } -static const struct gpio ams_delta_gpios[] __initconst_or_module = { - { - .gpio = AMS_DELTA_GPIO_PIN_KEYBRD_DATA, - .flags = GPIOF_DIR_IN, - .label = "serio-data", - }, - { - .gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK, - .flags = GPIOF_DIR_IN, - .label = "serio-clock", - }, - { - .gpio = AMS_DELTA_GPIO_PIN_KEYBRD_PWR, - .flags = GPIOF_OUT_INIT_LOW, - .label = "serio-power", - }, - { - .gpio = AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT, - .flags = GPIOF_OUT_INIT_LOW, - .label = "serio-dataout", - }, -}; - -static int __init ams_delta_serio_init(void) +static int ams_delta_serio_init(struct platform_device *pdev) { - int err; - - if (!machine_is_ams_delta()) - return -ENODEV; + struct ams_delta_serio *priv; + struct serio *serio; + int irq, err; - ams_delta_serio = kzalloc(sizeof(struct serio), GFP_KERNEL); - if (!ams_delta_serio) + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) return -ENOMEM; - ams_delta_serio->id.type = SERIO_8042; - ams_delta_serio->open = ams_delta_serio_open; - ams_delta_serio->close = ams_delta_serio_close; - strlcpy(ams_delta_serio->name, "AMS DELTA keyboard adapter", - sizeof(ams_delta_serio->name)); - strlcpy(ams_delta_serio->phys, "GPIO/serio0", - sizeof(ams_delta_serio->phys)); - - err = gpio_request_array(ams_delta_gpios, - ARRAY_SIZE(ams_delta_gpios)); - if (err) { - pr_err("ams_delta_serio: Couldn't request gpio pins\n"); - goto serio; + priv->fiq_buffer = pdev->dev.platform_data; + if (!priv->fiq_buffer) + return -EINVAL; + + priv->vcc = devm_regulator_get(&pdev->dev, "vcc"); + if (IS_ERR(priv->vcc)) { + err = PTR_ERR(priv->vcc); + dev_err(&pdev->dev, "regulator request failed (%d)\n", err); + /* + * When running on a non-dt platform and requested regulator + * is not available, devm_regulator_get() never returns + * -EPROBE_DEFER as it is not able to justify if the regulator + * may still appear later. On the other hand, the board can + * still set full constriants flag at late_initcall in order + * to instruct devm_regulator_get() to returnn a dummy one + * if sufficient. Hence, if we get -ENODEV here, let's convert + * it to -EPROBE_DEFER and wait for the board to decide or + * let Deferred Probe infrastructure handle this error. + */ + if (err == -ENODEV) + err = -EPROBE_DEFER; + return err; } - err = request_irq(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), - ams_delta_serio_interrupt, IRQ_TYPE_EDGE_RISING, - "ams-delta-serio", 0); + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return -ENXIO; + + err = devm_request_irq(&pdev->dev, irq, ams_delta_serio_interrupt, + IRQ_TYPE_EDGE_RISING, DRIVER_NAME, priv); if (err < 0) { - pr_err("ams_delta_serio: couldn't request gpio interrupt %d\n", - gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK)); - goto gpio; + dev_err(&pdev->dev, "IRQ request failed (%d)\n", err); + return err; } - /* - * Since GPIO register handling for keyboard clock pin is performed - * at FIQ level, switch back from edge to simple interrupt handler - * to avoid bad interaction. - */ - irq_set_handler(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), - handle_simple_irq); - serio_register_port(ams_delta_serio); - dev_info(&ams_delta_serio->dev, "%s\n", ams_delta_serio->name); + serio = kzalloc(sizeof(*serio), GFP_KERNEL); + if (!serio) + return -ENOMEM; + + priv->serio = serio; + + serio->id.type = SERIO_8042; + serio->open = ams_delta_serio_open; + serio->close = ams_delta_serio_close; + strlcpy(serio->name, "AMS DELTA keyboard adapter", sizeof(serio->name)); + strlcpy(serio->phys, dev_name(&pdev->dev), sizeof(serio->phys)); + serio->dev.parent = &pdev->dev; + serio->port_data = priv; + + serio_register_port(serio); + + platform_set_drvdata(pdev, priv); + + dev_info(&serio->dev, "%s\n", serio->name); return 0; -gpio: - gpio_free_array(ams_delta_gpios, - ARRAY_SIZE(ams_delta_gpios)); -serio: - kfree(ams_delta_serio); - return err; } -module_init(ams_delta_serio_init); -static void __exit ams_delta_serio_exit(void) +static int ams_delta_serio_exit(struct platform_device *pdev) { - serio_unregister_port(ams_delta_serio); - free_irq(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), 0); - gpio_free_array(ams_delta_gpios, - ARRAY_SIZE(ams_delta_gpios)); + struct ams_delta_serio *priv = platform_get_drvdata(pdev); + + serio_unregister_port(priv->serio); + + return 0; } -module_exit(ams_delta_serio_exit); + +static struct platform_driver ams_delta_serio_driver = { + .probe = ams_delta_serio_init, + .remove = ams_delta_serio_exit, + .driver = { + .name = DRIVER_NAME + }, +}; +module_platform_driver(ams_delta_serio_driver); diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index bb93cc53554e..bd25faf6d13d 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -672,13 +672,6 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } - err = tegra_mc_reset_setup(mc); - if (err < 0) { - dev_err(&pdev->dev, "failed to register reset controller: %d\n", - err); - return err; - } - mc->irq = platform_get_irq(pdev, 0); if (mc->irq < 0) { dev_err(&pdev->dev, "interrupt not specified\n"); @@ -697,13 +690,16 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } + err = tegra_mc_reset_setup(mc); + if (err < 0) + dev_err(&pdev->dev, "failed to register reset controller: %d\n", + err); + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) { mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); - if (IS_ERR(mc->smmu)) { + if (IS_ERR(mc->smmu)) dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", PTR_ERR(mc->smmu)); - return PTR_ERR(mc->smmu); - } } return 0; diff --git a/drivers/memory/ti-emif-pm.c b/drivers/memory/ti-emif-pm.c index 632651f4b6e8..2250d03ea17f 100644 --- a/drivers/memory/ti-emif-pm.c +++ b/drivers/memory/ti-emif-pm.c @@ -249,6 +249,34 @@ static const struct of_device_id ti_emif_of_match[] = { }; MODULE_DEVICE_TABLE(of, ti_emif_of_match); +#ifdef CONFIG_PM_SLEEP +static int ti_emif_resume(struct device *dev) +{ + unsigned long tmp = + __raw_readl((void *)emif_instance->ti_emif_sram_virt); + + /* + * Check to see if what we are copying is already present in the + * first byte at the destination, only copy if it is not which + * indicates we have lost context and sram no longer contains + * the PM code + */ + if (tmp != ti_emif_sram) + ti_emif_push_sram(dev, emif_instance); + + return 0; +} + +static int ti_emif_suspend(struct device *dev) +{ + /* + * The contents will be present in DDR hence no need to + * explicitly save + */ + return 0; +} +#endif /* CONFIG_PM_SLEEP */ + static int ti_emif_probe(struct platform_device *pdev) { int ret; @@ -308,12 +336,17 @@ static int ti_emif_remove(struct platform_device *pdev) return 0; } +static const struct dev_pm_ops ti_emif_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(ti_emif_suspend, ti_emif_resume) +}; + static struct platform_driver ti_emif_driver = { .probe = ti_emif_probe, .remove = ti_emif_remove, .driver = { .name = KBUILD_MODNAME, .of_match_table = of_match_ptr(ti_emif_of_match), + .pm = &ti_emif_pm_ops, }, }; module_platform_driver(ti_emif_driver); diff --git a/drivers/mtd/ubi/cdev.c b/drivers/mtd/ubi/cdev.c index 45c329694a5e..22547d7a84ea 100644 --- a/drivers/mtd/ubi/cdev.c +++ b/drivers/mtd/ubi/cdev.c @@ -367,6 +367,10 @@ static ssize_t vol_cdev_write(struct file *file, const char __user *buf, return count; } + /* + * We voluntarily do not take into account the skip_check flag + * as we want to make sure what we wrote was correctly written. + */ err = ubi_check_volume(ubi, vol->vol_id); if (err < 0) return err; @@ -622,6 +626,13 @@ static int verify_mkvol_req(const struct ubi_device *ubi, req->vol_type != UBI_STATIC_VOLUME) goto bad; + if (req->flags & ~UBI_VOL_VALID_FLGS) + goto bad; + + if (req->flags & UBI_VOL_SKIP_CRC_CHECK_FLG && + req->vol_type != UBI_STATIC_VOLUME) + goto bad; + if (req->alignment > ubi->leb_size) goto bad; diff --git a/drivers/mtd/ubi/kapi.c b/drivers/mtd/ubi/kapi.c index d4b2e8744498..e9e9ecbcedcc 100644 --- a/drivers/mtd/ubi/kapi.c +++ b/drivers/mtd/ubi/kapi.c @@ -202,7 +202,7 @@ struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode) desc->mode = mode; mutex_lock(&ubi->ckvol_mutex); - if (!vol->checked) { + if (!vol->checked && !vol->skip_check) { /* This is the first open - check the volume */ err = ubi_check_volume(ubi, vol_id); if (err < 0) { diff --git a/drivers/mtd/ubi/ubi-media.h b/drivers/mtd/ubi/ubi-media.h index 195ff8ca8211..b5fe8f82281b 100644 --- a/drivers/mtd/ubi/ubi-media.h +++ b/drivers/mtd/ubi/ubi-media.h @@ -45,6 +45,11 @@ enum { * Volume flags used in the volume table record. * * @UBI_VTBL_AUTORESIZE_FLG: auto-resize this volume + * @UBI_VTBL_SKIP_CRC_CHECK_FLG: skip the CRC check done on a static volume at + * open time. Should only be set on volumes that + * are used by upper layers doing this kind of + * check. Main use-case for this flag is + * boot-time reduction * * %UBI_VTBL_AUTORESIZE_FLG flag can be set only for one volume in the volume * table. UBI automatically re-sizes the volume which has this flag and makes @@ -76,6 +81,7 @@ enum { */ enum { UBI_VTBL_AUTORESIZE_FLG = 0x01, + UBI_VTBL_SKIP_CRC_CHECK_FLG = 0x02, }; /* diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index f5ba97c46160..d47b9e436e67 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -327,6 +327,9 @@ struct ubi_eba_leb_desc { * atomic LEB change * * @eba_tbl: EBA table of this volume (LEB->PEB mapping) + * @skip_check: %1 if CRC check of this static volume should be skipped. + * Directly reflects the presence of the + * %UBI_VTBL_SKIP_CRC_CHECK_FLG flag in the vtbl entry * @checked: %1 if this static volume was checked * @corrupted: %1 if the volume is corrupted (static volumes only) * @upd_marker: %1 if the update marker is set for this volume @@ -374,6 +377,7 @@ struct ubi_volume { void *upd_buf; struct ubi_eba_table *eba_tbl; + unsigned int skip_check:1; unsigned int checked:1; unsigned int corrupted:1; unsigned int upd_marker:1; diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index 0be516780e92..729588b94e41 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -174,6 +174,9 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) vol->dev.class = &ubi_class; vol->dev.groups = volume_dev_groups; + if (req->flags & UBI_VOL_SKIP_CRC_CHECK_FLG) + vol->skip_check = 1; + spin_lock(&ubi->volumes_lock); if (vol_id == UBI_VOL_NUM_AUTO) { /* Find unused volume ID */ @@ -299,6 +302,10 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) vtbl_rec.vol_type = UBI_VID_DYNAMIC; else vtbl_rec.vol_type = UBI_VID_STATIC; + + if (vol->skip_check) + vtbl_rec.flags |= UBI_VTBL_SKIP_CRC_CHECK_FLG; + memcpy(vtbl_rec.name, vol->name, vol->name_len); err = ubi_change_vtbl_record(ubi, vol_id, &vtbl_rec); @@ -733,6 +740,11 @@ static int self_check_volume(struct ubi_device *ubi, int vol_id) ubi_err(ubi, "bad used_bytes"); goto fail; } + + if (vol->skip_check) { + ubi_err(ubi, "bad skip_check"); + goto fail; + } } else { if (vol->used_ebs < 0 || vol->used_ebs > vol->reserved_pebs) { ubi_err(ubi, "bad used_ebs"); diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c index 94d7a865b135..1bc82154bb18 100644 --- a/drivers/mtd/ubi/vtbl.c +++ b/drivers/mtd/ubi/vtbl.c @@ -560,6 +560,9 @@ static int init_volumes(struct ubi_device *ubi, vol->name[vol->name_len] = '\0'; vol->vol_id = i; + if (vtbl[i].flags & UBI_VTBL_SKIP_CRC_CHECK_FLG) + vol->skip_check = 1; + if (vtbl[i].flags & UBI_VTBL_AUTORESIZE_FLG) { /* Auto re-size flag may be set only for one volume */ if (ubi->autoresize_vol_id != -1) { @@ -579,6 +582,16 @@ static int init_volumes(struct ubi_device *ubi, reserved_pebs += vol->reserved_pebs; /* + * We use ubi->peb_count and not vol->reserved_pebs because + * we want to keep the code simple. Otherwise we'd have to + * resize/check the bitmap upon volume resize too. + * Allocating a few bytes more does not hurt. + */ + err = ubi_fastmap_init_checkmap(vol, ubi->peb_count); + if (err) + return err; + + /* * In case of dynamic volume UBI knows nothing about how many * data is stored there. So assume the whole volume is used. */ @@ -620,16 +633,6 @@ static int init_volumes(struct ubi_device *ubi, (long long)(vol->used_ebs - 1) * vol->usable_leb_size; vol->used_bytes += av->last_data_size; vol->last_eb_bytes = av->last_data_size; - - /* - * We use ubi->peb_count and not vol->reserved_pebs because - * we want to keep the code simple. Otherwise we'd have to - * resize/check the bitmap upon volume resize too. - * Allocating a few bytes more does not hurt. - */ - err = ubi_fastmap_init_checkmap(vol, ubi->peb_count); - if (err) - return err; } /* And add the layout volume */ diff --git a/drivers/net/ethernet/smsc/smc911x.c b/drivers/net/ethernet/smsc/smc911x.c index 05157442a980..b1b53f6c452f 100644 --- a/drivers/net/ethernet/smsc/smc911x.c +++ b/drivers/net/ethernet/smsc/smc911x.c @@ -74,7 +74,6 @@ static const char version[] = #include <linux/skbuff.h> #include <linux/dmaengine.h> -#include <linux/dma/pxa-dma.h> #include <asm/io.h> @@ -1795,7 +1794,6 @@ static int smc911x_probe(struct net_device *dev) #ifdef SMC_USE_DMA struct dma_slave_config config; dma_cap_mask_t mask; - struct pxad_param param; #endif DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__); @@ -1971,15 +1969,8 @@ static int smc911x_probe(struct net_device *dev) dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - param.prio = PXAD_PRIO_LOWEST; - param.drcmr = -1UL; - - lp->rxdma = - dma_request_slave_channel_compat(mask, pxad_filter_fn, - ¶m, &dev->dev, "rx"); - lp->txdma = - dma_request_slave_channel_compat(mask, pxad_filter_fn, - ¶m, &dev->dev, "tx"); + lp->rxdma = dma_request_channel(mask, NULL, NULL); + lp->txdma = dma_request_channel(mask, NULL, NULL); lp->rxdma_active = 0; lp->txdma_active = 0; diff --git a/drivers/net/ethernet/smsc/smc91x.c b/drivers/net/ethernet/smsc/smc91x.c index 080428762858..b944828f9ea3 100644 --- a/drivers/net/ethernet/smsc/smc91x.c +++ b/drivers/net/ethernet/smsc/smc91x.c @@ -2019,17 +2019,10 @@ static int smc_probe(struct net_device *dev, void __iomem *ioaddr, # endif if (lp->cfg.flags & SMC91X_USE_DMA) { dma_cap_mask_t mask; - struct pxad_param param; dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - param.prio = PXAD_PRIO_LOWEST; - param.drcmr = -1UL; - - lp->dma_chan = - dma_request_slave_channel_compat(mask, pxad_filter_fn, - ¶m, &dev->dev, - "data"); + lp->dma_chan = dma_request_channel(mask, NULL, NULL); } #endif diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h index b337ee97e0c0..a27352229fc2 100644 --- a/drivers/net/ethernet/smsc/smc91x.h +++ b/drivers/net/ethernet/smsc/smc91x.h @@ -301,7 +301,6 @@ struct smc_local { * as RX which can overrun memory and lose packets. */ #include <linux/dma-mapping.h> -#include <linux/dma/pxa-dma.h> #ifdef SMC_insl #undef SMC_insl diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a4d262db9945..504d252716f2 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -286,7 +286,7 @@ config PWM_MTK_DISP config PWM_MEDIATEK tristate "MediaTek PWM support" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST help Generic PWM framework driver for Mediatek ARM SoC. diff --git a/drivers/pwm/pwm-berlin.c b/drivers/pwm/pwm-berlin.c index 771859aca4be..7c8d6a168ceb 100644 --- a/drivers/pwm/pwm-berlin.c +++ b/drivers/pwm/pwm-berlin.c @@ -21,8 +21,18 @@ #define BERLIN_PWM_EN 0x0 #define BERLIN_PWM_ENABLE BIT(0) #define BERLIN_PWM_CONTROL 0x4 -#define BERLIN_PWM_PRESCALE_MASK 0x7 -#define BERLIN_PWM_PRESCALE_MAX 4096 +/* + * The prescaler claims to support 8 different moduli, configured using the + * low three bits of PWM_CONTROL. (Sequentially, they are 1, 4, 8, 16, 64, + * 256, 1024, and 4096.) However, the moduli from 4 to 1024 appear to be + * implemented by internally shifting TCNT left without adding additional + * bits. So, the max TCNT that actually works for a modulus of 4 is 0x3fff; + * for 8, 0x1fff; and so on. This means that those moduli are entirely + * useless, as we could just do the shift ourselves. The 4096 modulus is + * implemented with a real prescaler, so we do use that, but we treat it + * as a flag instead of pretending the modulus is actually configurable. + */ +#define BERLIN_PWM_PRESCALE_4096 0x7 #define BERLIN_PWM_INVERT_POLARITY BIT(3) #define BERLIN_PWM_DUTY 0x8 #define BERLIN_PWM_TCNT 0xc @@ -46,10 +56,6 @@ static inline struct berlin_pwm_chip *to_berlin_pwm_chip(struct pwm_chip *chip) return container_of(chip, struct berlin_pwm_chip, chip); } -static const u32 prescaler_table[] = { - 1, 4, 8, 16, 64, 256, 1024, 4096 -}; - static inline u32 berlin_pwm_readl(struct berlin_pwm_chip *chip, unsigned int channel, unsigned long offset) { @@ -86,33 +92,32 @@ static int berlin_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm_dev, int duty_ns, int period_ns) { struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip); - unsigned int prescale; + bool prescale_4096 = false; u32 value, duty, period; - u64 cycles, tmp; + u64 cycles; cycles = clk_get_rate(pwm->clk); cycles *= period_ns; do_div(cycles, NSEC_PER_SEC); - for (prescale = 0; prescale < ARRAY_SIZE(prescaler_table); prescale++) { - tmp = cycles; - do_div(tmp, prescaler_table[prescale]); + if (cycles > BERLIN_PWM_MAX_TCNT) { + prescale_4096 = true; + cycles >>= 12; // Prescaled by 4096 - if (tmp <= BERLIN_PWM_MAX_TCNT) - break; + if (cycles > BERLIN_PWM_MAX_TCNT) + return -ERANGE; } - if (tmp > BERLIN_PWM_MAX_TCNT) - return -ERANGE; - - period = tmp; - cycles = tmp * duty_ns; + period = cycles; + cycles *= duty_ns; do_div(cycles, period_ns); duty = cycles; value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL); - value &= ~BERLIN_PWM_PRESCALE_MASK; - value |= prescale; + if (prescale_4096) + value |= BERLIN_PWM_PRESCALE_4096; + else + value &= ~BERLIN_PWM_PRESCALE_4096; berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL); berlin_pwm_writel(pwm, pwm_dev->hwpwm, duty, BERLIN_PWM_DUTY); diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 9c13694eaa24..98f6ac6cf6ab 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016 Google, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2, as published by - * the Free Software Foundation. - * * Expose a PWM controlled by the ChromeOS EC to the host processor. + * + * Copyright (C) 2016 Google, Inc. */ #include <linux/module.h> diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c index 557b4ea16796..883378d055c6 100644 --- a/drivers/pwm/pwm-fsl-ftm.c +++ b/drivers/pwm/pwm-fsl-ftm.c @@ -16,6 +16,7 @@ #include <linux/module.h> #include <linux/mutex.h> #include <linux/of_address.h> +#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/pwm.h> @@ -75,6 +76,10 @@ enum fsl_pwm_clk { FSL_PWM_CLK_MAX }; +struct fsl_ftm_soc { + bool has_enable_bits; +}; + struct fsl_pwm_chip { struct pwm_chip chip; @@ -87,7 +92,10 @@ struct fsl_pwm_chip { int period_ns; + struct clk *ipg_clk; struct clk *clk[FSL_PWM_CLK_MAX]; + + const struct fsl_ftm_soc *soc; }; static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) @@ -97,16 +105,32 @@ static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) { + int ret; struct fsl_pwm_chip *fpc = to_fsl_chip(chip); - return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); + ret = clk_prepare_enable(fpc->ipg_clk); + if (!ret && fpc->soc->has_enable_bits) { + mutex_lock(&fpc->lock); + regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), + BIT(pwm->hwpwm + 16)); + mutex_unlock(&fpc->lock); + } + + return ret; } static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) { struct fsl_pwm_chip *fpc = to_fsl_chip(chip); - clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); + if (fpc->soc->has_enable_bits) { + mutex_lock(&fpc->lock); + regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), + 0); + mutex_unlock(&fpc->lock); + } + + clk_disable_unprepare(fpc->ipg_clk); } static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, @@ -363,7 +387,7 @@ static int fsl_pwm_init(struct fsl_pwm_chip *fpc) { int ret; - ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); + ret = clk_prepare_enable(fpc->ipg_clk); if (ret) return ret; @@ -371,7 +395,7 @@ static int fsl_pwm_init(struct fsl_pwm_chip *fpc) regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); - clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); + clk_disable_unprepare(fpc->ipg_clk); return 0; } @@ -408,6 +432,7 @@ static int fsl_pwm_probe(struct platform_device *pdev) mutex_init(&fpc->lock); + fpc->soc = of_device_get_match_data(&pdev->dev); fpc->chip.dev = &pdev->dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -441,6 +466,15 @@ static int fsl_pwm_probe(struct platform_device *pdev) if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); + /* + * ipg_clk is the interface clock for the IP. If not provided, use the + * ftm_sys clock as the default. + */ + fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); + if (IS_ERR(fpc->ipg_clk)) + fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS]; + + fpc->chip.ops = &fsl_pwm_ops; fpc->chip.of_xlate = of_pwm_xlate_with_flags; fpc->chip.of_pwm_n_cells = 3; @@ -480,7 +514,7 @@ static int fsl_pwm_suspend(struct device *dev) if (!test_bit(PWMF_REQUESTED, &pwm->flags)) continue; - clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); + clk_disable_unprepare(fpc->ipg_clk); if (!pwm_is_enabled(pwm)) continue; @@ -503,7 +537,7 @@ static int fsl_pwm_resume(struct device *dev) if (!test_bit(PWMF_REQUESTED, &pwm->flags)) continue; - clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); + clk_prepare_enable(fpc->ipg_clk); if (!pwm_is_enabled(pwm)) continue; @@ -524,8 +558,17 @@ static const struct dev_pm_ops fsl_pwm_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume) }; +static const struct fsl_ftm_soc vf610_ftm_pwm = { + .has_enable_bits = false, +}; + +static const struct fsl_ftm_soc imx8qm_ftm_pwm = { + .has_enable_bits = true, +}; + static const struct of_device_id fsl_pwm_dt_ids[] = { - { .compatible = "fsl,vf610-ftm-pwm", }, + { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm }, + { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 08cbe8120588..1d5242c9cde0 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * simple driver for PWM (Pulse Width Modulator) controller * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> */ diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 328c124773b2..eb6674ce995f 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -57,6 +57,7 @@ static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { struct mtk_pwm_platform_data { unsigned int num_pwms; bool pwm45_fixup; + bool has_clks; }; /** @@ -86,6 +87,9 @@ static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm) struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); int ret; + if (!pc->soc->has_clks) + return 0; + ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]); if (ret < 0) return ret; @@ -112,6 +116,9 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); + if (!pc->soc->has_clks) + return; + clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]); clk_disable_unprepare(pc->clks[MTK_CLK_TOP]); @@ -239,7 +246,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) if (IS_ERR(pc->regs)) return PTR_ERR(pc->regs); - for (i = 0; i < data->num_pwms + 2; i++) { + for (i = 0; i < data->num_pwms + 2 && pc->soc->has_clks; i++) { pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); if (IS_ERR(pc->clks[i])) { dev_err(&pdev->dev, "clock: %s fail: %ld\n", @@ -274,22 +281,32 @@ static int mtk_pwm_remove(struct platform_device *pdev) static const struct mtk_pwm_platform_data mt2712_pwm_data = { .num_pwms = 8, .pwm45_fixup = false, + .has_clks = true, }; static const struct mtk_pwm_platform_data mt7622_pwm_data = { .num_pwms = 6, .pwm45_fixup = false, + .has_clks = true, }; static const struct mtk_pwm_platform_data mt7623_pwm_data = { .num_pwms = 5, .pwm45_fixup = true, + .has_clks = true, +}; + +static const struct mtk_pwm_platform_data mt7628_pwm_data = { + .num_pwms = 4, + .pwm45_fixup = true, + .has_clks = false, }; static const struct of_device_id mtk_pwm_of_match[] = { { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, + { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, { }, }; MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 822860b4801a..c1ed641b3e26 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -458,7 +458,6 @@ static int meson_pwm_init_channels(struct meson_pwm *meson, struct meson_pwm_channel *channels) { struct device *dev = meson->chip.dev; - struct device_node *np = dev->of_node; struct clk_init_data init; unsigned int i; char name[255]; @@ -467,7 +466,7 @@ static int meson_pwm_init_channels(struct meson_pwm *meson, for (i = 0; i < meson->chip.npwm; i++) { struct meson_pwm_channel *channel = &channels[i]; - snprintf(name, sizeof(name), "%pOF#mux%u", np, i); + snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); init.name = name; init.ops = &clk_mux_ops; diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c index a6017ad9926c..04c0f6b95c1a 100644 --- a/drivers/pwm/pwm-mxs.c +++ b/drivers/pwm/pwm-mxs.c @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <linux/clk.h> diff --git a/drivers/pwm/pwm-omap-dmtimer.c b/drivers/pwm/pwm-omap-dmtimer.c index 665da3c8fbce..f45798679e3c 100644 --- a/drivers/pwm/pwm-omap-dmtimer.c +++ b/drivers/pwm/pwm-omap-dmtimer.c @@ -264,8 +264,9 @@ static int pwm_omap_dmtimer_probe(struct platform_device *pdev) timer_pdata = dev_get_platdata(&timer_pdev->dev); if (!timer_pdata) { - dev_err(&pdev->dev, "dmtimer pdata structure NULL\n"); - ret = -EINVAL; + dev_dbg(&pdev->dev, + "dmtimer pdata structure NULL, deferring probe\n"); + ret = -EPROBE_DEFER; goto put; } diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 7c13e2505080..0059b24cfdc3 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -217,10 +217,8 @@ static int stm32_pwm_lp_probe(struct platform_device *pdev) static int stm32_pwm_lp_remove(struct platform_device *pdev) { struct stm32_pwm_lp *priv = platform_get_drvdata(pdev); - unsigned int i; - for (i = 0; i < priv->chip.npwm; i++) - pwm_disable(&priv->chip.pwms[i]); + pwm_disable(&priv->chip.pwms[0]); return pwmchip_remove(&priv->chip); } diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 4c22cb395040..f7b8a86fa5c5 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -33,10 +33,6 @@ #define TBCTL 0x00 #define TBPRD 0x0A -#define TBCTL_RUN_MASK (BIT(15) | BIT(14)) -#define TBCTL_STOP_NEXT 0 -#define TBCTL_STOP_ON_CYCLE BIT(14) -#define TBCTL_FREE_RUN (BIT(15) | BIT(14)) #define TBCTL_PRDLD_MASK BIT(3) #define TBCTL_PRDLD_SHDW 0 #define TBCTL_PRDLD_IMDT BIT(3) @@ -360,7 +356,7 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) /* Channels polarity can be configured from action qualifier module */ configure_polarity(pc, pwm->hwpwm); - /* Enable TBCLK before enabling PWM device */ + /* Enable TBCLK */ ret = clk_enable(pc->tbclk); if (ret) { dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n", @@ -368,9 +364,6 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) return ret; } - /* Enable time counter for free_run */ - ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); - return 0; } @@ -388,6 +381,8 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) aqcsfrc_mask = AQCSFRC_CSFA_MASK; } + /* Update shadow register first before modifying active register */ + ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); /* * Changes to immediate action on Action Qualifier. This puts * Action Qualifier control on PWM output from next TBCLK @@ -400,9 +395,6 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) /* Disabling TBCLK on PWM disable */ clk_disable(pc->tbclk); - /* Stop Time base counter */ - ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT); - /* Disable clock on PWM disable */ pm_runtime_put_sync(chip->dev); } diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index c0b292be1b72..a70262cb7e56 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -82,6 +82,15 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_QCOM_AOSS + bool "Qcom AOSS Reset Driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This enables the AOSS (always on subsystem) reset driver + for Qualcomm SDM845 SoCs. Say Y if you want to control + reset signals provided by AOSS for Modem, Venus, ADSP, + GPU, Camera, Wireless, Display subsystem. Otherwise, say N. + config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED @@ -138,6 +147,16 @@ config RESET_UNIPHIER Say Y if you want to control reset signals provided by System Control block, Media I/O block, Peripheral Block. +config RESET_UNIPHIER_USB3 + tristate "USB3 reset driver for UniPhier SoCs" + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF + default ARCH_UNIPHIER + select RESET_SIMPLE + help + Support for the USB3 core reset on UniPhier SoCs. + Say Y if you want to control reset signals provided by + USB3 glue layer. + config RESET_ZYNQ bool "ZYNQ Reset Driver" if COMPILE_TEST default ARCH_ZYNQ diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index c1261dcfe9ad..0676b6b1976f 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,11 +14,13 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o +obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c new file mode 100644 index 000000000000..36db96750450 --- /dev/null +++ b/drivers/reset/reset-qcom-aoss.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <dt-bindings/reset/qcom,sdm845-aoss.h> + +struct qcom_aoss_reset_map { + unsigned int reg; +}; + +struct qcom_aoss_desc { + const struct qcom_aoss_reset_map *resets; + size_t num_resets; +}; + +struct qcom_aoss_reset_data { + struct reset_controller_dev rcdev; + void __iomem *base; + const struct qcom_aoss_desc *desc; +}; + +static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = { + [AOSS_CC_MSS_RESTART] = {0x10000}, + [AOSS_CC_CAMSS_RESTART] = {0x11000}, + [AOSS_CC_VENUS_RESTART] = {0x12000}, + [AOSS_CC_GPU_RESTART] = {0x13000}, + [AOSS_CC_DISPSS_RESTART] = {0x14000}, + [AOSS_CC_WCSS_RESTART] = {0x20000}, + [AOSS_CC_LPASS_RESTART] = {0x30000}, +}; + +static const struct qcom_aoss_desc sdm845_aoss_desc = { + .resets = sdm845_aoss_resets, + .num_resets = ARRAY_SIZE(sdm845_aoss_resets), +}; + +static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data( + struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev); +} + +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev); + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + + writel(1, data->base + map->reg); + /* Wait 6 32kHz sleep cycles for reset */ + usleep_range(200, 300); + return 0; +} + +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev); + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + + writel(0, data->base + map->reg); + /* Wait 6 32kHz sleep cycles for reset */ + usleep_range(200, 300); + return 0; +} + +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + qcom_aoss_control_assert(rcdev, idx); + + return qcom_aoss_control_deassert(rcdev, idx); +} + +static const struct reset_control_ops qcom_aoss_reset_ops = { + .reset = qcom_aoss_control_reset, + .assert = qcom_aoss_control_assert, + .deassert = qcom_aoss_control_deassert, +}; + +static int qcom_aoss_reset_probe(struct platform_device *pdev) +{ + struct qcom_aoss_reset_data *data; + struct device *dev = &pdev->dev; + const struct qcom_aoss_desc *desc; + struct resource *res; + + desc = of_device_get_match_data(dev); + if (!desc) + return -EINVAL; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->desc = desc; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->base = devm_ioremap_resource(dev, res); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.ops = &qcom_aoss_reset_ops; + data->rcdev.nr_resets = desc->num_resets; + data->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static const struct of_device_id qcom_aoss_reset_of_match[] = { + { .compatible = "qcom,sdm845-aoss-cc", .data = &sdm845_aoss_desc }, + {} +}; + +static struct platform_driver qcom_aoss_reset_driver = { + .probe = qcom_aoss_reset_probe, + .driver = { + .name = "qcom_aoss_reset", + .of_match_table = qcom_aoss_reset_of_match, + }, +}; + +builtin_platform_driver(qcom_aoss_reset_driver); + +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index f7ce8910a392..a91107fc9e27 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -87,6 +87,7 @@ const struct reset_control_ops reset_simple_ops = { .deassert = reset_simple_deassert, .status = reset_simple_status, }; +EXPORT_SYMBOL_GPL(reset_simple_ops); /** * struct reset_simple_devdata - simple reset controller properties diff --git a/drivers/reset/reset-uniphier-usb3.c b/drivers/reset/reset-uniphier-usb3.c new file mode 100644 index 000000000000..ffa1b19b594d --- /dev/null +++ b/drivers/reset/reset-uniphier-usb3.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// reset-uniphier-usb3.c - USB3 reset driver for UniPhier +// Copyright 2018 Socionext Inc. +// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "reset-simple.h" + +#define MAX_CLKS 2 +#define MAX_RSTS 2 + +struct uniphier_usb3_reset_soc_data { + int nclks; + const char * const *clock_names; + int nrsts; + const char * const *reset_names; +}; + +struct uniphier_usb3_reset_priv { + struct clk_bulk_data clk[MAX_CLKS]; + struct reset_control *rst[MAX_RSTS]; + struct reset_simple_data rdata; + const struct uniphier_usb3_reset_soc_data *data; +}; + +static int uniphier_usb3_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct uniphier_usb3_reset_priv *priv; + struct resource *res; + resource_size_t size; + const char *name; + int i, ret, nr; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->data = of_device_get_match_data(dev); + if (WARN_ON(!priv->data || priv->data->nclks > MAX_CLKS || + priv->data->nrsts > MAX_RSTS)) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + size = resource_size(res); + priv->rdata.membase = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->rdata.membase)) + return PTR_ERR(priv->rdata.membase); + + for (i = 0; i < priv->data->nclks; i++) + priv->clk[i].id = priv->data->clock_names[i]; + ret = devm_clk_bulk_get(dev, priv->data->nclks, priv->clk); + if (ret) + return ret; + + for (i = 0; i < priv->data->nrsts; i++) { + name = priv->data->reset_names[i]; + priv->rst[i] = devm_reset_control_get_shared(dev, name); + if (IS_ERR(priv->rst[i])) + return PTR_ERR(priv->rst[i]); + } + + ret = clk_bulk_prepare_enable(priv->data->nclks, priv->clk); + if (ret) + return ret; + + for (nr = 0; nr < priv->data->nrsts; nr++) { + ret = reset_control_deassert(priv->rst[nr]); + if (ret) + goto out_rst_assert; + } + + spin_lock_init(&priv->rdata.lock); + priv->rdata.rcdev.owner = THIS_MODULE; + priv->rdata.rcdev.nr_resets = size * BITS_PER_BYTE; + priv->rdata.rcdev.ops = &reset_simple_ops; + priv->rdata.rcdev.of_node = dev->of_node; + priv->rdata.active_low = true; + + platform_set_drvdata(pdev, priv); + + ret = devm_reset_controller_register(dev, &priv->rdata.rcdev); + if (ret) + goto out_rst_assert; + + return 0; + +out_rst_assert: + while (nr--) + reset_control_assert(priv->rst[nr]); + + clk_bulk_disable_unprepare(priv->data->nclks, priv->clk); + + return ret; +} + +static int uniphier_usb3_reset_remove(struct platform_device *pdev) +{ + struct uniphier_usb3_reset_priv *priv = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < priv->data->nrsts; i++) + reset_control_assert(priv->rst[i]); + + clk_bulk_disable_unprepare(priv->data->nclks, priv->clk); + + return 0; +} + +static const char * const uniphier_pro4_clock_reset_names[] = { + "gio", "link", +}; + +static const struct uniphier_usb3_reset_soc_data uniphier_pro4_data = { + .nclks = ARRAY_SIZE(uniphier_pro4_clock_reset_names), + .clock_names = uniphier_pro4_clock_reset_names, + .nrsts = ARRAY_SIZE(uniphier_pro4_clock_reset_names), + .reset_names = uniphier_pro4_clock_reset_names, +}; + +static const char * const uniphier_pxs2_clock_reset_names[] = { + "link", +}; + +static const struct uniphier_usb3_reset_soc_data uniphier_pxs2_data = { + .nclks = ARRAY_SIZE(uniphier_pxs2_clock_reset_names), + .clock_names = uniphier_pxs2_clock_reset_names, + .nrsts = ARRAY_SIZE(uniphier_pxs2_clock_reset_names), + .reset_names = uniphier_pxs2_clock_reset_names, +}; + +static const struct of_device_id uniphier_usb3_reset_match[] = { + { + .compatible = "socionext,uniphier-pro4-usb3-reset", + .data = &uniphier_pro4_data, + }, + { + .compatible = "socionext,uniphier-pxs2-usb3-reset", + .data = &uniphier_pxs2_data, + }, + { + .compatible = "socionext,uniphier-ld20-usb3-reset", + .data = &uniphier_pxs2_data, + }, + { + .compatible = "socionext,uniphier-pxs3-usb3-reset", + .data = &uniphier_pxs2_data, + }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, uniphier_usb3_reset_match); + +static struct platform_driver uniphier_usb3_reset_driver = { + .probe = uniphier_usb3_reset_probe, + .remove = uniphier_usb3_reset_remove, + .driver = { + .name = "uniphier-usb3-reset", + .of_match_table = uniphier_usb3_reset_match, + }, +}; +module_platform_driver(uniphier_usb3_reset_driver); + +MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); +MODULE_DESCRIPTION("UniPhier USB3 Reset Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index e9030ff1bf2f..5605745663ae 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -202,6 +202,12 @@ static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ UNIPHIER_RESETX((id), 0x114, 24 + (ch)) +#define UNIPHIER_PERI_RESET_SCSSI(id) \ + UNIPHIER_RESETX((id), 0x110, 17) + +#define UNIPHIER_PERI_RESET_MCSSI(id) \ + UNIPHIER_RESETX((id), 0x114, 14) + static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { UNIPHIER_PERI_RESET_UART(0, 0), UNIPHIER_PERI_RESET_UART(1, 1), @@ -212,6 +218,7 @@ static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { UNIPHIER_PERI_RESET_I2C(6, 2), UNIPHIER_PERI_RESET_I2C(7, 3), UNIPHIER_PERI_RESET_I2C(8, 4), + UNIPHIER_PERI_RESET_SCSSI(11), UNIPHIER_RESET_END, }; @@ -227,6 +234,8 @@ static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { UNIPHIER_PERI_RESET_FI2C(8, 4), UNIPHIER_PERI_RESET_FI2C(9, 5), UNIPHIER_PERI_RESET_FI2C(10, 6), + UNIPHIER_PERI_RESET_SCSSI(11), + UNIPHIER_PERI_RESET_MCSSI(12), UNIPHIER_RESET_END, }; diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index dcf8c8065508..a5577dd5eb08 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -628,10 +628,26 @@ static const struct of_device_id ddr_shimphy_dt_ids[] = { static const struct of_device_id brcmstb_memc_of_match[] = { { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1", + .data = &ddr_seq, + }, + { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3", + .data = &ddr_seq_b22, + }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", + .data = &ddr_seq_b22, + }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1", + .data = &ddr_seq_b22, + }, + { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq, }, diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig index 7a9fb9baa66d..8f80e8bbf29e 100644 --- a/drivers/soc/fsl/Kconfig +++ b/drivers/soc/fsl/Kconfig @@ -1,7 +1,9 @@ # -# Freescale SOC drivers +# NXP/Freescale QorIQ series SOC drivers # +menu "NXP/Freescale QorIQ SoC drivers" + source "drivers/soc/fsl/qbman/Kconfig" source "drivers/soc/fsl/qe/Kconfig" @@ -16,3 +18,14 @@ config FSL_GUTS Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading RCW, should eventually be moved into this driver as well. + +config FSL_MC_DPIO + tristate "QorIQ DPAA2 DPIO driver" + depends on FSL_MC_BUS + help + Driver for the DPAA2 DPIO object. A DPIO provides queue and + buffer management facilities for software to interact with + other DPAA2 objects. This driver does not expose the DPIO + objects individually, but groups them under a service layer + API. +endmenu diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile index 44b3bebef24a..803ef1bfb5ff 100644 --- a/drivers/soc/fsl/Makefile +++ b/drivers/soc/fsl/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_FSL_DPAA) += qbman/ obj-$(CONFIG_QUICC_ENGINE) += qe/ obj-$(CONFIG_CPM) += qe/ obj-$(CONFIG_FSL_GUTS) += guts.o +obj-$(CONFIG_FSL_MC_DPIO) += dpio/ diff --git a/drivers/staging/fsl-mc/bus/dpio/Makefile b/drivers/soc/fsl/dpio/Makefile index b9ff24c76582..b9ff24c76582 100644 --- a/drivers/staging/fsl-mc/bus/dpio/Makefile +++ b/drivers/soc/fsl/dpio/Makefile diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h b/drivers/soc/fsl/dpio/dpio-cmd.h index ab8f82ee7ee5..ab8f82ee7ee5 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h +++ b/drivers/soc/fsl/dpio/dpio-cmd.h diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c b/drivers/soc/fsl/dpio/dpio-driver.c index 11a90a90d827..b60b77bfaffa 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c +++ b/drivers/soc/fsl/dpio/dpio-driver.c @@ -16,7 +16,7 @@ #include <linux/io.h> #include <linux/fsl/mc.h> -#include "../../include/dpaa2-io.h" +#include <soc/fsl/dpaa2-io.h> #include "qbman-portal.h" #include "dpio.h" diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c b/drivers/soc/fsl/dpio/dpio-service.c index 14ed2beb7432..9b17f72349ed 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c +++ b/drivers/soc/fsl/dpio/dpio-service.c @@ -6,7 +6,7 @@ */ #include <linux/types.h> #include <linux/fsl/mc.h> -#include "../../include/dpaa2-io.h" +#include <soc/fsl/dpaa2-io.h> #include <linux/init.h> #include <linux/module.h> #include <linux/platform_device.h> diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio.c b/drivers/soc/fsl/dpio/dpio.c index ff37c80e11a0..ff37c80e11a0 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio.c +++ b/drivers/soc/fsl/dpio/dpio.c diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio.h b/drivers/soc/fsl/dpio/dpio.h index 49194c8e45f1..49194c8e45f1 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio.h +++ b/drivers/soc/fsl/dpio/dpio.h diff --git a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c b/drivers/soc/fsl/dpio/qbman-portal.c index 116fafb28640..cf1d448ea468 100644 --- a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c +++ b/drivers/soc/fsl/dpio/qbman-portal.c @@ -8,7 +8,7 @@ #include <asm/cacheflush.h> #include <linux/io.h> #include <linux/slab.h> -#include "../../include/dpaa2-global.h" +#include <soc/fsl/dpaa2-global.h> #include "qbman-portal.h" diff --git a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h b/drivers/soc/fsl/dpio/qbman-portal.h index 69db3c818742..89d1dd9969b6 100644 --- a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h +++ b/drivers/soc/fsl/dpio/qbman-portal.h @@ -7,7 +7,7 @@ #ifndef __FSL_QBMAN_PORTAL_H #define __FSL_QBMAN_PORTAL_H -#include "../../include/dpaa2-fd.h" +#include <soc/fsl/dpaa2-fd.h> struct dpaa2_dq; struct qbman_swp; diff --git a/drivers/soc/fsl/qbman/Kconfig b/drivers/soc/fsl/qbman/Kconfig index fb4e6bf0a0c4..d570cb5fd381 100644 --- a/drivers/soc/fsl/qbman/Kconfig +++ b/drivers/soc/fsl/qbman/Kconfig @@ -1,5 +1,5 @@ menuconfig FSL_DPAA - bool "Freescale DPAA 1.x support" + bool "QorIQ DPAA1 framework support" depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE) select GENERIC_ALLOCATOR help diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index 73a2e08b47ef..fabba17e9d65 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -3,7 +3,7 @@ # config QUICC_ENGINE - bool "Freescale QUICC Engine (QE) Support" + bool "QUICC Engine (QE) framework support" depends on FSL_SOC && PPC32 select GENERIC_ALLOCATOR select CRC32 diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 3b27075c21a7..819bed0f5667 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -83,6 +83,33 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) spin_unlock_irqrestore(&qe_gc->lock, flags); } +static void qe_gpio_set_multiple(struct gpio_chip *gc, + unsigned long *mask, unsigned long *bits) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); + struct qe_pio_regs __iomem *regs = mm_gc->regs; + unsigned long flags; + int i; + + spin_lock_irqsave(&qe_gc->lock, flags); + + for (i = 0; i < gc->ngpio; i++) { + if (*mask == 0) + break; + if (__test_and_clear_bit(i, mask)) { + if (test_bit(i, bits)) + qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); + else + qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); + } + } + + out_be32(®s->cpdata, qe_gc->cpdata); + + spin_unlock_irqrestore(&qe_gc->lock, flags); +} + static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); @@ -298,6 +325,7 @@ static int __init qe_add_gpiochips(void) gc->direction_output = qe_gpio_dir_out; gc->get = qe_gpio_get; gc->set = qe_gpio_set; + gc->set_multiple = qe_gpio_set_multiple; ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc); if (ret) diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c index 546960a18d60..b3da635970ea 100644 --- a/drivers/soc/imx/gpc.c +++ b/drivers/soc/imx/gpc.c @@ -54,7 +54,6 @@ struct imx_pm_domain { unsigned int reg_offs; signed char cntr_pdn_bit; unsigned int ipg_rate_mhz; - unsigned int flags; }; static inline struct imx_pm_domain * @@ -69,9 +68,6 @@ static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd) int iso, iso2sw; u32 val; - if (pd->flags & PGC_DOMAIN_FLAG_NO_PD) - return -EBUSY; - /* Read ISO and ISO2SW power down delays */ regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val); iso = val & 0x3f; @@ -295,26 +291,31 @@ static struct imx_pm_domain imx_gpc_domains[] = { struct imx_gpc_dt_data { int num_domains; bool err009619_present; + bool err006287_present; }; static const struct imx_gpc_dt_data imx6q_dt_data = { .num_domains = 2, .err009619_present = false, + .err006287_present = false, }; static const struct imx_gpc_dt_data imx6qp_dt_data = { .num_domains = 2, .err009619_present = true, + .err006287_present = false, }; static const struct imx_gpc_dt_data imx6sl_dt_data = { .num_domains = 3, .err009619_present = false, + .err006287_present = true, }; static const struct imx_gpc_dt_data imx6sx_dt_data = { .num_domains = 4, .err009619_present = false, + .err006287_present = false, }; static const struct of_device_id imx_gpc_dt_ids[] = { @@ -434,8 +435,13 @@ static int imx_gpc_probe(struct platform_device *pdev) /* Disable PU power down in normal operation if ERR009619 is present */ if (of_id_data->err009619_present) - imx_gpc_domains[GPC_PGC_DOMAIN_PU].flags |= - PGC_DOMAIN_FLAG_NO_PD; + imx_gpc_domains[GPC_PGC_DOMAIN_PU].base.flags |= + GENPD_FLAG_ALWAYS_ON; + + /* Keep DISP always on if ERR006287 is present */ + if (of_id_data->err006287_present) + imx_gpc_domains[GPC_PGC_DOMAIN_DISPLAY].base.flags |= + GENPD_FLAG_ALWAYS_ON; if (!pgc_node) { ret = imx_gpc_old_dt_init(&pdev->dev, regmap, diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 2afae64061d8..4e931fdf4d09 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -146,6 +146,21 @@ static const u32 mt6397_regs[] = { [PWRAP_DEW_CIPHER_SWRST] = 0xbc24, }; +static const u32 mt6351_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x02F2, + [PWRAP_DEW_READ_TEST] = 0x02F4, + [PWRAP_DEW_WRITE_TEST] = 0x02F6, + [PWRAP_DEW_CRC_EN] = 0x02FA, + [PWRAP_DEW_CRC_VAL] = 0x02FC, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302, + [PWRAP_DEW_CIPHER_EN] = 0x0304, + [PWRAP_DEW_CIPHER_RDY] = 0x0306, + [PWRAP_DEW_CIPHER_MODE] = 0x0308, + [PWRAP_DEW_CIPHER_SWRST] = 0x030A, + [PWRAP_DEW_RDDMY_NO] = 0x030C, +}; + enum pwrap_regs { PWRAP_MUX_SEL, PWRAP_WRAP_EN, @@ -366,6 +381,39 @@ static int mt2701_regs[] = { [PWRAP_ADC_RDATA_ADDR2] = 0x154, }; +static int mt6797_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_SIDLY] = 0xC, + [PWRAP_RDDMY] = 0x10, + [PWRAP_CSHEXT_WRITE] = 0x18, + [PWRAP_CSHEXT_READ] = 0x1C, + [PWRAP_CSLEXT_START] = 0x20, + [PWRAP_CSLEXT_END] = 0x24, + [PWRAP_STAUPD_PRD] = 0x28, + [PWRAP_HARB_HPRIO] = 0x50, + [PWRAP_HIPRIO_ARB_EN] = 0x54, + [PWRAP_MAN_EN] = 0x60, + [PWRAP_MAN_CMD] = 0x64, + [PWRAP_WACS0_EN] = 0x70, + [PWRAP_WACS1_EN] = 0x84, + [PWRAP_WACS2_EN] = 0x98, + [PWRAP_INIT_DONE2] = 0x9C, + [PWRAP_WACS2_CMD] = 0xA0, + [PWRAP_WACS2_RDATA] = 0xA4, + [PWRAP_WACS2_VLDCLR] = 0xA8, + [PWRAP_INT_EN] = 0xC0, + [PWRAP_INT_FLG_RAW] = 0xC4, + [PWRAP_INT_FLG] = 0xC8, + [PWRAP_INT_CLR] = 0xCC, + [PWRAP_TIMER_EN] = 0xF4, + [PWRAP_WDT_UNIT] = 0xFC, + [PWRAP_WDT_SRC_EN] = 0x100, + [PWRAP_DCM_EN] = 0x1CC, + [PWRAP_DCM_DBC_PRD] = 0x1D4, +}; + static int mt7622_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -635,12 +683,14 @@ static int mt8135_regs[] = { enum pmic_type { PMIC_MT6323, + PMIC_MT6351, PMIC_MT6380, PMIC_MT6397, }; enum pwrap_type { PWRAP_MT2701, + PWRAP_MT6797, PWRAP_MT7622, PWRAP_MT8135, PWRAP_MT8173, @@ -1067,6 +1117,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_CIPHER_START); break; case PWRAP_MT2701: + case PWRAP_MT6797: case PWRAP_MT8173: pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); break; @@ -1080,8 +1131,6 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1); switch (wrp->slave->type) { case PMIC_MT6397: @@ -1091,6 +1140,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) 0x1); break; case PMIC_MT6323: + case PMIC_MT6351: pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN], 0x1); break; @@ -1367,6 +1417,15 @@ static const struct pwrap_slv_type pmic_mt6397 = { .pwrap_write = pwrap_write16, }; +static const struct pwrap_slv_type pmic_mt6351 = { + .dew_regs = mt6351_regs, + .type = PMIC_MT6351, + .regmap = &pwrap_regmap_config16, + .caps = 0, + .pwrap_read = pwrap_read16, + .pwrap_write = pwrap_write16, +}; + static const struct of_device_id of_slave_match_tbl[] = { { .compatible = "mediatek,mt6323", @@ -1381,6 +1440,9 @@ static const struct of_device_id of_slave_match_tbl[] = { .compatible = "mediatek,mt6397", .data = &pmic_mt6397, }, { + .compatible = "mediatek,mt6351", + .data = &pmic_mt6351, + }, { /* sentinel */ } }; @@ -1398,6 +1460,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = { .init_soc_specific = pwrap_mt2701_init_soc_specific, }; +static const struct pmic_wrapper_type pwrap_mt6797 = { + .regs = mt6797_regs, + .type = PWRAP_MT6797, + .arb_en_all = 0x01fff, + .int_en_all = 0xffffffc6, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .has_bridge = 0, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = NULL, +}; + static const struct pmic_wrapper_type pwrap_mt7622 = { .regs = mt7622_regs, .type = PWRAP_MT7622, @@ -1439,6 +1513,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701, }, { + .compatible = "mediatek,mt6797-pwrap", + .data = &pwrap_mt6797, + }, { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622, }, { diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 7dc0f20d7907..c37b0803c1b6 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -18,6 +18,9 @@ obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o +ifdef CONFIG_SMP +obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o +endif # Family obj-$(CONFIG_RST_RCAR) += rcar-rst.o diff --git a/drivers/soc/renesas/r9a06g032-smp.c b/drivers/soc/renesas/r9a06g032-smp.c new file mode 100644 index 000000000000..a1926e8d73f2 --- /dev/null +++ b/drivers/soc/renesas/r9a06g032-smp.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R9A06G032 Second CA7 enabler. + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> + * Derived from actions,s500-smp + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/smp.h> + +/* + * The second CPU is parked in ROM at boot time. It requires waking it after + * writing an address into the BOOTADDR register of sysctrl. + * + * So the default value of the "cpu-release-addr" corresponds to BOOTADDR... + * + * *However* the BOOTADDR register is not available when the kernel + * starts in NONSEC mode. + * + * So for NONSEC mode, the bootloader re-parks the second CPU into a pen + * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address, + * which is not restricted. + */ + +static void __iomem *cpu_bootaddr; + +static DEFINE_SPINLOCK(cpu_lock); + +static int +r9a06g032_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + if (!cpu_bootaddr) + return -ENODEV; + + spin_lock(&cpu_lock); + + writel(__pa_symbol(secondary_startup), cpu_bootaddr); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + spin_unlock(&cpu_lock); + + return 0; +} + +static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *dn; + int ret = -EINVAL, dns; + u32 bootaddr; + + dn = of_get_cpu_node(1, NULL); + if (!dn) { + pr_err("CPU#1: missing device tree node\n"); + return; + } + /* + * Determine the address from which the CPU is polling. + * The bootloader *does* change this property. + * Note: The property can be either 64 or 32 bits, so handle both cases + */ + if (of_find_property(dn, "cpu-release-addr", &dns)) { + if (dns == sizeof(u64)) { + u64 temp; + + ret = of_property_read_u64(dn, + "cpu-release-addr", &temp); + bootaddr = temp; + } else { + ret = of_property_read_u32(dn, + "cpu-release-addr", + &bootaddr); + } + } + of_node_put(dn); + if (ret) { + pr_err("CPU#1: invalid cpu-release-addr property\n"); + return; + } + pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr); + + cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr)); +} + +static const struct smp_operations r9a06g032_smp_ops __initconst = { + .smp_prepare_cpus = r9a06g032_smp_prepare_cpus, + .smp_boot_secondary = r9a06g032_smp_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(r9a06g032_smp, + "renesas,r9a06g032-smp", &r9a06g032_smp_ops); diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index 50d03d8b4f9a..029188e8be6e 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -58,6 +58,12 @@ #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */ +struct rcar_sysc_ch { + u16 chan_offs; + u8 chan_bit; + u8 isr_bit; +}; + static void __iomem *rcar_sysc_base; static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ @@ -143,12 +149,12 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on) return ret; } -int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch) +static int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch) { return rcar_sysc_power(sysc_ch, false); } -int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch) +static int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch) { return rcar_sysc_power(sysc_ch, true); } @@ -315,6 +321,8 @@ struct rcar_pm_domains { struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1]; }; +static struct genpd_onecell_data *rcar_sysc_onecell_data; + static int __init rcar_sysc_pd_init(void) { const struct rcar_sysc_info *info; @@ -326,9 +334,6 @@ static int __init rcar_sysc_pd_init(void) unsigned int i; int error; - if (rcar_sysc_base) - return 0; - np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match); if (!np) return -ENODEV; @@ -361,6 +366,7 @@ static int __init rcar_sysc_pd_init(void) domains->onecell_data.domains = domains->domains; domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains); + rcar_sysc_onecell_data = &domains->onecell_data; for (i = 0, syscier = 0; i < info->num_areas; i++) syscier |= BIT(info->areas[i].isr_bit); @@ -448,27 +454,39 @@ void __init rcar_sysc_nullify(struct rcar_sysc_area *areas, } } -void __init rcar_sysc_init(phys_addr_t base, u32 syscier) +#ifdef CONFIG_ARCH_R8A7779 +static int rcar_sysc_power_cpu(unsigned int idx, bool on) { - u32 syscimr; + struct generic_pm_domain *genpd; + struct rcar_sysc_pd *pd; + unsigned int i; - if (!rcar_sysc_pd_init()) - return; + if (!rcar_sysc_onecell_data) + return -ENODEV; - rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE); + for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) { + genpd = rcar_sysc_onecell_data->domains[i]; + if (!genpd) + continue; - /* - * Mask all interrupt sources to prevent the CPU from receiving them. - * Make sure not to clear reserved bits that were set before. - */ - syscimr = ioread32(rcar_sysc_base + SYSCIMR); - syscimr |= syscier; - pr_debug("%s: syscimr = 0x%08x\n", __func__, syscimr); - iowrite32(syscimr, rcar_sysc_base + SYSCIMR); + pd = to_rcar_pd(genpd); + if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx) + continue; - /* - * SYSC needs all interrupt sources enabled to control power. - */ - pr_debug("%s: syscier = 0x%08x\n", __func__, syscier); - iowrite32(syscier, rcar_sysc_base + SYSCIER); + return on ? rcar_sysc_power_up(&pd->ch) + : rcar_sysc_power_down(&pd->ch); + } + + return -ENOENT; +} + +int rcar_sysc_power_down_cpu(unsigned int cpu) +{ + return rcar_sysc_power_cpu(cpu, false); +} + +int rcar_sysc_power_up_cpu(unsigned int cpu) +{ + return rcar_sysc_power_cpu(cpu, true); } +#endif /* CONFIG_ARCH_R8A7779 */ diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 882be5ed7e84..b4b0f3480bd3 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -17,6 +17,7 @@ #include <linux/of_address.h> #include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/regmap.h> #include <linux/soc/sunxi/sunxi_sram.h> @@ -63,6 +64,12 @@ static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = { SUNXI_SRAM_MAP(1, 1, "emac")), }; +static struct sunxi_sram_desc sun4i_a10_sram_c1 = { + .data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31, + SUNXI_SRAM_MAP(0, 0, "cpu"), + SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")), +}; + static struct sunxi_sram_desc sun4i_a10_sram_d = { .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1, SUNXI_SRAM_MAP(0, 0, "cpu"), @@ -81,6 +88,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = { .data = &sun4i_a10_sram_a3_a4.data, }, { + .compatible = "allwinner,sun4i-a10-sram-c1", + .data = &sun4i_a10_sram_c1.data, + }, + { .compatible = "allwinner,sun4i-a10-sram-d", .data = &sun4i_a10_sram_d.data, }, @@ -281,13 +292,51 @@ int sunxi_sram_release(struct device *dev) } EXPORT_SYMBOL(sunxi_sram_release); +struct sunxi_sramc_variant { + bool has_emac_clock; +}; + +static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { + /* Nothing special */ +}; + +static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = { + .has_emac_clock = true, +}; + +#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 +static bool sunxi_sram_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + if (reg == SUNXI_SRAM_EMAC_CLOCK_REG) + return true; + return false; +} + +static struct regmap_config sunxi_sram_emac_clock_regmap = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + /* last defined register */ + .max_register = SUNXI_SRAM_EMAC_CLOCK_REG, + /* other devices have no business accessing other registers */ + .readable_reg = sunxi_sram_regmap_accessible_reg, + .writeable_reg = sunxi_sram_regmap_accessible_reg, +}; + static int sunxi_sram_probe(struct platform_device *pdev) { struct resource *res; struct dentry *d; + struct regmap *emac_clock; + const struct sunxi_sramc_variant *variant; sram_dev = &pdev->dev; + variant = of_device_get_match_data(&pdev->dev); + if (!variant) + return -EINVAL; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) @@ -300,12 +349,46 @@ static int sunxi_sram_probe(struct platform_device *pdev) if (!d) return -ENOMEM; + if (variant->has_emac_clock) { + emac_clock = devm_regmap_init_mmio(&pdev->dev, base, + &sunxi_sram_emac_clock_regmap); + + if (IS_ERR(emac_clock)) + return PTR_ERR(emac_clock); + } + return 0; } static const struct of_device_id sunxi_sram_dt_match[] = { - { .compatible = "allwinner,sun4i-a10-sram-controller" }, - { .compatible = "allwinner,sun50i-a64-sram-controller" }, + { + .compatible = "allwinner,sun4i-a10-sram-controller", + .data = &sun4i_a10_sramc_variant, + }, + { + .compatible = "allwinner,sun4i-a10-system-control", + .data = &sun4i_a10_sramc_variant, + }, + { + .compatible = "allwinner,sun5i-a13-system-control", + .data = &sun4i_a10_sramc_variant, + }, + { + .compatible = "allwinner,sun8i-a23-system-control", + .data = &sun4i_a10_sramc_variant, + }, + { + .compatible = "allwinner,sun8i-h3-system-control", + .data = &sun4i_a10_sramc_variant, + }, + { + .compatible = "allwinner,sun50i-a64-sram-controller", + .data = &sun50i_a64_sramc_variant, + }, + { + .compatible = "allwinner,sun50i-a64-system-control", + .data = &sun50i_a64_sramc_variant, + }, { }, }; MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 92770d84a288..be4570baad96 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -1,3 +1,17 @@ +# 64-bit ARM SoCs from TI +if ARM64 + +if ARCH_K3 + +config ARCH_K3_AM6_SOC + bool "K3 AM6 SoC" + help + Enable support for TI's AM6 SoC Family support + +endif + +endif + # # TI SOC drivers # diff --git a/drivers/soc/ti/pm33xx.c b/drivers/soc/ti/pm33xx.c index 652739c7f718..d0dab323651f 100644 --- a/drivers/soc/ti/pm33xx.c +++ b/drivers/soc/ti/pm33xx.c @@ -41,6 +41,8 @@ static struct am33xx_pm_sram_addr *pm_sram; static struct device *pm33xx_dev; static struct wkup_m3_ipc *m3_ipc; +static unsigned long suspend_wfi_flags; + static u32 sram_suspend_address(unsigned long addr) { return ((unsigned long)am33xx_do_wfi_sram + @@ -53,7 +55,7 @@ static int am33xx_pm_suspend(suspend_state_t suspend_state) int i, ret = 0; ret = pm_ops->soc_suspend((unsigned long)suspend_state, - am33xx_do_wfi_sram); + am33xx_do_wfi_sram, suspend_wfi_flags); if (ret) { dev_err(pm33xx_dev, "PM: Kernel suspend failure\n"); @@ -227,6 +229,7 @@ static int am33xx_push_sram_idle(void) ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data; ro_sram_data.amx3_pm_sram_data_phys = gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data); + ro_sram_data.rtc_base_virt = pm_ops->get_rtc_base_addr(); /* Save physical address to calculate resume offset during pm init */ am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool, @@ -310,6 +313,17 @@ static int am33xx_pm_probe(struct platform_device *pdev) suspend_set_ops(&am33xx_pm_ops); #endif /* CONFIG_SUSPEND */ + /* + * For a system suspend we must flush the caches, we want + * the DDR in self-refresh, we want to save the context + * of the EMIF, and we want the wkup_m3 to handle low-power + * transition. + */ + suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE; + suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH; + suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF; + suspend_wfi_flags |= WFI_FLAG_WAKE_M3; + ret = pm_ops->init(); if (ret) { dev_err(dev, "Unable to call core pm init!\n"); diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 369aef5e7228..f5cb8c0af09f 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -46,6 +46,7 @@ #define M3_BASELINE_VERSION 0x191 #define M3_STATUS_RESP_MASK (0xffff << 16) #define M3_FW_VERSION_MASK 0xffff +#define M3_WAKE_SRC_MASK 0xff #define M3_STATE_UNKNOWN 0 #define M3_STATE_RESET 1 @@ -55,6 +56,23 @@ static struct wkup_m3_ipc *m3_ipc_state; +static const struct wkup_m3_wakeup_src wakeups[] = { + {.irq_nr = 35, .src = "USB0_PHY"}, + {.irq_nr = 36, .src = "USB1_PHY"}, + {.irq_nr = 40, .src = "I2C0"}, + {.irq_nr = 41, .src = "RTC Timer"}, + {.irq_nr = 42, .src = "RTC Alarm"}, + {.irq_nr = 43, .src = "Timer0"}, + {.irq_nr = 44, .src = "Timer1"}, + {.irq_nr = 45, .src = "UART"}, + {.irq_nr = 46, .src = "GPIO0"}, + {.irq_nr = 48, .src = "MPU_WAKE"}, + {.irq_nr = 49, .src = "WDT0"}, + {.irq_nr = 50, .src = "WDT1"}, + {.irq_nr = 51, .src = "ADC_TSC"}, + {.irq_nr = 0, .src = "Unknown"}, +}; + static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc) { writel(AM33XX_M3_TXEV_ACK, @@ -329,12 +347,45 @@ static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc) return 0; } +/** + * wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3 + * @m3_ipc: Pointer to wkup_m3_ipc context + */ +static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc) +{ + unsigned int wakeup_src_idx; + int j, val; + + val = wkup_m3_ctrl_ipc_read(m3_ipc, 6); + + wakeup_src_idx = val & M3_WAKE_SRC_MASK; + + for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) { + if (wakeups[j].irq_nr == wakeup_src_idx) + return wakeups[j].src; + } + return wakeups[j].src; +} + +/** + * wkup_m3_set_rtc_only - Set the rtc_only flag + * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the + * wakeup src value + */ +static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc) +{ + if (m3_ipc_state) + m3_ipc_state->is_rtc_only = true; +} + static struct wkup_m3_ipc_ops ipc_ops = { .set_mem_type = wkup_m3_set_mem_type, .set_resume_address = wkup_m3_set_resume_address, .prepare_low_power = wkup_m3_prepare_low_power, .finish_low_power = wkup_m3_finish_low_power, .request_pm_status = wkup_m3_request_pm_status, + .request_wake_src = wkup_m3_request_wake_src, + .set_rtc_only = wkup_m3_set_rtc_only, }; /** @@ -484,6 +535,30 @@ static int wkup_m3_ipc_remove(struct platform_device *pdev) return 0; } +static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev) +{ + /* + * Nothing needs to be done on suspend even with rtc_only flag set + */ + return 0; +} + +static int __maybe_unused wkup_m3_ipc_resume(struct device *dev) +{ + if (m3_ipc_state->is_rtc_only) { + rproc_shutdown(m3_ipc_state->rproc); + rproc_boot(m3_ipc_state->rproc); + } + + m3_ipc_state->is_rtc_only = false; + + return 0; +} + +static const struct dev_pm_ops wkup_m3_ipc_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume) +}; + static const struct of_device_id wkup_m3_ipc_of_match[] = { { .compatible = "ti,am3352-wkup-m3-ipc", }, { .compatible = "ti,am4372-wkup-m3-ipc", }, @@ -497,6 +572,7 @@ static struct platform_driver wkup_m3_ipc_driver = { .driver = { .name = "wkup_m3_ipc", .of_match_table = wkup_m3_ipc_of_match, + .pm = &wkup_m3_ipc_pm_ops, }, }; diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 396fb3d56398..1abf76be2aa8 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -90,8 +90,6 @@ source "drivers/staging/clocking-wizard/Kconfig" source "drivers/staging/fbtft/Kconfig" -source "drivers/staging/fsl-mc/Kconfig" - source "drivers/staging/fsl-dpaa2/Kconfig" source "drivers/staging/wilc1000/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index ad7b4ca412ef..ab0cbe8815b1 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -35,7 +35,6 @@ obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/ obj-$(CONFIG_UNISYSSPAR) += unisys/ obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/ obj-$(CONFIG_FB_TFT) += fbtft/ -obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/ obj-$(CONFIG_FSL_DPAA2) += fsl-dpaa2/ obj-$(CONFIG_WILC1000) += wilc1000/ obj-$(CONFIG_MOST) += most/ diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c index e2dac44eccbe..9329fcad95ac 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c @@ -426,7 +426,7 @@ static int build_sg_fd(struct dpaa2_eth_priv *priv, dpaa2_fd_set_format(fd, dpaa2_fd_sg); dpaa2_fd_set_addr(fd, addr); dpaa2_fd_set_len(fd, skb->len); - dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_PTA | DPAA2_FD_CTRL_PTV1); + dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA | FD_CTRL_PTV1); if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) enable_tx_tstamp(fd, sgt_buf); @@ -479,7 +479,7 @@ static int build_single_fd(struct dpaa2_eth_priv *priv, dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start)); dpaa2_fd_set_len(fd, skb->len); dpaa2_fd_set_format(fd, dpaa2_fd_single); - dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_PTA | DPAA2_FD_CTRL_PTV1); + dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA | FD_CTRL_PTV1); if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) enable_tx_tstamp(fd, buffer_start); diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h index 506466778b2c..d54cb0b99d08 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h @@ -10,8 +10,8 @@ #include <linux/if_vlan.h> #include <linux/fsl/mc.h> -#include "../../fsl-mc/include/dpaa2-io.h" -#include "../../fsl-mc/include/dpaa2-fd.h" +#include <soc/fsl/dpaa2-io.h> +#include <soc/fsl/dpaa2-fd.h> #include "dpni.h" #include "dpni-cmd.h" @@ -97,21 +97,13 @@ struct dpaa2_eth_swa { #define DPAA2_FD_FRC_FAICFDV 0x0400 /* Error bits in FD CTRL */ -#define DPAA2_FD_CTRL_UFD 0x00000004 -#define DPAA2_FD_CTRL_SBE 0x00000008 -#define DPAA2_FD_CTRL_FSE 0x00000020 -#define DPAA2_FD_CTRL_FAERR 0x00000040 - -#define DPAA2_FD_RX_ERR_MASK (DPAA2_FD_CTRL_SBE | \ - DPAA2_FD_CTRL_FAERR) -#define DPAA2_FD_TX_ERR_MASK (DPAA2_FD_CTRL_UFD | \ - DPAA2_FD_CTRL_SBE | \ - DPAA2_FD_CTRL_FSE | \ - DPAA2_FD_CTRL_FAERR) +#define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) +#define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ + FD_CTRL_SBE | \ + FD_CTRL_FSE | \ + FD_CTRL_FAERR) /* Annotation bits in FD CTRL */ -#define DPAA2_FD_CTRL_PTA 0x00800000 -#define DPAA2_FD_CTRL_PTV1 0x00400000 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ /* Frame annotation status */ diff --git a/drivers/staging/fsl-mc/Kconfig b/drivers/staging/fsl-mc/Kconfig deleted file mode 100644 index 3002229bec1b..000000000000 --- a/drivers/staging/fsl-mc/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -source "drivers/staging/fsl-mc/bus/Kconfig" diff --git a/drivers/staging/fsl-mc/Makefile b/drivers/staging/fsl-mc/Makefile deleted file mode 100644 index 14683889dabd..000000000000 --- a/drivers/staging/fsl-mc/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# Freescale Management Complex (MC) bus drivers -obj-$(CONFIG_FSL_MC_BUS) += bus/ diff --git a/drivers/staging/fsl-mc/bus/Kconfig b/drivers/staging/fsl-mc/bus/Kconfig deleted file mode 100644 index 342453035269..000000000000 --- a/drivers/staging/fsl-mc/bus/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# DPAA2 fsl-mc bus -# -# Copyright (C) 2014-2016 Freescale Semiconductor, Inc. -# - -config FSL_MC_DPIO - tristate "QorIQ DPAA2 DPIO driver" - depends on FSL_MC_BUS - help - Driver for the DPAA2 DPIO object. A DPIO provides queue and - buffer management facilities for software to interact with - other DPAA2 objects. This driver does not expose the DPIO - objects individually, but groups them under a service layer - API. diff --git a/drivers/staging/fsl-mc/bus/Makefile b/drivers/staging/fsl-mc/bus/Makefile deleted file mode 100644 index 21d8ebc8ce21..000000000000 --- a/drivers/staging/fsl-mc/bus/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Freescale Management Complex (MC) bus drivers -# -# Copyright (C) 2014 Freescale Semiconductor, Inc. -# - -# MC DPIO driver -obj-$(CONFIG_FSL_MC_DPIO) += dpio/ diff --git a/drivers/tee/optee/Kconfig b/drivers/tee/optee/Kconfig index 0126de898036..3c59e19029be 100644 --- a/drivers/tee/optee/Kconfig +++ b/drivers/tee/optee/Kconfig @@ -5,3 +5,11 @@ config OPTEE help This implements the OP-TEE Trusted Execution Environment (TEE) driver. + +config OPTEE_SHM_NUM_PRIV_PAGES + int "Private Shared Memory Pages" + default 1 + depends on OPTEE + help + This sets the number of private shared memory pages to be + used by OP-TEE TEE driver. diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index e5fd5ed217da..e1aafe842d66 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -32,7 +32,7 @@ #define DRIVER_NAME "optee" -#define OPTEE_SHM_NUM_PRIV_PAGES 1 +#define OPTEE_SHM_NUM_PRIV_PAGES CONFIG_OPTEE_SHM_NUM_PRIV_PAGES /** * optee_from_msg_param() - convert from OPTEE_MSG parameters to diff --git a/drivers/tee/optee/rpc.c b/drivers/tee/optee/rpc.c index 41aea12e2bcc..b45c73dd37a5 100644 --- a/drivers/tee/optee/rpc.c +++ b/drivers/tee/optee/rpc.c @@ -48,7 +48,7 @@ static void handle_rpc_func_cmd_get_time(struct optee_msg_arg *arg) OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT) goto bad; - getnstimeofday64(&ts); + ktime_get_real_ts64(&ts); arg->params[0].u.value.a = ts.tv_sec; arg->params[0].u.value.b = ts.tv_nsec; diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index d9145a8f35d2..8e3bab1e0c1f 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -161,16 +161,10 @@ static int exynos_ehci_probe(struct platform_device *pdev) } exynos_ehci = to_exynos_ehci(hcd); - if (of_device_is_compatible(pdev->dev.of_node, - "samsung,exynos5440-ehci")) - goto skip_phy; - err = exynos_ehci_get_phy(&pdev->dev, exynos_ehci); if (err) goto fail_clk; -skip_phy: - exynos_ehci->clk = devm_clk_get(&pdev->dev, "usbhost"); if (IS_ERR(exynos_ehci->clk)) { @@ -304,7 +298,6 @@ static const struct dev_pm_ops exynos_ehci_pm_ops = { #ifdef CONFIG_OF static const struct of_device_id exynos_ehci_match[] = { { .compatible = "samsung,exynos4210-ehci" }, - { .compatible = "samsung,exynos5440-ehci" }, {}, }; MODULE_DEVICE_TABLE(of, exynos_ehci_match); diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c index a39fae41bc70..c0c4dcca6f3c 100644 --- a/drivers/usb/host/ohci-exynos.c +++ b/drivers/usb/host/ohci-exynos.c @@ -130,15 +130,10 @@ static int exynos_ohci_probe(struct platform_device *pdev) exynos_ohci = to_exynos_ohci(hcd); - if (of_device_is_compatible(pdev->dev.of_node, - "samsung,exynos5440-ohci")) - goto skip_phy; - err = exynos_ohci_get_phy(&pdev->dev, exynos_ohci); if (err) goto fail_clk; -skip_phy: exynos_ohci->clk = devm_clk_get(&pdev->dev, "usbhost"); if (IS_ERR(exynos_ohci->clk)) { @@ -270,7 +265,6 @@ static const struct dev_pm_ops exynos_ohci_pm_ops = { #ifdef CONFIG_OF static const struct of_device_id exynos_ohci_match[] = { { .compatible = "samsung,exynos4210-ohci" }, - { .compatible = "samsung,exynos5440-ohci" }, {}, }; MODULE_DEVICE_TABLE(of, exynos_ohci_match); diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig index e91edef98633..787792c3d08d 100644 --- a/drivers/video/console/Kconfig +++ b/drivers/video/console/Kconfig @@ -152,7 +152,7 @@ config FRAMEBUFFER_CONSOLE_ROTATION config FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER bool "Framebuffer Console Deferred Takeover" - depends on FRAMEBUFFER_CONSOLE=y && DUMMY_CONSOLE=y + depends on FB=y && FRAMEBUFFER_CONSOLE && DUMMY_CONSOLE help If enabled this defers the framebuffer console taking over the console from the dummy console until the first text is displayed on diff --git a/drivers/video/console/dummycon.c b/drivers/video/console/dummycon.c index 0254251fdd79..45ad925ad5f8 100644 --- a/drivers/video/console/dummycon.c +++ b/drivers/video/console/dummycon.c @@ -38,13 +38,11 @@ void dummycon_register_output_notifier(struct notifier_block *nb) if (dummycon_putc_called) nb->notifier_call(nb, 0, NULL); } -EXPORT_SYMBOL_GPL(dummycon_register_output_notifier); void dummycon_unregister_output_notifier(struct notifier_block *nb) { raw_notifier_chain_unregister(&dummycon_output_nh, nb); } -EXPORT_SYMBOL_GPL(dummycon_unregister_output_notifier); static void dummycon_putc(struct vc_data *vc, int c, int ypos, int xpos) { diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c index f09e17b60e45..09731b2f6815 100644 --- a/drivers/video/console/vgacon.c +++ b/drivers/video/console/vgacon.c @@ -112,6 +112,11 @@ EXPORT_SYMBOL(vgacon_text_force); static int __init text_mode(char *str) { vgacon_text_mode_force = true; + + pr_warning("You have booted with nomodeset. This means your GPU drivers are DISABLED\n"); + pr_warning("Any video related functionality will be severely degraded, and you may not even be able to suspend the system properly\n"); + pr_warning("Unless you actually understand what nomodeset does, you should reboot without enabling it\n"); + return 1; } diff --git a/drivers/video/fbdev/amifb.c b/drivers/video/fbdev/amifb.c index cc11c6061298..0777aff211e5 100644 --- a/drivers/video/fbdev/amifb.c +++ b/drivers/video/fbdev/amifb.c @@ -2303,7 +2303,7 @@ static void ami_build_copper(struct fb_info *info) ami_rebuild_copper(info->par); } - +#ifndef MODULE static void __init amifb_setup_mcap(char *spec) { char *p; @@ -2368,7 +2368,7 @@ static int __init amifb_setup(char *options) return 0; } - +#endif static int amifb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c index 5fb156bdcf4e..75ebbbf0a1fb 100644 --- a/drivers/video/fbdev/core/fbcon.c +++ b/drivers/video/fbdev/core/fbcon.c @@ -2234,8 +2234,8 @@ static int fbcon_switch(struct vc_data *vc) * * info->currcon = vc->vc_num; */ - for (i = 0; i < FB_MAX; i++) { - if (registered_fb[i] != NULL && registered_fb[i]->fbcon_par) { + for_each_registered_fb(i) { + if (registered_fb[i]->fbcon_par) { struct fbcon_ops *o = registered_fb[i]->fbcon_par; o->currcon = vc->vc_num; @@ -3124,11 +3124,9 @@ static int fbcon_fb_unregistered(struct fb_info *info) if (idx == info_idx) { info_idx = -1; - for (i = 0; i < FB_MAX; i++) { - if (registered_fb[i] != NULL) { - info_idx = i; - break; - } + for_each_registered_fb(i) { + info_idx = i; + break; } } @@ -3594,13 +3592,24 @@ static int fbcon_init_device(void) } #ifdef CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER +static void fbcon_register_existing_fbs(struct work_struct *work) +{ + int i; + + console_lock(); + + for_each_registered_fb(i) + fbcon_fb_registered(registered_fb[i]); + + console_unlock(); +} + static struct notifier_block fbcon_output_nb; +static DECLARE_WORK(fbcon_deferred_takeover_work, fbcon_register_existing_fbs); static int fbcon_output_notifier(struct notifier_block *nb, unsigned long action, void *data) { - int i; - WARN_CONSOLE_UNLOCKED(); pr_info("fbcon: Taking over console\n"); @@ -3609,45 +3618,37 @@ static int fbcon_output_notifier(struct notifier_block *nb, deferred_takeover = false; logo_shown = FBCON_LOGO_DONTSHOW; - for (i = 0; i < FB_MAX; i++) { - if (registered_fb[i]) - fbcon_fb_registered(registered_fb[i]); - } + /* We may get called in atomic context */ + schedule_work(&fbcon_deferred_takeover_work); return NOTIFY_OK; } - -static void fbcon_register_output_notifier(void) -{ - fbcon_output_nb.notifier_call = fbcon_output_notifier; - dummycon_register_output_notifier(&fbcon_output_nb); -} -#else -static inline void fbcon_register_output_notifier(void) {} #endif static void fbcon_start(void) { + WARN_CONSOLE_UNLOCKED(); + +#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER + if (conswitchp != &dummy_con) + deferred_takeover = false; + if (deferred_takeover) { - fbcon_register_output_notifier(); + fbcon_output_nb.notifier_call = fbcon_output_notifier; + dummycon_register_output_notifier(&fbcon_output_nb); return; } +#endif if (num_registered_fb) { int i; - console_lock(); - - for (i = 0; i < FB_MAX; i++) { - if (registered_fb[i] != NULL) { - info_idx = i; - break; - } + for_each_registered_fb(i) { + info_idx = i; + break; } do_fbcon_takeover(0); - console_unlock(); - } } @@ -3669,15 +3670,12 @@ static void fbcon_exit(void) kfree((void *)softback_buf); softback_buf = 0UL; - for (i = 0; i < FB_MAX; i++) { + for_each_registered_fb(i) { int pending = 0; mapped = 0; info = registered_fb[i]; - if (info == NULL) - continue; - if (info->queue.func) pending = cancel_work_sync(&info->queue); DPRINTK("fbcon: %s pending work\n", (pending ? "canceled" : @@ -3733,8 +3731,8 @@ void __init fb_console_init(void) for (i = 0; i < MAX_NR_CONSOLES; i++) con2fb_map[i] = -1; - console_unlock(); fbcon_start(); + console_unlock(); } #ifdef MODULE diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c index 609438d2465b..20405421a5ed 100644 --- a/drivers/video/fbdev/core/fbmem.c +++ b/drivers/video/fbdev/core/fbmem.c @@ -1347,6 +1347,7 @@ static long fb_compat_ioctl(struct file *file, unsigned int cmd, case FBIOGET_CON2FBMAP: case FBIOPUT_CON2FBMAP: arg = (unsigned long) compat_ptr(arg); + /* fall through */ case FBIOBLANK: ret = do_fb_ioctl(info, cmd, arg); break; @@ -1593,10 +1594,8 @@ static int do_remove_conflicting_framebuffers(struct apertures_struct *a, int i, ret; /* check all firmware fbs and kick off if the base addr overlaps */ - for (i = 0 ; i < FB_MAX; i++) { + for_each_registered_fb(i) { struct apertures_struct *gen_aper; - if (!registered_fb[i]) - continue; if (!(registered_fb[i]->flags & FBINFO_MISC_FIRMWARE)) continue; @@ -1691,25 +1690,30 @@ static int do_register_framebuffer(struct fb_info *fb_info) event.info = fb_info; if (!lockless_register_fb) console_lock(); + else + atomic_inc(&ignore_console_lock_warning); if (!lock_fb_info(fb_info)) { - if (!lockless_register_fb) - console_unlock(); - return -ENODEV; + ret = -ENODEV; + goto unlock_console; } + ret = 0; fb_notifier_call_chain(FB_EVENT_FB_REGISTERED, &event); unlock_fb_info(fb_info); +unlock_console: if (!lockless_register_fb) console_unlock(); - return 0; + else + atomic_dec(&ignore_console_lock_warning); + return ret; } -static int do_unregister_framebuffer(struct fb_info *fb_info) +static int unbind_console(struct fb_info *fb_info) { struct fb_event event; - int i, ret = 0; + int ret; + int i = fb_info->node; - i = fb_info->node; if (i < 0 || i >= FB_MAX || registered_fb[i] != fb_info) return -EINVAL; @@ -1724,17 +1728,29 @@ static int do_unregister_framebuffer(struct fb_info *fb_info) unlock_fb_info(fb_info); console_unlock(); + return ret; +} + +static int __unlink_framebuffer(struct fb_info *fb_info); + +static int do_unregister_framebuffer(struct fb_info *fb_info) +{ + struct fb_event event; + int ret; + + ret = unbind_console(fb_info); + if (ret) return -EINVAL; pm_vt_switch_unregister(fb_info->dev); - unlink_framebuffer(fb_info); + __unlink_framebuffer(fb_info); if (fb_info->pixmap.addr && (fb_info->pixmap.flags & FB_PIXMAP_DEFAULT)) kfree(fb_info->pixmap.addr); fb_destroy_modelist(&fb_info->modelist); - registered_fb[i] = NULL; + registered_fb[fb_info->node] = NULL; num_registered_fb--; fb_cleanup_device(fb_info); event.info = fb_info; @@ -1747,7 +1763,7 @@ static int do_unregister_framebuffer(struct fb_info *fb_info) return 0; } -int unlink_framebuffer(struct fb_info *fb_info) +static int __unlink_framebuffer(struct fb_info *fb_info) { int i; @@ -1759,6 +1775,20 @@ int unlink_framebuffer(struct fb_info *fb_info) device_destroy(fb_class, MKDEV(FB_MAJOR, i)); fb_info->dev = NULL; } + + return 0; +} + +int unlink_framebuffer(struct fb_info *fb_info) +{ + int ret; + + ret = __unlink_framebuffer(fb_info); + if (ret) + return ret; + + unbind_console(fb_info); + return 0; } EXPORT_SYMBOL(unlink_framebuffer); diff --git a/drivers/video/fbdev/core/modedb.c b/drivers/video/fbdev/core/modedb.c index 2510fa728d77..283d9307df21 100644 --- a/drivers/video/fbdev/core/modedb.c +++ b/drivers/video/fbdev/core/modedb.c @@ -628,45 +628,47 @@ static int fb_try_mode(struct fb_var_screeninfo *var, struct fb_info *info, } /** - * fb_find_mode - finds a valid video mode - * @var: frame buffer user defined part of display - * @info: frame buffer info structure - * @mode_option: string video mode to find - * @db: video mode database - * @dbsize: size of @db - * @default_mode: default video mode to fall back to - * @default_bpp: default color depth in bits per pixel + * fb_find_mode - finds a valid video mode + * @var: frame buffer user defined part of display + * @info: frame buffer info structure + * @mode_option: string video mode to find + * @db: video mode database + * @dbsize: size of @db + * @default_mode: default video mode to fall back to + * @default_bpp: default color depth in bits per pixel * - * Finds a suitable video mode, starting with the specified mode - * in @mode_option with fallback to @default_mode. If - * @default_mode fails, all modes in the video mode database will - * be tried. + * Finds a suitable video mode, starting with the specified mode + * in @mode_option with fallback to @default_mode. If + * @default_mode fails, all modes in the video mode database will + * be tried. * - * Valid mode specifiers for @mode_option: + * Valid mode specifiers for @mode_option:: * - * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m] or - * <name>[-<bpp>][@<refresh>] + * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][p][m] + * + * or :: * - * with <xres>, <yres>, <bpp> and <refresh> decimal numbers and - * <name> a string. + * <name>[-<bpp>][@<refresh>] * - * If 'M' is present after yres (and before refresh/bpp if present), - * the function will compute the timings using VESA(tm) Coordinated - * Video Timings (CVT). If 'R' is present after 'M', will compute with - * reduced blanking (for flatpanels). If 'i' is present, compute - * interlaced mode. If 'm' is present, add margins equal to 1.8% - * of xres rounded down to 8 pixels, and 1.8% of yres. The char - * 'i' and 'm' must be after 'M' and 'R'. Example: + * with <xres>, <yres>, <bpp> and <refresh> decimal numbers and + * <name> a string. * - * 1024x768MR-8@60m - Reduced blank with margins at 60Hz. + * If 'M' is present after yres (and before refresh/bpp if present), + * the function will compute the timings using VESA(tm) Coordinated + * Video Timings (CVT). If 'R' is present after 'M', will compute with + * reduced blanking (for flatpanels). If 'i' or 'p' are present, compute + * interlaced or progressive mode. If 'm' is present, add margins equal + * to 1.8% of xres rounded down to 8 pixels, and 1.8% of yres. The char + * 'i', 'p' and 'm' must be after 'M' and 'R'. Example:: * - * NOTE: The passed struct @var is _not_ cleared! This allows you - * to supply values for e.g. the grayscale and accel_flags fields. + * 1024x768MR-8@60m - Reduced blank with margins at 60Hz. * - * Returns zero for failure, 1 if using specified @mode_option, - * 2 if using specified @mode_option with an ignored refresh rate, - * 3 if default mode is used, 4 if fall back to any valid mode. + * NOTE: The passed struct @var is _not_ cleared! This allows you + * to supply values for e.g. the grayscale and accel_flags fields. * + * Returns zero for failure, 1 if using specified @mode_option, + * 2 if using specified @mode_option with an ignored refresh rate, + * 3 if default mode is used, 4 if fall back to any valid mode. */ int fb_find_mode(struct fb_var_screeninfo *var, @@ -697,7 +699,8 @@ int fb_find_mode(struct fb_var_screeninfo *var, unsigned int namelen = strlen(name); int res_specified = 0, bpp_specified = 0, refresh_specified = 0; unsigned int xres = 0, yres = 0, bpp = default_bpp, refresh = 0; - int yres_specified = 0, cvt = 0, rb = 0, interlace = 0; + int yres_specified = 0, cvt = 0, rb = 0; + int interlace_specified = 0, interlace = 0; int margins = 0; u32 best, diff, tdiff; @@ -748,9 +751,17 @@ int fb_find_mode(struct fb_var_screeninfo *var, if (!cvt) margins = 1; break; + case 'p': + if (!cvt) { + interlace = 0; + interlace_specified = 1; + } + break; case 'i': - if (!cvt) + if (!cvt) { interlace = 1; + interlace_specified = 1; + } break; default: goto done; @@ -819,11 +830,21 @@ done: if ((name_matches(db[i], name, namelen) || (res_specified && res_matches(db[i], xres, yres))) && !fb_try_mode(var, info, &db[i], bpp)) { - if (refresh_specified && db[i].refresh == refresh) - return 1; + const int db_interlace = (db[i].vmode & + FB_VMODE_INTERLACED ? 1 : 0); + int score = abs(db[i].refresh - refresh); + + if (interlace_specified) + score += abs(db_interlace - interlace); + + if (!interlace_specified || + db_interlace == interlace) + if (refresh_specified && + db[i].refresh == refresh) + return 1; - if (abs(db[i].refresh - refresh) < diff) { - diff = abs(db[i].refresh - refresh); + if (score < diff) { + diff = score; best = i; } } diff --git a/drivers/video/fbdev/efifb.c b/drivers/video/fbdev/efifb.c index c6f78d27947b..3946649b85c8 100644 --- a/drivers/video/fbdev/efifb.c +++ b/drivers/video/fbdev/efifb.c @@ -9,16 +9,39 @@ #include <linux/kernel.h> #include <linux/efi.h> +#include <linux/efi-bgrt.h> #include <linux/errno.h> #include <linux/fb.h> #include <linux/pci.h> #include <linux/platform_device.h> +#include <linux/printk.h> #include <linux/screen_info.h> #include <video/vga.h> #include <asm/efi.h> #include <drm/drm_utils.h> /* For drm_get_panel_orientation_quirk */ #include <drm/drm_connector.h> /* For DRM_MODE_PANEL_ORIENTATION_* */ +struct bmp_file_header { + u16 id; + u32 file_size; + u32 reserved; + u32 bitmap_offset; +} __packed; + +struct bmp_dib_header { + u32 dib_header_size; + s32 width; + s32 height; + u16 planes; + u16 bpp; + u32 compression; + u32 bitmap_size; + u32 horz_resolution; + u32 vert_resolution; + u32 colors_used; + u32 colors_important; +} __packed; + static bool request_mem_succeeded = false; static u64 mem_flags = EFI_MEMORY_WC | EFI_MEMORY_UC; @@ -66,6 +89,164 @@ static int efifb_setcolreg(unsigned regno, unsigned red, unsigned green, return 0; } +/* + * If fbcon deffered console takeover is configured, the intent is for the + * framebuffer to show the boot graphics (e.g. vendor logo) until there is some + * (error) message to display. But the boot graphics may have been destroyed by + * e.g. option ROM output, detect this and restore the boot graphics. + */ +#if defined CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER && \ + defined CONFIG_ACPI_BGRT +static void efifb_copy_bmp(u8 *src, u32 *dst, int width, struct screen_info *si) +{ + u8 r, g, b; + + while (width--) { + b = *src++; + g = *src++; + r = *src++; + *dst++ = (r << si->red_pos) | + (g << si->green_pos) | + (b << si->blue_pos); + } +} + +#ifdef CONFIG_X86 +/* + * On x86 some firmwares use a low non native resolution for the display when + * they have shown some text messages. While keeping the bgrt filled with info + * for the native resolution. If the bgrt image intended for the native + * resolution still fits, it will be displayed very close to the right edge of + * the display looking quite bad. This function checks for this. + */ +static bool efifb_bgrt_sanity_check(struct screen_info *si, u32 bmp_width) +{ + static const int default_resolutions[][2] = { + { 800, 600 }, + { 1024, 768 }, + { 1280, 1024 }, + }; + u32 i, right_margin; + + for (i = 0; i < ARRAY_SIZE(default_resolutions); i++) { + if (default_resolutions[i][0] == si->lfb_width && + default_resolutions[i][1] == si->lfb_height) + break; + } + /* If not a default resolution used for textmode, this should be fine */ + if (i >= ARRAY_SIZE(default_resolutions)) + return true; + + /* If the right margin is 5 times smaller then the left one, reject */ + right_margin = si->lfb_width - (bgrt_tab.image_offset_x + bmp_width); + if (right_margin < (bgrt_tab.image_offset_x / 5)) + return false; + + return true; +} +#else +static bool efifb_bgrt_sanity_check(struct screen_info *si, u32 bmp_width) +{ + return true; +} +#endif + +static void efifb_show_boot_graphics(struct fb_info *info) +{ + u32 bmp_width, bmp_height, bmp_pitch, screen_pitch, dst_x, y, src_y; + struct screen_info *si = &screen_info; + struct bmp_file_header *file_header; + struct bmp_dib_header *dib_header; + void *bgrt_image = NULL; + u8 *dst = info->screen_base; + + if (!bgrt_tab.image_address) { + pr_info("efifb: No BGRT, not showing boot graphics\n"); + return; + } + + /* Avoid flashing the logo if we're going to print std probe messages */ + if (console_loglevel > CONSOLE_LOGLEVEL_QUIET) + return; + + /* bgrt_tab.status is unreliable, so we don't check it */ + + if (si->lfb_depth != 32) { + pr_info("efifb: not 32 bits, not showing boot graphics\n"); + return; + } + + bgrt_image = memremap(bgrt_tab.image_address, bgrt_image_size, + MEMREMAP_WB); + if (!bgrt_image) { + pr_warn("efifb: Ignoring BGRT: failed to map image memory\n"); + return; + } + + if (bgrt_image_size < (sizeof(*file_header) + sizeof(*dib_header))) + goto error; + + file_header = bgrt_image; + if (file_header->id != 0x4d42 || file_header->reserved != 0) + goto error; + + dib_header = bgrt_image + sizeof(*file_header); + if (dib_header->dib_header_size != 40 || dib_header->width < 0 || + dib_header->planes != 1 || dib_header->bpp != 24 || + dib_header->compression != 0) + goto error; + + bmp_width = dib_header->width; + bmp_height = abs(dib_header->height); + bmp_pitch = round_up(3 * bmp_width, 4); + screen_pitch = si->lfb_linelength; + + if ((file_header->bitmap_offset + bmp_pitch * bmp_height) > + bgrt_image_size) + goto error; + + if ((bgrt_tab.image_offset_x + bmp_width) > si->lfb_width || + (bgrt_tab.image_offset_y + bmp_height) > si->lfb_height) + goto error; + + if (!efifb_bgrt_sanity_check(si, bmp_width)) + goto error; + + pr_info("efifb: showing boot graphics\n"); + + for (y = 0; y < si->lfb_height; y++, dst += si->lfb_linelength) { + /* Only background? */ + if (y < bgrt_tab.image_offset_y || + y >= (bgrt_tab.image_offset_y + bmp_height)) { + memset(dst, 0, 4 * si->lfb_width); + continue; + } + + src_y = y - bgrt_tab.image_offset_y; + /* Positive header height means upside down row order */ + if (dib_header->height > 0) + src_y = (bmp_height - 1) - src_y; + + memset(dst, 0, bgrt_tab.image_offset_x * 4); + dst_x = bgrt_tab.image_offset_x; + efifb_copy_bmp(bgrt_image + file_header->bitmap_offset + + src_y * bmp_pitch, + (u32 *)dst + dst_x, bmp_width, si); + dst_x += bmp_width; + memset((u32 *)dst + dst_x, 0, (si->lfb_width - dst_x) * 4); + } + + memunmap(bgrt_image); + return; + +error: + memunmap(bgrt_image); + pr_warn("efifb: Ignoring BGRT: unexpected or invalid BMP data\n"); +} +#else +static inline void efifb_show_boot_graphics(struct fb_info *info) {} +#endif + static void efifb_destroy(struct fb_info *info) { if (info->screen_base) { @@ -311,6 +492,8 @@ static int efifb_probe(struct platform_device *dev) goto err_release_fb; } + efifb_show_boot_graphics(info); + pr_info("efifb: framebuffer at 0x%lx, using %dk, total %dk\n", efifb_fix.smem_start, size_remap/1024, size_total/1024); pr_info("efifb: mode is %dx%dx%d, linelength=%d, pages=%d\n", diff --git a/drivers/video/fbdev/fsl-diu-fb.c b/drivers/video/fbdev/fsl-diu-fb.c index 1bfd13cbd4e3..bc9eb8afc313 100644 --- a/drivers/video/fbdev/fsl-diu-fb.c +++ b/drivers/video/fbdev/fsl-diu-fb.c @@ -360,6 +360,10 @@ struct mfb_info { * @ad[]: Area Descriptors for each real AOI * @gamma: gamma color table * @cursor: hardware cursor data + * @blank_cursor: blank cursor for hiding cursor + * @next_cursor: scratch space to build load cursor + * @edid_data: EDID information buffer + * @has_edid: whether or not the EDID buffer is valid * * This data structure must be allocated with 32-byte alignment, so that the * internal fields can be aligned properly. @@ -381,6 +385,8 @@ struct fsl_diu_data { __le16 cursor[MAX_CURS * MAX_CURS] __aligned(32); /* Blank cursor data -- used to hide the cursor */ __le16 blank_cursor[MAX_CURS * MAX_CURS] __aligned(32); + /* Scratch cursor data -- used to build new cursor */ + __le16 next_cursor[MAX_CURS * MAX_CURS] __aligned(32); uint8_t edid_data[EDID_LENGTH]; bool has_edid; } __aligned(32); @@ -1056,13 +1062,17 @@ static int fsl_diu_cursor(struct fb_info *info, struct fb_cursor *cursor) * FB_CUR_SETSHAPE - the cursor bitmask has changed */ if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { + /* + * Determine the size of the cursor image data. Normally, + * it's 8x16. + */ unsigned int image_size = - DIV_ROUND_UP(cursor->image.width, 8) * cursor->image.height; + DIV_ROUND_UP(cursor->image.width, 8) * + cursor->image.height; unsigned int image_words = DIV_ROUND_UP(image_size, sizeof(uint32_t)); unsigned int bg_idx = cursor->image.bg_color; unsigned int fg_idx = cursor->image.fg_color; - uint8_t buffer[image_size]; uint32_t *image, *source, *mask; uint16_t fg, bg; unsigned int i; @@ -1070,13 +1080,6 @@ static int fsl_diu_cursor(struct fb_info *info, struct fb_cursor *cursor) if (info->state != FBINFO_STATE_RUNNING) return 0; - /* - * Determine the size of the cursor image data. Normally, - * it's 8x16. - */ - image_size = DIV_ROUND_UP(cursor->image.width, 8) * - cursor->image.height; - bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | ((info->cmap.green[bg_idx] & 0xf8) << 2) | ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | @@ -1088,7 +1091,7 @@ static int fsl_diu_cursor(struct fb_info *info, struct fb_cursor *cursor) 1 << 15; /* Use 32-bit operations on the data to improve performance */ - image = (uint32_t *)buffer; + image = (uint32_t *)data->next_cursor; source = (uint32_t *)cursor->image.data; mask = (uint32_t *)cursor->mask; diff --git a/drivers/video/fbdev/goldfishfb.c b/drivers/video/fbdev/goldfishfb.c index 3b70044773b6..4377e3442638 100644 --- a/drivers/video/fbdev/goldfishfb.c +++ b/drivers/video/fbdev/goldfishfb.c @@ -26,6 +26,7 @@ #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/platform_device.h> +#include <linux/acpi.h> enum { FB_GET_WIDTH = 0x00, @@ -124,6 +125,7 @@ static int goldfish_fb_check_var(struct fb_var_screeninfo *var, static int goldfish_fb_set_par(struct fb_info *info) { struct goldfish_fb *fb = container_of(info, struct goldfish_fb, fb); + if (fb->rotation != fb->fb.var.rotate) { info->fix.line_length = info->var.xres * 2; fb->rotation = fb->fb.var.rotate; @@ -148,13 +150,14 @@ static int goldfish_fb_pan_display(struct fb_var_screeninfo *var, wait_event_timeout(fb->wait, fb->base_update_count != base_update_count, HZ / 15); if (fb->base_update_count == base_update_count) - pr_err("goldfish_fb_pan_display: timeout waiting for base update\n"); + pr_err("%s: timeout waiting for base update\n", __func__); return 0; } static int goldfish_fb_blank(int blank, struct fb_info *info) { struct goldfish_fb *fb = container_of(info, struct goldfish_fb, fb); + switch (blank) { case FB_BLANK_NORMAL: writel(1, fb->reg_base + FB_SET_BLANK); @@ -234,7 +237,7 @@ static int goldfish_fb_probe(struct platform_device *pdev) fb->fb.var.activate = FB_ACTIVATE_NOW; fb->fb.var.height = readl(fb->reg_base + FB_GET_PHYS_HEIGHT); fb->fb.var.width = readl(fb->reg_base + FB_GET_PHYS_WIDTH); - fb->fb.var.pixclock = 10000; + fb->fb.var.pixclock = 0; fb->fb.var.red.offset = 11; fb->fb.var.red.length = 5; @@ -301,6 +304,7 @@ static int goldfish_fb_remove(struct platform_device *pdev) dma_free_coherent(&pdev->dev, framesize, (void *)fb->fb.screen_base, fb->fb.fix.smem_start); iounmap(fb->reg_base); + kfree(fb); return 0; } @@ -310,12 +314,19 @@ static const struct of_device_id goldfish_fb_of_match[] = { }; MODULE_DEVICE_TABLE(of, goldfish_fb_of_match); +static const struct acpi_device_id goldfish_fb_acpi_match[] = { + { "GFSH0004", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, goldfish_fb_acpi_match); + static struct platform_driver goldfish_fb_driver = { .probe = goldfish_fb_probe, .remove = goldfish_fb_remove, .driver = { .name = "goldfish_fb", .of_match_table = goldfish_fb_of_match, + .acpi_match_table = ACPI_PTR(goldfish_fb_acpi_match), } }; diff --git a/drivers/video/fbdev/i740fb.c b/drivers/video/fbdev/i740fb.c index 7bc5f6056c77..f6d7b04d6dff 100644 --- a/drivers/video/fbdev/i740fb.c +++ b/drivers/video/fbdev/i740fb.c @@ -429,6 +429,7 @@ static int i740fb_decode_var(const struct fb_var_screeninfo *var, break; case 9 ... 15: bpp = 15; + /* fall through */ case 16: if ((1000000 / var->pixclock) > DACSPEED16) { dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n", diff --git a/drivers/video/fbdev/metronomefb.c b/drivers/video/fbdev/metronomefb.c index 9085e9525341..bb4fee52e501 100644 --- a/drivers/video/fbdev/metronomefb.c +++ b/drivers/video/fbdev/metronomefb.c @@ -233,7 +233,7 @@ static int load_waveform(u8 *mem, size_t size, int m, int t, /* check temperature range table checksum */ cksum_idx = sizeof(*wfm_hdr) + wfm_hdr->trc + 1; - if (cksum_idx > size) + if (cksum_idx >= size) return -EINVAL; cksum = calc_cksum(sizeof(*wfm_hdr), cksum_idx, mem); if (cksum != mem[cksum_idx]) { @@ -245,7 +245,7 @@ static int load_waveform(u8 *mem, size_t size, int m, int t, /* check waveform mode table address checksum */ wmta = get_unaligned_le32(wfm_hdr->wmta) & 0x00FFFFFF; cksum_idx = wmta + m*4 + 3; - if (cksum_idx > size) + if (cksum_idx >= size) return -EINVAL; cksum = calc_cksum(cksum_idx - 3, cksum_idx, mem); if (cksum != mem[cksum_idx]) { @@ -257,7 +257,7 @@ static int load_waveform(u8 *mem, size_t size, int m, int t, /* check waveform temperature table address checksum */ tta = get_unaligned_le32(mem + wmta + m * 4) & 0x00FFFFFF; cksum_idx = tta + trn*4 + 3; - if (cksum_idx > size) + if (cksum_idx >= size) return -EINVAL; cksum = calc_cksum(cksum_idx - 3, cksum_idx, mem); if (cksum != mem[cksum_idx]) { @@ -270,7 +270,7 @@ static int load_waveform(u8 *mem, size_t size, int m, int t, metromem buffer. this does runlength decoding of the waveform */ wfm_idx = get_unaligned_le32(mem + tta + trn * 4) & 0x00FFFFFF; owfm_idx = wfm_idx; - if (wfm_idx > size) + if (wfm_idx >= size) return -EINVAL; while (wfm_idx < size) { unsigned char rl; @@ -292,7 +292,7 @@ static int load_waveform(u8 *mem, size_t size, int m, int t, } cksum_idx = wfm_idx; - if (cksum_idx > size) + if (cksum_idx >= size) return -EINVAL; cksum = calc_cksum(owfm_idx, cksum_idx, mem); if (cksum != mem[cksum_idx]) { diff --git a/drivers/video/fbdev/omap/omapfb_main.c b/drivers/video/fbdev/omap/omapfb_main.c index 585f39efcff6..1c75f4806ed3 100644 --- a/drivers/video/fbdev/omap/omapfb_main.c +++ b/drivers/video/fbdev/omap/omapfb_main.c @@ -958,7 +958,7 @@ int omapfb_register_client(struct omapfb_notifier_block *omapfb_nb, { int r; - if ((unsigned)omapfb_nb->plane_idx > OMAPFB_PLANE_NUM) + if ((unsigned)omapfb_nb->plane_idx >= OMAPFB_PLANE_NUM) return -EINVAL; if (!notifier_inited) { diff --git a/drivers/video/fbdev/omap2/omapfb/Makefile b/drivers/video/fbdev/omap2/omapfb/Makefile index 602edfed09df..f54c3f56b641 100644 --- a/drivers/video/fbdev/omap2/omapfb/Makefile +++ b/drivers/video/fbdev/omap2/omapfb/Makefile @@ -2,5 +2,5 @@ obj-$(CONFIG_OMAP2_VRFB) += vrfb.o obj-y += dss/ obj-y += displays/ -obj-$(CONFIG_FB_OMAP2) += omapfb.o -omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o +obj-$(CONFIG_FB_OMAP2) += omap2fb.o +omap2fb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o diff --git a/drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c b/drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c index 3079a3df8c37..47f0459e3551 100644 --- a/drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c +++ b/drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c @@ -219,7 +219,7 @@ static int tpd_probe_of(struct platform_device *pdev) static int tpd_probe(struct platform_device *pdev) { - struct omap_dss_device *in, *dssdev; + struct omap_dss_device *dssdev; struct panel_drv_data *ddata; int r; struct gpio_desc *gpio; @@ -238,25 +238,30 @@ static int tpd_probe(struct platform_device *pdev) return -ENODEV; } - gpio = devm_gpiod_get_index_optional(&pdev->dev, NULL, 0, GPIOD_OUT_LOW); - if (IS_ERR(gpio)) + if (IS_ERR(gpio)) { + r = PTR_ERR(gpio); goto err_gpio; + } ddata->ct_cp_hpd_gpio = gpio; gpio = devm_gpiod_get_index_optional(&pdev->dev, NULL, 1, GPIOD_OUT_LOW); - if (IS_ERR(gpio)) + if (IS_ERR(gpio)) { + r = PTR_ERR(gpio); goto err_gpio; + } ddata->ls_oe_gpio = gpio; gpio = devm_gpiod_get_index(&pdev->dev, NULL, 2, GPIOD_IN); - if (IS_ERR(gpio)) + if (IS_ERR(gpio)) { + r = PTR_ERR(gpio); goto err_gpio; + } ddata->hpd_gpio = gpio; @@ -268,8 +273,6 @@ static int tpd_probe(struct platform_device *pdev) dssdev->owner = THIS_MODULE; dssdev->port_num = 1; - in = ddata->in; - r = omapdss_register_output(dssdev); if (r) { dev_err(&pdev->dev, "Failed to register output\n"); diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dispc.c b/drivers/video/fbdev/omap2/omapfb/dss/dispc.c index fb605aefd9b1..a06d9c25765c 100644 --- a/drivers/video/fbdev/omap2/omapfb/dss/dispc.c +++ b/drivers/video/fbdev/omap2/omapfb/dss/dispc.c @@ -1858,7 +1858,7 @@ static s32 pixinc(int pixels, u8 ps) return 1 - (-pixels + 1) * ps; else BUG(); - return 0; + return 0; } static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, @@ -1905,6 +1905,7 @@ static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, if (color_mode == OMAP_DSS_COLOR_YUV2 || color_mode == OMAP_DSS_COLOR_UYVY) width = width >> 1; + /* fall through */ case OMAP_DSS_ROT_90: case OMAP_DSS_ROT_270: *offset1 = 0; @@ -1927,6 +1928,7 @@ static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, if (color_mode == OMAP_DSS_COLOR_YUV2 || color_mode == OMAP_DSS_COLOR_UYVY) width = width >> 1; + /* fall through */ case OMAP_DSS_ROT_90 + 4: case OMAP_DSS_ROT_270 + 4: *offset1 = 0; diff --git a/drivers/video/fbdev/omap2/omapfb/omapfb-main.c b/drivers/video/fbdev/omap2/omapfb/omapfb-main.c index 3e7887c53d7c..b8b5b4ac0e09 100644 --- a/drivers/video/fbdev/omap2/omapfb/omapfb-main.c +++ b/drivers/video/fbdev/omap2/omapfb/omapfb-main.c @@ -893,6 +893,7 @@ int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl, / (var->bits_per_pixel >> 2); break; } + /* fall through */ default: screen_width = fix->line_length / (var->bits_per_pixel >> 3); break; diff --git a/drivers/video/fbdev/pm2fb.c b/drivers/video/fbdev/pm2fb.c index bd6c2f5f6095..1dcf02e12af4 100644 --- a/drivers/video/fbdev/pm2fb.c +++ b/drivers/video/fbdev/pm2fb.c @@ -233,8 +233,10 @@ static u32 to3264(u32 timing, int bpp, int is64) switch (bpp) { case 24: timing *= 3; + /* fall through */ case 8: timing >>= 1; + /* fall through */ case 16: timing >>= 1; case 32: diff --git a/drivers/video/fbdev/pxa3xx-gcu.c b/drivers/video/fbdev/pxa3xx-gcu.c index 0955622a1227..69cfb337c857 100644 --- a/drivers/video/fbdev/pxa3xx-gcu.c +++ b/drivers/video/fbdev/pxa3xx-gcu.c @@ -44,6 +44,7 @@ #include <linux/clk.h> #include <linux/fs.h> #include <linux/io.h> +#include <linux/of.h> #include "pxa3xx-gcu.h" @@ -703,11 +704,20 @@ static int pxa3xx_gcu_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_OF +static const struct of_device_id pxa3xx_gcu_of_match[] = { + { .compatible = "marvell,pxa300-gcu", }, + { } +}; +MODULE_DEVICE_TABLE(of, pxa3xx_gcu_of_match); +#endif + static struct platform_driver pxa3xx_gcu_driver = { .probe = pxa3xx_gcu_probe, .remove = pxa3xx_gcu_remove, .driver = { .name = DRV_NAME, + .of_match_table = of_match_ptr(pxa3xx_gcu_of_match), }, }; diff --git a/drivers/video/fbdev/pxafb.c b/drivers/video/fbdev/pxafb.c index 76722a59f55e..bbed039617a4 100644 --- a/drivers/video/fbdev/pxafb.c +++ b/drivers/video/fbdev/pxafb.c @@ -56,6 +56,7 @@ #include <linux/freezer.h> #include <linux/console.h> #include <linux/of_graph.h> +#include <linux/regulator/consumer.h> #include <video/of_display_timing.h> #include <video/videomode.h> @@ -1423,6 +1424,21 @@ static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) if (fbi->lcd_power) fbi->lcd_power(on, &fbi->fb.var); + + if (fbi->lcd_supply && fbi->lcd_supply_enabled != on) { + int ret; + + if (on) + ret = regulator_enable(fbi->lcd_supply); + else + ret = regulator_disable(fbi->lcd_supply); + + if (ret < 0) + pr_warn("Unable to %s LCD supply regulator: %d\n", + on ? "enable" : "disable", ret); + else + fbi->lcd_supply_enabled = on; + } } static void pxafb_enable_controller(struct pxafb_info *fbi) @@ -1799,19 +1815,17 @@ static struct pxafb_info *pxafb_init_fbinfo(struct device *dev, void *addr; /* Alloc the pxafb_info and pseudo_palette in one step */ - fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); + fbi = devm_kzalloc(dev, sizeof(struct pxafb_info) + sizeof(u32) * 16, + GFP_KERNEL); if (!fbi) - return NULL; + return ERR_PTR(-ENOMEM); - memset(fbi, 0, sizeof(struct pxafb_info)); fbi->dev = dev; fbi->inf = inf; - fbi->clk = clk_get(dev, NULL); - if (IS_ERR(fbi->clk)) { - kfree(fbi); - return NULL; - } + fbi->clk = devm_clk_get(dev, NULL); + if (IS_ERR(fbi->clk)) + return ERR_CAST(fbi->clk); strcpy(fbi->fb.fix.id, PXA_NAME); @@ -2128,8 +2142,9 @@ static int of_get_pxafb_display(struct device *dev, struct device_node *disp, return -EINVAL; ret = -ENOMEM; - info->modes = kmalloc_array(timings->num_timings, - sizeof(info->modes[0]), GFP_KERNEL); + info->modes = devm_kcalloc(dev, timings->num_timings, + sizeof(info->modes[0]), + GFP_KERNEL); if (!info->modes) goto out; info->num_modes = timings->num_timings; @@ -2288,10 +2303,9 @@ static int pxafb_probe(struct platform_device *dev) } fbi = pxafb_init_fbinfo(&dev->dev, inf); - if (!fbi) { - /* only reason for pxafb_init_fbinfo to fail is kmalloc */ + if (IS_ERR(fbi)) { dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); - ret = -ENOMEM; + ret = PTR_ERR(fbi); goto failed; } @@ -2301,25 +2315,26 @@ static int pxafb_probe(struct platform_device *dev) fbi->backlight_power = inf->pxafb_backlight_power; fbi->lcd_power = inf->pxafb_lcd_power; + fbi->lcd_supply = devm_regulator_get_optional(&dev->dev, "lcd"); + if (IS_ERR(fbi->lcd_supply)) { + if (PTR_ERR(fbi->lcd_supply) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + fbi->lcd_supply = NULL; + } + r = platform_get_resource(dev, IORESOURCE_MEM, 0); if (r == NULL) { dev_err(&dev->dev, "no I/O memory resource defined\n"); ret = -ENODEV; - goto failed_fbi; - } - - r = request_mem_region(r->start, resource_size(r), dev->name); - if (r == NULL) { - dev_err(&dev->dev, "failed to request I/O memory\n"); - ret = -EBUSY; - goto failed_fbi; + goto failed; } - fbi->mmio_base = ioremap(r->start, resource_size(r)); - if (fbi->mmio_base == NULL) { - dev_err(&dev->dev, "failed to map I/O memory\n"); + fbi->mmio_base = devm_ioremap_resource(&dev->dev, r); + if (IS_ERR(fbi->mmio_base)) { + dev_err(&dev->dev, "failed to get I/O memory\n"); ret = -EBUSY; - goto failed_free_res; + goto failed; } fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff)); @@ -2328,7 +2343,7 @@ static int pxafb_probe(struct platform_device *dev) if (fbi->dma_buff == NULL) { dev_err(&dev->dev, "failed to allocate memory for DMA\n"); ret = -ENOMEM; - goto failed_free_io; + goto failed; } ret = pxafb_init_video_memory(fbi); @@ -2345,7 +2360,7 @@ static int pxafb_probe(struct platform_device *dev) goto failed_free_mem; } - ret = request_irq(irq, pxafb_handle_irq, 0, "LCD", fbi); + ret = devm_request_irq(&dev->dev, irq, pxafb_handle_irq, 0, "LCD", fbi); if (ret) { dev_err(&dev->dev, "request_irq failed: %d\n", ret); ret = -EBUSY; @@ -2355,7 +2370,7 @@ static int pxafb_probe(struct platform_device *dev) ret = pxafb_smart_init(fbi); if (ret) { dev_err(&dev->dev, "failed to initialize smartpanel\n"); - goto failed_free_irq; + goto failed_free_mem; } /* @@ -2365,13 +2380,13 @@ static int pxafb_probe(struct platform_device *dev) ret = pxafb_check_var(&fbi->fb.var, &fbi->fb); if (ret) { dev_err(&dev->dev, "failed to get suitable mode\n"); - goto failed_free_irq; + goto failed_free_mem; } ret = pxafb_set_par(&fbi->fb); if (ret) { dev_err(&dev->dev, "Failed to set parameters\n"); - goto failed_free_irq; + goto failed_free_mem; } platform_set_drvdata(dev, fbi); @@ -2404,20 +2419,11 @@ static int pxafb_probe(struct platform_device *dev) failed_free_cmap: if (fbi->fb.cmap.len) fb_dealloc_cmap(&fbi->fb.cmap); -failed_free_irq: - free_irq(irq, fbi); failed_free_mem: free_pages_exact(fbi->video_mem, fbi->video_mem_size); failed_free_dma: dma_free_coherent(&dev->dev, fbi->dma_buff_size, fbi->dma_buff, fbi->dma_buff_phys); -failed_free_io: - iounmap(fbi->mmio_base); -failed_free_res: - release_mem_region(r->start, resource_size(r)); -failed_fbi: - clk_put(fbi->clk); - kfree(fbi); failed: return ret; } @@ -2425,8 +2431,6 @@ failed: static int pxafb_remove(struct platform_device *dev) { struct pxafb_info *fbi = platform_get_drvdata(dev); - struct resource *r; - int irq; struct fb_info *info; if (!fbi) @@ -2442,22 +2446,11 @@ static int pxafb_remove(struct platform_device *dev) if (fbi->fb.cmap.len) fb_dealloc_cmap(&fbi->fb.cmap); - irq = platform_get_irq(dev, 0); - free_irq(irq, fbi); - free_pages_exact(fbi->video_mem, fbi->video_mem_size); dma_free_wc(&dev->dev, fbi->dma_buff_size, fbi->dma_buff, fbi->dma_buff_phys); - iounmap(fbi->mmio_base); - - r = platform_get_resource(dev, IORESOURCE_MEM, 0); - release_mem_region(r->start, resource_size(r)); - - clk_put(fbi->clk); - kfree(fbi); - return 0; } diff --git a/drivers/video/fbdev/pxafb.h b/drivers/video/fbdev/pxafb.h index 5dc414e26fc8..b641289c8a99 100644 --- a/drivers/video/fbdev/pxafb.h +++ b/drivers/video/fbdev/pxafb.h @@ -165,6 +165,9 @@ struct pxafb_info { struct notifier_block freq_policy; #endif + struct regulator *lcd_supply; + bool lcd_supply_enabled; + void (*lcd_power)(int, struct fb_var_screeninfo *); void (*backlight_power)(int); diff --git a/drivers/video/fbdev/simplefb.c b/drivers/video/fbdev/simplefb.c index a3c44ecf4523..9a9d748b07f2 100644 --- a/drivers/video/fbdev/simplefb.c +++ b/drivers/video/fbdev/simplefb.c @@ -27,8 +27,8 @@ #include <linux/platform_data/simplefb.h> #include <linux/platform_device.h> #include <linux/clk.h> -#include <linux/clk-provider.h> #include <linux/of.h> +#include <linux/of_clk.h> #include <linux/of_platform.h> #include <linux/parser.h> #include <linux/regulator/consumer.h> diff --git a/drivers/video/fbdev/tdfxfb.c b/drivers/video/fbdev/tdfxfb.c index dec1fed9880e..fbbf26b170f7 100644 --- a/drivers/video/fbdev/tdfxfb.c +++ b/drivers/video/fbdev/tdfxfb.c @@ -522,6 +522,7 @@ static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) case 32: var->transp.offset = 24; var->transp.length = 8; + /* fall through */ case 24: var->red.offset = 16; var->green.offset = 8; diff --git a/drivers/video/fbdev/tridentfb.c b/drivers/video/fbdev/tridentfb.c index 284706184b1b..f4b745590600 100644 --- a/drivers/video/fbdev/tridentfb.c +++ b/drivers/video/fbdev/tridentfb.c @@ -777,9 +777,6 @@ static int get_nativex(struct tridentfb_par *par) case 3: x = 800; y = 600; break; - case 4: - x = 1400; y = 1050; - break; case 1: default: x = 640; y = 480; diff --git a/drivers/video/fbdev/udlfb.c b/drivers/video/fbdev/udlfb.c index f365d4862015..afbd6101c78e 100644 --- a/drivers/video/fbdev/udlfb.c +++ b/drivers/video/fbdev/udlfb.c @@ -25,8 +25,8 @@ #include <linux/fb.h> #include <linux/vmalloc.h> #include <linux/slab.h> -#include <linux/prefetch.h> #include <linux/delay.h> +#include <asm/unaligned.h> #include <video/udlfb.h> #include "edid.h" @@ -72,6 +72,13 @@ static bool fb_defio = 1; /* Detect mmap writes using page faults */ static bool shadow = 1; /* Optionally disable shadow framebuffer */ static int pixel_limit; /* Optionally force a pixel resolution limit */ +struct dlfb_deferred_free { + struct list_head list; + void *mem; +}; + +static int dlfb_realloc_framebuffer(struct dlfb_data *dlfb, struct fb_info *info, u32 new_len); + /* dlfb keeps a list of urbs for efficient bulk transfers */ static void dlfb_urb_completion(struct urb *urb); static struct urb *dlfb_get_urb(struct dlfb_data *dlfb); @@ -367,9 +374,6 @@ static int dlfb_trim_hline(const u8 *bback, const u8 **bfront, int *width_bytes) int start = width; int end = width; - prefetch((void *) front); - prefetch((void *) back); - for (j = 0; j < width; j++) { if (back[j] != front[j]) { start = j; @@ -423,7 +427,9 @@ static void dlfb_compress_hline( const uint16_t *const pixel_end, uint32_t *device_address_ptr, uint8_t **command_buffer_ptr, - const uint8_t *const cmd_buffer_end) + const uint8_t *const cmd_buffer_end, + unsigned long back_buffer_offset, + int *ident_ptr) { const uint16_t *pixel = *pixel_start_ptr; uint32_t dev_addr = *device_address_ptr; @@ -436,7 +442,13 @@ static void dlfb_compress_hline( const uint16_t *raw_pixel_start = NULL; const uint16_t *cmd_pixel_start, *cmd_pixel_end = NULL; - prefetchw((void *) cmd); /* pull in one cache line at least */ + if (back_buffer_offset && + *pixel == *(u16 *)((u8 *)pixel + back_buffer_offset)) { + pixel++; + dev_addr += BPP; + (*ident_ptr)++; + continue; + } *cmd++ = 0xAF; *cmd++ = 0x6B; @@ -450,29 +462,39 @@ static void dlfb_compress_hline( raw_pixels_count_byte = cmd++; /* we'll know this later */ raw_pixel_start = pixel; - cmd_pixel_end = pixel + min(MAX_CMD_PIXELS + 1, - min((int)(pixel_end - pixel), - (int)(cmd_buffer_end - cmd) / BPP)); + cmd_pixel_end = pixel + min3(MAX_CMD_PIXELS + 1UL, + (unsigned long)(pixel_end - pixel), + (unsigned long)(cmd_buffer_end - 1 - cmd) / BPP); - prefetch_range((void *) pixel, (cmd_pixel_end - pixel) * BPP); + if (back_buffer_offset) { + /* note: the framebuffer may change under us, so we must test for underflow */ + while (cmd_pixel_end - 1 > pixel && + *(cmd_pixel_end - 1) == *(u16 *)((u8 *)(cmd_pixel_end - 1) + back_buffer_offset)) + cmd_pixel_end--; + } while (pixel < cmd_pixel_end) { const uint16_t * const repeating_pixel = pixel; + u16 pixel_value = *pixel; - *cmd++ = *pixel >> 8; - *cmd++ = *pixel; + put_unaligned_be16(pixel_value, cmd); + if (back_buffer_offset) + *(u16 *)((u8 *)pixel + back_buffer_offset) = pixel_value; + cmd += 2; pixel++; if (unlikely((pixel < cmd_pixel_end) && - (*pixel == *repeating_pixel))) { + (*pixel == pixel_value))) { /* go back and fill in raw pixel count */ *raw_pixels_count_byte = ((repeating_pixel - raw_pixel_start) + 1) & 0xFF; - while ((pixel < cmd_pixel_end) - && (*pixel == *repeating_pixel)) { + do { + if (back_buffer_offset) + *(u16 *)((u8 *)pixel + back_buffer_offset) = pixel_value; pixel++; - } + } while ((pixel < cmd_pixel_end) && + (*pixel == pixel_value)); /* immediately after raw data is repeat byte */ *cmd++ = ((pixel - repeating_pixel) - 1) & 0xFF; @@ -486,13 +508,16 @@ static void dlfb_compress_hline( if (pixel > raw_pixel_start) { /* finalize last RAW span */ *raw_pixels_count_byte = (pixel-raw_pixel_start) & 0xFF; + } else { + /* undo unused byte */ + cmd--; } *cmd_pixels_count_byte = (pixel - cmd_pixel_start) & 0xFF; - dev_addr += (pixel - cmd_pixel_start) * BPP; + dev_addr += (u8 *)pixel - (u8 *)cmd_pixel_start; } - if (cmd_buffer_end <= MIN_RLX_CMD_BYTES + cmd) { + if (cmd_buffer_end - MIN_RLX_CMD_BYTES <= cmd) { /* Fill leftover bytes with no-ops */ if (cmd_buffer_end > cmd) memset(cmd, 0xAF, cmd_buffer_end - cmd); @@ -520,6 +545,7 @@ static int dlfb_render_hline(struct dlfb_data *dlfb, struct urb **urb_ptr, struct urb *urb = *urb_ptr; u8 *cmd = *urb_buf_ptr; u8 *cmd_end = (u8 *) urb->transfer_buffer + urb->transfer_buffer_length; + unsigned long back_buffer_offset = 0; line_start = (u8 *) (front + byte_offset); next_pixel = line_start; @@ -530,6 +556,8 @@ static int dlfb_render_hline(struct dlfb_data *dlfb, struct urb **urb_ptr, const u8 *back_start = (u8 *) (dlfb->backing_buffer + byte_offset); + back_buffer_offset = (unsigned long)back_start - (unsigned long)line_start; + *ident_ptr += dlfb_trim_hline(back_start, &next_pixel, &byte_width); @@ -538,16 +566,14 @@ static int dlfb_render_hline(struct dlfb_data *dlfb, struct urb **urb_ptr, dev_addr += offset; back_start += offset; line_start += offset; - - memcpy((char *)back_start, (char *) line_start, - byte_width); } while (next_pixel < line_end) { dlfb_compress_hline((const uint16_t **) &next_pixel, (const uint16_t *) line_end, &dev_addr, - (u8 **) &cmd, (u8 *) cmd_end); + (u8 **) &cmd, (u8 *) cmd_end, back_buffer_offset, + ident_ptr); if (cmd >= cmd_end) { int len = cmd - (u8 *) urb->transfer_buffer; @@ -610,8 +636,11 @@ static int dlfb_handle_damage(struct dlfb_data *dlfb, int x, int y, } if (cmd > (char *) urb->transfer_buffer) { + int len; + if (cmd < (char *) urb->transfer_buffer + urb->transfer_buffer_length) + *cmd++ = 0xAF; /* Send partial buffer remaining before exiting */ - int len = cmd - (char *) urb->transfer_buffer; + len = cmd - (char *) urb->transfer_buffer; ret = dlfb_submit_urb(dlfb, urb, len); bytes_sent += len; } else @@ -735,8 +764,11 @@ static void dlfb_dpy_deferred_io(struct fb_info *info, } if (cmd > (char *) urb->transfer_buffer) { + int len; + if (cmd < (char *) urb->transfer_buffer + urb->transfer_buffer_length) + *cmd++ = 0xAF; /* Send partial buffer remaining before exiting */ - int len = cmd - (char *) urb->transfer_buffer; + len = cmd - (char *) urb->transfer_buffer; dlfb_submit_urb(dlfb, urb, len); bytes_sent += len; } else @@ -917,19 +949,17 @@ static void dlfb_free(struct kref *kref) { struct dlfb_data *dlfb = container_of(kref, struct dlfb_data, kref); + while (!list_empty(&dlfb->deferred_free)) { + struct dlfb_deferred_free *d = list_entry(dlfb->deferred_free.next, struct dlfb_deferred_free, list); + list_del(&d->list); + vfree(d->mem); + kfree(d); + } vfree(dlfb->backing_buffer); kfree(dlfb->edid); kfree(dlfb); } -static void dlfb_release_urb_work(struct work_struct *work) -{ - struct urb_node *unode = container_of(work, struct urb_node, - release_urb_work.work); - - up(&unode->dlfb->urbs.limit_sem); -} - static void dlfb_free_framebuffer(struct dlfb_data *dlfb) { struct fb_info *info = dlfb->info; @@ -1018,10 +1048,6 @@ static int dlfb_ops_check_var(struct fb_var_screeninfo *var, struct fb_videomode mode; struct dlfb_data *dlfb = info->par; - /* TODO: support dynamically changing framebuffer size */ - if ((var->xres * var->yres * 2) > info->fix.smem_len) - return -EINVAL; - /* set device-specific elements of var unrelated to mode */ dlfb_var_color_format(var); @@ -1039,22 +1065,42 @@ static int dlfb_ops_set_par(struct fb_info *info) int result; u16 *pix_framebuffer; int i; + struct fb_var_screeninfo fvs; + u32 line_length = info->var.xres * (info->var.bits_per_pixel / 8); + + /* clear the activate field because it causes spurious miscompares */ + fvs = info->var; + fvs.activate = 0; + fvs.vmode &= ~FB_VMODE_SMOOTH_XPAN; + + if (!memcmp(&dlfb->current_mode, &fvs, sizeof(struct fb_var_screeninfo))) + return 0; + + result = dlfb_realloc_framebuffer(dlfb, info, info->var.yres * line_length); + if (result) + return result; result = dlfb_set_video_mode(dlfb, &info->var); - if ((result == 0) && (dlfb->fb_count == 0)) { + if (result) + return result; + + dlfb->current_mode = fvs; + info->fix.line_length = line_length; + + if (dlfb->fb_count == 0) { /* paint greenscreen */ pix_framebuffer = (u16 *) info->screen_base; for (i = 0; i < info->fix.smem_len / 2; i++) pix_framebuffer[i] = 0x37e6; - - dlfb_handle_damage(dlfb, 0, 0, info->var.xres, info->var.yres, - info->screen_base); } - return result; + dlfb_handle_damage(dlfb, 0, 0, info->var.xres, info->var.yres, + info->screen_base); + + return 0; } /* To fonzi the jukebox (e.g. make blanking changes take effect) */ @@ -1129,21 +1175,29 @@ static struct fb_ops dlfb_ops = { }; +static void dlfb_deferred_vfree(struct dlfb_data *dlfb, void *mem) +{ + struct dlfb_deferred_free *d = kmalloc(sizeof(struct dlfb_deferred_free), GFP_KERNEL); + if (!d) + return; + d->mem = mem; + list_add(&d->list, &dlfb->deferred_free); +} + /* * Assumes &info->lock held by caller * Assumes no active clients have framebuffer open */ -static int dlfb_realloc_framebuffer(struct dlfb_data *dlfb, struct fb_info *info) +static int dlfb_realloc_framebuffer(struct dlfb_data *dlfb, struct fb_info *info, u32 new_len) { - int old_len = info->fix.smem_len; - int new_len; - unsigned char *old_fb = info->screen_base; + u32 old_len = info->fix.smem_len; + const void *old_fb = (const void __force *)info->screen_base; unsigned char *new_fb; unsigned char *new_back = NULL; - new_len = info->fix.line_length * info->var.yres; + new_len = PAGE_ALIGN(new_len); - if (PAGE_ALIGN(new_len) > old_len) { + if (new_len > old_len) { /* * Alloc system memory for virtual framebuffer */ @@ -1152,14 +1206,15 @@ static int dlfb_realloc_framebuffer(struct dlfb_data *dlfb, struct fb_info *info dev_err(info->dev, "Virtual framebuffer alloc failed\n"); return -ENOMEM; } + memset(new_fb, 0xff, new_len); if (info->screen_base) { memcpy(new_fb, old_fb, old_len); - vfree(info->screen_base); + dlfb_deferred_vfree(dlfb, (void __force *)info->screen_base); } - info->screen_base = new_fb; - info->fix.smem_len = PAGE_ALIGN(new_len); + info->screen_base = (char __iomem *)new_fb; + info->fix.smem_len = new_len; info->fix.smem_start = (unsigned long) new_fb; info->flags = udlfb_info_flags; @@ -1175,7 +1230,7 @@ static int dlfb_realloc_framebuffer(struct dlfb_data *dlfb, struct fb_info *info dev_info(info->dev, "No shadow/backing buffer allocated\n"); else { - vfree(dlfb->backing_buffer); + dlfb_deferred_vfree(dlfb, dlfb->backing_buffer); dlfb->backing_buffer = new_back; } } @@ -1327,11 +1382,6 @@ static int dlfb_setup_modes(struct dlfb_data *dlfb, * with mode size info, we can now alloc our framebuffer. */ memcpy(&info->fix, &dlfb_fix, sizeof(dlfb_fix)); - info->fix.line_length = info->var.xres * - (info->var.bits_per_pixel / 8); - - result = dlfb_realloc_framebuffer(dlfb, info); - } else result = -EINVAL; @@ -1419,7 +1469,10 @@ static ssize_t edid_store( if (!dlfb->edid || memcmp(src, dlfb->edid, src_size)) return -EINVAL; - dlfb_ops_set_par(fb_info); + ret = dlfb_ops_set_par(fb_info); + if (ret) + return ret; + return src_size; } @@ -1579,6 +1632,7 @@ static int dlfb_usb_probe(struct usb_interface *intf, } kref_init(&dlfb->kref); /* matching kref_put in usb .disconnect fn */ + INIT_LIST_HEAD(&dlfb->deferred_free); dlfb->udev = usbdev; usb_set_intfdata(intf, dlfb); @@ -1649,7 +1703,8 @@ static void dlfb_init_framebuffer_work(struct work_struct *work) dlfb->info = info; info->par = dlfb; info->pseudo_palette = dlfb->pseudo_palette; - info->fbops = &dlfb_ops; + dlfb->ops = dlfb_ops; + info->fbops = &dlfb->ops; retval = fb_alloc_cmap(&info->cmap, 256, 0); if (retval < 0) { @@ -1675,7 +1730,9 @@ static void dlfb_init_framebuffer_work(struct work_struct *work) dlfb_select_std_channel(dlfb); dlfb_ops_check_var(&info->var, info); - dlfb_ops_set_par(info); + retval = dlfb_ops_set_par(info); + if (retval) + goto error; retval = register_framebuffer(info); if (retval < 0) { @@ -1789,14 +1846,7 @@ static void dlfb_urb_completion(struct urb *urb) dlfb->urbs.available++; spin_unlock_irqrestore(&dlfb->urbs.lock, flags); - /* - * When using fb_defio, we deadlock if up() is called - * while another is waiting. So queue to another process. - */ - if (fb_defio) - schedule_delayed_work(&unode->release_urb_work, 0); - else - up(&dlfb->urbs.limit_sem); + up(&dlfb->urbs.limit_sem); } static void dlfb_free_urb_list(struct dlfb_data *dlfb) @@ -1805,23 +1855,17 @@ static void dlfb_free_urb_list(struct dlfb_data *dlfb) struct list_head *node; struct urb_node *unode; struct urb *urb; - int ret; - unsigned long flags; /* keep waiting and freeing, until we've got 'em all */ while (count--) { + down(&dlfb->urbs.limit_sem); - /* Getting interrupted means a leak, but ok at disconnect */ - ret = down_interruptible(&dlfb->urbs.limit_sem); - if (ret) - break; - - spin_lock_irqsave(&dlfb->urbs.lock, flags); + spin_lock_irq(&dlfb->urbs.lock); node = dlfb->urbs.list.next; /* have reserved one with sem */ list_del_init(node); - spin_unlock_irqrestore(&dlfb->urbs.lock, flags); + spin_unlock_irq(&dlfb->urbs.lock); unode = list_entry(node, struct urb_node, entry); urb = unode->urb; @@ -1838,25 +1882,27 @@ static void dlfb_free_urb_list(struct dlfb_data *dlfb) static int dlfb_alloc_urb_list(struct dlfb_data *dlfb, int count, size_t size) { - int i = 0; struct urb *urb; struct urb_node *unode; char *buf; + size_t wanted_size = count * size; spin_lock_init(&dlfb->urbs.lock); +retry: dlfb->urbs.size = size; INIT_LIST_HEAD(&dlfb->urbs.list); - while (i < count) { + sema_init(&dlfb->urbs.limit_sem, 0); + dlfb->urbs.count = 0; + dlfb->urbs.available = 0; + + while (dlfb->urbs.count * size < wanted_size) { unode = kzalloc(sizeof(*unode), GFP_KERNEL); if (!unode) break; unode->dlfb = dlfb; - INIT_DELAYED_WORK(&unode->release_urb_work, - dlfb_release_urb_work); - urb = usb_alloc_urb(0, GFP_KERNEL); if (!urb) { kfree(unode); @@ -1864,11 +1910,16 @@ static int dlfb_alloc_urb_list(struct dlfb_data *dlfb, int count, size_t size) } unode->urb = urb; - buf = usb_alloc_coherent(dlfb->udev, MAX_TRANSFER, GFP_KERNEL, + buf = usb_alloc_coherent(dlfb->udev, size, GFP_KERNEL, &urb->transfer_dma); if (!buf) { kfree(unode); usb_free_urb(urb); + if (size > PAGE_SIZE) { + size /= 2; + dlfb_free_urb_list(dlfb); + goto retry; + } break; } @@ -1879,14 +1930,12 @@ static int dlfb_alloc_urb_list(struct dlfb_data *dlfb, int count, size_t size) list_add_tail(&unode->entry, &dlfb->urbs.list); - i++; + up(&dlfb->urbs.limit_sem); + dlfb->urbs.count++; + dlfb->urbs.available++; } - sema_init(&dlfb->urbs.limit_sem, i); - dlfb->urbs.count = i; - dlfb->urbs.available = i; - - return i; + return dlfb->urbs.count; } static struct urb *dlfb_get_urb(struct dlfb_data *dlfb) @@ -1894,7 +1943,6 @@ static struct urb *dlfb_get_urb(struct dlfb_data *dlfb) int ret; struct list_head *entry; struct urb_node *unode; - unsigned long flags; /* Wait for an in-flight buffer to complete and get re-queued */ ret = down_timeout(&dlfb->urbs.limit_sem, GET_URB_TIMEOUT); @@ -1906,14 +1954,14 @@ static struct urb *dlfb_get_urb(struct dlfb_data *dlfb) return NULL; } - spin_lock_irqsave(&dlfb->urbs.lock, flags); + spin_lock_irq(&dlfb->urbs.lock); BUG_ON(list_empty(&dlfb->urbs.list)); /* reserved one with limit_sem */ entry = dlfb->urbs.list.next; list_del_init(entry); dlfb->urbs.available--; - spin_unlock_irqrestore(&dlfb->urbs.lock, flags); + spin_unlock_irq(&dlfb->urbs.lock); unode = list_entry(entry, struct urb_node, entry); return unode->urb; diff --git a/drivers/video/fbdev/via/lcd.c b/drivers/video/fbdev/via/lcd.c index 5d21ff436ec8..b9305d73a1e5 100644 --- a/drivers/video/fbdev/via/lcd.c +++ b/drivers/video/fbdev/via/lcd.c @@ -758,6 +758,7 @@ static void set_lcd_output_path(int set_iga, int output_interface) viaparinfo->chip_info->gfx_chip_name)) viafb_write_reg_mask(CR97, VIACR, 0x84, BIT7 + BIT2 + BIT1 + BIT0); + /* fall through */ case INTERFACE_DVP0: case INTERFACE_DVP1: case INTERFACE_DFP_HIGH: diff --git a/drivers/video/fbdev/via/viafbdev.c b/drivers/video/fbdev/via/viafbdev.c index d2f785068ef4..7bb7e90b8f00 100644 --- a/drivers/video/fbdev/via/viafbdev.c +++ b/drivers/video/fbdev/via/viafbdev.c @@ -19,6 +19,7 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include <linux/compiler.h> #include <linux/module.h> #include <linux/seq_file.h> #include <linux/slab.h> @@ -1468,7 +1469,7 @@ static const struct file_operations viafb_vt1636_proc_fops = { #endif /* CONFIG_FB_VIA_DIRECT_PROCFS */ -static int viafb_sup_odev_proc_show(struct seq_file *m, void *v) +static int __maybe_unused viafb_sup_odev_proc_show(struct seq_file *m, void *v) { via_odev_to_seq(m, supported_odev_map[ viaparinfo->shared->chip_info.gfx_chip_name]); diff --git a/drivers/xen/mcelog.c b/drivers/xen/mcelog.c index 262835ace35d..b8bf61abb65b 100644 --- a/drivers/xen/mcelog.c +++ b/drivers/xen/mcelog.c @@ -288,7 +288,6 @@ static int mc_queue_handle(uint32_t flags) int ret = 0; mc_op.cmd = XEN_MC_fetch; - mc_op.interface_version = XEN_MCA_INTERFACE_VERSION; set_xen_guest_handle(mc_op.u.mc_fetch.data, &g_mi); do { mc_op.u.mc_fetch.flags = flags; @@ -358,7 +357,6 @@ static int bind_virq_for_mce(void) /* Fetch physical CPU Numbers */ mc_op.cmd = XEN_MC_physcpuinfo; - mc_op.interface_version = XEN_MCA_INTERFACE_VERSION; set_xen_guest_handle(mc_op.u.mc_physcpuinfo.info, g_physinfo); ret = HYPERVISOR_mca(&mc_op); if (ret) { diff --git a/drivers/xen/xen-acpi-processor.c b/drivers/xen/xen-acpi-processor.c index b29f4e40851f..fbb9137c7d02 100644 --- a/drivers/xen/xen-acpi-processor.c +++ b/drivers/xen/xen-acpi-processor.c @@ -362,6 +362,12 @@ read_acpi_id(acpi_handle handle, u32 lvl, void *context, void **rv) default: return AE_OK; } + if (invalid_phys_cpuid(acpi_get_phys_id(handle, + acpi_type == ACPI_TYPE_DEVICE, + acpi_id))) { + pr_debug("CPU with ACPI ID %u is unavailable\n", acpi_id); + return AE_OK; + } /* There are more ACPI Processor objects than in x2APIC or MADT. * This can happen with incorrect ACPI SSDT declerations. */ if (acpi_id >= nr_acpi_bits) { diff --git a/fs/lockd/clntlock.c b/fs/lockd/clntlock.c index 96c1d14c18f1..c2a128678e6e 100644 --- a/fs/lockd/clntlock.c +++ b/fs/lockd/clntlock.c @@ -187,7 +187,7 @@ __be32 nlmclnt_grant(const struct sockaddr *addr, const struct nlm_lock *lock) continue; if (!rpc_cmp_addr(nlm_addr(block->b_host), addr)) continue; - if (nfs_compare_fh(NFS_FH(file_inode(fl_blocked->fl_file)) ,fh) != 0) + if (nfs_compare_fh(NFS_FH(locks_inode(fl_blocked->fl_file)), fh) != 0) continue; /* Alright, we found a lock. Set the return status * and wake up the caller diff --git a/fs/lockd/clntproc.c b/fs/lockd/clntproc.c index a2c0dfc6fdc0..d20b92f271c2 100644 --- a/fs/lockd/clntproc.c +++ b/fs/lockd/clntproc.c @@ -128,7 +128,7 @@ static void nlmclnt_setlockargs(struct nlm_rqst *req, struct file_lock *fl) char *nodename = req->a_host->h_rpcclnt->cl_nodename; nlmclnt_next_cookie(&argp->cookie); - memcpy(&lock->fh, NFS_FH(file_inode(fl->fl_file)), sizeof(struct nfs_fh)); + memcpy(&lock->fh, NFS_FH(locks_inode(fl->fl_file)), sizeof(struct nfs_fh)); lock->caller = nodename; lock->oh.data = req->a_owner; lock->oh.len = snprintf(req->a_owner, sizeof(req->a_owner), "%u@%s", diff --git a/fs/lockd/svclock.c b/fs/lockd/svclock.c index 3701bccab478..74330daeab71 100644 --- a/fs/lockd/svclock.c +++ b/fs/lockd/svclock.c @@ -405,8 +405,8 @@ nlmsvc_lock(struct svc_rqst *rqstp, struct nlm_file *file, __be32 ret; dprintk("lockd: nlmsvc_lock(%s/%ld, ty=%d, pi=%d, %Ld-%Ld, bl=%d)\n", - file_inode(file->f_file)->i_sb->s_id, - file_inode(file->f_file)->i_ino, + locks_inode(file->f_file)->i_sb->s_id, + locks_inode(file->f_file)->i_ino, lock->fl.fl_type, lock->fl.fl_pid, (long long)lock->fl.fl_start, (long long)lock->fl.fl_end, @@ -511,8 +511,8 @@ nlmsvc_testlock(struct svc_rqst *rqstp, struct nlm_file *file, __be32 ret; dprintk("lockd: nlmsvc_testlock(%s/%ld, ty=%d, %Ld-%Ld)\n", - file_inode(file->f_file)->i_sb->s_id, - file_inode(file->f_file)->i_ino, + locks_inode(file->f_file)->i_sb->s_id, + locks_inode(file->f_file)->i_ino, lock->fl.fl_type, (long long)lock->fl.fl_start, (long long)lock->fl.fl_end); @@ -566,8 +566,8 @@ nlmsvc_unlock(struct net *net, struct nlm_file *file, struct nlm_lock *lock) int error; dprintk("lockd: nlmsvc_unlock(%s/%ld, pi=%d, %Ld-%Ld)\n", - file_inode(file->f_file)->i_sb->s_id, - file_inode(file->f_file)->i_ino, + locks_inode(file->f_file)->i_sb->s_id, + locks_inode(file->f_file)->i_ino, lock->fl.fl_pid, (long long)lock->fl.fl_start, (long long)lock->fl.fl_end); @@ -595,8 +595,8 @@ nlmsvc_cancel_blocked(struct net *net, struct nlm_file *file, struct nlm_lock *l int status = 0; dprintk("lockd: nlmsvc_cancel(%s/%ld, pi=%d, %Ld-%Ld)\n", - file_inode(file->f_file)->i_sb->s_id, - file_inode(file->f_file)->i_ino, + locks_inode(file->f_file)->i_sb->s_id, + locks_inode(file->f_file)->i_ino, lock->fl.fl_pid, (long long)lock->fl.fl_start, (long long)lock->fl.fl_end); diff --git a/fs/lockd/svcsubs.c b/fs/lockd/svcsubs.c index 4ec3d6e03e76..899360ba3b84 100644 --- a/fs/lockd/svcsubs.c +++ b/fs/lockd/svcsubs.c @@ -44,7 +44,7 @@ static inline void nlm_debug_print_fh(char *msg, struct nfs_fh *f) static inline void nlm_debug_print_file(char *msg, struct nlm_file *file) { - struct inode *inode = file_inode(file->f_file); + struct inode *inode = locks_inode(file->f_file); dprintk("lockd: %s %s/%ld\n", msg, inode->i_sb->s_id, inode->i_ino); @@ -414,7 +414,7 @@ nlmsvc_match_sb(void *datap, struct nlm_file *file) { struct super_block *sb = datap; - return sb == file_inode(file->f_file)->i_sb; + return sb == locks_inode(file->f_file)->i_sb; } /** diff --git a/fs/nfs/blocklayout/blocklayout.c b/fs/nfs/blocklayout/blocklayout.c index 7cb5c38c19e4..06cb0c1d9aee 100644 --- a/fs/nfs/blocklayout/blocklayout.c +++ b/fs/nfs/blocklayout/blocklayout.c @@ -753,6 +753,7 @@ out: case -ENODEV: /* Our extent block devices are unavailable */ set_bit(NFS_LSEG_UNAVAILABLE, &lseg->pls_flags); + /* Fall through */ case 0: return lseg; default: diff --git a/fs/nfs/blocklayout/dev.c b/fs/nfs/blocklayout/dev.c index a7efd83779d2..dec5880ac6de 100644 --- a/fs/nfs/blocklayout/dev.c +++ b/fs/nfs/blocklayout/dev.c @@ -204,7 +204,7 @@ static bool bl_map_stripe(struct pnfs_block_dev *dev, u64 offset, chunk = div_u64(offset, dev->chunk_size); div_u64_rem(chunk, dev->nr_children, &chunk_idx); - if (chunk_idx > dev->nr_children) { + if (chunk_idx >= dev->nr_children) { dprintk("%s: invalid chunk idx %d (%lld/%lld)\n", __func__, chunk_idx, offset, dev->chunk_size); /* error, should not happen */ diff --git a/fs/nfs/callback.h b/fs/nfs/callback.h index a20a0bce40a4..8f34daf85f70 100644 --- a/fs/nfs/callback.h +++ b/fs/nfs/callback.h @@ -184,6 +184,18 @@ struct cb_notify_lock_args { extern __be32 nfs4_callback_notify_lock(void *argp, void *resp, struct cb_process_state *cps); #endif /* CONFIG_NFS_V4_1 */ +#ifdef CONFIG_NFS_V4_2 +struct cb_offloadargs { + struct nfs_fh coa_fh; + nfs4_stateid coa_stateid; + uint32_t error; + uint64_t wr_count; + struct nfs_writeverf wr_writeverf; +}; + +extern __be32 nfs4_callback_offload(void *args, void *dummy, + struct cb_process_state *cps); +#endif /* CONFIG_NFS_V4_2 */ extern int check_gss_callback_principal(struct nfs_client *, struct svc_rqst *); extern __be32 nfs4_callback_getattr(void *argp, void *resp, struct cb_process_state *cps); diff --git a/fs/nfs/callback_proc.c b/fs/nfs/callback_proc.c index 64c214fb9da6..fa515d5ea5ba 100644 --- a/fs/nfs/callback_proc.c +++ b/fs/nfs/callback_proc.c @@ -215,9 +215,9 @@ static u32 pnfs_check_callback_stateid(struct pnfs_layout_hdr *lo, { u32 oldseq, newseq; - /* Is the stateid still not initialised? */ + /* Is the stateid not initialised? */ if (!pnfs_layout_is_valid(lo)) - return NFS4ERR_DELAY; + return NFS4ERR_NOMATCHING_LAYOUT; /* Mismatched stateid? */ if (!nfs4_stateid_match_other(&lo->plh_stateid, new)) @@ -273,7 +273,6 @@ static u32 initiate_file_draining(struct nfs_client *clp, rv = pnfs_check_callback_stateid(lo, &args->cbl_stateid); if (rv != NFS_OK) goto unlock; - pnfs_set_layout_stateid(lo, &args->cbl_stateid, true); /* * Enforce RFC5661 Section 12.5.5.2.1.5 (Bulk Recall and Return) @@ -283,19 +282,23 @@ static u32 initiate_file_draining(struct nfs_client *clp, goto unlock; } - if (pnfs_mark_matching_lsegs_return(lo, &free_me_list, + pnfs_set_layout_stateid(lo, &args->cbl_stateid, true); + switch (pnfs_mark_matching_lsegs_return(lo, &free_me_list, &args->cbl_range, be32_to_cpu(args->cbl_stateid.seqid))) { + case 0: + case -EBUSY: + /* There are layout segments that need to be returned */ rv = NFS4_OK; - goto unlock; - } - - /* Embrace your forgetfulness! */ - rv = NFS4ERR_NOMATCHING_LAYOUT; + break; + case -ENOENT: + /* Embrace your forgetfulness! */ + rv = NFS4ERR_NOMATCHING_LAYOUT; - if (NFS_SERVER(ino)->pnfs_curr_ld->return_range) { - NFS_SERVER(ino)->pnfs_curr_ld->return_range(lo, - &args->cbl_range); + if (NFS_SERVER(ino)->pnfs_curr_ld->return_range) { + NFS_SERVER(ino)->pnfs_curr_ld->return_range(lo, + &args->cbl_range); + } } unlock: spin_unlock(&ino->i_lock); @@ -328,8 +331,6 @@ static u32 initiate_bulk_draining(struct nfs_client *clp, static u32 do_callback_layoutrecall(struct nfs_client *clp, struct cb_layoutrecallargs *args) { - write_seqcount_begin(&clp->cl_callback_count); - write_seqcount_end(&clp->cl_callback_count); if (args->cbl_recall_type == RETURN_FILE) return initiate_file_draining(clp, args); return initiate_bulk_draining(clp, args); @@ -441,11 +442,14 @@ validate_seqid(const struct nfs4_slot_table *tbl, const struct nfs4_slot *slot, * a match. If the slot is in use and the sequence numbers match, the * client is still waiting for a response to the original request. */ -static bool referring_call_exists(struct nfs_client *clp, +static int referring_call_exists(struct nfs_client *clp, uint32_t nrclists, - struct referring_call_list *rclists) + struct referring_call_list *rclists, + spinlock_t *lock) + __releases(lock) + __acquires(lock) { - bool status = false; + int status = 0; int i, j; struct nfs4_session *session; struct nfs4_slot_table *tbl; @@ -468,8 +472,10 @@ static bool referring_call_exists(struct nfs_client *clp, for (j = 0; j < rclist->rcl_nrefcalls; j++) { ref = &rclist->rcl_refcalls[j]; + spin_unlock(lock); status = nfs4_slot_wait_on_seqid(tbl, ref->rc_slotid, ref->rc_sequenceid, HZ >> 1) < 0; + spin_lock(lock); if (status) goto out; } @@ -546,7 +552,8 @@ __be32 nfs4_callback_sequence(void *argp, void *resp, * related callback was received before the response to the original * call. */ - if (referring_call_exists(clp, args->csa_nrclists, args->csa_rclists)) { + if (referring_call_exists(clp, args->csa_nrclists, args->csa_rclists, + &tbl->slot_tbl_lock) < 0) { status = htonl(NFS4ERR_DELAY); goto out_unlock; } @@ -660,3 +667,57 @@ __be32 nfs4_callback_notify_lock(void *argp, void *resp, return htonl(NFS4_OK); } #endif /* CONFIG_NFS_V4_1 */ +#ifdef CONFIG_NFS_V4_2 +static void nfs4_copy_cb_args(struct nfs4_copy_state *cp_state, + struct cb_offloadargs *args) +{ + cp_state->count = args->wr_count; + cp_state->error = args->error; + if (!args->error) { + cp_state->verf.committed = args->wr_writeverf.committed; + memcpy(&cp_state->verf.verifier.data[0], + &args->wr_writeverf.verifier.data[0], + NFS4_VERIFIER_SIZE); + } +} + +__be32 nfs4_callback_offload(void *data, void *dummy, + struct cb_process_state *cps) +{ + struct cb_offloadargs *args = data; + struct nfs_server *server; + struct nfs4_copy_state *copy; + bool found = false; + + spin_lock(&cps->clp->cl_lock); + rcu_read_lock(); + list_for_each_entry_rcu(server, &cps->clp->cl_superblocks, + client_link) { + list_for_each_entry(copy, &server->ss_copies, copies) { + if (memcmp(args->coa_stateid.other, + copy->stateid.other, + sizeof(args->coa_stateid.other))) + continue; + nfs4_copy_cb_args(copy, args); + complete(©->completion); + found = true; + goto out; + } + } +out: + rcu_read_unlock(); + if (!found) { + copy = kzalloc(sizeof(struct nfs4_copy_state), GFP_NOFS); + if (!copy) { + spin_unlock(&cps->clp->cl_lock); + return htonl(NFS4ERR_SERVERFAULT); + } + memcpy(©->stateid, &args->coa_stateid, NFS4_STATEID_SIZE); + nfs4_copy_cb_args(copy, args); + list_add_tail(©->copies, &cps->clp->pending_cb_stateids); + } + spin_unlock(&cps->clp->cl_lock); + + return 0; +} +#endif /* CONFIG_NFS_V4_2 */ diff --git a/fs/nfs/callback_xdr.c b/fs/nfs/callback_xdr.c index a813979b5be0..a87a56273407 100644 --- a/fs/nfs/callback_xdr.c +++ b/fs/nfs/callback_xdr.c @@ -38,6 +38,9 @@ #define CB_OP_RECALLSLOT_RES_MAXSZ (CB_OP_HDR_RES_MAXSZ) #define CB_OP_NOTIFY_LOCK_RES_MAXSZ (CB_OP_HDR_RES_MAXSZ) #endif /* CONFIG_NFS_V4_1 */ +#ifdef CONFIG_NFS_V4_2 +#define CB_OP_OFFLOAD_RES_MAXSZ (CB_OP_HDR_RES_MAXSZ) +#endif /* CONFIG_NFS_V4_2 */ #define NFSDBG_FACILITY NFSDBG_CALLBACK @@ -527,7 +530,72 @@ static __be32 decode_notify_lock_args(struct svc_rqst *rqstp, } #endif /* CONFIG_NFS_V4_1 */ +#ifdef CONFIG_NFS_V4_2 +static __be32 decode_write_response(struct xdr_stream *xdr, + struct cb_offloadargs *args) +{ + __be32 *p; + + /* skip the always zero field */ + p = read_buf(xdr, 4); + if (unlikely(!p)) + goto out; + p++; + + /* decode count, stable_how, verifier */ + p = xdr_inline_decode(xdr, 8 + 4); + if (unlikely(!p)) + goto out; + p = xdr_decode_hyper(p, &args->wr_count); + args->wr_writeverf.committed = be32_to_cpup(p); + p = xdr_inline_decode(xdr, NFS4_VERIFIER_SIZE); + if (likely(p)) { + memcpy(&args->wr_writeverf.verifier.data[0], p, + NFS4_VERIFIER_SIZE); + return 0; + } +out: + return htonl(NFS4ERR_RESOURCE); +} + +static __be32 decode_offload_args(struct svc_rqst *rqstp, + struct xdr_stream *xdr, + void *data) +{ + struct cb_offloadargs *args = data; + __be32 *p; + __be32 status; + + /* decode fh */ + status = decode_fh(xdr, &args->coa_fh); + if (unlikely(status != 0)) + return status; + /* decode stateid */ + status = decode_stateid(xdr, &args->coa_stateid); + if (unlikely(status != 0)) + return status; + + /* decode status */ + p = read_buf(xdr, 4); + if (unlikely(!p)) + goto out; + args->error = ntohl(*p++); + if (!args->error) { + status = decode_write_response(xdr, args); + if (unlikely(status != 0)) + return status; + } else { + p = xdr_inline_decode(xdr, 8); + if (unlikely(!p)) + goto out; + p = xdr_decode_hyper(p, &args->wr_count); + } + return 0; +out: + return htonl(NFS4ERR_RESOURCE); +} +#endif /* CONFIG_NFS_V4_2 */ static __be32 encode_string(struct xdr_stream *xdr, unsigned int len, const char *str) { if (unlikely(xdr_stream_encode_opaque(xdr, str, len) < 0)) @@ -773,7 +841,10 @@ preprocess_nfs42_op(int nop, unsigned int op_nr, struct callback_op **op) if (status != htonl(NFS4ERR_OP_ILLEGAL)) return status; - if (op_nr == OP_CB_OFFLOAD) + if (op_nr == OP_CB_OFFLOAD) { + *op = &callback_ops[op_nr]; + return htonl(NFS_OK); + } else return htonl(NFS4ERR_NOTSUPP); return htonl(NFS4ERR_OP_ILLEGAL); } @@ -883,16 +954,21 @@ static __be32 nfs4_callback_compound(struct svc_rqst *rqstp) if (hdr_arg.minorversion == 0) { cps.clp = nfs4_find_client_ident(SVC_NET(rqstp), hdr_arg.cb_ident); - if (!cps.clp || !check_gss_callback_principal(cps.clp, rqstp)) + if (!cps.clp || !check_gss_callback_principal(cps.clp, rqstp)) { + if (cps.clp) + nfs_put_client(cps.clp); goto out_invalidcred; + } } cps.minorversion = hdr_arg.minorversion; hdr_res.taglen = hdr_arg.taglen; hdr_res.tag = hdr_arg.tag; - if (encode_compound_hdr_res(&xdr_out, &hdr_res) != 0) + if (encode_compound_hdr_res(&xdr_out, &hdr_res) != 0) { + if (cps.clp) + nfs_put_client(cps.clp); return rpc_system_err; - + } while (status == 0 && nops != hdr_arg.nops) { status = process_op(nops, rqstp, &xdr_in, rqstp->rq_argp, &xdr_out, rqstp->rq_resp, @@ -969,6 +1045,13 @@ static struct callback_op callback_ops[] = { .res_maxsize = CB_OP_NOTIFY_LOCK_RES_MAXSZ, }, #endif /* CONFIG_NFS_V4_1 */ +#ifdef CONFIG_NFS_V4_2 + [OP_CB_OFFLOAD] = { + .process_op = nfs4_callback_offload, + .decode_args = decode_offload_args, + .res_maxsize = CB_OP_OFFLOAD_RES_MAXSZ, + }, +#endif /* CONFIG_NFS_V4_2 */ }; /* diff --git a/fs/nfs/client.c b/fs/nfs/client.c index 377a61654a88..96d5f8135eb9 100644 --- a/fs/nfs/client.c +++ b/fs/nfs/client.c @@ -886,6 +886,7 @@ struct nfs_server *nfs_alloc_server(void) INIT_LIST_HEAD(&server->delegations); INIT_LIST_HEAD(&server->layouts); INIT_LIST_HEAD(&server->state_owners_lru); + INIT_LIST_HEAD(&server->ss_copies); atomic_set(&server->active, 0); diff --git a/fs/nfs/dir.c b/fs/nfs/dir.c index d7f158c3efc8..8bfaa658b2c1 100644 --- a/fs/nfs/dir.c +++ b/fs/nfs/dir.c @@ -904,23 +904,29 @@ static loff_t nfs_llseek_dir(struct file *filp, loff_t offset, int whence) dfprintk(FILE, "NFS: llseek dir(%pD2, %lld, %d)\n", filp, offset, whence); - inode_lock(inode); switch (whence) { - case 1: - offset += filp->f_pos; - case 0: - if (offset >= 0) - break; - default: - offset = -EINVAL; - goto out; + default: + return -EINVAL; + case SEEK_SET: + if (offset < 0) + return -EINVAL; + inode_lock(inode); + break; + case SEEK_CUR: + if (offset == 0) + return filp->f_pos; + inode_lock(inode); + offset += filp->f_pos; + if (offset < 0) { + inode_unlock(inode); + return -EINVAL; + } } if (offset != filp->f_pos) { filp->f_pos = offset; dir_ctx->dir_cookie = 0; dir_ctx->duped = 0; } -out: inode_unlock(inode); return offset; } @@ -1032,7 +1038,7 @@ int nfs_lookup_verify_inode(struct inode *inode, unsigned int flags) if (flags & LOOKUP_REVAL) goto out_force; out: - return (inode->i_nlink == 0) ? -ENOENT : 0; + return (inode->i_nlink == 0) ? -ESTALE : 0; out_force: if (flags & LOOKUP_RCU) return -ECHILD; @@ -2499,7 +2505,9 @@ static int nfs_execute_ok(struct inode *inode, int mask) struct nfs_server *server = NFS_SERVER(inode); int ret = 0; - if (nfs_check_cache_invalid(inode, NFS_INO_INVALID_ACCESS)) { + if (S_ISDIR(inode->i_mode)) + return 0; + if (nfs_check_cache_invalid(inode, NFS_INO_INVALID_OTHER)) { if (mask & MAY_NOT_BLOCK) return -ECHILD; ret = __nfs_revalidate_inode(server, inode); diff --git a/fs/nfs/direct.c b/fs/nfs/direct.c index 621c517b325c..aa12c3063bae 100644 --- a/fs/nfs/direct.c +++ b/fs/nfs/direct.c @@ -758,7 +758,7 @@ static void nfs_direct_write_schedule_work(struct work_struct *work) static void nfs_direct_write_complete(struct nfs_direct_req *dreq) { - schedule_work(&dreq->work); /* Calls nfs_direct_write_schedule_work */ + queue_work(nfsiod_workqueue, &dreq->work); /* Calls nfs_direct_write_schedule_work */ } static void nfs_direct_write_completion(struct nfs_pgio_header *hdr) diff --git a/fs/nfs/file.c b/fs/nfs/file.c index 81cca49a8375..29553fdba8af 100644 --- a/fs/nfs/file.c +++ b/fs/nfs/file.c @@ -532,13 +532,13 @@ const struct address_space_operations nfs_file_aops = { * writable, implying that someone is about to modify the page through a * shared-writable mapping */ -static int nfs_vm_page_mkwrite(struct vm_fault *vmf) +static vm_fault_t nfs_vm_page_mkwrite(struct vm_fault *vmf) { struct page *page = vmf->page; struct file *filp = vmf->vma->vm_file; struct inode *inode = file_inode(filp); unsigned pagelen; - int ret = VM_FAULT_NOPAGE; + vm_fault_t ret = VM_FAULT_NOPAGE; struct address_space *mapping; dfprintk(PAGECACHE, "NFS: vm_page_mkwrite(%pD2(%lu), offset %lld)\n", diff --git a/fs/nfs/flexfilelayout/flexfilelayout.c b/fs/nfs/flexfilelayout/flexfilelayout.c index 8f003792ccde..cae43333ef16 100644 --- a/fs/nfs/flexfilelayout/flexfilelayout.c +++ b/fs/nfs/flexfilelayout/flexfilelayout.c @@ -812,7 +812,6 @@ ff_layout_pg_get_read(struct nfs_pageio_descriptor *pgio, struct nfs_page *req, bool strict_iomode) { -retry_strict: pnfs_put_lseg(pgio->pg_lseg); pgio->pg_lseg = pnfs_update_layout(pgio->pg_inode, req->wb_context, @@ -825,16 +824,6 @@ retry_strict: pgio->pg_error = PTR_ERR(pgio->pg_lseg); pgio->pg_lseg = NULL; } - - /* If we don't have checking, do get a IOMODE_RW - * segment, and the server wants to avoid READs - * there, then retry! - */ - if (pgio->pg_lseg && !strict_iomode && - ff_layout_avoid_read_on_rw(pgio->pg_lseg)) { - strict_iomode = true; - goto retry_strict; - } } static void @@ -849,14 +838,16 @@ ff_layout_pg_init_read(struct nfs_pageio_descriptor *pgio, retry: pnfs_generic_pg_check_layout(pgio); /* Use full layout for now */ - if (!pgio->pg_lseg) + if (!pgio->pg_lseg) { ff_layout_pg_get_read(pgio, req, false); - else if (ff_layout_avoid_read_on_rw(pgio->pg_lseg)) + if (!pgio->pg_lseg) + goto out_nolseg; + } + if (ff_layout_avoid_read_on_rw(pgio->pg_lseg)) { ff_layout_pg_get_read(pgio, req, true); - - /* If no lseg, fall back to read through mds */ - if (pgio->pg_lseg == NULL) - goto out_mds; + if (!pgio->pg_lseg) + goto out_nolseg; + } ds = ff_layout_choose_best_ds_for_read(pgio->pg_lseg, 0, &ds_idx); if (!ds) { @@ -878,6 +869,9 @@ retry: pgm->pg_bsize = mirror->mirror_ds->ds_versions[0].rsize; return; +out_nolseg: + if (pgio->pg_error < 0) + return; out_mds: pnfs_put_lseg(pgio->pg_lseg); pgio->pg_lseg = NULL; @@ -1323,6 +1317,7 @@ static void ff_layout_read_record_layoutstats_done(struct rpc_task *task, FF_LAYOUT_COMP(hdr->lseg, hdr->pgio_mirror_idx), hdr->args.count, hdr->res.count); + set_bit(NFS_LSEG_LAYOUTRETURN, &hdr->lseg->pls_flags); } static int ff_layout_read_prepare_common(struct rpc_task *task, @@ -1507,6 +1502,7 @@ static void ff_layout_write_record_layoutstats_done(struct rpc_task *task, FF_LAYOUT_COMP(hdr->lseg, hdr->pgio_mirror_idx), hdr->args.count, hdr->res.count, hdr->res.verf->committed); + set_bit(NFS_LSEG_LAYOUTRETURN, &hdr->lseg->pls_flags); } static int ff_layout_write_prepare_common(struct rpc_task *task, @@ -1615,6 +1611,7 @@ static void ff_layout_commit_record_layoutstats_done(struct rpc_task *task, nfs4_ff_layout_stat_io_end_write(task, FF_LAYOUT_COMP(cdata->lseg, cdata->ds_commit_index), count, count, NFS_FILE_SYNC); + set_bit(NFS_LSEG_LAYOUTRETURN, &cdata->lseg->pls_flags); } static void ff_layout_commit_prepare_common(struct rpc_task *task, diff --git a/fs/nfs/nfs3acl.c b/fs/nfs/nfs3acl.c index 7173a4ee862c..9fce18548f7e 100644 --- a/fs/nfs/nfs3acl.c +++ b/fs/nfs/nfs3acl.c @@ -108,6 +108,7 @@ struct posix_acl *nfs3_get_acl(struct inode *inode, int type) case -EPROTONOSUPPORT: dprintk("NFS_V3_ACL extension not supported; disabling\n"); server->caps &= ~NFS_CAP_ACLS; + /* fall through */ case -ENOTSUPP: status = -EOPNOTSUPP; default: @@ -229,6 +230,7 @@ static int __nfs3_proc_setacls(struct inode *inode, struct posix_acl *acl, dprintk("NFS_V3_ACL SETACL RPC not supported" "(will not retry)\n"); server->caps &= ~NFS_CAP_ACLS; + /* fall through */ case -ENOTSUPP: status = -EOPNOTSUPP; } diff --git a/fs/nfs/nfs42proc.c b/fs/nfs/nfs42proc.c index 5f59b6f65a42..ac5b784a1de0 100644 --- a/fs/nfs/nfs42proc.c +++ b/fs/nfs/nfs42proc.c @@ -17,6 +17,7 @@ #include "internal.h" #define NFSDBG_FACILITY NFSDBG_PROC +static int nfs42_do_offload_cancel_async(struct file *dst, nfs4_stateid *std); static int _nfs42_proc_fallocate(struct rpc_message *msg, struct file *filep, struct nfs_lock_context *lock, loff_t offset, loff_t len) @@ -130,6 +131,91 @@ out_unlock: return err; } +static int handle_async_copy(struct nfs42_copy_res *res, + struct nfs_server *server, + struct file *src, + struct file *dst, + nfs4_stateid *src_stateid) +{ + struct nfs4_copy_state *copy; + int status = NFS4_OK; + bool found_pending = false; + struct nfs_open_context *ctx = nfs_file_open_context(dst); + + spin_lock(&server->nfs_client->cl_lock); + list_for_each_entry(copy, &server->nfs_client->pending_cb_stateids, + copies) { + if (memcmp(&res->write_res.stateid, ©->stateid, + NFS4_STATEID_SIZE)) + continue; + found_pending = true; + list_del(©->copies); + break; + } + if (found_pending) { + spin_unlock(&server->nfs_client->cl_lock); + goto out; + } + + copy = kzalloc(sizeof(struct nfs4_copy_state), GFP_NOFS); + if (!copy) { + spin_unlock(&server->nfs_client->cl_lock); + return -ENOMEM; + } + memcpy(©->stateid, &res->write_res.stateid, NFS4_STATEID_SIZE); + init_completion(©->completion); + copy->parent_state = ctx->state; + + list_add_tail(©->copies, &server->ss_copies); + spin_unlock(&server->nfs_client->cl_lock); + + status = wait_for_completion_interruptible(©->completion); + spin_lock(&server->nfs_client->cl_lock); + list_del_init(©->copies); + spin_unlock(&server->nfs_client->cl_lock); + if (status == -ERESTARTSYS) { + goto out_cancel; + } else if (copy->flags) { + status = -EAGAIN; + goto out_cancel; + } +out: + res->write_res.count = copy->count; + memcpy(&res->write_res.verifier, ©->verf, sizeof(copy->verf)); + status = -copy->error; + + kfree(copy); + return status; +out_cancel: + nfs42_do_offload_cancel_async(dst, ©->stateid); + kfree(copy); + return status; +} + +static int process_copy_commit(struct file *dst, loff_t pos_dst, + struct nfs42_copy_res *res) +{ + struct nfs_commitres cres; + int status = -ENOMEM; + + cres.verf = kzalloc(sizeof(struct nfs_writeverf), GFP_NOFS); + if (!cres.verf) + goto out; + + status = nfs4_proc_commit(dst, pos_dst, res->write_res.count, &cres); + if (status) + goto out_free; + if (nfs_write_verifier_cmp(&res->write_res.verifier.verifier, + &cres.verf->verifier)) { + dprintk("commit verf differs from copy verf\n"); + status = -EAGAIN; + } +out_free: + kfree(cres.verf); +out: + return status; +} + static ssize_t _nfs42_proc_copy(struct file *src, struct nfs_lock_context *src_lock, struct file *dst, @@ -168,9 +254,16 @@ static ssize_t _nfs42_proc_copy(struct file *src, if (status) return status; - res->commit_res.verf = kzalloc(sizeof(struct nfs_writeverf), GFP_NOFS); - if (!res->commit_res.verf) - return -ENOMEM; + res->commit_res.verf = NULL; + if (args->sync) { + res->commit_res.verf = + kzalloc(sizeof(struct nfs_writeverf), GFP_NOFS); + if (!res->commit_res.verf) + return -ENOMEM; + } + set_bit(NFS_CLNT_DST_SSC_COPY_STATE, + &dst_lock->open_context->state->flags); + status = nfs4_call_sync(server->client, server, &msg, &args->seq_args, &res->seq_res, 0); if (status == -ENOTSUPP) @@ -178,18 +271,34 @@ static ssize_t _nfs42_proc_copy(struct file *src, if (status) goto out; - if (nfs_write_verifier_cmp(&res->write_res.verifier.verifier, + if (args->sync && + nfs_write_verifier_cmp(&res->write_res.verifier.verifier, &res->commit_res.verf->verifier)) { status = -EAGAIN; goto out; } + if (!res->synchronous) { + status = handle_async_copy(res, server, src, dst, + &args->src_stateid); + if (status) + return status; + } + + if ((!res->synchronous || !args->sync) && + res->write_res.verifier.committed != NFS_FILE_SYNC) { + status = process_copy_commit(dst, pos_dst, res); + if (status) + return status; + } + truncate_pagecache_range(dst_inode, pos_dst, pos_dst + res->write_res.count); status = res->write_res.count; out: - kfree(res->commit_res.verf); + if (args->sync) + kfree(res->commit_res.verf); return status; } @@ -206,6 +315,7 @@ ssize_t nfs42_proc_copy(struct file *src, loff_t pos_src, .dst_fh = NFS_FH(file_inode(dst)), .dst_pos = pos_dst, .count = count, + .sync = false, }; struct nfs42_copy_res res; struct nfs4_exception src_exception = { @@ -247,7 +357,11 @@ ssize_t nfs42_proc_copy(struct file *src, loff_t pos_src, if (err == -ENOTSUPP) { err = -EOPNOTSUPP; break; - } if (err == -EAGAIN) { + } else if (err == -EAGAIN) { + dst_exception.retry = 1; + continue; + } else if (err == -NFS4ERR_OFFLOAD_NO_REQS && !args.sync) { + args.sync = true; dst_exception.retry = 1; continue; } @@ -264,6 +378,89 @@ out_put_src_lock: return err; } +struct nfs42_offloadcancel_data { + struct nfs_server *seq_server; + struct nfs42_offload_status_args args; + struct nfs42_offload_status_res res; +}; + +static void nfs42_offload_cancel_prepare(struct rpc_task *task, void *calldata) +{ + struct nfs42_offloadcancel_data *data = calldata; + + nfs4_setup_sequence(data->seq_server->nfs_client, + &data->args.osa_seq_args, + &data->res.osr_seq_res, task); +} + +static void nfs42_offload_cancel_done(struct rpc_task *task, void *calldata) +{ + struct nfs42_offloadcancel_data *data = calldata; + + nfs41_sequence_done(task, &data->res.osr_seq_res); + if (task->tk_status && + nfs4_async_handle_error(task, data->seq_server, NULL, + NULL) == -EAGAIN) + rpc_restart_call_prepare(task); +} + +static void nfs42_free_offloadcancel_data(void *data) +{ + kfree(data); +} + +static const struct rpc_call_ops nfs42_offload_cancel_ops = { + .rpc_call_prepare = nfs42_offload_cancel_prepare, + .rpc_call_done = nfs42_offload_cancel_done, + .rpc_release = nfs42_free_offloadcancel_data, +}; + +static int nfs42_do_offload_cancel_async(struct file *dst, + nfs4_stateid *stateid) +{ + struct nfs_server *dst_server = NFS_SERVER(file_inode(dst)); + struct nfs42_offloadcancel_data *data = NULL; + struct nfs_open_context *ctx = nfs_file_open_context(dst); + struct rpc_task *task; + struct rpc_message msg = { + .rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_OFFLOAD_CANCEL], + .rpc_cred = ctx->cred, + }; + struct rpc_task_setup task_setup_data = { + .rpc_client = dst_server->client, + .rpc_message = &msg, + .callback_ops = &nfs42_offload_cancel_ops, + .workqueue = nfsiod_workqueue, + .flags = RPC_TASK_ASYNC, + }; + int status; + + if (!(dst_server->caps & NFS_CAP_OFFLOAD_CANCEL)) + return -EOPNOTSUPP; + + data = kzalloc(sizeof(struct nfs42_offloadcancel_data), GFP_NOFS); + if (data == NULL) + return -ENOMEM; + + data->seq_server = dst_server; + data->args.osa_src_fh = NFS_FH(file_inode(dst)); + memcpy(&data->args.osa_stateid, stateid, + sizeof(data->args.osa_stateid)); + msg.rpc_argp = &data->args; + msg.rpc_resp = &data->res; + task_setup_data.callback_data = data; + nfs4_init_sequence(&data->args.osa_seq_args, &data->res.osr_seq_res, + 1, 0); + task = rpc_run_task(&task_setup_data); + if (IS_ERR(task)) + return PTR_ERR(task); + status = rpc_wait_for_completion_task(task); + if (status == -ENOTSUPP) + dst_server->caps &= ~NFS_CAP_OFFLOAD_CANCEL; + rpc_put_task(task); + return status; +} + static loff_t _nfs42_proc_llseek(struct file *filep, struct nfs_lock_context *lock, loff_t offset, int whence) { diff --git a/fs/nfs/nfs42xdr.c b/fs/nfs/nfs42xdr.c index 5966e1e7b1f5..69f72ed2bf87 100644 --- a/fs/nfs/nfs42xdr.c +++ b/fs/nfs/nfs42xdr.c @@ -26,6 +26,9 @@ NFS42_WRITE_RES_SIZE + \ 1 /* cr_consecutive */ + \ 1 /* cr_synchronous */) +#define encode_offload_cancel_maxsz (op_encode_hdr_maxsz + \ + XDR_QUADLEN(NFS4_STATEID_SIZE)) +#define decode_offload_cancel_maxsz (op_decode_hdr_maxsz) #define encode_deallocate_maxsz (op_encode_hdr_maxsz + \ encode_fallocate_maxsz) #define decode_deallocate_maxsz (op_decode_hdr_maxsz) @@ -75,6 +78,12 @@ decode_putfh_maxsz + \ decode_copy_maxsz + \ decode_commit_maxsz) +#define NFS4_enc_offload_cancel_sz (compound_encode_hdr_maxsz + \ + encode_putfh_maxsz + \ + encode_offload_cancel_maxsz) +#define NFS4_dec_offload_cancel_sz (compound_decode_hdr_maxsz + \ + decode_putfh_maxsz + \ + decode_offload_cancel_maxsz) #define NFS4_enc_deallocate_sz (compound_encode_hdr_maxsz + \ encode_putfh_maxsz + \ encode_deallocate_maxsz + \ @@ -141,10 +150,18 @@ static void encode_copy(struct xdr_stream *xdr, encode_uint64(xdr, args->count); encode_uint32(xdr, 1); /* consecutive = true */ - encode_uint32(xdr, 1); /* synchronous = true */ + encode_uint32(xdr, args->sync); encode_uint32(xdr, 0); /* src server list */ } +static void encode_offload_cancel(struct xdr_stream *xdr, + const struct nfs42_offload_status_args *args, + struct compound_hdr *hdr) +{ + encode_op_hdr(xdr, OP_OFFLOAD_CANCEL, decode_offload_cancel_maxsz, hdr); + encode_nfs4_stateid(xdr, &args->osa_stateid); +} + static void encode_deallocate(struct xdr_stream *xdr, const struct nfs42_falloc_args *args, struct compound_hdr *hdr) @@ -256,7 +273,27 @@ static void nfs4_xdr_enc_copy(struct rpc_rqst *req, encode_savefh(xdr, &hdr); encode_putfh(xdr, args->dst_fh, &hdr); encode_copy(xdr, args, &hdr); - encode_copy_commit(xdr, args, &hdr); + if (args->sync) + encode_copy_commit(xdr, args, &hdr); + encode_nops(&hdr); +} + +/* + * Encode OFFLOAD_CANEL request + */ +static void nfs4_xdr_enc_offload_cancel(struct rpc_rqst *req, + struct xdr_stream *xdr, + const void *data) +{ + const struct nfs42_offload_status_args *args = data; + struct compound_hdr hdr = { + .minorversion = nfs4_xdr_minorversion(&args->osa_seq_args), + }; + + encode_compound_hdr(xdr, req, &hdr); + encode_sequence(xdr, &args->osa_seq_args, &hdr); + encode_putfh(xdr, args->osa_src_fh, &hdr); + encode_offload_cancel(xdr, args, &hdr); encode_nops(&hdr); } @@ -353,21 +390,23 @@ static int decode_write_response(struct xdr_stream *xdr, struct nfs42_write_res *res) { __be32 *p; + int status, count; - p = xdr_inline_decode(xdr, 4 + 8 + 4); + p = xdr_inline_decode(xdr, 4); if (unlikely(!p)) goto out_overflow; - - /* - * We never use asynchronous mode, so warn if a server returns - * a stateid. - */ - if (unlikely(*p != 0)) { - pr_err_once("%s: server has set unrequested " - "asynchronous mode\n", __func__); + count = be32_to_cpup(p); + if (count > 1) return -EREMOTEIO; + else if (count == 1) { + status = decode_opaque_fixed(xdr, &res->stateid, + NFS4_STATEID_SIZE); + if (unlikely(status)) + goto out_overflow; } - p++; + p = xdr_inline_decode(xdr, 8 + 4); + if (unlikely(!p)) + goto out_overflow; p = xdr_decode_hyper(p, &res->count); res->verifier.committed = be32_to_cpup(p); return decode_verifier(xdr, &res->verifier.verifier); @@ -413,6 +452,12 @@ static int decode_copy(struct xdr_stream *xdr, struct nfs42_copy_res *res) return decode_copy_requirements(xdr, res); } +static int decode_offload_cancel(struct xdr_stream *xdr, + struct nfs42_offload_status_res *res) +{ + return decode_op_hdr(xdr, OP_OFFLOAD_CANCEL); +} + static int decode_deallocate(struct xdr_stream *xdr, struct nfs42_falloc_res *res) { return decode_op_hdr(xdr, OP_DEALLOCATE); @@ -507,7 +552,34 @@ static int nfs4_xdr_dec_copy(struct rpc_rqst *rqstp, status = decode_copy(xdr, res); if (status) goto out; - status = decode_commit(xdr, &res->commit_res); + if (res->commit_res.verf) + status = decode_commit(xdr, &res->commit_res); +out: + return status; +} + +/* + * Decode OFFLOAD_CANCEL response + */ +static int nfs4_xdr_dec_offload_cancel(struct rpc_rqst *rqstp, + struct xdr_stream *xdr, + void *data) +{ + struct nfs42_offload_status_res *res = data; + struct compound_hdr hdr; + int status; + + status = decode_compound_hdr(xdr, &hdr); + if (status) + goto out; + status = decode_sequence(xdr, &res->osr_seq_res, rqstp); + if (status) + goto out; + status = decode_putfh(xdr); + if (status) + goto out; + status = decode_offload_cancel(xdr, res); + out: return status; } diff --git a/fs/nfs/nfs4_fs.h b/fs/nfs/nfs4_fs.h index 51beb6e38c90..3a6904173214 100644 --- a/fs/nfs/nfs4_fs.h +++ b/fs/nfs/nfs4_fs.h @@ -163,6 +163,9 @@ enum { NFS_STATE_RECOVERY_FAILED, /* OPEN stateid state recovery failed */ NFS_STATE_MAY_NOTIFY_LOCK, /* server may CB_NOTIFY_LOCK */ NFS_STATE_CHANGE_WAIT, /* A state changing operation is outstanding */ +#ifdef CONFIG_NFS_V4_2 + NFS_CLNT_DST_SSC_COPY_STATE, /* dst server open state on client*/ +#endif /* CONFIG_NFS_V4_2 */ }; struct nfs4_state { @@ -273,6 +276,9 @@ int nfs4_replace_transport(struct nfs_server *server, /* nfs4proc.c */ extern int nfs4_handle_exception(struct nfs_server *, int, struct nfs4_exception *); +extern int nfs4_async_handle_error(struct rpc_task *task, + struct nfs_server *server, + struct nfs4_state *state, long *timeout); extern int nfs4_call_sync(struct rpc_clnt *, struct nfs_server *, struct rpc_message *, struct nfs4_sequence_args *, struct nfs4_sequence_res *, int); @@ -505,7 +511,7 @@ extern int nfs4_sequence_done(struct rpc_task *task, struct nfs4_sequence_res *res); extern void nfs4_free_lock_state(struct nfs_server *server, struct nfs4_lock_state *lsp); - +extern int nfs4_proc_commit(struct file *dst, __u64 offset, __u32 count, struct nfs_commitres *res); extern const nfs4_stateid zero_stateid; extern const nfs4_stateid invalid_stateid; diff --git a/fs/nfs/nfs4client.c b/fs/nfs/nfs4client.c index 979631411a0e..146e30862234 100644 --- a/fs/nfs/nfs4client.c +++ b/fs/nfs/nfs4client.c @@ -156,9 +156,23 @@ nfs4_shutdown_ds_clients(struct nfs_client *clp) } } +static void +nfs4_cleanup_callback(struct nfs_client *clp) +{ + struct nfs4_copy_state *cp_state; + + while (!list_empty(&clp->pending_cb_stateids)) { + cp_state = list_entry(clp->pending_cb_stateids.next, + struct nfs4_copy_state, copies); + list_del(&cp_state->copies); + kfree(cp_state); + } +} + void nfs41_shutdown_client(struct nfs_client *clp) { if (nfs4_has_session(clp)) { + nfs4_cleanup_callback(clp); nfs4_shutdown_ds_clients(clp); nfs4_destroy_session(clp->cl_session); nfs4_destroy_clientid(clp); @@ -202,6 +216,7 @@ struct nfs_client *nfs4_alloc_client(const struct nfs_client_initdata *cl_init) #if IS_ENABLED(CONFIG_NFS_V4_1) init_waitqueue_head(&clp->cl_lock_waitq); #endif + INIT_LIST_HEAD(&clp->pending_cb_stateids); return clp; error: @@ -1127,7 +1142,7 @@ struct nfs_server *nfs4_create_referral_server(struct nfs_clone_mount *data, nfs_server_copy_userdata(server, parent_server); /* Get a client representation */ -#ifdef CONFIG_SUNRPC_XPRT_RDMA +#if IS_ENABLED(CONFIG_SUNRPC_XPRT_RDMA) rpc_set_port(data->addr, NFS_RDMA_PORT); error = nfs4_set_client(server, data->hostname, data->addr, @@ -1139,7 +1154,7 @@ struct nfs_server *nfs4_create_referral_server(struct nfs_clone_mount *data, parent_client->cl_net); if (!error) goto init_server; -#endif /* CONFIG_SUNRPC_XPRT_RDMA */ +#endif /* IS_ENABLED(CONFIG_SUNRPC_XPRT_RDMA) */ rpc_set_port(data->addr, NFS_PORT); error = nfs4_set_client(server, data->hostname, @@ -1153,7 +1168,7 @@ struct nfs_server *nfs4_create_referral_server(struct nfs_clone_mount *data, if (error < 0) goto error; -#ifdef CONFIG_SUNRPC_XPRT_RDMA +#if IS_ENABLED(CONFIG_SUNRPC_XPRT_RDMA) init_server: #endif error = nfs_init_server_rpcclient(server, parent_server->client->cl_timeout, data->authflavor); diff --git a/fs/nfs/nfs4file.c b/fs/nfs/nfs4file.c index 6b3b372b59b9..4288a6ecaf75 100644 --- a/fs/nfs/nfs4file.c +++ b/fs/nfs/nfs4file.c @@ -133,10 +133,15 @@ static ssize_t nfs4_copy_file_range(struct file *file_in, loff_t pos_in, struct file *file_out, loff_t pos_out, size_t count, unsigned int flags) { + ssize_t ret; + if (file_inode(file_in) == file_inode(file_out)) return -EINVAL; - - return nfs42_proc_copy(file_in, pos_in, file_out, pos_out, count); +retry: + ret = nfs42_proc_copy(file_in, pos_in, file_out, pos_out, count); + if (ret == -EAGAIN) + goto retry; + return ret; } static loff_t nfs4_file_llseek(struct file *filep, loff_t offset, int whence) @@ -149,6 +154,7 @@ static loff_t nfs4_file_llseek(struct file *filep, loff_t offset, int whence) ret = nfs42_proc_llseek(filep, offset, whence); if (ret != -ENOTSUPP) return ret; + /* Fall through */ default: return nfs_file_llseek(filep, offset, whence); } diff --git a/fs/nfs/nfs4idmap.c b/fs/nfs/nfs4idmap.c index b6f9d84ba19b..3f23b6840547 100644 --- a/fs/nfs/nfs4idmap.c +++ b/fs/nfs/nfs4idmap.c @@ -506,6 +506,7 @@ static int nfs_idmap_prepare_message(char *desc, struct idmap *idmap, switch (token) { case Opt_find_uid: im->im_type = IDMAP_TYPE_USER; + /* Fall through */ case Opt_find_gid: im->im_conv = IDMAP_CONV_NAMETOID; ret = match_strlcpy(im->im_name, &substr, IDMAP_NAMESZ); @@ -513,9 +514,12 @@ static int nfs_idmap_prepare_message(char *desc, struct idmap *idmap, case Opt_find_user: im->im_type = IDMAP_TYPE_USER; + /* Fall through */ case Opt_find_group: im->im_conv = IDMAP_CONV_IDTONAME; ret = match_int(&substr, &im->im_id); + if (ret) + goto out; break; default: diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index b790976d3913..34830f6457ea 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -449,6 +449,7 @@ static int nfs4_do_handle_exception(struct nfs_server *server, stateid); goto wait_on_recovery; } + /* Fall through */ case -NFS4ERR_OPENMODE: if (inode) { int err; @@ -501,8 +502,10 @@ static int nfs4_do_handle_exception(struct nfs_server *server, ret = -EBUSY; break; } + /* Fall through */ case -NFS4ERR_DELAY: nfs_inc_server_stats(server, NFSIOS_DELAY); + /* Fall through */ case -NFS4ERR_GRACE: case -NFS4ERR_LAYOUTTRYLATER: case -NFS4ERR_RECALLCONFLICT: @@ -581,12 +584,19 @@ nfs4_async_handle_exception(struct rpc_task *task, struct nfs_server *server, ret = -EIO; return ret; out_retry: - if (ret == 0) + if (ret == 0) { exception->retry = 1; + /* + * For NFS4ERR_MOVED, the client transport will need to + * be recomputed after migration recovery has completed. + */ + if (errorcode == -NFS4ERR_MOVED) + rpc_task_release_transport(task); + } return ret; } -static int +int nfs4_async_handle_error(struct rpc_task *task, struct nfs_server *server, struct nfs4_state *state, long *timeout) { @@ -1071,15 +1081,30 @@ int nfs4_call_sync(struct rpc_clnt *clnt, return nfs4_call_sync_sequence(clnt, server, msg, args, res); } -static void update_changeattr(struct inode *dir, struct nfs4_change_info *cinfo, - unsigned long timestamp) +static void +nfs4_inc_nlink_locked(struct inode *inode) +{ + NFS_I(inode)->cache_validity |= NFS_INO_INVALID_OTHER; + inc_nlink(inode); +} + +static void +nfs4_dec_nlink_locked(struct inode *inode) +{ + NFS_I(inode)->cache_validity |= NFS_INO_INVALID_OTHER; + drop_nlink(inode); +} + +static void +update_changeattr_locked(struct inode *dir, struct nfs4_change_info *cinfo, + unsigned long timestamp, unsigned long cache_validity) { struct nfs_inode *nfsi = NFS_I(dir); - spin_lock(&dir->i_lock); nfsi->cache_validity |= NFS_INO_INVALID_CTIME | NFS_INO_INVALID_MTIME - | NFS_INO_INVALID_DATA; + | NFS_INO_INVALID_DATA + | cache_validity; if (cinfo->atomic && cinfo->before == inode_peek_iversion_raw(dir)) { nfsi->cache_validity &= ~NFS_INO_REVAL_PAGECACHE; nfsi->attrtimeo_timestamp = jiffies; @@ -1092,7 +1117,16 @@ static void update_changeattr(struct inode *dir, struct nfs4_change_info *cinfo, inode_set_iversion_raw(dir, cinfo->after); nfsi->read_cache_jiffies = timestamp; nfsi->attr_gencount = nfs_inc_attr_generation_counter(); + nfsi->cache_validity &= ~NFS_INO_INVALID_CHANGE; nfs_fscache_invalidate(dir); +} + +static void +update_changeattr(struct inode *dir, struct nfs4_change_info *cinfo, + unsigned long timestamp, unsigned long cache_validity) +{ + spin_lock(&dir->i_lock); + update_changeattr_locked(dir, cinfo, timestamp, cache_validity); spin_unlock(&dir->i_lock); } @@ -1354,6 +1388,7 @@ static int can_open_delegated(struct nfs_delegation *delegation, fmode_t fmode, case NFS4_OPEN_CLAIM_PREVIOUS: if (!test_bit(NFS_DELEGATION_NEED_RECLAIM, &delegation->flags)) break; + /* Fall through */ default: return 0; } @@ -1773,6 +1808,10 @@ nfs4_opendata_check_deleg(struct nfs4_opendata *data, struct nfs4_state *state) data->o_res.delegation_type, &data->o_res.delegation, data->o_res.pagemod_limit); + + if (data->o_res.do_recall) + nfs_async_inode_return_delegation(state->inode, + &data->o_res.delegation); } /* @@ -2119,6 +2158,7 @@ int nfs4_open_delegation_recall(struct nfs_open_context *ctx, err = nfs4_open_recover_helper(opendata, FMODE_WRITE); if (err) break; + /* Fall through */ case FMODE_READ: err = nfs4_open_recover_helper(opendata, FMODE_READ); } @@ -2248,6 +2288,7 @@ static void nfs4_open_prepare(struct rpc_task *task, void *calldata) case NFS4_OPEN_CLAIM_DELEG_CUR_FH: case NFS4_OPEN_CLAIM_DELEG_PREV_FH: data->o_arg.open_bitmap = &nfs4_open_noattr_bitmap[0]; + /* Fall through */ case NFS4_OPEN_CLAIM_FH: task->tk_msg.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_OPEN_NOATTR]; } @@ -2481,7 +2522,7 @@ static int _nfs4_proc_open(struct nfs4_opendata *data, if (data->file_created || inode_peek_iversion_raw(dir) != o_res->cinfo.after) update_changeattr(dir, &o_res->cinfo, - o_res->f_attr->time_start); + o_res->f_attr->time_start, 0); } if ((o_res->rflags & NFS4_OPEN_RESULT_LOCKTYPE_POSIX) == 0) server->caps &= ~NFS_CAP_POSIX_LOCK; @@ -2843,6 +2884,9 @@ static int _nfs4_open_and_get_state(struct nfs4_opendata *opendata, nfs_save_change_attribute(d_inode(opendata->dir))); } + /* Parse layoutget results before we check for access */ + pnfs_parse_lgopen(state->inode, opendata->lgp, ctx); + ret = nfs4_opendata_access(sp->so_cred, opendata, state, fmode, flags); if (ret != 0) goto out; @@ -2851,8 +2895,6 @@ static int _nfs4_open_and_get_state(struct nfs4_opendata *opendata, nfs_inode_attach_open_context(ctx); if (read_seqcount_retry(&sp->so_reclaim_seqcount, seq)) nfs4_schedule_stateid_recovery(server, state); - else - pnfs_parse_lgopen(state->inode, opendata->lgp, ctx); } out: @@ -3220,7 +3262,8 @@ static void nfs4_close_done(struct rpc_task *task, void *data) calldata->res.lr_res = NULL; break; case -NFS4ERR_OLD_STATEID: - if (nfs4_refresh_layout_stateid(&calldata->arg.lr_args->stateid, + if (nfs4_layoutreturn_refresh_stateid(&calldata->arg.lr_args->stateid, + &calldata->arg.lr_args->range, calldata->inode)) goto lr_restart; /* Fallthrough */ @@ -4236,7 +4279,8 @@ out: return status; } -static int _nfs4_proc_remove(struct inode *dir, const struct qstr *name) +static int +_nfs4_proc_remove(struct inode *dir, const struct qstr *name, u32 ftype) { struct nfs_server *server = NFS_SERVER(dir); struct nfs_removeargs args = { @@ -4255,8 +4299,14 @@ static int _nfs4_proc_remove(struct inode *dir, const struct qstr *name) int status; status = nfs4_call_sync(server->client, server, &msg, &args.seq_args, &res.seq_res, 1); - if (status == 0) - update_changeattr(dir, &res.cinfo, timestamp); + if (status == 0) { + spin_lock(&dir->i_lock); + update_changeattr_locked(dir, &res.cinfo, timestamp, 0); + /* Removing a directory decrements nlink in the parent */ + if (ftype == NF4DIR && dir->i_nlink > 2) + nfs4_dec_nlink_locked(dir); + spin_unlock(&dir->i_lock); + } return status; } @@ -4273,7 +4323,7 @@ static int nfs4_proc_remove(struct inode *dir, struct dentry *dentry) nfs4_inode_make_writeable(inode); } do { - err = _nfs4_proc_remove(dir, &dentry->d_name); + err = _nfs4_proc_remove(dir, &dentry->d_name, NF4REG); trace_nfs4_remove(dir, &dentry->d_name, err); err = nfs4_handle_exception(NFS_SERVER(dir), err, &exception); @@ -4287,7 +4337,7 @@ static int nfs4_proc_rmdir(struct inode *dir, const struct qstr *name) int err; do { - err = _nfs4_proc_remove(dir, name); + err = _nfs4_proc_remove(dir, name, NF4DIR); trace_nfs4_remove(dir, name, err); err = nfs4_handle_exception(NFS_SERVER(dir), err, &exception); @@ -4331,7 +4381,8 @@ static int nfs4_proc_unlink_done(struct rpc_task *task, struct inode *dir) &data->timeout) == -EAGAIN) return 0; if (task->tk_status == 0) - update_changeattr(dir, &res->cinfo, res->dir_attr->time_start); + update_changeattr(dir, &res->cinfo, + res->dir_attr->time_start, 0); return 1; } @@ -4373,9 +4424,18 @@ static int nfs4_proc_rename_done(struct rpc_task *task, struct inode *old_dir, return 0; if (task->tk_status == 0) { - update_changeattr(old_dir, &res->old_cinfo, res->old_fattr->time_start); - if (new_dir != old_dir) - update_changeattr(new_dir, &res->new_cinfo, res->new_fattr->time_start); + if (new_dir != old_dir) { + /* Note: If we moved a directory, nlink will change */ + update_changeattr(old_dir, &res->old_cinfo, + res->old_fattr->time_start, + NFS_INO_INVALID_OTHER); + update_changeattr(new_dir, &res->new_cinfo, + res->new_fattr->time_start, + NFS_INO_INVALID_OTHER); + } else + update_changeattr(old_dir, &res->old_cinfo, + res->old_fattr->time_start, + 0); } return 1; } @@ -4416,7 +4476,7 @@ static int _nfs4_proc_link(struct inode *inode, struct inode *dir, const struct status = nfs4_call_sync(server->client, server, &msg, &arg.seq_args, &res.seq_res, 1); if (!status) { - update_changeattr(dir, &res.cinfo, res.fattr->time_start); + update_changeattr(dir, &res.cinfo, res.fattr->time_start, 0); status = nfs_post_op_update_inode(inode, res.fattr); if (!status) nfs_setsecurity(inode, res.fattr, res.label); @@ -4491,8 +4551,13 @@ static int nfs4_do_create(struct inode *dir, struct dentry *dentry, struct nfs4_ int status = nfs4_call_sync(NFS_SERVER(dir)->client, NFS_SERVER(dir), &data->msg, &data->arg.seq_args, &data->res.seq_res, 1); if (status == 0) { - update_changeattr(dir, &data->res.dir_cinfo, - data->res.fattr->time_start); + spin_lock(&dir->i_lock); + update_changeattr_locked(dir, &data->res.dir_cinfo, + data->res.fattr->time_start, 0); + /* Creating a directory bumps nlink in the parent */ + if (data->arg.ftype == NF4DIR) + nfs4_inc_nlink_locked(dir); + spin_unlock(&dir->i_lock); status = nfs_instantiate(dentry, data->res.fh, data->res.fattr, data->res.label); } return status; @@ -5073,6 +5138,40 @@ static void nfs4_proc_commit_setup(struct nfs_commit_data *data, struct rpc_mess nfs4_state_protect(server->nfs_client, NFS_SP4_MACH_CRED_COMMIT, clnt, msg); } +static int _nfs4_proc_commit(struct file *dst, struct nfs_commitargs *args, + struct nfs_commitres *res) +{ + struct inode *dst_inode = file_inode(dst); + struct nfs_server *server = NFS_SERVER(dst_inode); + struct rpc_message msg = { + .rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_COMMIT], + .rpc_argp = args, + .rpc_resp = res, + }; + + args->fh = NFS_FH(dst_inode); + return nfs4_call_sync(server->client, server, &msg, + &args->seq_args, &res->seq_res, 1); +} + +int nfs4_proc_commit(struct file *dst, __u64 offset, __u32 count, struct nfs_commitres *res) +{ + struct nfs_commitargs args = { + .offset = offset, + .count = count, + }; + struct nfs_server *dst_server = NFS_SERVER(file_inode(dst)); + struct nfs4_exception exception = { }; + int status; + + do { + status = _nfs4_proc_commit(dst, &args, res); + status = nfs4_handle_exception(dst_server, status, &exception); + } while (exception.retry); + + return status; +} + struct nfs4_renewdata { struct nfs_client *client; unsigned long timestamp; @@ -5902,7 +6001,8 @@ static void nfs4_delegreturn_done(struct rpc_task *task, void *calldata) data->res.lr_res = NULL; break; case -NFS4ERR_OLD_STATEID: - if (nfs4_refresh_layout_stateid(&data->args.lr_args->stateid, + if (nfs4_layoutreturn_refresh_stateid(&data->args.lr_args->stateid, + &data->args.lr_args->range, data->inode)) goto lr_restart; /* Fallthrough */ @@ -6209,11 +6309,13 @@ static void nfs4_locku_done(struct rpc_task *task, void *data) if (nfs4_update_lock_stateid(calldata->lsp, &calldata->res.stateid)) break; + /* Fall through */ case -NFS4ERR_ADMIN_REVOKED: case -NFS4ERR_EXPIRED: nfs4_free_revoked_stateid(calldata->server, &calldata->arg.stateid, task->tk_msg.rpc_cred); + /* Fall through */ case -NFS4ERR_BAD_STATEID: case -NFS4ERR_OLD_STATEID: case -NFS4ERR_STALE_STATEID: @@ -7727,7 +7829,7 @@ static int nfs4_sp4_select_mode(struct nfs_client *clp, } out: clp->cl_sp4_flags = flags; - return 0; + return ret; } struct nfs41_exchange_id_data { @@ -8168,7 +8270,7 @@ static void nfs4_init_channel_attrs(struct nfs41_create_session_args *args, args->bc_attrs.max_resp_sz = max_bc_payload; args->bc_attrs.max_resp_sz_cached = 0; args->bc_attrs.max_ops = NFS4_MAX_BACK_CHANNEL_OPS; - args->bc_attrs.max_reqs = min_t(unsigned short, max_session_cb_slots, 1); + args->bc_attrs.max_reqs = max_t(unsigned short, max_session_cb_slots, 1); dprintk("%s: Back Channel : max_rqst_sz=%u max_resp_sz=%u " "max_resp_sz_cached=%u max_ops=%u max_reqs=%u\n", @@ -8851,7 +8953,8 @@ static void nfs4_layoutreturn_done(struct rpc_task *task, void *calldata) server = NFS_SERVER(lrp->args.inode); switch (task->tk_status) { case -NFS4ERR_OLD_STATEID: - if (nfs4_refresh_layout_stateid(&lrp->args.stateid, + if (nfs4_layoutreturn_refresh_stateid(&lrp->args.stateid, + &lrp->args.range, lrp->args.inode)) goto out_restart; /* Fallthrough */ @@ -9554,6 +9657,7 @@ static const struct nfs4_minor_version_ops nfs_v4_2_minor_ops = { | NFS_CAP_LGOPEN | NFS_CAP_ALLOCATE | NFS_CAP_COPY + | NFS_CAP_OFFLOAD_CANCEL | NFS_CAP_DEALLOCATE | NFS_CAP_SEEK | NFS_CAP_LAYOUTSTATS diff --git a/fs/nfs/nfs4state.c b/fs/nfs/nfs4state.c index 2bf2eaa08ca7..3df0eb52da1c 100644 --- a/fs/nfs/nfs4state.c +++ b/fs/nfs/nfs4state.c @@ -274,7 +274,7 @@ static int nfs4_drain_slot_tbl(struct nfs4_slot_table *tbl) static int nfs4_begin_drain_session(struct nfs_client *clp) { struct nfs4_session *ses = clp->cl_session; - int ret = 0; + int ret; if (clp->cl_slot_tbl) return nfs4_drain_slot_tbl(clp->cl_slot_tbl); @@ -1525,6 +1525,7 @@ restart: default: pr_err("NFS: %s: unhandled error %d\n", __func__, status); + /* Fall through */ case -ENOMEM: case -NFS4ERR_DENIED: case -NFS4ERR_RECLAIM_BAD: @@ -1588,6 +1589,22 @@ restart: } clear_bit(NFS_STATE_RECLAIM_NOGRACE, &state->flags); +#ifdef CONFIG_NFS_V4_2 + if (test_bit(NFS_CLNT_DST_SSC_COPY_STATE, &state->flags)) { + struct nfs4_copy_state *copy; + + spin_lock(&sp->so_server->nfs_client->cl_lock); + list_for_each_entry(copy, &sp->so_server->ss_copies, copies) { + if (memcmp(&state->stateid.other, ©->parent_state->stateid.other, NFS4_STATEID_SIZE)) + continue; + copy->flags = 1; + complete(©->completion); + printk("AGLO: server rebooted waking up the copy\n"); + break; + } + spin_unlock(&sp->so_server->nfs_client->cl_lock); + } +#endif /* CONFIG_NFS_V4_2 */ nfs4_put_open_state(state); spin_lock(&sp->so_lock); goto restart; @@ -1597,6 +1614,7 @@ restart: default: printk(KERN_ERR "NFS: %s: unhandled error %d\n", __func__, status); + /* Fall through */ case -ENOENT: case -ENOMEM: case -EACCES: @@ -1608,6 +1626,7 @@ restart: break; case -EAGAIN: ssleep(1); + /* Fall through */ case -NFS4ERR_ADMIN_REVOKED: case -NFS4ERR_STALE_STATEID: case -NFS4ERR_OLD_STATEID: @@ -1939,7 +1958,9 @@ static int nfs4_establish_lease(struct nfs_client *clp) clp->cl_mvops->reboot_recovery_ops; int status; - nfs4_begin_drain_session(clp); + status = nfs4_begin_drain_session(clp); + if (status != 0) + return status; cred = nfs4_get_clid_cred(clp); if (cred == NULL) return -ENOENT; @@ -2027,7 +2048,9 @@ static int nfs4_try_migration(struct nfs_server *server, struct rpc_cred *cred) goto out; } - nfs4_begin_drain_session(clp); + status = nfs4_begin_drain_session(clp); + if (status != 0) + return status; status = nfs4_replace_transport(server, locations); if (status != 0) { @@ -2190,9 +2213,11 @@ again: case -ETIMEDOUT: if (clnt->cl_softrtry) break; + /* Fall through */ case -NFS4ERR_DELAY: case -EAGAIN: ssleep(1); + /* Fall through */ case -NFS4ERR_STALE_CLIENTID: dprintk("NFS: %s after status %d, retrying\n", __func__, status); @@ -2204,6 +2229,7 @@ again: } if (clnt->cl_auth->au_flavor == RPC_AUTH_UNIX) break; + /* Fall through */ case -NFS4ERR_CLID_INUSE: case -NFS4ERR_WRONGSEC: /* No point in retrying if we already used RPC_AUTH_UNIX */ @@ -2374,7 +2400,9 @@ static int nfs4_reset_session(struct nfs_client *clp) if (!nfs4_has_session(clp)) return 0; - nfs4_begin_drain_session(clp); + status = nfs4_begin_drain_session(clp); + if (status != 0) + return status; cred = nfs4_get_clid_cred(clp); status = nfs4_proc_destroy_session(clp->cl_session, cred); switch (status) { @@ -2417,7 +2445,9 @@ static int nfs4_bind_conn_to_session(struct nfs_client *clp) if (!nfs4_has_session(clp)) return 0; - nfs4_begin_drain_session(clp); + ret = nfs4_begin_drain_session(clp); + if (ret != 0) + return ret; cred = nfs4_get_clid_cred(clp); ret = nfs4_proc_bind_conn_to_session(clp, cred); if (cred) diff --git a/fs/nfs/nfs4xdr.c b/fs/nfs/nfs4xdr.c index cd41d2577a04..b7bde12d8cd5 100644 --- a/fs/nfs/nfs4xdr.c +++ b/fs/nfs/nfs4xdr.c @@ -7789,6 +7789,7 @@ const struct rpc_procinfo nfs4_procedures[] = { PROC42(LAYOUTSTATS, enc_layoutstats, dec_layoutstats), PROC42(CLONE, enc_clone, dec_clone), PROC42(COPY, enc_copy, dec_copy), + PROC42(OFFLOAD_CANCEL, enc_offload_cancel, dec_offload_cancel), PROC(LOOKUPP, enc_lookupp, dec_lookupp), }; diff --git a/fs/nfs/pagelist.c b/fs/nfs/pagelist.c index 67d19cd92e44..bb5476a6d264 100644 --- a/fs/nfs/pagelist.c +++ b/fs/nfs/pagelist.c @@ -561,6 +561,7 @@ static void nfs_pgio_rpcsetup(struct nfs_pgio_header *hdr, case FLUSH_COND_STABLE: if (nfs_reqs_to_commit(cinfo)) break; + /* fall through */ default: hdr->args.stable = NFS_FILE_SYNC; } diff --git a/fs/nfs/pnfs.c b/fs/nfs/pnfs.c index bcc3addec3c5..e8f232de484f 100644 --- a/fs/nfs/pnfs.c +++ b/fs/nfs/pnfs.c @@ -361,18 +361,32 @@ pnfs_clear_lseg_state(struct pnfs_layout_segment *lseg, /* * Update the seqid of a layout stateid */ -bool nfs4_refresh_layout_stateid(nfs4_stateid *dst, struct inode *inode) +bool nfs4_layoutreturn_refresh_stateid(nfs4_stateid *dst, + struct pnfs_layout_range *dst_range, + struct inode *inode) { struct pnfs_layout_hdr *lo; + struct pnfs_layout_range range = { + .iomode = IOMODE_ANY, + .offset = 0, + .length = NFS4_MAX_UINT64, + }; bool ret = false; + LIST_HEAD(head); + int err; spin_lock(&inode->i_lock); lo = NFS_I(inode)->layout; if (lo && nfs4_stateid_match_other(dst, &lo->plh_stateid)) { - dst->seqid = lo->plh_stateid.seqid; - ret = true; + err = pnfs_mark_matching_lsegs_return(lo, &head, &range, 0); + if (err != -EBUSY) { + dst->seqid = lo->plh_stateid.seqid; + *dst_range = range; + ret = true; + } } spin_unlock(&inode->i_lock); + pnfs_free_lseg_list(&head); return ret; } @@ -1018,7 +1032,6 @@ pnfs_alloc_init_layoutget_args(struct inode *ino, nfs4_stateid_copy(&lgp->args.stateid, stateid); lgp->gfp_flags = gfp_flags; lgp->cred = get_rpccred(ctx->cred); - lgp->callback_count = raw_seqcount_begin(&server->nfs_client->cl_callback_count); return lgp; } @@ -1160,12 +1173,21 @@ static bool pnfs_layout_need_return(struct pnfs_layout_hdr *lo) { struct pnfs_layout_segment *s; + enum pnfs_iomode iomode; + u32 seq; if (!test_bit(NFS_LAYOUT_RETURN_REQUESTED, &lo->plh_flags)) return false; - /* Defer layoutreturn until all lsegs are done */ + seq = lo->plh_return_seq; + iomode = lo->plh_return_iomode; + + /* Defer layoutreturn until all recalled lsegs are done */ list_for_each_entry(s, &lo->plh_segs, pls_list) { + if (seq && pnfs_seqid_is_newer(s->pls_seq, seq)) + continue; + if (iomode != IOMODE_ANY && s->pls_range.iomode != iomode) + continue; if (test_bit(NFS_LSEG_LAYOUTRETURN, &s->pls_flags)) return false; } @@ -1609,7 +1631,7 @@ pnfs_lseg_range_match(const struct pnfs_layout_range *ls_range, (range->iomode != ls_range->iomode && strict_iomode) || !pnfs_lseg_range_intersecting(ls_range, range)) - return 0; + return false; /* range1 covers only the first byte in the range */ range1 = *range; @@ -1631,7 +1653,6 @@ pnfs_find_lseg(struct pnfs_layout_hdr *lo, list_for_each_entry(lseg, &lo->plh_segs, pls_list) { if (test_bit(NFS_LSEG_VALID, &lseg->pls_flags) && - !test_bit(NFS_LSEG_LAYOUTRETURN, &lseg->pls_flags) && pnfs_lseg_range_match(&lseg->pls_range, range, strict_iomode)) { ret = pnfs_get_lseg(lseg); @@ -1731,6 +1752,17 @@ static bool pnfs_prepare_to_retry_layoutget(struct pnfs_layout_hdr *lo) TASK_UNINTERRUPTIBLE); } +static void nfs_layoutget_begin(struct pnfs_layout_hdr *lo) +{ + atomic_inc(&lo->plh_outstanding); +} + +static void nfs_layoutget_end(struct pnfs_layout_hdr *lo) +{ + if (atomic_dec_and_test(&lo->plh_outstanding)) + wake_up_var(&lo->plh_outstanding); +} + static void pnfs_clear_first_layoutget(struct pnfs_layout_hdr *lo) { unsigned long *bitlock = &lo->plh_flags; @@ -1791,12 +1823,6 @@ pnfs_update_layout(struct inode *ino, goto out; } - if (iomode == IOMODE_READ && i_size_read(ino) == 0) { - trace_pnfs_update_layout(ino, pos, count, iomode, lo, lseg, - PNFS_UPDATE_LAYOUT_RD_ZEROLEN); - goto out; - } - if (pnfs_within_mdsthreshold(ctx, ino, iomode)) { trace_pnfs_update_layout(ino, pos, count, iomode, lo, lseg, PNFS_UPDATE_LAYOUT_MDSTHRESH); @@ -1830,6 +1856,21 @@ lookup_again: goto out_unlock; } + /* + * If the layout segment list is empty, but there are outstanding + * layoutget calls, then they might be subject to a layoutrecall. + */ + if (list_empty(&lo->plh_segs) && + atomic_read(&lo->plh_outstanding) != 0) { + spin_unlock(&ino->i_lock); + if (wait_var_event_killable(&lo->plh_outstanding, + atomic_read(&lo->plh_outstanding) == 0 + || !list_empty(&lo->plh_segs))) + goto out_put_layout_hdr; + pnfs_put_layout_hdr(lo); + goto lookup_again; + } + lseg = pnfs_find_lseg(lo, &arg, strict_iomode); if (lseg) { trace_pnfs_update_layout(ino, pos, count, iomode, lo, lseg, @@ -1903,7 +1944,7 @@ lookup_again: PNFS_UPDATE_LAYOUT_BLOCKED); goto out_unlock; } - atomic_inc(&lo->plh_outstanding); + nfs_layoutget_begin(lo); spin_unlock(&ino->i_lock); _add_to_server_list(lo, server); @@ -1920,14 +1961,14 @@ lookup_again: if (!lgp) { trace_pnfs_update_layout(ino, pos, count, iomode, lo, NULL, PNFS_UPDATE_LAYOUT_NOMEM); - atomic_dec(&lo->plh_outstanding); + nfs_layoutget_end(lo); goto out_put_layout_hdr; } lseg = nfs4_proc_layoutget(lgp, &timeout); trace_pnfs_update_layout(ino, pos, count, iomode, lo, lseg, PNFS_UPDATE_LAYOUT_SEND_LAYOUTGET); - atomic_dec(&lo->plh_outstanding); + nfs_layoutget_end(lo); if (IS_ERR(lseg)) { switch(PTR_ERR(lseg)) { case -EBUSY: @@ -1935,15 +1976,6 @@ lookup_again: lseg = NULL; break; case -ERECALLCONFLICT: - /* Huh? We hold no layouts, how is there a recall? */ - if (first) { - lseg = NULL; - break; - } - /* Destroy the existing layout and start over */ - if (time_after(jiffies, giveup)) - pnfs_destroy_layout(NFS_I(ino)); - /* Fallthrough */ case -EAGAIN: break; default: @@ -2022,7 +2054,7 @@ _pnfs_grab_empty_layout(struct inode *ino, struct nfs_open_context *ctx) goto out_unlock; if (test_and_set_bit(NFS_LAYOUT_FIRST_LAYOUTGET, &lo->plh_flags)) goto out_unlock; - atomic_inc(&lo->plh_outstanding); + nfs_layoutget_begin(lo); spin_unlock(&ino->i_lock); _add_to_server_list(lo, NFS_SERVER(ino)); return lo; @@ -2146,9 +2178,6 @@ void pnfs_parse_lgopen(struct inode *ino, struct nfs4_layoutget *lgp, } else lo = NFS_I(lgp->args.inode)->layout; - if (read_seqcount_retry(&srv->nfs_client->cl_callback_count, - lgp->callback_count)) - return; lseg = pnfs_layout_process(lgp); if (!IS_ERR(lseg)) { iomode = lgp->args.range.iomode; @@ -2163,8 +2192,8 @@ void nfs4_lgopen_release(struct nfs4_layoutget *lgp) struct inode *inode = lgp->args.inode; if (inode) { struct pnfs_layout_hdr *lo = NFS_I(inode)->layout; - atomic_dec(&lo->plh_outstanding); pnfs_clear_first_layoutget(lo); + nfs_layoutget_end(lo); } pnfs_layoutget_free(lgp); } @@ -2238,15 +2267,31 @@ out_forget: return ERR_PTR(-EAGAIN); } +static int +mark_lseg_invalid_or_return(struct pnfs_layout_segment *lseg, + struct list_head *tmp_list) +{ + if (!mark_lseg_invalid(lseg, tmp_list)) + return 0; + pnfs_cache_lseg_for_layoutreturn(lseg->pls_layout, lseg); + return 1; +} + /** * pnfs_mark_matching_lsegs_return - Free or return matching layout segments * @lo: pointer to layout header * @tmp_list: list header to be used with pnfs_free_lseg_list() * @return_range: describe layout segment ranges to be returned + * @seq: stateid seqid to match * * This function is mainly intended for use by layoutrecall. It attempts * to free the layout segment immediately, or else to mark it for return * as soon as its reference count drops to zero. + * + * Returns + * - 0: a layoutreturn needs to be scheduled. + * - EBUSY: there are layout segment that are still in use. + * - ENOENT: there are no layout segments that need to be returned. */ int pnfs_mark_matching_lsegs_return(struct pnfs_layout_hdr *lo, @@ -2259,9 +2304,6 @@ pnfs_mark_matching_lsegs_return(struct pnfs_layout_hdr *lo, dprintk("%s:Begin lo %p\n", __func__, lo); - if (list_empty(&lo->plh_segs)) - return 0; - assert_spin_locked(&lo->plh_inode->i_lock); list_for_each_entry_safe(lseg, next, &lo->plh_segs, pls_list) @@ -2271,16 +2313,23 @@ pnfs_mark_matching_lsegs_return(struct pnfs_layout_hdr *lo, lseg, lseg->pls_range.iomode, lseg->pls_range.offset, lseg->pls_range.length); - if (mark_lseg_invalid(lseg, tmp_list)) + if (mark_lseg_invalid_or_return(lseg, tmp_list)) continue; remaining++; set_bit(NFS_LSEG_LAYOUTRETURN, &lseg->pls_flags); } - if (remaining) + if (remaining) { pnfs_set_plh_return_info(lo, return_range->iomode, seq); + return -EBUSY; + } - return remaining; + if (!list_empty(&lo->plh_return_segs)) { + pnfs_set_plh_return_info(lo, return_range->iomode, seq); + return 0; + } + + return -ENOENT; } void pnfs_error_mark_layout_for_return(struct inode *inode, @@ -2305,7 +2354,7 @@ void pnfs_error_mark_layout_for_return(struct inode *inode, * segments at hand when sending layoutreturn. See pnfs_put_lseg() * for how it works. */ - if (!pnfs_mark_matching_lsegs_return(lo, &lo->plh_return_segs, &range, 0)) { + if (pnfs_mark_matching_lsegs_return(lo, &lo->plh_return_segs, &range, 0) != -EBUSY) { nfs4_stateid stateid; enum pnfs_iomode iomode; diff --git a/fs/nfs/pnfs.h b/fs/nfs/pnfs.h index 3fe81424337d..ece367ebde69 100644 --- a/fs/nfs/pnfs.h +++ b/fs/nfs/pnfs.h @@ -259,7 +259,9 @@ int pnfs_destroy_layouts_byfsid(struct nfs_client *clp, bool is_recall); int pnfs_destroy_layouts_byclid(struct nfs_client *clp, bool is_recall); -bool nfs4_refresh_layout_stateid(nfs4_stateid *dst, struct inode *inode); +bool nfs4_layoutreturn_refresh_stateid(nfs4_stateid *dst, + struct pnfs_layout_range *dst_range, + struct inode *inode); void pnfs_put_layout_hdr(struct pnfs_layout_hdr *lo); void pnfs_set_layout_stateid(struct pnfs_layout_hdr *lo, const nfs4_stateid *new, @@ -780,7 +782,8 @@ static inline void nfs4_pnfs_v3_ds_connect_unload(void) { } -static inline bool nfs4_refresh_layout_stateid(nfs4_stateid *dst, +static inline bool nfs4_layoutreturn_refresh_stateid(nfs4_stateid *dst, + struct pnfs_layout_range *dst_range, struct inode *inode) { return false; diff --git a/fs/nfs/pnfs_nfs.c b/fs/nfs/pnfs_nfs.c index 32ba2d471853..d5e4d3cd8c7f 100644 --- a/fs/nfs/pnfs_nfs.c +++ b/fs/nfs/pnfs_nfs.c @@ -61,7 +61,7 @@ EXPORT_SYMBOL_GPL(pnfs_generic_commit_release); /* The generic layer is about to remove the req from the commit list. * If this will make the bucket empty, it will need to put the lseg reference. - * Note this must be called holding i_lock + * Note this must be called holding nfsi->commit_mutex */ void pnfs_generic_clear_request_commit(struct nfs_page *req, @@ -149,9 +149,7 @@ restart: if (list_empty(&b->written)) { freeme = b->wlseg; b->wlseg = NULL; - spin_unlock(&cinfo->inode->i_lock); pnfs_put_lseg(freeme); - spin_lock(&cinfo->inode->i_lock); goto restart; } } @@ -167,7 +165,7 @@ static void pnfs_generic_retry_commit(struct nfs_commit_info *cinfo, int idx) LIST_HEAD(pages); int i; - spin_lock(&cinfo->inode->i_lock); + mutex_lock(&NFS_I(cinfo->inode)->commit_mutex); for (i = idx; i < fl_cinfo->nbuckets; i++) { bucket = &fl_cinfo->buckets[i]; if (list_empty(&bucket->committing)) @@ -177,12 +175,12 @@ static void pnfs_generic_retry_commit(struct nfs_commit_info *cinfo, int idx) list_for_each(pos, &bucket->committing) cinfo->ds->ncommitting--; list_splice_init(&bucket->committing, &pages); - spin_unlock(&cinfo->inode->i_lock); + mutex_unlock(&NFS_I(cinfo->inode)->commit_mutex); nfs_retry_commit(&pages, freeme, cinfo, i); pnfs_put_lseg(freeme); - spin_lock(&cinfo->inode->i_lock); + mutex_lock(&NFS_I(cinfo->inode)->commit_mutex); } - spin_unlock(&cinfo->inode->i_lock); + mutex_unlock(&NFS_I(cinfo->inode)->commit_mutex); } static unsigned int @@ -222,13 +220,13 @@ void pnfs_fetch_commit_bucket_list(struct list_head *pages, struct list_head *pos; bucket = &cinfo->ds->buckets[data->ds_commit_index]; - spin_lock(&cinfo->inode->i_lock); + mutex_lock(&NFS_I(cinfo->inode)->commit_mutex); list_for_each(pos, &bucket->committing) cinfo->ds->ncommitting--; list_splice_init(&bucket->committing, pages); data->lseg = bucket->clseg; bucket->clseg = NULL; - spin_unlock(&cinfo->inode->i_lock); + mutex_unlock(&NFS_I(cinfo->inode)->commit_mutex); } diff --git a/fs/nfs/super.c b/fs/nfs/super.c index 5e470e233c83..ac4b2f005778 100644 --- a/fs/nfs/super.c +++ b/fs/nfs/super.c @@ -884,7 +884,7 @@ int nfs_show_stats(struct seq_file *m, struct dentry *root) #endif seq_printf(m, "\n"); - rpc_print_iostats(m, nfss->client); + rpc_clnt_show_stats(m, nfss->client); return 0; } @@ -2899,7 +2899,7 @@ static int param_set_portnr(const char *val, const struct kernel_param *kp) if (!val) return -EINVAL; ret = kstrtoul(val, 0, &num); - if (ret == -EINVAL || num > NFS_CALLBACK_MAXPORTNR) + if (ret || num > NFS_CALLBACK_MAXPORTNR) return -EINVAL; *((unsigned int *)kp->arg) = num; return 0; diff --git a/fs/nfs/write.c b/fs/nfs/write.c index a057b4f45a46..586726a590d8 100644 --- a/fs/nfs/write.c +++ b/fs/nfs/write.c @@ -1406,6 +1406,8 @@ static void nfs_async_write_error(struct list_head *head) static void nfs_async_write_reschedule_io(struct nfs_pgio_header *hdr) { nfs_async_write_error(&hdr->pages); + filemap_fdatawrite_range(hdr->inode->i_mapping, hdr->args.offset, + hdr->args.offset + hdr->args.count - 1); } static const struct nfs_pgio_completion_ops nfs_async_write_completion_ops = { diff --git a/fs/nfsd/netns.h b/fs/nfsd/netns.h index 36358d435cb0..426f55005697 100644 --- a/fs/nfsd/netns.h +++ b/fs/nfsd/netns.h @@ -102,6 +102,7 @@ struct nfsd_net { time_t nfsd4_lease; time_t nfsd4_grace; + bool somebody_reclaimed; bool nfsd_net_up; bool lockd_up; diff --git a/fs/nfsd/nfs3proc.c b/fs/nfsd/nfs3proc.c index 6259a4b8579f..9eb8086ea841 100644 --- a/fs/nfsd/nfs3proc.c +++ b/fs/nfsd/nfs3proc.c @@ -202,7 +202,8 @@ nfsd3_proc_write(struct svc_rqst *rqstp) fh_copy(&resp->fh, &argp->fh); resp->committed = argp->stable; - nvecs = svc_fill_write_vector(rqstp, &argp->first, cnt); + nvecs = svc_fill_write_vector(rqstp, rqstp->rq_arg.pages, + &argp->first, cnt); if (!nvecs) RETURN_STATUS(nfserr_io); nfserr = nfsd_write(rqstp, &resp->fh, argp->offset, @@ -289,6 +290,7 @@ nfsd3_proc_symlink(struct svc_rqst *rqstp) RETURN_STATUS(nfserr_nametoolong); argp->tname = svc_fill_symlink_pathname(rqstp, &argp->first, + page_address(rqstp->rq_arg.pages[0]), argp->tlen); if (IS_ERR(argp->tname)) RETURN_STATUS(nfserrno(PTR_ERR(argp->tname))); @@ -302,6 +304,7 @@ nfsd3_proc_symlink(struct svc_rqst *rqstp) fh_init(&resp->fh, NFS3_FHSIZE); nfserr = nfsd_symlink(rqstp, &resp->dirfh, argp->fname, argp->flen, argp->tname, &resp->fh); + kfree(argp->tname); RETURN_STATUS(nfserr); } diff --git a/fs/nfsd/nfs4callback.c b/fs/nfsd/nfs4callback.c index 1f04d2a70d25..601bf33c26a0 100644 --- a/fs/nfsd/nfs4callback.c +++ b/fs/nfsd/nfs4callback.c @@ -746,30 +746,17 @@ static int max_cb_time(struct net *net) return max(nn->nfsd4_lease/10, (time_t)1) * HZ; } -static struct rpc_cred *callback_cred; - -int set_callback_cred(void) -{ - if (callback_cred) - return 0; - callback_cred = rpc_lookup_machine_cred("nfs"); - if (!callback_cred) - return -ENOMEM; - return 0; -} - -void cleanup_callback_cred(void) -{ - if (callback_cred) { - put_rpccred(callback_cred); - callback_cred = NULL; - } -} - static struct rpc_cred *get_backchannel_cred(struct nfs4_client *clp, struct rpc_clnt *client, struct nfsd4_session *ses) { if (clp->cl_minorversion == 0) { - return get_rpccred(callback_cred); + char *principal = clp->cl_cred.cr_targ_princ ? + clp->cl_cred.cr_targ_princ : "nfs"; + struct rpc_cred *cred; + + cred = rpc_lookup_machine_cred(principal); + if (!IS_ERR(cred)) + get_rpccred(cred); + return cred; } else { struct rpc_auth *auth = client->cl_auth; struct auth_cred acred = {}; @@ -980,6 +967,7 @@ static bool nfsd4_cb_sequence_done(struct rpc_task *task, struct nfsd4_callback break; case -ESERVERFAULT: ++session->se_cb_seq_nr; + /* Fall through */ case 1: case -NFS4ERR_BADSESSION: nfsd4_mark_cb_fault(cb->cb_clp, cb->cb_seq_status); diff --git a/fs/nfsd/nfs4layouts.c b/fs/nfsd/nfs4layouts.c index 228faf00a594..2b36aa037ce0 100644 --- a/fs/nfsd/nfs4layouts.c +++ b/fs/nfsd/nfs4layouts.c @@ -133,27 +133,20 @@ void nfsd4_setup_layout_type(struct svc_export *exp) if (!(exp->ex_flags & NFSEXP_PNFS)) return; - /* - * If flex file is configured, use it by default. Otherwise - * check if the file system supports exporting a block-like layout. - * If the block device supports reservations prefer the SCSI layout, - * otherwise advertise the block layout. - */ #ifdef CONFIG_NFSD_FLEXFILELAYOUT exp->ex_layout_types |= 1 << LAYOUT_FLEX_FILES; #endif #ifdef CONFIG_NFSD_BLOCKLAYOUT - /* overwrite flex file layout selection if needed */ if (sb->s_export_op->get_uuid && sb->s_export_op->map_blocks && sb->s_export_op->commit_blocks) exp->ex_layout_types |= 1 << LAYOUT_BLOCK_VOLUME; #endif #ifdef CONFIG_NFSD_SCSILAYOUT - /* overwrite block layout selection if needed */ if (sb->s_export_op->map_blocks && sb->s_export_op->commit_blocks && - sb->s_bdev && sb->s_bdev->bd_disk->fops->pr_ops) + sb->s_bdev && sb->s_bdev->bd_disk->fops->pr_ops && + blk_queue_scsi_passthrough(sb->s_bdev->bd_disk->queue)) exp->ex_layout_types |= 1 << LAYOUT_SCSI; #endif } diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index 5d99e8810b85..b7bc6e1a85ac 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -354,6 +354,7 @@ nfsd4_open(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, struct svc_fh *resfh = NULL; struct net *net = SVC_NET(rqstp); struct nfsd_net *nn = net_generic(net, nfsd_net_id); + bool reclaim = false; dprintk("NFSD: nfsd4_open filename %.*s op_openowner %p\n", (int)open->op_fname.len, open->op_fname.data, @@ -424,6 +425,7 @@ nfsd4_open(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, if (status) goto out; open->op_openowner->oo_flags |= NFS4_OO_CONFIRMED; + reclaim = true; case NFS4_OPEN_CLAIM_FH: case NFS4_OPEN_CLAIM_DELEG_CUR_FH: status = do_open_fhandle(rqstp, cstate, open); @@ -452,6 +454,8 @@ nfsd4_open(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, WARN(status && open->op_created, "nfsd4_process_open2 failed to open newly-created file! status=%u\n", be32_to_cpu(status)); + if (reclaim && !status) + nn->somebody_reclaimed = true; out: if (resfh && resfh != &cstate->current_fh) { fh_dup2(&cstate->current_fh, resfh); @@ -982,24 +986,6 @@ out: return status; } -static int fill_in_write_vector(struct kvec *vec, struct nfsd4_write *write) -{ - int i = 1; - int buflen = write->wr_buflen; - - vec[0].iov_base = write->wr_head.iov_base; - vec[0].iov_len = min_t(int, buflen, write->wr_head.iov_len); - buflen -= vec[0].iov_len; - - while (buflen) { - vec[i].iov_base = page_address(write->wr_pagelist[i - 1]); - vec[i].iov_len = min_t(int, PAGE_SIZE, buflen); - buflen -= vec[i].iov_len; - i++; - } - return i; -} - static __be32 nfsd4_write(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, union nfsd4_op_u *u) @@ -1027,7 +1013,10 @@ nfsd4_write(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, write->wr_how_written = write->wr_stable_how; gen_boot_verifier(&write->wr_verifier, SVC_NET(rqstp)); - nvecs = fill_in_write_vector(rqstp->rq_vec, write); + nvecs = svc_fill_write_vector(rqstp, write->wr_pagelist, + &write->wr_head, write->wr_buflen); + if (!nvecs) + return nfserr_io; WARN_ON_ONCE(nvecs > ARRAY_SIZE(rqstp->rq_vec)); status = nfsd_vfs_write(rqstp, &cstate->current_fh, filp, @@ -1599,7 +1588,7 @@ static const char *nfsd4_op_name(unsigned opnum); */ static __be32 nfs41_check_op_ordering(struct nfsd4_compoundargs *args) { - struct nfsd4_op *op = &args->ops[0]; + struct nfsd4_op *first_op = &args->ops[0]; /* These ordering requirements don't apply to NFSv4.0: */ if (args->minorversion == 0) @@ -1607,12 +1596,17 @@ static __be32 nfs41_check_op_ordering(struct nfsd4_compoundargs *args) /* This is weird, but OK, not our problem: */ if (args->opcnt == 0) return nfs_ok; - if (op->status == nfserr_op_illegal) + if (first_op->status == nfserr_op_illegal) return nfs_ok; - if (!(nfsd4_ops[op->opnum].op_flags & ALLOWED_AS_FIRST_OP)) + if (!(nfsd4_ops[first_op->opnum].op_flags & ALLOWED_AS_FIRST_OP)) return nfserr_op_not_in_session; - if (op->opnum == OP_SEQUENCE) + if (first_op->opnum == OP_SEQUENCE) return nfs_ok; + /* + * So first_op is something allowed outside a session, like + * EXCHANGE_ID; but then it has to be the only op in the + * compound: + */ if (args->opcnt != 1) return nfserr_not_only_op; return nfs_ok; @@ -1726,6 +1720,7 @@ nfsd4_proc_compound(struct svc_rqst *rqstp) if (status) { op = &args->ops[0]; op->status = status; + resp->opcnt = 1; goto encode_op; } diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 857141446d6b..b0ca0efd2875 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -1979,8 +1979,10 @@ static int copy_cred(struct svc_cred *target, struct svc_cred *source) target->cr_principal = kstrdup(source->cr_principal, GFP_KERNEL); target->cr_raw_principal = kstrdup(source->cr_raw_principal, GFP_KERNEL); - if ((source->cr_principal && ! target->cr_principal) || - (source->cr_raw_principal && ! target->cr_raw_principal)) + target->cr_targ_princ = kstrdup(source->cr_targ_princ, GFP_KERNEL); + if ((source->cr_principal && !target->cr_principal) || + (source->cr_raw_principal && !target->cr_raw_principal) || + (source->cr_targ_princ && !target->cr_targ_princ)) return -ENOMEM; target->cr_flavor = source->cr_flavor; @@ -2057,6 +2059,7 @@ same_creds(struct svc_cred *cr1, struct svc_cred *cr2) || (!gid_eq(cr1->cr_gid, cr2->cr_gid)) || !groups_equal(cr1->cr_group_info, cr2->cr_group_info)) return false; + /* XXX: check that cr_targ_princ fields match ? */ if (cr1->cr_principal == cr2->cr_principal) return true; if (!cr1->cr_principal || !cr2->cr_principal) @@ -2956,18 +2959,18 @@ out_no_session: return status; } -static bool nfsd4_compound_in_session(struct nfsd4_session *session, struct nfs4_sessionid *sid) +static bool nfsd4_compound_in_session(struct nfsd4_compound_state *cstate, struct nfs4_sessionid *sid) { - if (!session) + if (!cstate->session) return false; - return !memcmp(sid, &session->se_sessionid, sizeof(*sid)); + return !memcmp(sid, &cstate->session->se_sessionid, sizeof(*sid)); } __be32 nfsd4_destroy_session(struct svc_rqst *r, struct nfsd4_compound_state *cstate, union nfsd4_op_u *u) { - struct nfsd4_destroy_session *sessionid = &u->destroy_session; + struct nfs4_sessionid *sessionid = &u->destroy_session.sessionid; struct nfsd4_session *ses; __be32 status; int ref_held_by_me = 0; @@ -2975,14 +2978,14 @@ nfsd4_destroy_session(struct svc_rqst *r, struct nfsd4_compound_state *cstate, struct nfsd_net *nn = net_generic(net, nfsd_net_id); status = nfserr_not_only_op; - if (nfsd4_compound_in_session(cstate->session, &sessionid->sessionid)) { + if (nfsd4_compound_in_session(cstate, sessionid)) { if (!nfsd4_last_compound_op(r)) goto out; ref_held_by_me++; } - dump_sessionid(__func__, &sessionid->sessionid); + dump_sessionid(__func__, sessionid); spin_lock(&nn->client_lock); - ses = find_in_sessionid_hashtbl(&sessionid->sessionid, net, &status); + ses = find_in_sessionid_hashtbl(sessionid, net, &status); if (!ses) goto out_client_lock; status = nfserr_wrong_cred; @@ -3945,9 +3948,9 @@ static void nfsd_break_one_deleg(struct nfs4_delegation *dp) /* * We're assuming the state code never drops its reference * without first removing the lease. Since we're in this lease - * callback (and since the lease code is serialized by the kernel - * lock) we know the server hasn't removed the lease yet, we know - * it's safe to take a reference. + * callback (and since the lease code is serialized by the + * i_lock) we know the server hasn't removed the lease yet, and + * we know it's safe to take a reference. */ refcount_inc(&dp->dl_stid.sc_count); nfsd4_run_cb(&dp->dl_recall); @@ -4693,6 +4696,28 @@ nfsd4_end_grace(struct nfsd_net *nn) */ } +/* + * If we've waited a lease period but there are still clients trying to + * reclaim, wait a little longer to give them a chance to finish. + */ +static bool clients_still_reclaiming(struct nfsd_net *nn) +{ + unsigned long now = get_seconds(); + unsigned long double_grace_period_end = nn->boot_time + + 2 * nn->nfsd4_lease; + + if (!nn->somebody_reclaimed) + return false; + nn->somebody_reclaimed = false; + /* + * If we've given them *two* lease times to reclaim, and they're + * still not done, give up: + */ + if (time_after(now, double_grace_period_end)) + return false; + return true; +} + static time_t nfs4_laundromat(struct nfsd_net *nn) { @@ -4706,6 +4731,11 @@ nfs4_laundromat(struct nfsd_net *nn) time_t t, new_timeo = nn->nfsd4_lease; dprintk("NFSD: laundromat service - starting\n"); + + if (clients_still_reclaiming(nn)) { + new_timeo = 0; + goto out; + } nfsd4_end_grace(nn); INIT_LIST_HEAD(&reaplist); spin_lock(&nn->client_lock); @@ -4803,7 +4833,7 @@ nfs4_laundromat(struct nfsd_net *nn) posix_unblock_lock(&nbl->nbl_lock); free_blocked_lock(nbl); } - +out: new_timeo = max_t(time_t, new_timeo, NFSD_LAUNDROMAT_MINTIMEOUT); return new_timeo; } @@ -6053,6 +6083,8 @@ nfsd4_lock(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, case 0: /* success! */ nfs4_inc_and_copy_stateid(&lock->lk_resp_stateid, &lock_stp->st_stid); status = 0; + if (lock->lk_reclaim) + nn->somebody_reclaimed = true; break; case FILE_LOCK_DEFERRED: nbl = NULL; @@ -6293,7 +6325,7 @@ check_for_locks(struct nfs4_file *fp, struct nfs4_lockowner *lowner) return status; } - inode = file_inode(filp); + inode = locks_inode(filp); flctx = inode->i_flctx; if (flctx && !list_empty_careful(&flctx->flc_posix)) { @@ -7199,14 +7231,10 @@ nfs4_state_start(void) { int ret; - ret = set_callback_cred(); - if (ret) - return ret; - laundry_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, "nfsd4"); if (laundry_wq == NULL) { ret = -ENOMEM; - goto out_cleanup_cred; + goto out; } ret = nfsd4_create_callback_queue(); if (ret) @@ -7217,8 +7245,7 @@ nfs4_state_start(void) out_free_laundry: destroy_workqueue(laundry_wq); -out_cleanup_cred: - cleanup_callback_cred(); +out: return ret; } @@ -7255,7 +7282,6 @@ nfs4_state_shutdown(void) { destroy_workqueue(laundry_wq); nfsd4_destroy_callback_queue(); - cleanup_callback_cred(); } static void diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index a96843c59fc1..418fa9c78186 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -1390,10 +1390,8 @@ nfsd4_decode_exchange_id(struct nfsd4_compoundargs *argp, p += XDR_QUADLEN(dummy); } - /* ssp_window and ssp_num_gss_handles */ + /* ignore ssp_window and ssp_num_gss_handles: */ READ_BUF(8); - dummy = be32_to_cpup(p++); - dummy = be32_to_cpup(p++); break; default: goto xdr_error; @@ -2006,6 +2004,31 @@ static __be32 *encode_change(__be32 *p, struct kstat *stat, struct inode *inode, return p; } +/* + * ctime (in NFSv4, time_metadata) is not writeable, and the client + * doesn't really care what resolution could theoretically be stored by + * the filesystem. + * + * The client cares how close together changes can be while still + * guaranteeing ctime changes. For most filesystems (which have + * timestamps with nanosecond fields) that is limited by the resolution + * of the time returned from current_time() (which I'm assuming to be + * 1/HZ). + */ +static __be32 *encode_time_delta(__be32 *p, struct inode *inode) +{ + struct timespec ts; + u32 ns; + + ns = max_t(u32, NSEC_PER_SEC/HZ, inode->i_sb->s_time_gran); + ts = ns_to_timespec(ns); + + p = xdr_encode_hyper(p, ts.tv_sec); + *p++ = cpu_to_be32(ts.tv_nsec); + + return p; +} + static __be32 *encode_cinfo(__be32 *p, struct nfsd4_change_info *c) { *p++ = cpu_to_be32(c->atomic); @@ -2797,9 +2820,7 @@ out_acl: p = xdr_reserve_space(xdr, 12); if (!p) goto out_resource; - *p++ = cpu_to_be32(0); - *p++ = cpu_to_be32(1); - *p++ = cpu_to_be32(0); + p = encode_time_delta(p, d_inode(dentry)); } if (bmval1 & FATTR4_WORD1_TIME_METADATA) { p = xdr_reserve_space(xdr, 12); @@ -2868,6 +2889,16 @@ out_acl: goto out; } + if (bmval2 & FATTR4_WORD2_CHANGE_ATTR_TYPE) { + p = xdr_reserve_space(xdr, 4); + if (!p) + goto out_resource; + if (IS_I_VERSION(d_inode(dentry))) + *p++ = cpu_to_be32(NFS4_CHANGE_TYPE_IS_MONOTONIC_INCR); + else + *p++ = cpu_to_be32(NFS4_CHANGE_TYPE_IS_TIME_METADATA); + } + if (bmval2 & FATTR4_WORD2_SECURITY_LABEL) { status = nfsd4_encode_security_label(xdr, rqstp, context, contextlen); diff --git a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c index d107b4426f7e..7fb9f7c667b1 100644 --- a/fs/nfsd/nfsctl.c +++ b/fs/nfsd/nfsctl.c @@ -73,7 +73,7 @@ static ssize_t write_recoverydir(struct file *file, char *buf, size_t size); static ssize_t write_v4_end_grace(struct file *file, char *buf, size_t size); #endif -static ssize_t (*write_op[])(struct file *, char *, size_t) = { +static ssize_t (*const write_op[])(struct file *, char *, size_t) = { [NFSD_Fh] = write_filehandle, [NFSD_FO_UnlockIP] = write_unlock_ip, [NFSD_FO_UnlockFS] = write_unlock_fs, @@ -1237,8 +1237,9 @@ static __net_init int nfsd_init_net(struct net *net) retval = nfsd_idmap_init(net); if (retval) goto out_idmap_error; - nn->nfsd4_lease = 90; /* default lease time */ - nn->nfsd4_grace = 90; + nn->nfsd4_lease = 45; /* default lease time */ + nn->nfsd4_grace = 45; + nn->somebody_reclaimed = false; nn->clverifier_counter = prandom_u32(); nn->clientid_counter = prandom_u32(); diff --git a/fs/nfsd/nfsd.h b/fs/nfsd/nfsd.h index 3fce905d0365..066899929863 100644 --- a/fs/nfsd/nfsd.h +++ b/fs/nfsd/nfsd.h @@ -360,6 +360,7 @@ void nfsd_lockd_shutdown(void); #define NFSD4_2_SUPPORTED_ATTRS_WORD2 \ (NFSD4_1_SUPPORTED_ATTRS_WORD2 | \ + FATTR4_WORD2_CHANGE_ATTR_TYPE | \ FATTR4_WORD2_MODE_UMASK | \ NFSD4_2_SECURITY_ATTRS) diff --git a/fs/nfsd/nfsfh.c b/fs/nfsd/nfsfh.c index a008e7634181..b319080288c3 100644 --- a/fs/nfsd/nfsfh.c +++ b/fs/nfsd/nfsfh.c @@ -451,7 +451,7 @@ static bool fsid_type_ok_for_exp(u8 fsid_type, struct svc_export *exp) switch (fsid_type) { case FSID_DEV: if (!old_valid_dev(exp_sb(exp)->s_dev)) - return 0; + return false; /* FALL THROUGH */ case FSID_MAJOR_MINOR: case FSID_ENCODE_DEV: @@ -461,13 +461,13 @@ static bool fsid_type_ok_for_exp(u8 fsid_type, struct svc_export *exp) case FSID_UUID8: case FSID_UUID16: if (!is_root_export(exp)) - return 0; + return false; /* fall through */ case FSID_UUID4_INUM: case FSID_UUID16_INUM: return exp->ex_uuid != NULL; } - return 1; + return true; } diff --git a/fs/nfsd/nfsproc.c b/fs/nfsd/nfsproc.c index f107f9fa8e15..0d20fd161225 100644 --- a/fs/nfsd/nfsproc.c +++ b/fs/nfsd/nfsproc.c @@ -218,7 +218,8 @@ nfsd_proc_write(struct svc_rqst *rqstp) SVCFH_fmt(&argp->fh), argp->len, argp->offset); - nvecs = svc_fill_write_vector(rqstp, &argp->first, cnt); + nvecs = svc_fill_write_vector(rqstp, rqstp->rq_arg.pages, + &argp->first, cnt); if (!nvecs) return nfserr_io; nfserr = nfsd_write(rqstp, fh_copy(&resp->fh, &argp->fh), @@ -453,6 +454,7 @@ nfsd_proc_symlink(struct svc_rqst *rqstp) return nfserr_nametoolong; argp->tname = svc_fill_symlink_pathname(rqstp, &argp->first, + page_address(rqstp->rq_arg.pages[0]), argp->tlen); if (IS_ERR(argp->tname)) return nfserrno(PTR_ERR(argp->tname)); @@ -465,6 +467,7 @@ nfsd_proc_symlink(struct svc_rqst *rqstp) nfserr = nfsd_symlink(rqstp, &argp->ffh, argp->fname, argp->flen, argp->tname, &newfh); + kfree(argp->tname); fh_put(&argp->ffh); fh_put(&newfh); return nfserr; diff --git a/fs/nfsd/state.h b/fs/nfsd/state.h index f3772ea8ba0d..0b15dac7e609 100644 --- a/fs/nfsd/state.h +++ b/fs/nfsd/state.h @@ -617,8 +617,6 @@ extern struct nfs4_client_reclaim *nfsd4_find_reclaim_client(const char *recdir, struct nfsd_net *nn); extern __be32 nfs4_check_open_reclaim(clientid_t *clid, struct nfsd4_compound_state *cstate, struct nfsd_net *nn); -extern int set_callback_cred(void); -extern void cleanup_callback_cred(void); extern void nfsd4_probe_callback(struct nfs4_client *clp); extern void nfsd4_probe_callback_sync(struct nfs4_client *clp); extern void nfsd4_change_callback(struct nfs4_client *clp, struct nfs4_cb_conn *); diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig index 83a961bf7280..bbc78549be4c 100644 --- a/fs/ubifs/Kconfig +++ b/fs/ubifs/Kconfig @@ -51,9 +51,20 @@ config UBIFS_ATIME_SUPPORT If unsure, say 'N' +config UBIFS_FS_XATTR + bool "UBIFS XATTR support" + depends on UBIFS_FS + default y + help + Saying Y here includes support for extended attributes (xattrs). + Xattrs are name:value pairs associated with inodes by + the kernel or by users (see the attr(5) manual page). + + If unsure, say Y. + config UBIFS_FS_ENCRYPTION bool "UBIFS Encryption" - depends on UBIFS_FS && BLOCK + depends on UBIFS_FS && UBIFS_FS_XATTR && BLOCK select FS_ENCRYPTION default n help @@ -64,7 +75,7 @@ config UBIFS_FS_ENCRYPTION config UBIFS_FS_SECURITY bool "UBIFS Security Labels" - depends on UBIFS_FS + depends on UBIFS_FS && UBIFS_FS_XATTR default y help Security labels provide an access control facility to support Linux diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile index 9758f709c736..6197d7e539e4 100644 --- a/fs/ubifs/Makefile +++ b/fs/ubifs/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_UBIFS_FS) += ubifs.o ubifs-y += shrinker.o journal.o file.o dir.o super.o sb.o io.o ubifs-y += tnc.o master.o scan.o replay.o log.o commit.o gc.o orphan.o ubifs-y += budget.o find.o tnc_commit.o compress.o lpt.o lprops.o -ubifs-y += recovery.o ioctl.o lpt_commit.o tnc_misc.o xattr.o debug.o +ubifs-y += recovery.o ioctl.o lpt_commit.o tnc_misc.o debug.o ubifs-y += misc.o ubifs-$(CONFIG_UBIFS_FS_ENCRYPTION) += crypto.o +ubifs-$(CONFIG_UBIFS_FS_XATTR) += xattr.o diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c index 11a11b32a2a9..7ef22baf9d15 100644 --- a/fs/ubifs/budget.c +++ b/fs/ubifs/budget.c @@ -439,16 +439,16 @@ int ubifs_budget_space(struct ubifs_info *c, struct ubifs_budget_req *req) { int err, idx_growth, data_growth, dd_growth, retried = 0; - ubifs_assert(req->new_page <= 1); - ubifs_assert(req->dirtied_page <= 1); - ubifs_assert(req->new_dent <= 1); - ubifs_assert(req->mod_dent <= 1); - ubifs_assert(req->new_ino <= 1); - ubifs_assert(req->new_ino_d <= UBIFS_MAX_INO_DATA); - ubifs_assert(req->dirtied_ino <= 4); - ubifs_assert(req->dirtied_ino_d <= UBIFS_MAX_INO_DATA * 4); - ubifs_assert(!(req->new_ino_d & 7)); - ubifs_assert(!(req->dirtied_ino_d & 7)); + ubifs_assert(c, req->new_page <= 1); + ubifs_assert(c, req->dirtied_page <= 1); + ubifs_assert(c, req->new_dent <= 1); + ubifs_assert(c, req->mod_dent <= 1); + ubifs_assert(c, req->new_ino <= 1); + ubifs_assert(c, req->new_ino_d <= UBIFS_MAX_INO_DATA); + ubifs_assert(c, req->dirtied_ino <= 4); + ubifs_assert(c, req->dirtied_ino_d <= UBIFS_MAX_INO_DATA * 4); + ubifs_assert(c, !(req->new_ino_d & 7)); + ubifs_assert(c, !(req->dirtied_ino_d & 7)); data_growth = calc_data_growth(c, req); dd_growth = calc_dd_growth(c, req); @@ -458,9 +458,9 @@ int ubifs_budget_space(struct ubifs_info *c, struct ubifs_budget_req *req) again: spin_lock(&c->space_lock); - ubifs_assert(c->bi.idx_growth >= 0); - ubifs_assert(c->bi.data_growth >= 0); - ubifs_assert(c->bi.dd_growth >= 0); + ubifs_assert(c, c->bi.idx_growth >= 0); + ubifs_assert(c, c->bi.data_growth >= 0); + ubifs_assert(c, c->bi.dd_growth >= 0); if (unlikely(c->bi.nospace) && (c->bi.nospace_rp || !can_use_rp(c))) { dbg_budg("no space"); @@ -526,20 +526,20 @@ again: */ void ubifs_release_budget(struct ubifs_info *c, struct ubifs_budget_req *req) { - ubifs_assert(req->new_page <= 1); - ubifs_assert(req->dirtied_page <= 1); - ubifs_assert(req->new_dent <= 1); - ubifs_assert(req->mod_dent <= 1); - ubifs_assert(req->new_ino <= 1); - ubifs_assert(req->new_ino_d <= UBIFS_MAX_INO_DATA); - ubifs_assert(req->dirtied_ino <= 4); - ubifs_assert(req->dirtied_ino_d <= UBIFS_MAX_INO_DATA * 4); - ubifs_assert(!(req->new_ino_d & 7)); - ubifs_assert(!(req->dirtied_ino_d & 7)); + ubifs_assert(c, req->new_page <= 1); + ubifs_assert(c, req->dirtied_page <= 1); + ubifs_assert(c, req->new_dent <= 1); + ubifs_assert(c, req->mod_dent <= 1); + ubifs_assert(c, req->new_ino <= 1); + ubifs_assert(c, req->new_ino_d <= UBIFS_MAX_INO_DATA); + ubifs_assert(c, req->dirtied_ino <= 4); + ubifs_assert(c, req->dirtied_ino_d <= UBIFS_MAX_INO_DATA * 4); + ubifs_assert(c, !(req->new_ino_d & 7)); + ubifs_assert(c, !(req->dirtied_ino_d & 7)); if (!req->recalculate) { - ubifs_assert(req->idx_growth >= 0); - ubifs_assert(req->data_growth >= 0); - ubifs_assert(req->dd_growth >= 0); + ubifs_assert(c, req->idx_growth >= 0); + ubifs_assert(c, req->data_growth >= 0); + ubifs_assert(c, req->dd_growth >= 0); } if (req->recalculate) { @@ -561,13 +561,13 @@ void ubifs_release_budget(struct ubifs_info *c, struct ubifs_budget_req *req) c->bi.dd_growth -= req->dd_growth; c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c); - ubifs_assert(c->bi.idx_growth >= 0); - ubifs_assert(c->bi.data_growth >= 0); - ubifs_assert(c->bi.dd_growth >= 0); - ubifs_assert(c->bi.min_idx_lebs < c->main_lebs); - ubifs_assert(!(c->bi.idx_growth & 7)); - ubifs_assert(!(c->bi.data_growth & 7)); - ubifs_assert(!(c->bi.dd_growth & 7)); + ubifs_assert(c, c->bi.idx_growth >= 0); + ubifs_assert(c, c->bi.data_growth >= 0); + ubifs_assert(c, c->bi.dd_growth >= 0); + ubifs_assert(c, c->bi.min_idx_lebs < c->main_lebs); + ubifs_assert(c, !(c->bi.idx_growth & 7)); + ubifs_assert(c, !(c->bi.data_growth & 7)); + ubifs_assert(c, !(c->bi.dd_growth & 7)); spin_unlock(&c->space_lock); } @@ -680,7 +680,7 @@ long long ubifs_get_free_space_nolock(struct ubifs_info *c) int rsvd_idx_lebs, lebs; long long available, outstanding, free; - ubifs_assert(c->bi.min_idx_lebs == ubifs_calc_min_idx_lebs(c)); + ubifs_assert(c, c->bi.min_idx_lebs == ubifs_calc_min_idx_lebs(c)); outstanding = c->bi.data_growth + c->bi.dd_growth; available = ubifs_calc_available(c, c->bi.min_idx_lebs); diff --git a/fs/ubifs/commit.c b/fs/ubifs/commit.c index 63f56619991d..591f2c7a48f0 100644 --- a/fs/ubifs/commit.c +++ b/fs/ubifs/commit.c @@ -91,9 +91,9 @@ static int nothing_to_commit(struct ubifs_info *c) if (c->nroot && test_bit(DIRTY_CNODE, &c->nroot->flags)) return 0; - ubifs_assert(atomic_long_read(&c->dirty_zn_cnt) == 0); - ubifs_assert(c->dirty_pn_cnt == 0); - ubifs_assert(c->dirty_nn_cnt == 0); + ubifs_assert(c, atomic_long_read(&c->dirty_zn_cnt) == 0); + ubifs_assert(c, c->dirty_pn_cnt == 0); + ubifs_assert(c, c->dirty_nn_cnt == 0); return 1; } @@ -113,7 +113,7 @@ static int do_commit(struct ubifs_info *c) struct ubifs_lp_stats lst; dbg_cmt("start"); - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (c->ro_error) { err = -EROFS; diff --git a/fs/ubifs/crypto.c b/fs/ubifs/crypto.c index 55c508fe8131..4aaedf2d7f44 100644 --- a/fs/ubifs/crypto.c +++ b/fs/ubifs/crypto.c @@ -32,7 +32,7 @@ int ubifs_encrypt(const struct inode *inode, struct ubifs_data_node *dn, struct page *ret; unsigned int pad_len = round_up(in_len, UBIFS_CIPHER_BLOCK_SIZE); - ubifs_assert(pad_len <= *out_len); + ubifs_assert(c, pad_len <= *out_len); dn->compr_size = cpu_to_le16(in_len); /* pad to full block cipher length */ @@ -63,7 +63,7 @@ int ubifs_decrypt(const struct inode *inode, struct ubifs_data_node *dn, return -EINVAL; } - ubifs_assert(dlen <= UBIFS_BLOCK_SIZE); + ubifs_assert(c, dlen <= UBIFS_BLOCK_SIZE); err = fscrypt_decrypt_page(inode, virt_to_page(&dn->data), dlen, offset_in_page(&dn->data), block); if (err) { diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c index 7cd8a7b95299..564e330d05b1 100644 --- a/fs/ubifs/debug.c +++ b/fs/ubifs/debug.c @@ -134,7 +134,7 @@ const char *dbg_snprintf_key(const struct ubifs_info *c, } } else len -= snprintf(p, len, "bad key format %d", c->key_fmt); - ubifs_assert(len > 0); + ubifs_assert(c, len > 0); return p; } @@ -276,7 +276,7 @@ void ubifs_dump_inode(struct ubifs_info *c, const struct inode *inode) return; pr_err("List of directory entries:\n"); - ubifs_assert(!mutex_is_locked(&c->tnc_mutex)); + ubifs_assert(c, !mutex_is_locked(&c->tnc_mutex)); lowest_dent_key(c, &key, inode->i_ino); while (1) { @@ -931,7 +931,7 @@ void ubifs_dump_tnc(struct ubifs_info *c) pr_err("\n"); pr_err("(pid %d) start dumping TNC tree\n", current->pid); - znode = ubifs_tnc_levelorder_next(c->zroot.znode, NULL); + znode = ubifs_tnc_levelorder_next(c, c->zroot.znode, NULL); level = znode->level; pr_err("== Level %d ==\n", level); while (znode) { @@ -940,7 +940,7 @@ void ubifs_dump_tnc(struct ubifs_info *c) pr_err("== Level %d ==\n", level); } ubifs_dump_znode(c, znode); - znode = ubifs_tnc_levelorder_next(c->zroot.znode, znode); + znode = ubifs_tnc_levelorder_next(c, c->zroot.znode, znode); } pr_err("(pid %d) finish dumping TNC tree\n", current->pid); } @@ -1183,7 +1183,7 @@ static int dbg_check_key_order(struct ubifs_info *c, struct ubifs_zbranch *zbr1, union ubifs_key key; char key_buf[DBG_KEY_BUF_LEN]; - ubifs_assert(!keys_cmp(c, &zbr1->key, &zbr2->key)); + ubifs_assert(c, !keys_cmp(c, &zbr1->key, &zbr2->key)); dent1 = kmalloc(UBIFS_MAX_DENT_NODE_SZ, GFP_NOFS); if (!dent1) return -ENOMEM; @@ -1479,7 +1479,7 @@ int dbg_check_tnc(struct ubifs_info *c, int extra) if (!dbg_is_chk_index(c)) return 0; - ubifs_assert(mutex_is_locked(&c->tnc_mutex)); + ubifs_assert(c, mutex_is_locked(&c->tnc_mutex)); if (!c->zroot.znode) return 0; @@ -1505,7 +1505,7 @@ int dbg_check_tnc(struct ubifs_info *c, int extra) } prev = znode; - znode = ubifs_tnc_postorder_next(znode); + znode = ubifs_tnc_postorder_next(c, znode); if (!znode) break; @@ -2036,7 +2036,7 @@ static int check_leaf(struct ubifs_info *c, struct ubifs_zbranch *zbr, long long blk_offs; struct ubifs_data_node *dn = node; - ubifs_assert(zbr->len >= UBIFS_DATA_NODE_SZ); + ubifs_assert(c, zbr->len >= UBIFS_DATA_NODE_SZ); /* * Search the inode node this data node belongs to and insert @@ -2066,7 +2066,7 @@ static int check_leaf(struct ubifs_info *c, struct ubifs_zbranch *zbr, struct ubifs_dent_node *dent = node; struct fsck_inode *fscki1; - ubifs_assert(zbr->len >= UBIFS_DENT_NODE_SZ); + ubifs_assert(c, zbr->len >= UBIFS_DENT_NODE_SZ); err = ubifs_validate_entry(c, dent); if (err) @@ -2461,7 +2461,7 @@ static int power_cut_emulated(struct ubifs_info *c, int lnum, int write) { struct ubifs_debug_info *d = c->dbg; - ubifs_assert(dbg_is_tst_rcvry(c)); + ubifs_assert(c, dbg_is_tst_rcvry(c)); if (!d->pc_cnt) { /* First call - decide delay to the power cut */ @@ -3081,6 +3081,28 @@ void dbg_debugfs_exit(void) debugfs_remove_recursive(dfs_rootdir); } +void ubifs_assert_failed(struct ubifs_info *c, const char *expr, + const char *file, int line) +{ + ubifs_err(c, "UBIFS assert failed: %s, in %s:%u", expr, file, line); + + switch (c->assert_action) { + case ASSACT_PANIC: + BUG(); + break; + + case ASSACT_RO: + ubifs_ro_mode(c, -EINVAL); + break; + + case ASSACT_REPORT: + default: + dump_stack(); + break; + + } +} + /** * ubifs_debugging_init - initialize UBIFS debugging. * @c: UBIFS file-system description object diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h index e03d5179769a..64c6977c189b 100644 --- a/fs/ubifs/debug.h +++ b/fs/ubifs/debug.h @@ -148,19 +148,21 @@ struct ubifs_global_debug_info { unsigned int tst_rcvry:1; }; -#define ubifs_assert(expr) do { \ +void ubifs_assert_failed(struct ubifs_info *c, const char *expr, + const char *file, int line); + +#define ubifs_assert(c, expr) do { \ if (unlikely(!(expr))) { \ - pr_crit("UBIFS assert failed in %s at %u (pid %d)\n", \ - __func__, __LINE__, current->pid); \ - dump_stack(); \ + ubifs_assert_failed((struct ubifs_info *)c, #expr, __FILE__, \ + __LINE__); \ } \ } while (0) #define ubifs_assert_cmt_locked(c) do { \ if (unlikely(down_write_trylock(&(c)->commit_sem))) { \ up_write(&(c)->commit_sem); \ - pr_crit("commit lock is not locked!\n"); \ - ubifs_assert(0); \ + ubifs_err(c, "commit lock is not locked!\n"); \ + ubifs_assert(c, 0); \ } \ } while (0) diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c index 9da224d4f2da..5767b373a8ff 100644 --- a/fs/ubifs/dir.c +++ b/fs/ubifs/dir.c @@ -240,8 +240,8 @@ static struct dentry *ubifs_lookup(struct inode *dir, struct dentry *dentry, } if (nm.hash) { - ubifs_assert(fname_len(&nm) == 0); - ubifs_assert(fname_name(&nm) == NULL); + ubifs_assert(c, fname_len(&nm) == 0); + ubifs_assert(c, fname_name(&nm) == NULL); dent_key_init_hash(c, &key, dir->i_ino, nm.hash); err = ubifs_tnc_lookup_dh(c, &key, dent, nm.minor_hash); } else { @@ -404,7 +404,7 @@ static int do_tmpfile(struct inode *dir, struct dentry *dentry, if (whiteout) { init_special_inode(inode, inode->i_mode, WHITEOUT_DEV); - ubifs_assert(inode->i_op == &ubifs_file_inode_operations); + ubifs_assert(c, inode->i_op == &ubifs_file_inode_operations); } err = ubifs_init_security(dir, inode, &dentry->d_name); @@ -421,7 +421,7 @@ static int do_tmpfile(struct inode *dir, struct dentry *dentry, } else { d_tmpfile(dentry, inode); } - ubifs_assert(ui->dirty); + ubifs_assert(c, ui->dirty); instantiated = 1; mutex_unlock(&ui->ui_mutex); @@ -556,7 +556,7 @@ static int ubifs_readdir(struct file *file, struct dir_context *ctx) /* File positions 0 and 1 correspond to "." and ".." */ if (ctx->pos < 2) { - ubifs_assert(!file->private_data); + ubifs_assert(c, !file->private_data); if (!dir_emit_dots(file, ctx)) { if (encrypted) fscrypt_fname_free_buffer(&fstr); @@ -597,7 +597,7 @@ static int ubifs_readdir(struct file *file, struct dir_context *ctx) dbg_gen("ino %llu, new f_pos %#x", (unsigned long long)le64_to_cpu(dent->inum), key_hash_flash(c, &dent->key)); - ubifs_assert(le64_to_cpu(dent->ch.sqnum) > + ubifs_assert(c, le64_to_cpu(dent->ch.sqnum) > ubifs_inode(dir)->creat_sqnum); fname_len(&nm) = le16_to_cpu(dent->nlen); @@ -716,8 +716,8 @@ static int ubifs_link(struct dentry *old_dentry, struct inode *dir, dbg_gen("dent '%pd' to ino %lu (nlink %d) in dir ino %lu", dentry, inode->i_ino, inode->i_nlink, dir->i_ino); - ubifs_assert(inode_is_locked(dir)); - ubifs_assert(inode_is_locked(inode)); + ubifs_assert(c, inode_is_locked(dir)); + ubifs_assert(c, inode_is_locked(inode)); err = fscrypt_prepare_link(old_dentry, dir, dentry); if (err) @@ -804,8 +804,8 @@ static int ubifs_unlink(struct inode *dir, struct dentry *dentry) sz_change = CALC_DENT_SIZE(fname_len(&nm)); - ubifs_assert(inode_is_locked(dir)); - ubifs_assert(inode_is_locked(inode)); + ubifs_assert(c, inode_is_locked(dir)); + ubifs_assert(c, inode_is_locked(inode)); err = dbg_check_synced_i_size(c, inode); if (err) goto out_fname; @@ -896,8 +896,8 @@ static int ubifs_rmdir(struct inode *dir, struct dentry *dentry) dbg_gen("directory '%pd', ino %lu in dir ino %lu", dentry, inode->i_ino, dir->i_ino); - ubifs_assert(inode_is_locked(dir)); - ubifs_assert(inode_is_locked(inode)); + ubifs_assert(c, inode_is_locked(dir)); + ubifs_assert(c, inode_is_locked(inode)); err = ubifs_check_dir_empty(d_inode(dentry)); if (err) return err; @@ -1123,8 +1123,7 @@ static int ubifs_symlink(struct inode *dir, struct dentry *dentry, struct ubifs_inode *ui; struct ubifs_inode *dir_ui = ubifs_inode(dir); struct ubifs_info *c = dir->i_sb->s_fs_info; - int err, len = strlen(symname); - int sz_change = CALC_DENT_SIZE(len); + int err, sz_change, len = strlen(symname); struct fscrypt_str disk_link; struct ubifs_budget_req req = { .new_ino = 1, .new_dent = 1, .new_ino_d = ALIGN(len, 8), @@ -1151,6 +1150,8 @@ static int ubifs_symlink(struct inode *dir, struct dentry *dentry, if (err) goto out_budg; + sz_change = CALC_DENT_SIZE(fname_len(&nm)); + inode = ubifs_new_inode(c, dir, S_IFLNK | S_IRWXUGO); if (IS_ERR(inode)) { err = PTR_ERR(inode); @@ -1294,7 +1295,7 @@ static int do_rename(struct inode *old_dir, struct dentry *old_dentry, new_dentry, new_dir->i_ino, flags); if (unlink) - ubifs_assert(inode_is_locked(new_inode)); + ubifs_assert(c, inode_is_locked(new_inode)); if (unlink && is_dir) { err = ubifs_check_dir_empty(new_inode); @@ -1348,7 +1349,7 @@ static int do_rename(struct inode *old_dir, struct dentry *old_dentry, whiteout_ui = ubifs_inode(whiteout); whiteout_ui->data = dev; whiteout_ui->data_len = ubifs_encode_dev(dev, MKDEV(0, 0)); - ubifs_assert(!whiteout_ui->dirty); + ubifs_assert(c, !whiteout_ui->dirty); } lock_4_inodes(old_dir, new_dir, new_inode, whiteout); @@ -1508,7 +1509,7 @@ static int ubifs_xrename(struct inode *old_dir, struct dentry *old_dentry, int err; struct fscrypt_name fst_nm, snd_nm; - ubifs_assert(fst_inode && snd_inode); + ubifs_assert(c, fst_inode && snd_inode); err = fscrypt_setup_filename(old_dir, &old_dentry->d_name, 0, &fst_nm); if (err) @@ -1555,12 +1556,13 @@ static int ubifs_rename(struct inode *old_dir, struct dentry *old_dentry, unsigned int flags) { int err; + struct ubifs_info *c = old_dir->i_sb->s_fs_info; if (flags & ~(RENAME_NOREPLACE | RENAME_WHITEOUT | RENAME_EXCHANGE)) return -EINVAL; - ubifs_assert(inode_is_locked(old_dir)); - ubifs_assert(inode_is_locked(new_dir)); + ubifs_assert(c, inode_is_locked(old_dir)); + ubifs_assert(c, inode_is_locked(new_dir)); err = fscrypt_prepare_rename(old_dir, old_dentry, new_dir, new_dentry, flags); @@ -1647,7 +1649,9 @@ const struct inode_operations ubifs_dir_inode_operations = { .rename = ubifs_rename, .setattr = ubifs_setattr, .getattr = ubifs_getattr, +#ifdef CONFIG_UBIFS_FS_XATTR .listxattr = ubifs_listxattr, +#endif #ifdef CONFIG_UBIFS_ATIME_SUPPORT .update_time = ubifs_update_time, #endif diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c index fd7eb6fe9090..1b78f2e09218 100644 --- a/fs/ubifs/file.c +++ b/fs/ubifs/file.c @@ -71,7 +71,7 @@ static int read_block(struct inode *inode, void *addr, unsigned int block, return err; } - ubifs_assert(le64_to_cpu(dn->ch.sqnum) > + ubifs_assert(c, le64_to_cpu(dn->ch.sqnum) > ubifs_inode(inode)->creat_sqnum); len = le32_to_cpu(dn->size); if (len <= 0 || len > UBIFS_BLOCK_SIZE) @@ -115,12 +115,13 @@ static int do_readpage(struct page *page) unsigned int block, beyond; struct ubifs_data_node *dn; struct inode *inode = page->mapping->host; + struct ubifs_info *c = inode->i_sb->s_fs_info; loff_t i_size = i_size_read(inode); dbg_gen("ino %lu, pg %lu, i_size %lld, flags %#lx", inode->i_ino, page->index, i_size, page->flags); - ubifs_assert(!PageChecked(page)); - ubifs_assert(!PagePrivate(page)); + ubifs_assert(c, !PageChecked(page)); + ubifs_assert(c, !PagePrivate(page)); addr = kmap(page); @@ -441,8 +442,8 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, int skipped_read = 0; struct page *page; - ubifs_assert(ubifs_inode(inode)->ui_size == inode->i_size); - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, ubifs_inode(inode)->ui_size == inode->i_size); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (unlikely(c->ro_error)) return -EROFS; @@ -481,7 +482,7 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, err = allocate_budget(c, page, ui, appending); if (unlikely(err)) { - ubifs_assert(err == -ENOSPC); + ubifs_assert(c, err == -ENOSPC); /* * If we skipped reading the page because we were going to * write all of it, then it is not up to date. @@ -498,7 +499,7 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, * everything and fall-back to slow-path. */ if (appending) { - ubifs_assert(mutex_is_locked(&ui->ui_mutex)); + ubifs_assert(c, mutex_is_locked(&ui->ui_mutex)); mutex_unlock(&ui->ui_mutex); } unlock_page(page); @@ -595,7 +596,7 @@ static int ubifs_write_end(struct file *file, struct address_space *mapping, * '__set_page_dirty_nobuffers()'. */ __mark_inode_dirty(inode, I_DIRTY_DATASYNC); - ubifs_assert(mutex_is_locked(&ui->ui_mutex)); + ubifs_assert(c, mutex_is_locked(&ui->ui_mutex)); mutex_unlock(&ui->ui_mutex); } @@ -648,7 +649,7 @@ static int populate_page(struct ubifs_info *c, struct page *page, dn = bu->buf + (bu->zbranch[nn].offs - offs); - ubifs_assert(le64_to_cpu(dn->ch.sqnum) > + ubifs_assert(c, le64_to_cpu(dn->ch.sqnum) > ubifs_inode(inode)->creat_sqnum); len = le32_to_cpu(dn->size); @@ -767,8 +768,8 @@ static int ubifs_do_bulk_read(struct ubifs_info *c, struct bu_info *bu, bu->buf_len = bu->zbranch[bu->cnt - 1].offs + bu->zbranch[bu->cnt - 1].len - bu->zbranch[0].offs; - ubifs_assert(bu->buf_len > 0); - ubifs_assert(bu->buf_len <= c->leb_size); + ubifs_assert(c, bu->buf_len > 0); + ubifs_assert(c, bu->buf_len <= c->leb_size); bu->buf = kmalloc(bu->buf_len, GFP_NOFS | __GFP_NOWARN); if (!bu->buf) goto out_bu_off; @@ -920,7 +921,7 @@ static int do_writepage(struct page *page, int len) #ifdef UBIFS_DEBUG struct ubifs_inode *ui = ubifs_inode(inode); spin_lock(&ui->ui_lock); - ubifs_assert(page->index <= ui->synced_i_size >> PAGE_SHIFT); + ubifs_assert(c, page->index <= ui->synced_i_size >> PAGE_SHIFT); spin_unlock(&ui->ui_lock); #endif @@ -949,7 +950,7 @@ static int do_writepage(struct page *page, int len) ubifs_ro_mode(c, err); } - ubifs_assert(PagePrivate(page)); + ubifs_assert(c, PagePrivate(page)); if (PageChecked(page)) release_new_page_budget(c); else @@ -1014,6 +1015,7 @@ static int do_writepage(struct page *page, int len) static int ubifs_writepage(struct page *page, struct writeback_control *wbc) { struct inode *inode = page->mapping->host; + struct ubifs_info *c = inode->i_sb->s_fs_info; struct ubifs_inode *ui = ubifs_inode(inode); loff_t i_size = i_size_read(inode), synced_i_size; pgoff_t end_index = i_size >> PAGE_SHIFT; @@ -1022,7 +1024,7 @@ static int ubifs_writepage(struct page *page, struct writeback_control *wbc) dbg_gen("ino %lu, pg %lu, pg flags %#lx", inode->i_ino, page->index, page->flags); - ubifs_assert(PagePrivate(page)); + ubifs_assert(c, PagePrivate(page)); /* Is the page fully outside @i_size? (truncate in progress) */ if (page->index > end_index || (page->index == end_index && !len)) { @@ -1167,7 +1169,7 @@ static int do_truncation(struct ubifs_info *c, struct inode *inode, * 'ubifs_jnl_truncate()' will see an already * truncated (and up to date) data node. */ - ubifs_assert(PagePrivate(page)); + ubifs_assert(c, PagePrivate(page)); clear_page_dirty_for_io(page); if (UBIFS_BLOCKS_PER_PAGE_SHIFT) @@ -1303,7 +1305,7 @@ static void ubifs_invalidatepage(struct page *page, unsigned int offset, struct inode *inode = page->mapping->host; struct ubifs_info *c = inode->i_sb->s_fs_info; - ubifs_assert(PagePrivate(page)); + ubifs_assert(c, PagePrivate(page)); if (offset || length < PAGE_SIZE) /* Partial page remains dirty */ return; @@ -1365,11 +1367,10 @@ out: * granularity, they are not updated. This is an optimization. */ static inline int mctime_update_needed(const struct inode *inode, - const struct timespec *now) + const struct timespec64 *now) { - struct timespec64 now64 = timespec_to_timespec64(*now); - if (!timespec64_equal(&inode->i_mtime, &now64) || - !timespec64_equal(&inode->i_ctime, &now64)) + if (!timespec64_equal(&inode->i_mtime, now) || + !timespec64_equal(&inode->i_ctime, now)) return 1; return 0; } @@ -1425,7 +1426,7 @@ int ubifs_update_time(struct inode *inode, struct timespec64 *time, */ static int update_mctime(struct inode *inode) { - struct timespec now = timespec64_to_timespec(current_time(inode)); + struct timespec64 now = current_time(inode); struct ubifs_inode *ui = ubifs_inode(inode); struct ubifs_info *c = inode->i_sb->s_fs_info; @@ -1462,13 +1463,15 @@ static ssize_t ubifs_write_iter(struct kiocb *iocb, struct iov_iter *from) static int ubifs_set_page_dirty(struct page *page) { int ret; + struct inode *inode = page->mapping->host; + struct ubifs_info *c = inode->i_sb->s_fs_info; ret = __set_page_dirty_nobuffers(page); /* * An attempt to dirty a page without budgeting for it - should not * happen. */ - ubifs_assert(ret == 0); + ubifs_assert(c, ret == 0); return ret; } @@ -1497,14 +1500,17 @@ static int ubifs_migrate_page(struct address_space *mapping, static int ubifs_releasepage(struct page *page, gfp_t unused_gfp_flags) { + struct inode *inode = page->mapping->host; + struct ubifs_info *c = inode->i_sb->s_fs_info; + /* * An attempt to release a dirty page without budgeting for it - should * not happen. */ if (PageWriteback(page)) return 0; - ubifs_assert(PagePrivate(page)); - ubifs_assert(0); + ubifs_assert(c, PagePrivate(page)); + ubifs_assert(c, 0); ClearPagePrivate(page); ClearPageChecked(page); return 1; @@ -1519,13 +1525,13 @@ static vm_fault_t ubifs_vm_page_mkwrite(struct vm_fault *vmf) struct page *page = vmf->page; struct inode *inode = file_inode(vmf->vma->vm_file); struct ubifs_info *c = inode->i_sb->s_fs_info; - struct timespec now = timespec64_to_timespec(current_time(inode)); + struct timespec64 now = current_time(inode); struct ubifs_budget_req req = { .new_page = 1 }; int err, update_time; dbg_gen("ino %lu, pg %lu, i_size %lld", inode->i_ino, page->index, i_size_read(inode)); - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (unlikely(c->ro_error)) return VM_FAULT_SIGBUS; /* -EROFS */ @@ -1654,7 +1660,9 @@ const struct address_space_operations ubifs_file_address_operations = { const struct inode_operations ubifs_file_inode_operations = { .setattr = ubifs_setattr, .getattr = ubifs_getattr, +#ifdef CONFIG_UBIFS_FS_XATTR .listxattr = ubifs_listxattr, +#endif #ifdef CONFIG_UBIFS_ATIME_SUPPORT .update_time = ubifs_update_time, #endif @@ -1664,7 +1672,9 @@ const struct inode_operations ubifs_symlink_inode_operations = { .get_link = ubifs_get_link, .setattr = ubifs_setattr, .getattr = ubifs_getattr, +#ifdef CONFIG_UBIFS_FS_XATTR .listxattr = ubifs_listxattr, +#endif #ifdef CONFIG_UBIFS_ATIME_SUPPORT .update_time = ubifs_update_time, #endif diff --git a/arch/arm/mach-uniphier/Makefile b/fs/ubifs/file.h index e69de29bb2d1..e69de29bb2d1 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/fs/ubifs/file.h diff --git a/fs/ubifs/find.c b/fs/ubifs/find.c index 9571616b5dda..f9646835b026 100644 --- a/fs/ubifs/find.c +++ b/fs/ubifs/find.c @@ -183,18 +183,18 @@ static const struct ubifs_lprops *scan_for_dirty(struct ubifs_info *c, &data); if (err) return ERR_PTR(err); - ubifs_assert(data.lnum >= c->main_first && data.lnum < c->leb_cnt); + ubifs_assert(c, data.lnum >= c->main_first && data.lnum < c->leb_cnt); c->lscan_lnum = data.lnum; lprops = ubifs_lpt_lookup_dirty(c, data.lnum); if (IS_ERR(lprops)) return lprops; - ubifs_assert(lprops->lnum == data.lnum); - ubifs_assert(lprops->free + lprops->dirty >= min_space); - ubifs_assert(lprops->dirty >= c->dead_wm || + ubifs_assert(c, lprops->lnum == data.lnum); + ubifs_assert(c, lprops->free + lprops->dirty >= min_space); + ubifs_assert(c, lprops->dirty >= c->dead_wm || (pick_free && lprops->free + lprops->dirty == c->leb_size)); - ubifs_assert(!(lprops->flags & LPROPS_TAKEN)); - ubifs_assert(!exclude_index || !(lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, !(lprops->flags & LPROPS_TAKEN)); + ubifs_assert(c, !exclude_index || !(lprops->flags & LPROPS_INDEX)); return lprops; } @@ -315,7 +315,7 @@ int ubifs_find_dirty_leb(struct ubifs_info *c, struct ubifs_lprops *ret_lp, lp = idx_lp; if (lp) { - ubifs_assert(lp->free + lp->dirty >= c->dead_wm); + ubifs_assert(c, lp->free + lp->dirty >= c->dead_wm); goto found; } @@ -326,7 +326,7 @@ int ubifs_find_dirty_leb(struct ubifs_info *c, struct ubifs_lprops *ret_lp, err = PTR_ERR(lp); goto out; } - ubifs_assert(lp->dirty >= c->dead_wm || + ubifs_assert(c, lp->dirty >= c->dead_wm || (pick_free && lp->free + lp->dirty == c->leb_size)); found: @@ -462,15 +462,15 @@ const struct ubifs_lprops *do_find_free_space(struct ubifs_info *c, &data); if (err) return ERR_PTR(err); - ubifs_assert(data.lnum >= c->main_first && data.lnum < c->leb_cnt); + ubifs_assert(c, data.lnum >= c->main_first && data.lnum < c->leb_cnt); c->lscan_lnum = data.lnum; lprops = ubifs_lpt_lookup_dirty(c, data.lnum); if (IS_ERR(lprops)) return lprops; - ubifs_assert(lprops->lnum == data.lnum); - ubifs_assert(lprops->free >= min_space); - ubifs_assert(!(lprops->flags & LPROPS_TAKEN)); - ubifs_assert(!(lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, lprops->lnum == data.lnum); + ubifs_assert(c, lprops->free >= min_space); + ubifs_assert(c, !(lprops->flags & LPROPS_TAKEN)); + ubifs_assert(c, !(lprops->flags & LPROPS_INDEX)); return lprops; } @@ -574,7 +574,7 @@ int ubifs_find_free_space(struct ubifs_info *c, int min_space, int *offs, } dbg_find("found LEB %d, free %d", lnum, c->leb_size - *offs); - ubifs_assert(*offs <= c->leb_size - min_space); + ubifs_assert(c, *offs <= c->leb_size - min_space); return lnum; out: @@ -642,15 +642,15 @@ static const struct ubifs_lprops *scan_for_leb_for_idx(struct ubifs_info *c) &data); if (err) return ERR_PTR(err); - ubifs_assert(data.lnum >= c->main_first && data.lnum < c->leb_cnt); + ubifs_assert(c, data.lnum >= c->main_first && data.lnum < c->leb_cnt); c->lscan_lnum = data.lnum; lprops = ubifs_lpt_lookup_dirty(c, data.lnum); if (IS_ERR(lprops)) return lprops; - ubifs_assert(lprops->lnum == data.lnum); - ubifs_assert(lprops->free + lprops->dirty == c->leb_size); - ubifs_assert(!(lprops->flags & LPROPS_TAKEN)); - ubifs_assert(!(lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, lprops->lnum == data.lnum); + ubifs_assert(c, lprops->free + lprops->dirty == c->leb_size); + ubifs_assert(c, !(lprops->flags & LPROPS_TAKEN)); + ubifs_assert(c, !(lprops->flags & LPROPS_INDEX)); return lprops; } @@ -690,7 +690,7 @@ int ubifs_find_free_leb_for_idx(struct ubifs_info *c) */ if (c->in_a_category_cnt != c->main_lebs || c->lst.empty_lebs - c->lst.taken_empty_lebs > 0) { - ubifs_assert(c->freeable_cnt == 0); + ubifs_assert(c, c->freeable_cnt == 0); lprops = scan_for_leb_for_idx(c); if (IS_ERR(lprops)) { err = PTR_ERR(lprops); @@ -750,10 +750,7 @@ static int cmp_dirty_idx(const struct ubifs_lprops **a, static void swap_dirty_idx(struct ubifs_lprops **a, struct ubifs_lprops **b, int size) { - struct ubifs_lprops *t = *a; - - *a = *b; - *b = t; + swap(*a, *b); } /** @@ -870,15 +867,15 @@ static int find_dirty_idx_leb(struct ubifs_info *c) if (err) return err; found: - ubifs_assert(data.lnum >= c->main_first && data.lnum < c->leb_cnt); + ubifs_assert(c, data.lnum >= c->main_first && data.lnum < c->leb_cnt); c->lscan_lnum = data.lnum; lprops = ubifs_lpt_lookup_dirty(c, data.lnum); if (IS_ERR(lprops)) return PTR_ERR(lprops); - ubifs_assert(lprops->lnum == data.lnum); - ubifs_assert(lprops->free + lprops->dirty >= c->min_idx_node_sz); - ubifs_assert(!(lprops->flags & LPROPS_TAKEN)); - ubifs_assert((lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, lprops->lnum == data.lnum); + ubifs_assert(c, lprops->free + lprops->dirty >= c->min_idx_node_sz); + ubifs_assert(c, !(lprops->flags & LPROPS_TAKEN)); + ubifs_assert(c, (lprops->flags & LPROPS_INDEX)); dbg_find("found dirty LEB %d, free %d, dirty %d, flags %#x", lprops->lnum, lprops->free, lprops->dirty, lprops->flags); @@ -947,8 +944,8 @@ static int find_dirtiest_idx_leb(struct ubifs_info *c) } dbg_find("LEB %d, dirty %d and free %d flags %#x", lp->lnum, lp->dirty, lp->free, lp->flags); - ubifs_assert(lp->flags & LPROPS_TAKEN); - ubifs_assert(lp->flags & LPROPS_INDEX); + ubifs_assert(c, lp->flags & LPROPS_TAKEN); + ubifs_assert(c, lp->flags & LPROPS_INDEX); return lnum; } diff --git a/fs/ubifs/gc.c b/fs/ubifs/gc.c index a03a47cf880d..d2680e0b4a36 100644 --- a/fs/ubifs/gc.c +++ b/fs/ubifs/gc.c @@ -83,7 +83,7 @@ static int switch_gc_head(struct ubifs_info *c) int err, gc_lnum = c->gc_lnum; struct ubifs_wbuf *wbuf = &c->jheads[GCHD].wbuf; - ubifs_assert(gc_lnum != -1); + ubifs_assert(c, gc_lnum != -1); dbg_gc("switch GC head from LEB %d:%d to LEB %d (waste %d bytes)", wbuf->lnum, wbuf->offs + wbuf->used, gc_lnum, c->leb_size - wbuf->offs - wbuf->used); @@ -131,10 +131,10 @@ static int data_nodes_cmp(void *priv, struct list_head *a, struct list_head *b) sa = list_entry(a, struct ubifs_scan_node, list); sb = list_entry(b, struct ubifs_scan_node, list); - ubifs_assert(key_type(c, &sa->key) == UBIFS_DATA_KEY); - ubifs_assert(key_type(c, &sb->key) == UBIFS_DATA_KEY); - ubifs_assert(sa->type == UBIFS_DATA_NODE); - ubifs_assert(sb->type == UBIFS_DATA_NODE); + ubifs_assert(c, key_type(c, &sa->key) == UBIFS_DATA_KEY); + ubifs_assert(c, key_type(c, &sb->key) == UBIFS_DATA_KEY); + ubifs_assert(c, sa->type == UBIFS_DATA_NODE); + ubifs_assert(c, sb->type == UBIFS_DATA_NODE); inuma = key_inum(c, &sa->key); inumb = key_inum(c, &sb->key); @@ -175,9 +175,9 @@ static int nondata_nodes_cmp(void *priv, struct list_head *a, sa = list_entry(a, struct ubifs_scan_node, list); sb = list_entry(b, struct ubifs_scan_node, list); - ubifs_assert(key_type(c, &sa->key) != UBIFS_DATA_KEY && + ubifs_assert(c, key_type(c, &sa->key) != UBIFS_DATA_KEY && key_type(c, &sb->key) != UBIFS_DATA_KEY); - ubifs_assert(sa->type != UBIFS_DATA_NODE && + ubifs_assert(c, sa->type != UBIFS_DATA_NODE && sb->type != UBIFS_DATA_NODE); /* Inodes go before directory entries */ @@ -189,13 +189,13 @@ static int nondata_nodes_cmp(void *priv, struct list_head *a, if (sb->type == UBIFS_INO_NODE) return 1; - ubifs_assert(key_type(c, &sa->key) == UBIFS_DENT_KEY || + ubifs_assert(c, key_type(c, &sa->key) == UBIFS_DENT_KEY || key_type(c, &sa->key) == UBIFS_XENT_KEY); - ubifs_assert(key_type(c, &sb->key) == UBIFS_DENT_KEY || + ubifs_assert(c, key_type(c, &sb->key) == UBIFS_DENT_KEY || key_type(c, &sb->key) == UBIFS_XENT_KEY); - ubifs_assert(sa->type == UBIFS_DENT_NODE || + ubifs_assert(c, sa->type == UBIFS_DENT_NODE || sa->type == UBIFS_XENT_NODE); - ubifs_assert(sb->type == UBIFS_DENT_NODE || + ubifs_assert(c, sb->type == UBIFS_DENT_NODE || sb->type == UBIFS_XENT_NODE); inuma = key_inum(c, &sa->key); @@ -250,7 +250,7 @@ static int sort_nodes(struct ubifs_info *c, struct ubifs_scan_leb *sleb, /* Separate data nodes and non-data nodes */ list_for_each_entry_safe(snod, tmp, &sleb->nodes, list) { - ubifs_assert(snod->type == UBIFS_INO_NODE || + ubifs_assert(c, snod->type == UBIFS_INO_NODE || snod->type == UBIFS_DATA_NODE || snod->type == UBIFS_DENT_NODE || snod->type == UBIFS_XENT_NODE || @@ -266,7 +266,7 @@ static int sort_nodes(struct ubifs_info *c, struct ubifs_scan_leb *sleb, continue; } - ubifs_assert(key_type(c, &snod->key) == UBIFS_DATA_KEY || + ubifs_assert(c, key_type(c, &snod->key) == UBIFS_DATA_KEY || key_type(c, &snod->key) == UBIFS_INO_KEY || key_type(c, &snod->key) == UBIFS_DENT_KEY || key_type(c, &snod->key) == UBIFS_XENT_KEY); @@ -469,21 +469,21 @@ int ubifs_garbage_collect_leb(struct ubifs_info *c, struct ubifs_lprops *lp) struct ubifs_wbuf *wbuf = &c->jheads[GCHD].wbuf; int err = 0, lnum = lp->lnum; - ubifs_assert(c->gc_lnum != -1 || wbuf->offs + wbuf->used == 0 || + ubifs_assert(c, c->gc_lnum != -1 || wbuf->offs + wbuf->used == 0 || c->need_recovery); - ubifs_assert(c->gc_lnum != lnum); - ubifs_assert(wbuf->lnum != lnum); + ubifs_assert(c, c->gc_lnum != lnum); + ubifs_assert(c, wbuf->lnum != lnum); if (lp->free + lp->dirty == c->leb_size) { /* Special case - a free LEB */ dbg_gc("LEB %d is free, return it", lp->lnum); - ubifs_assert(!(lp->flags & LPROPS_INDEX)); + ubifs_assert(c, !(lp->flags & LPROPS_INDEX)); if (lp->free != c->leb_size) { /* * Write buffers must be sync'd before unmapping * freeable LEBs, because one of them may contain data - * which obsoletes something in 'lp->pnum'. + * which obsoletes something in 'lp->lnum'. */ err = gc_sync_wbufs(c); if (err) @@ -513,7 +513,7 @@ int ubifs_garbage_collect_leb(struct ubifs_info *c, struct ubifs_lprops *lp) if (IS_ERR(sleb)) return PTR_ERR(sleb); - ubifs_assert(!list_empty(&sleb->nodes)); + ubifs_assert(c, !list_empty(&sleb->nodes)); snod = list_entry(sleb->nodes.next, struct ubifs_scan_node, list); if (snod->type == UBIFS_IDX_NODE) { @@ -525,7 +525,7 @@ int ubifs_garbage_collect_leb(struct ubifs_info *c, struct ubifs_lprops *lp) struct ubifs_idx_node *idx = snod->node; int level = le16_to_cpu(idx->level); - ubifs_assert(snod->type == UBIFS_IDX_NODE); + ubifs_assert(c, snod->type == UBIFS_IDX_NODE); key_read(c, ubifs_idx_key(c, idx), &snod->key); err = ubifs_dirty_idx_node(c, &snod->key, level, lnum, snod->offs); @@ -648,7 +648,7 @@ int ubifs_garbage_collect(struct ubifs_info *c, int anyway) struct ubifs_wbuf *wbuf = &c->jheads[GCHD].wbuf; ubifs_assert_cmt_locked(c); - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (ubifs_gc_should_commit(c)) return -EAGAIN; @@ -661,7 +661,7 @@ int ubifs_garbage_collect(struct ubifs_info *c, int anyway) } /* We expect the write-buffer to be empty on entry */ - ubifs_assert(!wbuf->used); + ubifs_assert(c, !wbuf->used); for (i = 0; ; i++) { int space_before, space_after; @@ -752,7 +752,7 @@ int ubifs_garbage_collect(struct ubifs_info *c, int anyway) continue; } - ubifs_assert(ret == LEB_RETAINED); + ubifs_assert(c, ret == LEB_RETAINED); space_after = c->leb_size - wbuf->offs - wbuf->used; dbg_gc("LEB %d retained, freed %d bytes", lp.lnum, space_after - space_before); @@ -812,8 +812,8 @@ out_unlock: return ret; out: - ubifs_assert(ret < 0); - ubifs_assert(ret != -ENOSPC && ret != -EAGAIN); + ubifs_assert(c, ret < 0); + ubifs_assert(c, ret != -ENOSPC && ret != -EAGAIN); ubifs_wbuf_sync_nolock(wbuf); ubifs_ro_mode(c, ret); mutex_unlock(&wbuf->io_mutex); @@ -848,8 +848,8 @@ int ubifs_gc_start_commit(struct ubifs_info *c) lp = ubifs_fast_find_freeable(c); if (!lp) break; - ubifs_assert(!(lp->flags & LPROPS_TAKEN)); - ubifs_assert(!(lp->flags & LPROPS_INDEX)); + ubifs_assert(c, !(lp->flags & LPROPS_TAKEN)); + ubifs_assert(c, !(lp->flags & LPROPS_INDEX)); err = ubifs_leb_unmap(c, lp->lnum); if (err) goto out; @@ -858,8 +858,8 @@ int ubifs_gc_start_commit(struct ubifs_info *c) err = PTR_ERR(lp); goto out; } - ubifs_assert(!(lp->flags & LPROPS_TAKEN)); - ubifs_assert(!(lp->flags & LPROPS_INDEX)); + ubifs_assert(c, !(lp->flags & LPROPS_TAKEN)); + ubifs_assert(c, !(lp->flags & LPROPS_INDEX)); } /* Mark GC'd index LEBs OK to unmap after this commit finishes */ @@ -880,8 +880,8 @@ int ubifs_gc_start_commit(struct ubifs_info *c) err = -ENOMEM; goto out; } - ubifs_assert(!(lp->flags & LPROPS_TAKEN)); - ubifs_assert(lp->flags & LPROPS_INDEX); + ubifs_assert(c, !(lp->flags & LPROPS_TAKEN)); + ubifs_assert(c, lp->flags & LPROPS_INDEX); /* Don't release the LEB until after the next commit */ flags = (lp->flags | LPROPS_TAKEN) ^ LPROPS_INDEX; lp = ubifs_change_lp(c, lp, c->leb_size, 0, flags, 1); @@ -890,8 +890,8 @@ int ubifs_gc_start_commit(struct ubifs_info *c) kfree(idx_gc); goto out; } - ubifs_assert(lp->flags & LPROPS_TAKEN); - ubifs_assert(!(lp->flags & LPROPS_INDEX)); + ubifs_assert(c, lp->flags & LPROPS_TAKEN); + ubifs_assert(c, !(lp->flags & LPROPS_INDEX)); idx_gc->lnum = lp->lnum; idx_gc->unmap = 1; list_add(&idx_gc->list, &c->idx_gc); diff --git a/fs/ubifs/io.c b/fs/ubifs/io.c index fe77e9625e84..099bec94b820 100644 --- a/fs/ubifs/io.c +++ b/fs/ubifs/io.c @@ -119,7 +119,7 @@ int ubifs_leb_write(struct ubifs_info *c, int lnum, const void *buf, int offs, { int err; - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (c->ro_error) return -EROFS; if (!dbg_is_tst_rcvry(c)) @@ -139,7 +139,7 @@ int ubifs_leb_change(struct ubifs_info *c, int lnum, const void *buf, int len) { int err; - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (c->ro_error) return -EROFS; if (!dbg_is_tst_rcvry(c)) @@ -159,7 +159,7 @@ int ubifs_leb_unmap(struct ubifs_info *c, int lnum) { int err; - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (c->ro_error) return -EROFS; if (!dbg_is_tst_rcvry(c)) @@ -178,7 +178,7 @@ int ubifs_leb_map(struct ubifs_info *c, int lnum) { int err; - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (c->ro_error) return -EROFS; if (!dbg_is_tst_rcvry(c)) @@ -241,8 +241,8 @@ int ubifs_check_node(const struct ubifs_info *c, const void *buf, int lnum, uint32_t crc, node_crc, magic; const struct ubifs_ch *ch = buf; - ubifs_assert(lnum >= 0 && lnum < c->leb_cnt && offs >= 0); - ubifs_assert(!(offs & 7) && offs < c->leb_size); + ubifs_assert(c, lnum >= 0 && lnum < c->leb_cnt && offs >= 0); + ubifs_assert(c, !(offs & 7) && offs < c->leb_size); magic = le32_to_cpu(ch->magic); if (magic != UBIFS_NODE_MAGIC) { @@ -319,7 +319,7 @@ void ubifs_pad(const struct ubifs_info *c, void *buf, int pad) { uint32_t crc; - ubifs_assert(pad >= 0 && !(pad & 7)); + ubifs_assert(c, pad >= 0 && !(pad & 7)); if (pad >= UBIFS_PAD_NODE_SZ) { struct ubifs_ch *ch = buf; @@ -382,7 +382,7 @@ void ubifs_prepare_node(struct ubifs_info *c, void *node, int len, int pad) struct ubifs_ch *ch = node; unsigned long long sqnum = next_sqnum(c); - ubifs_assert(len >= UBIFS_CH_SZ); + ubifs_assert(c, len >= UBIFS_CH_SZ); ch->magic = cpu_to_le32(UBIFS_NODE_MAGIC); ch->len = cpu_to_le32(len); @@ -415,7 +415,7 @@ void ubifs_prep_grp_node(struct ubifs_info *c, void *node, int len, int last) struct ubifs_ch *ch = node; unsigned long long sqnum = next_sqnum(c); - ubifs_assert(len >= UBIFS_CH_SZ); + ubifs_assert(c, len >= UBIFS_CH_SZ); ch->magic = cpu_to_le32(UBIFS_NODE_MAGIC); ch->len = cpu_to_le32(len); @@ -448,9 +448,10 @@ static enum hrtimer_restart wbuf_timer_callback_nolock(struct hrtimer *timer) /** * new_wbuf_timer - start new write-buffer timer. + * @c: UBIFS file-system description object * @wbuf: write-buffer descriptor */ -static void new_wbuf_timer_nolock(struct ubifs_wbuf *wbuf) +static void new_wbuf_timer_nolock(struct ubifs_info *c, struct ubifs_wbuf *wbuf) { ktime_t softlimit = ms_to_ktime(dirty_writeback_interval * 10); unsigned long long delta = dirty_writeback_interval; @@ -458,8 +459,8 @@ static void new_wbuf_timer_nolock(struct ubifs_wbuf *wbuf) /* centi to milli, milli to nano, then 10% */ delta *= 10ULL * NSEC_PER_MSEC / 10ULL; - ubifs_assert(!hrtimer_active(&wbuf->timer)); - ubifs_assert(delta <= ULONG_MAX); + ubifs_assert(c, !hrtimer_active(&wbuf->timer)); + ubifs_assert(c, delta <= ULONG_MAX); if (wbuf->no_timer) return; @@ -508,14 +509,14 @@ int ubifs_wbuf_sync_nolock(struct ubifs_wbuf *wbuf) dbg_io("LEB %d:%d, %d bytes, jhead %s", wbuf->lnum, wbuf->offs, wbuf->used, dbg_jhead(wbuf->jhead)); - ubifs_assert(!(wbuf->avail & 7)); - ubifs_assert(wbuf->offs + wbuf->size <= c->leb_size); - ubifs_assert(wbuf->size >= c->min_io_size); - ubifs_assert(wbuf->size <= c->max_write_size); - ubifs_assert(wbuf->size % c->min_io_size == 0); - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !(wbuf->avail & 7)); + ubifs_assert(c, wbuf->offs + wbuf->size <= c->leb_size); + ubifs_assert(c, wbuf->size >= c->min_io_size); + ubifs_assert(c, wbuf->size <= c->max_write_size); + ubifs_assert(c, wbuf->size % c->min_io_size == 0); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (c->leb_size - wbuf->offs >= c->max_write_size) - ubifs_assert(!((wbuf->offs + wbuf->size) % c->max_write_size)); + ubifs_assert(c, !((wbuf->offs + wbuf->size) % c->max_write_size)); if (c->ro_error) return -EROFS; @@ -576,11 +577,11 @@ int ubifs_wbuf_seek_nolock(struct ubifs_wbuf *wbuf, int lnum, int offs) const struct ubifs_info *c = wbuf->c; dbg_io("LEB %d:%d, jhead %s", lnum, offs, dbg_jhead(wbuf->jhead)); - ubifs_assert(lnum >= 0 && lnum < c->leb_cnt); - ubifs_assert(offs >= 0 && offs <= c->leb_size); - ubifs_assert(offs % c->min_io_size == 0 && !(offs & 7)); - ubifs_assert(lnum != wbuf->lnum); - ubifs_assert(wbuf->used == 0); + ubifs_assert(c, lnum >= 0 && lnum < c->leb_cnt); + ubifs_assert(c, offs >= 0 && offs <= c->leb_size); + ubifs_assert(c, offs % c->min_io_size == 0 && !(offs & 7)); + ubifs_assert(c, lnum != wbuf->lnum); + ubifs_assert(c, wbuf->used == 0); spin_lock(&wbuf->lock); wbuf->lnum = lnum; @@ -610,7 +611,7 @@ int ubifs_bg_wbufs_sync(struct ubifs_info *c) { int err, i; - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (!c->need_wbuf_sync) return 0; c->need_wbuf_sync = 0; @@ -686,18 +687,18 @@ int ubifs_wbuf_write_nolock(struct ubifs_wbuf *wbuf, void *buf, int len) dbg_io("%d bytes (%s) to jhead %s wbuf at LEB %d:%d", len, dbg_ntype(((struct ubifs_ch *)buf)->node_type), dbg_jhead(wbuf->jhead), wbuf->lnum, wbuf->offs + wbuf->used); - ubifs_assert(len > 0 && wbuf->lnum >= 0 && wbuf->lnum < c->leb_cnt); - ubifs_assert(wbuf->offs >= 0 && wbuf->offs % c->min_io_size == 0); - ubifs_assert(!(wbuf->offs & 7) && wbuf->offs <= c->leb_size); - ubifs_assert(wbuf->avail > 0 && wbuf->avail <= wbuf->size); - ubifs_assert(wbuf->size >= c->min_io_size); - ubifs_assert(wbuf->size <= c->max_write_size); - ubifs_assert(wbuf->size % c->min_io_size == 0); - ubifs_assert(mutex_is_locked(&wbuf->io_mutex)); - ubifs_assert(!c->ro_media && !c->ro_mount); - ubifs_assert(!c->space_fixup); + ubifs_assert(c, len > 0 && wbuf->lnum >= 0 && wbuf->lnum < c->leb_cnt); + ubifs_assert(c, wbuf->offs >= 0 && wbuf->offs % c->min_io_size == 0); + ubifs_assert(c, !(wbuf->offs & 7) && wbuf->offs <= c->leb_size); + ubifs_assert(c, wbuf->avail > 0 && wbuf->avail <= wbuf->size); + ubifs_assert(c, wbuf->size >= c->min_io_size); + ubifs_assert(c, wbuf->size <= c->max_write_size); + ubifs_assert(c, wbuf->size % c->min_io_size == 0); + ubifs_assert(c, mutex_is_locked(&wbuf->io_mutex)); + ubifs_assert(c, !c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->space_fixup); if (c->leb_size - wbuf->offs >= c->max_write_size) - ubifs_assert(!((wbuf->offs + wbuf->size) % c->max_write_size)); + ubifs_assert(c, !((wbuf->offs + wbuf->size) % c->max_write_size)); if (c->leb_size - wbuf->offs - wbuf->used < aligned_len) { err = -ENOSPC; @@ -834,7 +835,7 @@ exit: } if (wbuf->used) - new_wbuf_timer_nolock(wbuf); + new_wbuf_timer_nolock(c, wbuf); return 0; @@ -869,10 +870,10 @@ int ubifs_write_node(struct ubifs_info *c, void *buf, int len, int lnum, dbg_io("LEB %d:%d, %s, length %d (aligned %d)", lnum, offs, dbg_ntype(((struct ubifs_ch *)buf)->node_type), len, buf_len); - ubifs_assert(lnum >= 0 && lnum < c->leb_cnt && offs >= 0); - ubifs_assert(offs % c->min_io_size == 0 && offs < c->leb_size); - ubifs_assert(!c->ro_media && !c->ro_mount); - ubifs_assert(!c->space_fixup); + ubifs_assert(c, lnum >= 0 && lnum < c->leb_cnt && offs >= 0); + ubifs_assert(c, offs % c->min_io_size == 0 && offs < c->leb_size); + ubifs_assert(c, !c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->space_fixup); if (c->ro_error) return -EROFS; @@ -909,9 +910,9 @@ int ubifs_read_node_wbuf(struct ubifs_wbuf *wbuf, void *buf, int type, int len, dbg_io("LEB %d:%d, %s, length %d, jhead %s", lnum, offs, dbg_ntype(type), len, dbg_jhead(wbuf->jhead)); - ubifs_assert(wbuf && lnum >= 0 && lnum < c->leb_cnt && offs >= 0); - ubifs_assert(!(offs & 7) && offs < c->leb_size); - ubifs_assert(type >= 0 && type < UBIFS_NODE_TYPES_CNT); + ubifs_assert(c, wbuf && lnum >= 0 && lnum < c->leb_cnt && offs >= 0); + ubifs_assert(c, !(offs & 7) && offs < c->leb_size); + ubifs_assert(c, type >= 0 && type < UBIFS_NODE_TYPES_CNT); spin_lock(&wbuf->lock); overlap = (lnum == wbuf->lnum && offs + len > wbuf->offs); @@ -984,10 +985,10 @@ int ubifs_read_node(const struct ubifs_info *c, void *buf, int type, int len, struct ubifs_ch *ch = buf; dbg_io("LEB %d:%d, %s, length %d", lnum, offs, dbg_ntype(type), len); - ubifs_assert(lnum >= 0 && lnum < c->leb_cnt && offs >= 0); - ubifs_assert(len >= UBIFS_CH_SZ && offs + len <= c->leb_size); - ubifs_assert(!(offs & 7) && offs < c->leb_size); - ubifs_assert(type >= 0 && type < UBIFS_NODE_TYPES_CNT); + ubifs_assert(c, lnum >= 0 && lnum < c->leb_cnt && offs >= 0); + ubifs_assert(c, len >= UBIFS_CH_SZ && offs + len <= c->leb_size); + ubifs_assert(c, !(offs & 7) && offs < c->leb_size); + ubifs_assert(c, type >= 0 && type < UBIFS_NODE_TYPES_CNT); err = ubifs_leb_read(c, lnum, buf, offs, len, 0); if (err && err != -EBADMSG) diff --git a/fs/ubifs/journal.c b/fs/ubifs/journal.c index 07b4956e0425..802565a17733 100644 --- a/fs/ubifs/journal.c +++ b/fs/ubifs/journal.c @@ -111,7 +111,7 @@ static int reserve_space(struct ubifs_info *c, int jhead, int len) * better to try to allocate space at the ends of eraseblocks. This is * what the squeeze parameter does. */ - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); squeeze = (jhead == BASEHD); again: mutex_lock_nested(&wbuf->io_mutex, wbuf->jhead); @@ -215,7 +215,7 @@ out_unlock: out_return: /* An error occurred and the LEB has to be returned to lprops */ - ubifs_assert(err < 0); + ubifs_assert(c, err < 0); err1 = ubifs_return_leb(c, lnum); if (err1 && err == -EAGAIN) /* @@ -246,7 +246,7 @@ static int write_node(struct ubifs_info *c, int jhead, void *node, int len, { struct ubifs_wbuf *wbuf = &c->jheads[jhead].wbuf; - ubifs_assert(jhead != GCHD); + ubifs_assert(c, jhead != GCHD); *lnum = c->jheads[jhead].wbuf.lnum; *offs = c->jheads[jhead].wbuf.offs + c->jheads[jhead].wbuf.used; @@ -278,7 +278,7 @@ static int write_head(struct ubifs_info *c, int jhead, void *buf, int len, int err; struct ubifs_wbuf *wbuf = &c->jheads[jhead].wbuf; - ubifs_assert(jhead != GCHD); + ubifs_assert(c, jhead != GCHD); *lnum = c->jheads[jhead].wbuf.lnum; *offs = c->jheads[jhead].wbuf.offs + c->jheads[jhead].wbuf.used; @@ -317,6 +317,7 @@ again: down_read(&c->commit_sem); err = reserve_space(c, jhead, len); if (!err) + /* c->commit_sem will get released via finish_reservation(). */ return 0; up_read(&c->commit_sem); @@ -548,7 +549,7 @@ int ubifs_jnl_update(struct ubifs_info *c, const struct inode *dir, struct ubifs_ino_node *ino; union ubifs_key dent_key, ino_key; - ubifs_assert(mutex_is_locked(&host_ui->ui_mutex)); + ubifs_assert(c, mutex_is_locked(&host_ui->ui_mutex)); dlen = UBIFS_DENT_NODE_SZ + fname_len(nm) + 1; ilen = UBIFS_INO_NODE_SZ; @@ -664,6 +665,11 @@ int ubifs_jnl_update(struct ubifs_info *c, const struct inode *dir, spin_lock(&ui->ui_lock); ui->synced_i_size = ui->ui_size; spin_unlock(&ui->ui_lock); + if (xent) { + spin_lock(&host_ui->ui_lock); + host_ui->synced_i_size = host_ui->ui_size; + spin_unlock(&host_ui->ui_lock); + } mark_inode_clean(c, ui); mark_inode_clean(c, host_ui); return 0; @@ -707,7 +713,7 @@ int ubifs_jnl_write_data(struct ubifs_info *c, const struct inode *inode, dbg_jnlk(key, "ino %lu, blk %u, len %d, key ", (unsigned long)key_inum(c, key), key_block(c, key), len); - ubifs_assert(len <= UBIFS_BLOCK_SIZE); + ubifs_assert(c, len <= UBIFS_BLOCK_SIZE); if (encrypted) dlen += UBIFS_CIPHER_BLOCK_SIZE; @@ -738,7 +744,7 @@ int ubifs_jnl_write_data(struct ubifs_info *c, const struct inode *inode, out_len = compr_len = dlen - UBIFS_DATA_NODE_SZ; ubifs_compress(c, buf, len, &data->data, &compr_len, &compr_type); - ubifs_assert(compr_len <= UBIFS_BLOCK_SIZE); + ubifs_assert(c, compr_len <= UBIFS_BLOCK_SIZE); if (encrypted) { err = ubifs_encrypt(inode, data, compr_len, &out_len, key_block(c, key)); @@ -898,7 +904,7 @@ int ubifs_jnl_delete_inode(struct ubifs_info *c, const struct inode *inode) int err; struct ubifs_inode *ui = ubifs_inode(inode); - ubifs_assert(inode->i_nlink == 0); + ubifs_assert(c, inode->i_nlink == 0); if (ui->del_cmtno != c->cmt_no) /* A commit happened for sure */ @@ -953,10 +959,10 @@ int ubifs_jnl_xrename(struct ubifs_info *c, const struct inode *fst_dir, int twoparents = (fst_dir != snd_dir); void *p; - ubifs_assert(ubifs_inode(fst_dir)->data_len == 0); - ubifs_assert(ubifs_inode(snd_dir)->data_len == 0); - ubifs_assert(mutex_is_locked(&ubifs_inode(fst_dir)->ui_mutex)); - ubifs_assert(mutex_is_locked(&ubifs_inode(snd_dir)->ui_mutex)); + ubifs_assert(c, ubifs_inode(fst_dir)->data_len == 0); + ubifs_assert(c, ubifs_inode(snd_dir)->data_len == 0); + ubifs_assert(c, mutex_is_locked(&ubifs_inode(fst_dir)->ui_mutex)); + ubifs_assert(c, mutex_is_locked(&ubifs_inode(snd_dir)->ui_mutex)); dlen1 = UBIFS_DENT_NODE_SZ + fname_len(snd_nm) + 1; dlen2 = UBIFS_DENT_NODE_SZ + fname_len(fst_nm) + 1; @@ -1096,16 +1102,16 @@ int ubifs_jnl_rename(struct ubifs_info *c, const struct inode *old_dir, int move = (old_dir != new_dir); struct ubifs_inode *uninitialized_var(new_ui); - ubifs_assert(ubifs_inode(old_dir)->data_len == 0); - ubifs_assert(ubifs_inode(new_dir)->data_len == 0); - ubifs_assert(mutex_is_locked(&ubifs_inode(old_dir)->ui_mutex)); - ubifs_assert(mutex_is_locked(&ubifs_inode(new_dir)->ui_mutex)); + ubifs_assert(c, ubifs_inode(old_dir)->data_len == 0); + ubifs_assert(c, ubifs_inode(new_dir)->data_len == 0); + ubifs_assert(c, mutex_is_locked(&ubifs_inode(old_dir)->ui_mutex)); + ubifs_assert(c, mutex_is_locked(&ubifs_inode(new_dir)->ui_mutex)); dlen1 = UBIFS_DENT_NODE_SZ + fname_len(new_nm) + 1; dlen2 = UBIFS_DENT_NODE_SZ + fname_len(old_nm) + 1; if (new_inode) { new_ui = ubifs_inode(new_inode); - ubifs_assert(mutex_is_locked(&new_ui->ui_mutex)); + ubifs_assert(c, mutex_is_locked(&new_ui->ui_mutex)); ilen = UBIFS_INO_NODE_SZ; if (!last_reference) ilen += new_ui->data_len; @@ -1282,8 +1288,7 @@ static int truncate_data_node(const struct ubifs_info *c, const struct inode *in int *new_len) { void *buf; - int err, compr_type; - u32 dlen, out_len, old_dlen; + int err, dlen, compr_type, out_len, old_dlen; out_len = le32_to_cpu(dn->size); buf = kmalloc_array(out_len, WORST_COMPR_FACTOR, GFP_NOFS); @@ -1319,7 +1324,7 @@ static int truncate_data_node(const struct ubifs_info *c, const struct inode *in dn->compr_size = 0; } - ubifs_assert(out_len <= UBIFS_BLOCK_SIZE); + ubifs_assert(c, out_len <= UBIFS_BLOCK_SIZE); dn->compr_type = cpu_to_le16(compr_type); dn->size = cpu_to_le32(*new_len); *new_len = UBIFS_DATA_NODE_SZ + out_len; @@ -1358,9 +1363,9 @@ int ubifs_jnl_truncate(struct ubifs_info *c, const struct inode *inode, dbg_jnl("ino %lu, size %lld -> %lld", (unsigned long)inum, old_size, new_size); - ubifs_assert(!ui->data_len); - ubifs_assert(S_ISREG(inode->i_mode)); - ubifs_assert(mutex_is_locked(&ui->ui_mutex)); + ubifs_assert(c, !ui->data_len); + ubifs_assert(c, S_ISREG(inode->i_mode)); + ubifs_assert(c, mutex_is_locked(&ui->ui_mutex)); sz = UBIFS_TRUN_NODE_SZ + UBIFS_INO_NODE_SZ + UBIFS_MAX_DATA_NODE_SZ * WORST_COMPR_FACTOR; @@ -1388,7 +1393,16 @@ int ubifs_jnl_truncate(struct ubifs_info *c, const struct inode *inode, else if (err) goto out_free; else { - if (le32_to_cpu(dn->size) <= dlen) + int dn_len = le32_to_cpu(dn->size); + + if (dn_len <= 0 || dn_len > UBIFS_BLOCK_SIZE) { + ubifs_err(c, "bad data node (block %u, inode %lu)", + blk, inode->i_ino); + ubifs_dump_node(c, dn); + goto out_free; + } + + if (dn_len <= dlen) dlen = 0; /* Nothing to do */ else { err = truncate_data_node(c, inode, blk, dn, &dlen); @@ -1488,8 +1502,8 @@ int ubifs_jnl_delete_xattr(struct ubifs_info *c, const struct inode *host, int sync = IS_DIRSYNC(host); struct ubifs_inode *host_ui = ubifs_inode(host); - ubifs_assert(inode->i_nlink == 0); - ubifs_assert(mutex_is_locked(&host_ui->ui_mutex)); + ubifs_assert(c, inode->i_nlink == 0); + ubifs_assert(c, mutex_is_locked(&host_ui->ui_mutex)); /* * Since we are deleting the inode, we do not bother to attach any data @@ -1598,9 +1612,9 @@ int ubifs_jnl_change_xattr(struct ubifs_info *c, const struct inode *inode, int sync = IS_DIRSYNC(host); dbg_jnl("ino %lu, ino %lu", host->i_ino, inode->i_ino); - ubifs_assert(host->i_nlink > 0); - ubifs_assert(inode->i_nlink > 0); - ubifs_assert(mutex_is_locked(&host_ui->ui_mutex)); + ubifs_assert(c, host->i_nlink > 0); + ubifs_assert(c, inode->i_nlink > 0); + ubifs_assert(c, mutex_is_locked(&host_ui->ui_mutex)); len1 = UBIFS_INO_NODE_SZ + host_ui->data_len; len2 = UBIFS_INO_NODE_SZ + ubifs_inode(inode)->data_len; diff --git a/fs/ubifs/key.h b/fs/ubifs/key.h index b1f7c0caa3ac..2feff6cbbb77 100644 --- a/fs/ubifs/key.h +++ b/fs/ubifs/key.h @@ -161,8 +161,8 @@ static inline void dent_key_init(const struct ubifs_info *c, { uint32_t hash = c->key_hash(fname_name(nm), fname_len(nm)); - ubifs_assert(!(hash & ~UBIFS_S_KEY_HASH_MASK)); - ubifs_assert(!nm->hash && !nm->minor_hash); + ubifs_assert(c, !(hash & ~UBIFS_S_KEY_HASH_MASK)); + ubifs_assert(c, !nm->hash && !nm->minor_hash); key->u32[0] = inum; key->u32[1] = hash | (UBIFS_DENT_KEY << UBIFS_S_KEY_HASH_BITS); } @@ -179,7 +179,7 @@ static inline void dent_key_init_hash(const struct ubifs_info *c, union ubifs_key *key, ino_t inum, uint32_t hash) { - ubifs_assert(!(hash & ~UBIFS_S_KEY_HASH_MASK)); + ubifs_assert(c, !(hash & ~UBIFS_S_KEY_HASH_MASK)); key->u32[0] = inum; key->u32[1] = hash | (UBIFS_DENT_KEY << UBIFS_S_KEY_HASH_BITS); } @@ -198,7 +198,7 @@ static inline void dent_key_init_flash(const struct ubifs_info *c, void *k, union ubifs_key *key = k; uint32_t hash = c->key_hash(fname_name(nm), fname_len(nm)); - ubifs_assert(!(hash & ~UBIFS_S_KEY_HASH_MASK)); + ubifs_assert(c, !(hash & ~UBIFS_S_KEY_HASH_MASK)); key->j32[0] = cpu_to_le32(inum); key->j32[1] = cpu_to_le32(hash | (UBIFS_DENT_KEY << UBIFS_S_KEY_HASH_BITS)); @@ -231,7 +231,7 @@ static inline void xent_key_init(const struct ubifs_info *c, { uint32_t hash = c->key_hash(fname_name(nm), fname_len(nm)); - ubifs_assert(!(hash & ~UBIFS_S_KEY_HASH_MASK)); + ubifs_assert(c, !(hash & ~UBIFS_S_KEY_HASH_MASK)); key->u32[0] = inum; key->u32[1] = hash | (UBIFS_XENT_KEY << UBIFS_S_KEY_HASH_BITS); } @@ -249,7 +249,7 @@ static inline void xent_key_init_flash(const struct ubifs_info *c, void *k, union ubifs_key *key = k; uint32_t hash = c->key_hash(fname_name(nm), fname_len(nm)); - ubifs_assert(!(hash & ~UBIFS_S_KEY_HASH_MASK)); + ubifs_assert(c, !(hash & ~UBIFS_S_KEY_HASH_MASK)); key->j32[0] = cpu_to_le32(inum); key->j32[1] = cpu_to_le32(hash | (UBIFS_XENT_KEY << UBIFS_S_KEY_HASH_BITS)); @@ -280,7 +280,7 @@ static inline void data_key_init(const struct ubifs_info *c, union ubifs_key *key, ino_t inum, unsigned int block) { - ubifs_assert(!(block & ~UBIFS_S_KEY_BLOCK_MASK)); + ubifs_assert(c, !(block & ~UBIFS_S_KEY_BLOCK_MASK)); key->u32[0] = inum; key->u32[1] = block | (UBIFS_DATA_KEY << UBIFS_S_KEY_BLOCK_BITS); } diff --git a/fs/ubifs/log.c b/fs/ubifs/log.c index 7cffa120a750..86b0828f5499 100644 --- a/fs/ubifs/log.c +++ b/fs/ubifs/log.c @@ -132,7 +132,7 @@ void ubifs_add_bud(struct ubifs_info *c, struct ubifs_bud *bud) while (*p) { parent = *p; b = rb_entry(parent, struct ubifs_bud, rb); - ubifs_assert(bud->lnum != b->lnum); + ubifs_assert(c, bud->lnum != b->lnum); if (bud->lnum < b->lnum) p = &(*p)->rb_left; else @@ -145,7 +145,7 @@ void ubifs_add_bud(struct ubifs_info *c, struct ubifs_bud *bud) jhead = &c->jheads[bud->jhead]; list_add_tail(&bud->list, &jhead->buds_list); } else - ubifs_assert(c->replaying && c->ro_mount); + ubifs_assert(c, c->replaying && c->ro_mount); /* * Note, although this is a new bud, we anyway account this space now, @@ -189,7 +189,7 @@ int ubifs_add_bud_to_log(struct ubifs_info *c, int jhead, int lnum, int offs) } mutex_lock(&c->log_mutex); - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (c->ro_error) { err = -EROFS; goto out_unlock; @@ -244,7 +244,7 @@ int ubifs_add_bud_to_log(struct ubifs_info *c, int jhead, int lnum, int offs) if (c->lhead_offs > c->leb_size - c->ref_node_alsz) { c->lhead_lnum = ubifs_next_log_lnum(c, c->lhead_lnum); - ubifs_assert(c->lhead_lnum != c->ltail_lnum); + ubifs_assert(c, c->lhead_lnum != c->ltail_lnum); c->lhead_offs = 0; } @@ -301,7 +301,7 @@ static void remove_buds(struct ubifs_info *c) { struct rb_node *p; - ubifs_assert(list_empty(&c->old_buds)); + ubifs_assert(c, list_empty(&c->old_buds)); c->cmt_bud_bytes = 0; spin_lock(&c->buds_lock); p = rb_first(&c->buds); @@ -409,7 +409,7 @@ int ubifs_log_start_commit(struct ubifs_info *c, int *ltail_lnum) /* Switch to the next log LEB */ if (c->lhead_offs) { c->lhead_lnum = ubifs_next_log_lnum(c, c->lhead_lnum); - ubifs_assert(c->lhead_lnum != c->ltail_lnum); + ubifs_assert(c, c->lhead_lnum != c->ltail_lnum); c->lhead_offs = 0; } diff --git a/fs/ubifs/lprops.c b/fs/ubifs/lprops.c index f5a46844340c..fa8d775c9753 100644 --- a/fs/ubifs/lprops.c +++ b/fs/ubifs/lprops.c @@ -187,9 +187,9 @@ static int add_to_lpt_heap(struct ubifs_info *c, struct ubifs_lprops *lprops, /* Compare to some other LEB on the bottom of heap */ /* Pick a position kind of randomly */ cpos = (((size_t)lprops >> 4) & b) + b; - ubifs_assert(cpos >= b); - ubifs_assert(cpos < LPT_HEAP_SZ); - ubifs_assert(cpos < heap->cnt); + ubifs_assert(c, cpos >= b); + ubifs_assert(c, cpos < LPT_HEAP_SZ); + ubifs_assert(c, cpos < heap->cnt); val1 = get_heap_comp_val(lprops, cat); val2 = get_heap_comp_val(heap->arr[cpos], cat); @@ -230,8 +230,8 @@ static void remove_from_lpt_heap(struct ubifs_info *c, int hpos = lprops->hpos; heap = &c->lpt_heap[cat - 1]; - ubifs_assert(hpos >= 0 && hpos < heap->cnt); - ubifs_assert(heap->arr[hpos] == lprops); + ubifs_assert(c, hpos >= 0 && hpos < heap->cnt); + ubifs_assert(c, heap->arr[hpos] == lprops); heap->cnt -= 1; if (hpos < heap->cnt) { heap->arr[hpos] = heap->arr[heap->cnt]; @@ -296,13 +296,13 @@ void ubifs_add_to_cat(struct ubifs_info *c, struct ubifs_lprops *lprops, list_add(&lprops->list, &c->frdi_idx_list); break; default: - ubifs_assert(0); + ubifs_assert(c, 0); } lprops->flags &= ~LPROPS_CAT_MASK; lprops->flags |= cat; c->in_a_category_cnt += 1; - ubifs_assert(c->in_a_category_cnt <= c->main_lebs); + ubifs_assert(c, c->in_a_category_cnt <= c->main_lebs); } /** @@ -324,20 +324,20 @@ static void ubifs_remove_from_cat(struct ubifs_info *c, break; case LPROPS_FREEABLE: c->freeable_cnt -= 1; - ubifs_assert(c->freeable_cnt >= 0); + ubifs_assert(c, c->freeable_cnt >= 0); /* Fall through */ case LPROPS_UNCAT: case LPROPS_EMPTY: case LPROPS_FRDI_IDX: - ubifs_assert(!list_empty(&lprops->list)); + ubifs_assert(c, !list_empty(&lprops->list)); list_del(&lprops->list); break; default: - ubifs_assert(0); + ubifs_assert(c, 0); } c->in_a_category_cnt -= 1; - ubifs_assert(c->in_a_category_cnt >= 0); + ubifs_assert(c, c->in_a_category_cnt >= 0); } /** @@ -369,7 +369,7 @@ void ubifs_replace_cat(struct ubifs_info *c, struct ubifs_lprops *old_lprops, list_replace(&old_lprops->list, &new_lprops->list); break; default: - ubifs_assert(0); + ubifs_assert(c, 0); } } @@ -412,7 +412,7 @@ int ubifs_categorize_lprops(const struct ubifs_info *c, return LPROPS_UNCAT; if (lprops->free == c->leb_size) { - ubifs_assert(!(lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, !(lprops->flags & LPROPS_INDEX)); return LPROPS_EMPTY; } @@ -478,7 +478,7 @@ static void change_category(struct ubifs_info *c, struct ubifs_lprops *lprops) */ int ubifs_calc_dark(const struct ubifs_info *c, int spc) { - ubifs_assert(!(spc & 7)); + ubifs_assert(c, !(spc & 7)); if (spc < c->dark_wm) return spc; @@ -543,27 +543,27 @@ const struct ubifs_lprops *ubifs_change_lp(struct ubifs_info *c, dbg_lp("LEB %d, free %d, dirty %d, flags %d", lprops->lnum, free, dirty, flags); - ubifs_assert(mutex_is_locked(&c->lp_mutex)); - ubifs_assert(c->lst.empty_lebs >= 0 && + ubifs_assert(c, mutex_is_locked(&c->lp_mutex)); + ubifs_assert(c, c->lst.empty_lebs >= 0 && c->lst.empty_lebs <= c->main_lebs); - ubifs_assert(c->freeable_cnt >= 0); - ubifs_assert(c->freeable_cnt <= c->main_lebs); - ubifs_assert(c->lst.taken_empty_lebs >= 0); - ubifs_assert(c->lst.taken_empty_lebs <= c->lst.empty_lebs); - ubifs_assert(!(c->lst.total_free & 7) && !(c->lst.total_dirty & 7)); - ubifs_assert(!(c->lst.total_dead & 7) && !(c->lst.total_dark & 7)); - ubifs_assert(!(c->lst.total_used & 7)); - ubifs_assert(free == LPROPS_NC || free >= 0); - ubifs_assert(dirty == LPROPS_NC || dirty >= 0); + ubifs_assert(c, c->freeable_cnt >= 0); + ubifs_assert(c, c->freeable_cnt <= c->main_lebs); + ubifs_assert(c, c->lst.taken_empty_lebs >= 0); + ubifs_assert(c, c->lst.taken_empty_lebs <= c->lst.empty_lebs); + ubifs_assert(c, !(c->lst.total_free & 7) && !(c->lst.total_dirty & 7)); + ubifs_assert(c, !(c->lst.total_dead & 7) && !(c->lst.total_dark & 7)); + ubifs_assert(c, !(c->lst.total_used & 7)); + ubifs_assert(c, free == LPROPS_NC || free >= 0); + ubifs_assert(c, dirty == LPROPS_NC || dirty >= 0); if (!is_lprops_dirty(c, lprops)) { lprops = ubifs_lpt_lookup_dirty(c, lprops->lnum); if (IS_ERR(lprops)) return lprops; } else - ubifs_assert(lprops == ubifs_lpt_lookup_dirty(c, lprops->lnum)); + ubifs_assert(c, lprops == ubifs_lpt_lookup_dirty(c, lprops->lnum)); - ubifs_assert(!(lprops->free & 7) && !(lprops->dirty & 7)); + ubifs_assert(c, !(lprops->free & 7) && !(lprops->dirty & 7)); spin_lock(&c->space_lock); if ((lprops->flags & LPROPS_TAKEN) && lprops->free == c->leb_size) @@ -768,15 +768,15 @@ const struct ubifs_lprops *ubifs_fast_find_free(struct ubifs_info *c) struct ubifs_lprops *lprops; struct ubifs_lpt_heap *heap; - ubifs_assert(mutex_is_locked(&c->lp_mutex)); + ubifs_assert(c, mutex_is_locked(&c->lp_mutex)); heap = &c->lpt_heap[LPROPS_FREE - 1]; if (heap->cnt == 0) return NULL; lprops = heap->arr[0]; - ubifs_assert(!(lprops->flags & LPROPS_TAKEN)); - ubifs_assert(!(lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, !(lprops->flags & LPROPS_TAKEN)); + ubifs_assert(c, !(lprops->flags & LPROPS_INDEX)); return lprops; } @@ -791,15 +791,15 @@ const struct ubifs_lprops *ubifs_fast_find_empty(struct ubifs_info *c) { struct ubifs_lprops *lprops; - ubifs_assert(mutex_is_locked(&c->lp_mutex)); + ubifs_assert(c, mutex_is_locked(&c->lp_mutex)); if (list_empty(&c->empty_list)) return NULL; lprops = list_entry(c->empty_list.next, struct ubifs_lprops, list); - ubifs_assert(!(lprops->flags & LPROPS_TAKEN)); - ubifs_assert(!(lprops->flags & LPROPS_INDEX)); - ubifs_assert(lprops->free == c->leb_size); + ubifs_assert(c, !(lprops->flags & LPROPS_TAKEN)); + ubifs_assert(c, !(lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, lprops->free == c->leb_size); return lprops; } @@ -814,16 +814,16 @@ const struct ubifs_lprops *ubifs_fast_find_freeable(struct ubifs_info *c) { struct ubifs_lprops *lprops; - ubifs_assert(mutex_is_locked(&c->lp_mutex)); + ubifs_assert(c, mutex_is_locked(&c->lp_mutex)); if (list_empty(&c->freeable_list)) return NULL; lprops = list_entry(c->freeable_list.next, struct ubifs_lprops, list); - ubifs_assert(!(lprops->flags & LPROPS_TAKEN)); - ubifs_assert(!(lprops->flags & LPROPS_INDEX)); - ubifs_assert(lprops->free + lprops->dirty == c->leb_size); - ubifs_assert(c->freeable_cnt > 0); + ubifs_assert(c, !(lprops->flags & LPROPS_TAKEN)); + ubifs_assert(c, !(lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, lprops->free + lprops->dirty == c->leb_size); + ubifs_assert(c, c->freeable_cnt > 0); return lprops; } @@ -838,15 +838,15 @@ const struct ubifs_lprops *ubifs_fast_find_frdi_idx(struct ubifs_info *c) { struct ubifs_lprops *lprops; - ubifs_assert(mutex_is_locked(&c->lp_mutex)); + ubifs_assert(c, mutex_is_locked(&c->lp_mutex)); if (list_empty(&c->frdi_idx_list)) return NULL; lprops = list_entry(c->frdi_idx_list.next, struct ubifs_lprops, list); - ubifs_assert(!(lprops->flags & LPROPS_TAKEN)); - ubifs_assert((lprops->flags & LPROPS_INDEX)); - ubifs_assert(lprops->free + lprops->dirty == c->leb_size); + ubifs_assert(c, !(lprops->flags & LPROPS_TAKEN)); + ubifs_assert(c, (lprops->flags & LPROPS_INDEX)); + ubifs_assert(c, lprops->free + lprops->dirty == c->leb_size); return lprops; } @@ -1089,10 +1089,6 @@ static int scan_check_cb(struct ubifs_info *c, } } - buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); - if (!buf) - return -ENOMEM; - /* * After an unclean unmount, empty and freeable LEBs * may contain garbage - do not scan them. @@ -1111,6 +1107,10 @@ static int scan_check_cb(struct ubifs_info *c, return LPT_SCAN_CONTINUE; } + buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); + if (!buf) + return -ENOMEM; + sleb = ubifs_scan(c, lnum, 0, buf, 0); if (IS_ERR(sleb)) { ret = PTR_ERR(sleb); diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c index 8e99dad18880..31393370e334 100644 --- a/fs/ubifs/lpt.c +++ b/fs/ubifs/lpt.c @@ -225,21 +225,22 @@ static int calc_dflt_lpt_geom(struct ubifs_info *c, int *main_lebs, /** * pack_bits - pack bit fields end-to-end. + * @c: UBIFS file-system description object * @addr: address at which to pack (passed and next address returned) * @pos: bit position at which to pack (passed and next position returned) * @val: value to pack * @nrbits: number of bits of value to pack (1-32) */ -static void pack_bits(uint8_t **addr, int *pos, uint32_t val, int nrbits) +static void pack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, uint32_t val, int nrbits) { uint8_t *p = *addr; int b = *pos; - ubifs_assert(nrbits > 0); - ubifs_assert(nrbits <= 32); - ubifs_assert(*pos >= 0); - ubifs_assert(*pos < 8); - ubifs_assert((val >> nrbits) == 0 || nrbits == 32); + ubifs_assert(c, nrbits > 0); + ubifs_assert(c, nrbits <= 32); + ubifs_assert(c, *pos >= 0); + ubifs_assert(c, *pos < 8); + ubifs_assert(c, (val >> nrbits) == 0 || nrbits == 32); if (b) { *p |= ((uint8_t)val) << b; nrbits += b; @@ -274,13 +275,14 @@ static void pack_bits(uint8_t **addr, int *pos, uint32_t val, int nrbits) /** * ubifs_unpack_bits - unpack bit fields. + * @c: UBIFS file-system description object * @addr: address at which to unpack (passed and next address returned) * @pos: bit position at which to unpack (passed and next position returned) * @nrbits: number of bits of value to unpack (1-32) * * This functions returns the value unpacked. */ -uint32_t ubifs_unpack_bits(uint8_t **addr, int *pos, int nrbits) +uint32_t ubifs_unpack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, int nrbits) { const int k = 32 - nrbits; uint8_t *p = *addr; @@ -288,10 +290,10 @@ uint32_t ubifs_unpack_bits(uint8_t **addr, int *pos, int nrbits) uint32_t uninitialized_var(val); const int bytes = (nrbits + b + 7) >> 3; - ubifs_assert(nrbits > 0); - ubifs_assert(nrbits <= 32); - ubifs_assert(*pos >= 0); - ubifs_assert(*pos < 8); + ubifs_assert(c, nrbits > 0); + ubifs_assert(c, nrbits <= 32); + ubifs_assert(c, *pos >= 0); + ubifs_assert(c, *pos < 8); if (b) { switch (bytes) { case 2: @@ -337,7 +339,7 @@ uint32_t ubifs_unpack_bits(uint8_t **addr, int *pos, int nrbits) p += nrbits >> 3; *addr = p; *pos = b; - ubifs_assert((val >> nrbits) == 0 || nrbits - b == 32); + ubifs_assert(c, (val >> nrbits) == 0 || nrbits - b == 32); return val; } @@ -354,24 +356,24 @@ void ubifs_pack_pnode(struct ubifs_info *c, void *buf, int i, pos = 0; uint16_t crc; - pack_bits(&addr, &pos, UBIFS_LPT_PNODE, UBIFS_LPT_TYPE_BITS); + pack_bits(c, &addr, &pos, UBIFS_LPT_PNODE, UBIFS_LPT_TYPE_BITS); if (c->big_lpt) - pack_bits(&addr, &pos, pnode->num, c->pcnt_bits); + pack_bits(c, &addr, &pos, pnode->num, c->pcnt_bits); for (i = 0; i < UBIFS_LPT_FANOUT; i++) { - pack_bits(&addr, &pos, pnode->lprops[i].free >> 3, + pack_bits(c, &addr, &pos, pnode->lprops[i].free >> 3, c->space_bits); - pack_bits(&addr, &pos, pnode->lprops[i].dirty >> 3, + pack_bits(c, &addr, &pos, pnode->lprops[i].dirty >> 3, c->space_bits); if (pnode->lprops[i].flags & LPROPS_INDEX) - pack_bits(&addr, &pos, 1, 1); + pack_bits(c, &addr, &pos, 1, 1); else - pack_bits(&addr, &pos, 0, 1); + pack_bits(c, &addr, &pos, 0, 1); } crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, c->pnode_sz - UBIFS_LPT_CRC_BYTES); addr = buf; pos = 0; - pack_bits(&addr, &pos, crc, UBIFS_LPT_CRC_BITS); + pack_bits(c, &addr, &pos, crc, UBIFS_LPT_CRC_BITS); } /** @@ -387,23 +389,23 @@ void ubifs_pack_nnode(struct ubifs_info *c, void *buf, int i, pos = 0; uint16_t crc; - pack_bits(&addr, &pos, UBIFS_LPT_NNODE, UBIFS_LPT_TYPE_BITS); + pack_bits(c, &addr, &pos, UBIFS_LPT_NNODE, UBIFS_LPT_TYPE_BITS); if (c->big_lpt) - pack_bits(&addr, &pos, nnode->num, c->pcnt_bits); + pack_bits(c, &addr, &pos, nnode->num, c->pcnt_bits); for (i = 0; i < UBIFS_LPT_FANOUT; i++) { int lnum = nnode->nbranch[i].lnum; if (lnum == 0) lnum = c->lpt_last + 1; - pack_bits(&addr, &pos, lnum - c->lpt_first, c->lpt_lnum_bits); - pack_bits(&addr, &pos, nnode->nbranch[i].offs, + pack_bits(c, &addr, &pos, lnum - c->lpt_first, c->lpt_lnum_bits); + pack_bits(c, &addr, &pos, nnode->nbranch[i].offs, c->lpt_offs_bits); } crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, c->nnode_sz - UBIFS_LPT_CRC_BYTES); addr = buf; pos = 0; - pack_bits(&addr, &pos, crc, UBIFS_LPT_CRC_BITS); + pack_bits(c, &addr, &pos, crc, UBIFS_LPT_CRC_BITS); } /** @@ -419,16 +421,16 @@ void ubifs_pack_ltab(struct ubifs_info *c, void *buf, int i, pos = 0; uint16_t crc; - pack_bits(&addr, &pos, UBIFS_LPT_LTAB, UBIFS_LPT_TYPE_BITS); + pack_bits(c, &addr, &pos, UBIFS_LPT_LTAB, UBIFS_LPT_TYPE_BITS); for (i = 0; i < c->lpt_lebs; i++) { - pack_bits(&addr, &pos, ltab[i].free, c->lpt_spc_bits); - pack_bits(&addr, &pos, ltab[i].dirty, c->lpt_spc_bits); + pack_bits(c, &addr, &pos, ltab[i].free, c->lpt_spc_bits); + pack_bits(c, &addr, &pos, ltab[i].dirty, c->lpt_spc_bits); } crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, c->ltab_sz - UBIFS_LPT_CRC_BYTES); addr = buf; pos = 0; - pack_bits(&addr, &pos, crc, UBIFS_LPT_CRC_BITS); + pack_bits(c, &addr, &pos, crc, UBIFS_LPT_CRC_BITS); } /** @@ -443,14 +445,14 @@ void ubifs_pack_lsave(struct ubifs_info *c, void *buf, int *lsave) int i, pos = 0; uint16_t crc; - pack_bits(&addr, &pos, UBIFS_LPT_LSAVE, UBIFS_LPT_TYPE_BITS); + pack_bits(c, &addr, &pos, UBIFS_LPT_LSAVE, UBIFS_LPT_TYPE_BITS); for (i = 0; i < c->lsave_cnt; i++) - pack_bits(&addr, &pos, lsave[i], c->lnum_bits); + pack_bits(c, &addr, &pos, lsave[i], c->lnum_bits); crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, c->lsave_sz - UBIFS_LPT_CRC_BYTES); addr = buf; pos = 0; - pack_bits(&addr, &pos, crc, UBIFS_LPT_CRC_BITS); + pack_bits(c, &addr, &pos, crc, UBIFS_LPT_CRC_BITS); } /** @@ -465,7 +467,7 @@ void ubifs_add_lpt_dirt(struct ubifs_info *c, int lnum, int dirty) return; dbg_lp("LEB %d add %d to %d", lnum, dirty, c->ltab[lnum - c->lpt_first].dirty); - ubifs_assert(lnum >= c->lpt_first && lnum <= c->lpt_last); + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); c->ltab[lnum - c->lpt_first].dirty += dirty; } @@ -481,7 +483,7 @@ static void set_ltab(struct ubifs_info *c, int lnum, int free, int dirty) dbg_lp("LEB %d free %d dirty %d to %d %d", lnum, c->ltab[lnum - c->lpt_first].free, c->ltab[lnum - c->lpt_first].dirty, free, dirty); - ubifs_assert(lnum >= c->lpt_first && lnum <= c->lpt_last); + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); c->ltab[lnum - c->lpt_first].free = free; c->ltab[lnum - c->lpt_first].dirty = dirty; } @@ -639,7 +641,7 @@ int ubifs_create_dflt_lpt(struct ubifs_info *c, int *main_lebs, int lpt_first, goto out; } - ubifs_assert(!c->ltab); + ubifs_assert(c, !c->ltab); c->ltab = ltab; /* Needed by set_ltab */ /* Initialize LPT's own lprops */ @@ -918,7 +920,7 @@ static int check_lpt_crc(const struct ubifs_info *c, void *buf, int len) uint8_t *addr = buf; uint16_t crc, calc_crc; - crc = ubifs_unpack_bits(&addr, &pos, UBIFS_LPT_CRC_BITS); + crc = ubifs_unpack_bits(c, &addr, &pos, UBIFS_LPT_CRC_BITS); calc_crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, len - UBIFS_LPT_CRC_BYTES); if (crc != calc_crc) { @@ -944,7 +946,7 @@ static int check_lpt_type(const struct ubifs_info *c, uint8_t **addr, { int node_type; - node_type = ubifs_unpack_bits(addr, pos, UBIFS_LPT_TYPE_BITS); + node_type = ubifs_unpack_bits(c, addr, pos, UBIFS_LPT_TYPE_BITS); if (node_type != type) { ubifs_err(c, "invalid type (%d) in LPT node type %d", node_type, type); @@ -972,16 +974,16 @@ static int unpack_pnode(const struct ubifs_info *c, void *buf, if (err) return err; if (c->big_lpt) - pnode->num = ubifs_unpack_bits(&addr, &pos, c->pcnt_bits); + pnode->num = ubifs_unpack_bits(c, &addr, &pos, c->pcnt_bits); for (i = 0; i < UBIFS_LPT_FANOUT; i++) { struct ubifs_lprops * const lprops = &pnode->lprops[i]; - lprops->free = ubifs_unpack_bits(&addr, &pos, c->space_bits); + lprops->free = ubifs_unpack_bits(c, &addr, &pos, c->space_bits); lprops->free <<= 3; - lprops->dirty = ubifs_unpack_bits(&addr, &pos, c->space_bits); + lprops->dirty = ubifs_unpack_bits(c, &addr, &pos, c->space_bits); lprops->dirty <<= 3; - if (ubifs_unpack_bits(&addr, &pos, 1)) + if (ubifs_unpack_bits(c, &addr, &pos, 1)) lprops->flags = LPROPS_INDEX; else lprops->flags = 0; @@ -1009,16 +1011,16 @@ int ubifs_unpack_nnode(const struct ubifs_info *c, void *buf, if (err) return err; if (c->big_lpt) - nnode->num = ubifs_unpack_bits(&addr, &pos, c->pcnt_bits); + nnode->num = ubifs_unpack_bits(c, &addr, &pos, c->pcnt_bits); for (i = 0; i < UBIFS_LPT_FANOUT; i++) { int lnum; - lnum = ubifs_unpack_bits(&addr, &pos, c->lpt_lnum_bits) + + lnum = ubifs_unpack_bits(c, &addr, &pos, c->lpt_lnum_bits) + c->lpt_first; if (lnum == c->lpt_last + 1) lnum = 0; nnode->nbranch[i].lnum = lnum; - nnode->nbranch[i].offs = ubifs_unpack_bits(&addr, &pos, + nnode->nbranch[i].offs = ubifs_unpack_bits(c, &addr, &pos, c->lpt_offs_bits); } err = check_lpt_crc(c, buf, c->nnode_sz); @@ -1041,8 +1043,8 @@ static int unpack_ltab(const struct ubifs_info *c, void *buf) if (err) return err; for (i = 0; i < c->lpt_lebs; i++) { - int free = ubifs_unpack_bits(&addr, &pos, c->lpt_spc_bits); - int dirty = ubifs_unpack_bits(&addr, &pos, c->lpt_spc_bits); + int free = ubifs_unpack_bits(c, &addr, &pos, c->lpt_spc_bits); + int dirty = ubifs_unpack_bits(c, &addr, &pos, c->lpt_spc_bits); if (free < 0 || free > c->leb_size || dirty < 0 || dirty > c->leb_size || free + dirty > c->leb_size) @@ -1073,7 +1075,7 @@ static int unpack_lsave(const struct ubifs_info *c, void *buf) if (err) return err; for (i = 0; i < c->lsave_cnt; i++) { - int lnum = ubifs_unpack_bits(&addr, &pos, c->lnum_bits); + int lnum = ubifs_unpack_bits(c, &addr, &pos, c->lnum_bits); if (lnum < c->main_first || lnum >= c->leb_cnt) return -EINVAL; @@ -1515,7 +1517,7 @@ static struct ubifs_nnode *dirty_cow_nnode(struct ubifs_info *c, branch->cnode->parent = n; } - ubifs_assert(!test_bit(OBSOLETE_CNODE, &nnode->flags)); + ubifs_assert(c, !test_bit(OBSOLETE_CNODE, &nnode->flags)); __set_bit(OBSOLETE_CNODE, &nnode->flags); c->dirty_nn_cnt += 1; @@ -1558,7 +1560,7 @@ static struct ubifs_pnode *dirty_cow_pnode(struct ubifs_info *c, __clear_bit(COW_CNODE, &p->flags); replace_cats(c, pnode, p); - ubifs_assert(!test_bit(OBSOLETE_CNODE, &pnode->flags)); + ubifs_assert(c, !test_bit(OBSOLETE_CNODE, &pnode->flags)); __set_bit(OBSOLETE_CNODE, &pnode->flags); c->dirty_pn_cnt += 1; @@ -1613,7 +1615,7 @@ struct ubifs_lprops *ubifs_lpt_lookup_dirty(struct ubifs_info *c, int lnum) dbg_lp("LEB %d, free %d, dirty %d, flags %d", lnum, pnode->lprops[iip].free, pnode->lprops[iip].dirty, pnode->lprops[iip].flags); - ubifs_assert(test_bit(DIRTY_CNODE, &pnode->flags)); + ubifs_assert(c, test_bit(DIRTY_CNODE, &pnode->flags)); return &pnode->lprops[iip]; } @@ -1889,9 +1891,9 @@ static struct ubifs_pnode *scan_get_pnode(struct ubifs_info *c, lprops->flags = ubifs_categorize_lprops(c, lprops); } } else { - ubifs_assert(branch->lnum >= c->lpt_first && + ubifs_assert(c, branch->lnum >= c->lpt_first && branch->lnum <= c->lpt_last); - ubifs_assert(branch->offs >= 0 && branch->offs < c->leb_size); + ubifs_assert(c, branch->offs >= 0 && branch->offs < c->leb_size); err = ubifs_leb_read(c, branch->lnum, buf, branch->offs, c->pnode_sz, 1); if (err) @@ -1935,8 +1937,8 @@ int ubifs_lpt_scan_nolock(struct ubifs_info *c, int start_lnum, int end_lnum, start_lnum = c->main_first; } - ubifs_assert(start_lnum >= c->main_first && start_lnum < c->leb_cnt); - ubifs_assert(end_lnum >= c->main_first && end_lnum < c->leb_cnt); + ubifs_assert(c, start_lnum >= c->main_first && start_lnum < c->leb_cnt); + ubifs_assert(c, end_lnum >= c->main_first && end_lnum < c->leb_cnt); if (!c->nroot) { err = ubifs_read_nnode(c, NULL, 0); @@ -2055,7 +2057,7 @@ again: iip = pnode->iip; while (1) { h -= 1; - ubifs_assert(h >= 0); + ubifs_assert(c, h >= 0); nnode = path[h].ptr.nnode; if (iip + 1 < UBIFS_LPT_FANOUT) break; @@ -2234,7 +2236,7 @@ int dbg_check_lpt_nodes(struct ubifs_info *c, struct ubifs_cnode *cnode, return 0; while (cnode) { - ubifs_assert(row >= 0); + ubifs_assert(c, row >= 0); nnode = cnode->parent; if (cnode->level) { /* cnode is a nnode */ diff --git a/fs/ubifs/lpt_commit.c b/fs/ubifs/lpt_commit.c index 78da65b2fb85..7ce30994bbba 100644 --- a/fs/ubifs/lpt_commit.c +++ b/fs/ubifs/lpt_commit.c @@ -34,13 +34,14 @@ static int dbg_populate_lsave(struct ubifs_info *c); /** * first_dirty_cnode - find first dirty cnode. + * @c: UBIFS file-system description object * @nnode: nnode at which to start * * This function returns the first dirty cnode or %NULL if there is not one. */ -static struct ubifs_cnode *first_dirty_cnode(struct ubifs_nnode *nnode) +static struct ubifs_cnode *first_dirty_cnode(const struct ubifs_info *c, struct ubifs_nnode *nnode) { - ubifs_assert(nnode); + ubifs_assert(c, nnode); while (1) { int i, cont = 0; @@ -64,16 +65,17 @@ static struct ubifs_cnode *first_dirty_cnode(struct ubifs_nnode *nnode) /** * next_dirty_cnode - find next dirty cnode. + * @c: UBIFS file-system description object * @cnode: cnode from which to begin searching * * This function returns the next dirty cnode or %NULL if there is not one. */ -static struct ubifs_cnode *next_dirty_cnode(struct ubifs_cnode *cnode) +static struct ubifs_cnode *next_dirty_cnode(const struct ubifs_info *c, struct ubifs_cnode *cnode) { struct ubifs_nnode *nnode; int i; - ubifs_assert(cnode); + ubifs_assert(c, cnode); nnode = cnode->parent; if (!nnode) return NULL; @@ -83,7 +85,7 @@ static struct ubifs_cnode *next_dirty_cnode(struct ubifs_cnode *cnode) if (cnode->level == 0) return cnode; /* cnode is a pnode */ /* cnode is a nnode */ - return first_dirty_cnode((struct ubifs_nnode *)cnode); + return first_dirty_cnode(c, (struct ubifs_nnode *)cnode); } } return (struct ubifs_cnode *)nnode; @@ -106,15 +108,15 @@ static int get_cnodes_to_commit(struct ubifs_info *c) if (!test_bit(DIRTY_CNODE, &c->nroot->flags)) return 0; - c->lpt_cnext = first_dirty_cnode(c->nroot); + c->lpt_cnext = first_dirty_cnode(c, c->nroot); cnode = c->lpt_cnext; if (!cnode) return 0; cnt += 1; while (1) { - ubifs_assert(!test_bit(COW_CNODE, &cnode->flags)); + ubifs_assert(c, !test_bit(COW_CNODE, &cnode->flags)); __set_bit(COW_CNODE, &cnode->flags); - cnext = next_dirty_cnode(cnode); + cnext = next_dirty_cnode(c, cnode); if (!cnext) { cnode->cnext = c->lpt_cnext; break; @@ -125,7 +127,7 @@ static int get_cnodes_to_commit(struct ubifs_info *c) } dbg_cmt("committing %d cnodes", cnt); dbg_lp("committing %d cnodes", cnt); - ubifs_assert(cnt == c->dirty_nn_cnt + c->dirty_pn_cnt); + ubifs_assert(c, cnt == c->dirty_nn_cnt + c->dirty_pn_cnt); return cnt; } @@ -141,7 +143,7 @@ static void upd_ltab(struct ubifs_info *c, int lnum, int free, int dirty) dbg_lp("LEB %d free %d dirty %d to %d +%d", lnum, c->ltab[lnum - c->lpt_first].free, c->ltab[lnum - c->lpt_first].dirty, free, dirty); - ubifs_assert(lnum >= c->lpt_first && lnum <= c->lpt_last); + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); c->ltab[lnum - c->lpt_first].free = free; c->ltab[lnum - c->lpt_first].dirty += dirty; } @@ -237,7 +239,7 @@ static int layout_cnodes(struct ubifs_info *c) if (err) goto no_space; offs = 0; - ubifs_assert(lnum >= c->lpt_first && + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); /* Try to place lsave and ltab nicely */ if (!done_lsave) { @@ -280,7 +282,7 @@ static int layout_cnodes(struct ubifs_info *c) if (err) goto no_space; offs = 0; - ubifs_assert(lnum >= c->lpt_first && + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); } done_lsave = 1; @@ -300,7 +302,7 @@ static int layout_cnodes(struct ubifs_info *c) if (err) goto no_space; offs = 0; - ubifs_assert(lnum >= c->lpt_first && + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); } c->ltab_lnum = lnum; @@ -423,7 +425,7 @@ static int write_cnodes(struct ubifs_info *c) if (err) goto no_space; offs = from = 0; - ubifs_assert(lnum >= c->lpt_first && + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); err = ubifs_leb_unmap(c, lnum); if (err) @@ -480,7 +482,7 @@ static int write_cnodes(struct ubifs_info *c) if (err) goto no_space; offs = from = 0; - ubifs_assert(lnum >= c->lpt_first && + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); err = ubifs_leb_unmap(c, lnum); if (err) @@ -506,7 +508,7 @@ static int write_cnodes(struct ubifs_info *c) if (err) goto no_space; offs = from = 0; - ubifs_assert(lnum >= c->lpt_first && + ubifs_assert(c, lnum >= c->lpt_first && lnum <= c->lpt_last); err = ubifs_leb_unmap(c, lnum); if (err) @@ -806,7 +808,7 @@ static void populate_lsave(struct ubifs_info *c) struct ubifs_lpt_heap *heap; int i, cnt = 0; - ubifs_assert(c->big_lpt); + ubifs_assert(c, c->big_lpt); if (!(c->lpt_drty_flgs & LSAVE_DIRTY)) { c->lpt_drty_flgs |= LSAVE_DIRTY; ubifs_add_lpt_dirt(c, c->lsave_lnum, c->lsave_sz); @@ -1095,8 +1097,8 @@ static int get_lpt_node_type(const struct ubifs_info *c, uint8_t *buf, uint8_t *addr = buf + UBIFS_LPT_CRC_BYTES; int pos = 0, node_type; - node_type = ubifs_unpack_bits(&addr, &pos, UBIFS_LPT_TYPE_BITS); - *node_num = ubifs_unpack_bits(&addr, &pos, c->pcnt_bits); + node_type = ubifs_unpack_bits(c, &addr, &pos, UBIFS_LPT_TYPE_BITS); + *node_num = ubifs_unpack_bits(c, &addr, &pos, c->pcnt_bits); return node_type; } @@ -1116,7 +1118,7 @@ static int is_a_node(const struct ubifs_info *c, uint8_t *buf, int len) if (len < UBIFS_LPT_CRC_BYTES + (UBIFS_LPT_TYPE_BITS + 7) / 8) return 0; - node_type = ubifs_unpack_bits(&addr, &pos, UBIFS_LPT_TYPE_BITS); + node_type = ubifs_unpack_bits(c, &addr, &pos, UBIFS_LPT_TYPE_BITS); if (node_type == UBIFS_LPT_NOT_A_NODE) return 0; node_len = get_lpt_node_len(c, node_type); @@ -1124,7 +1126,7 @@ static int is_a_node(const struct ubifs_info *c, uint8_t *buf, int len) return 0; pos = 0; addr = buf; - crc = ubifs_unpack_bits(&addr, &pos, UBIFS_LPT_CRC_BITS); + crc = ubifs_unpack_bits(c, &addr, &pos, UBIFS_LPT_CRC_BITS); calc_crc = crc16(-1, buf + UBIFS_LPT_CRC_BYTES, node_len - UBIFS_LPT_CRC_BYTES); if (crc != calc_crc) @@ -1170,7 +1172,7 @@ static int lpt_gc_lnum(struct ubifs_info *c, int lnum) node_type = get_lpt_node_type(c, buf, &node_num); node_len = get_lpt_node_len(c, node_type); offs = c->leb_size - len; - ubifs_assert(node_len != 0); + ubifs_assert(c, node_len != 0); mutex_lock(&c->lp_mutex); err = make_node_dirty(c, node_type, node_num, lnum, offs); mutex_unlock(&c->lp_mutex); @@ -1195,7 +1197,7 @@ static int lpt_gc(struct ubifs_info *c) mutex_lock(&c->lp_mutex); for (i = 0; i < c->lpt_lebs; i++) { - ubifs_assert(!c->ltab[i].tgc); + ubifs_assert(c, !c->ltab[i].tgc); if (i + c->lpt_first == c->nhead_lnum || c->ltab[i].free + c->ltab[i].dirty == c->leb_size) continue; @@ -1271,7 +1273,7 @@ int ubifs_lpt_start_commit(struct ubifs_info *c) populate_lsave(c); cnt = get_cnodes_to_commit(c); - ubifs_assert(cnt != 0); + ubifs_assert(c, cnt != 0); err = layout_cnodes(c); if (err) diff --git a/fs/ubifs/master.c b/fs/ubifs/master.c index c6a5e39e2ba5..9df4a41bba52 100644 --- a/fs/ubifs/master.c +++ b/fs/ubifs/master.c @@ -360,7 +360,7 @@ int ubifs_write_master(struct ubifs_info *c) { int err, lnum, offs, len; - ubifs_assert(!c->ro_media && !c->ro_mount); + ubifs_assert(c, !c->ro_media && !c->ro_mount); if (c->ro_error) return -EROFS; diff --git a/fs/ubifs/misc.c b/fs/ubifs/misc.c index 586fd5b578a7..cd23de0f211d 100644 --- a/fs/ubifs/misc.c +++ b/fs/ubifs/misc.c @@ -56,3 +56,14 @@ void ubifs_warn(const struct ubifs_info *c, const char *fmt, ...) va_end(args); } + +static char *assert_names[] = { + [ASSACT_REPORT] = "report", + [ASSACT_RO] = "read-only", + [ASSACT_PANIC] = "panic", +}; + +const char *ubifs_assert_action_name(struct ubifs_info *c) +{ + return assert_names[c->assert_action]; +} diff --git a/fs/ubifs/misc.h b/fs/ubifs/misc.h index caf83d68fb38..21d35d7dd975 100644 --- a/fs/ubifs/misc.h +++ b/fs/ubifs/misc.h @@ -105,25 +105,27 @@ static inline struct ubifs_inode *ubifs_inode(const struct inode *inode) /** * ubifs_compr_present - check if compressor was compiled in. * @compr_type: compressor type to check + * @c: the UBIFS file-system description object * * This function returns %1 of compressor of type @compr_type is present, and * %0 if not. */ -static inline int ubifs_compr_present(int compr_type) +static inline int ubifs_compr_present(struct ubifs_info *c, int compr_type) { - ubifs_assert(compr_type >= 0 && compr_type < UBIFS_COMPR_TYPES_CNT); + ubifs_assert(c, compr_type >= 0 && compr_type < UBIFS_COMPR_TYPES_CNT); return !!ubifs_compressors[compr_type]->capi_name; } /** * ubifs_compr_name - get compressor name string by its type. * @compr_type: compressor type + * @c: the UBIFS file-system description object * * This function returns compressor type string. */ -static inline const char *ubifs_compr_name(int compr_type) +static inline const char *ubifs_compr_name(struct ubifs_info *c, int compr_type) { - ubifs_assert(compr_type >= 0 && compr_type < UBIFS_COMPR_TYPES_CNT); + ubifs_assert(c, compr_type >= 0 && compr_type < UBIFS_COMPR_TYPES_CNT); return ubifs_compressors[compr_type]->name; } @@ -262,8 +264,8 @@ static inline void ubifs_get_lprops(struct ubifs_info *c) */ static inline void ubifs_release_lprops(struct ubifs_info *c) { - ubifs_assert(mutex_is_locked(&c->lp_mutex)); - ubifs_assert(c->lst.empty_lebs >= 0 && + ubifs_assert(c, mutex_is_locked(&c->lp_mutex)); + ubifs_assert(c, c->lst.empty_lebs >= 0 && c->lst.empty_lebs <= c->main_lebs); mutex_unlock(&c->lp_mutex); } @@ -285,4 +287,6 @@ static inline int ubifs_next_log_lnum(const struct ubifs_info *c, int lnum) return lnum; } +const char *ubifs_assert_action_name(struct ubifs_info *c); + #endif /* __UBIFS_MISC_H__ */ diff --git a/fs/ubifs/orphan.c b/fs/ubifs/orphan.c index caf2d123e9ee..8f70494efb0c 100644 --- a/fs/ubifs/orphan.c +++ b/fs/ubifs/orphan.c @@ -172,8 +172,8 @@ int ubifs_orphan_start_commit(struct ubifs_info *c) spin_lock(&c->orphan_lock); last = &c->orph_cnext; list_for_each_entry(orphan, &c->orph_new, new_list) { - ubifs_assert(orphan->new); - ubifs_assert(!orphan->cmt); + ubifs_assert(c, orphan->new); + ubifs_assert(c, !orphan->cmt); orphan->new = 0; orphan->cmt = 1; *last = orphan; @@ -244,7 +244,7 @@ static int do_write_orph_node(struct ubifs_info *c, int len, int atomic) int err = 0; if (atomic) { - ubifs_assert(c->ohead_offs == 0); + ubifs_assert(c, c->ohead_offs == 0); ubifs_prepare_node(c, c->orph_buf, len, 1); len = ALIGN(len, c->min_io_size); err = ubifs_leb_change(c, c->ohead_lnum, c->orph_buf, len); @@ -276,7 +276,7 @@ static int write_orph_node(struct ubifs_info *c, int atomic) struct ubifs_orph_node *orph; int gap, err, len, cnt, i; - ubifs_assert(c->cmt_orphans > 0); + ubifs_assert(c, c->cmt_orphans > 0); gap = c->leb_size - c->ohead_offs; if (gap < UBIFS_ORPH_NODE_SZ + sizeof(__le64)) { c->ohead_lnum += 1; @@ -295,14 +295,14 @@ static int write_orph_node(struct ubifs_info *c, int atomic) if (cnt > c->cmt_orphans) cnt = c->cmt_orphans; len = UBIFS_ORPH_NODE_SZ + cnt * sizeof(__le64); - ubifs_assert(c->orph_buf); + ubifs_assert(c, c->orph_buf); orph = c->orph_buf; orph->ch.node_type = UBIFS_ORPH_NODE; spin_lock(&c->orphan_lock); cnext = c->orph_cnext; for (i = 0; i < cnt; i++) { orphan = cnext; - ubifs_assert(orphan->cmt); + ubifs_assert(c, orphan->cmt); orph->inos[i] = cpu_to_le64(orphan->inum); orphan->cmt = 0; cnext = orphan->cnext; @@ -316,9 +316,9 @@ static int write_orph_node(struct ubifs_info *c, int atomic) else /* Mark the last node of the commit */ orph->cmt_no = cpu_to_le64((c->cmt_no) | (1ULL << 63)); - ubifs_assert(c->ohead_offs + len <= c->leb_size); - ubifs_assert(c->ohead_lnum >= c->orph_first); - ubifs_assert(c->ohead_lnum <= c->orph_last); + ubifs_assert(c, c->ohead_offs + len <= c->leb_size); + ubifs_assert(c, c->ohead_lnum >= c->orph_first); + ubifs_assert(c, c->ohead_lnum <= c->orph_last); err = do_write_orph_node(c, len, atomic); c->ohead_offs += ALIGN(len, c->min_io_size); c->ohead_offs = ALIGN(c->ohead_offs, 8); @@ -388,7 +388,7 @@ static int consolidate(struct ubifs_info *c) cnt += 1; } *last = NULL; - ubifs_assert(cnt == c->tot_orphans - c->new_orphans); + ubifs_assert(c, cnt == c->tot_orphans - c->new_orphans); c->cmt_orphans = cnt; c->ohead_lnum = c->orph_first; c->ohead_offs = 0; @@ -415,7 +415,7 @@ static int commit_orphans(struct ubifs_info *c) { int avail, atomic = 0, err; - ubifs_assert(c->cmt_orphans > 0); + ubifs_assert(c, c->cmt_orphans > 0); avail = avail_orphs(c); if (avail < c->cmt_orphans) { /* Not enough space to write new orphans, so consolidate */ @@ -446,8 +446,8 @@ static void erase_deleted(struct ubifs_info *c) while (dnext) { orphan = dnext; dnext = orphan->dnext; - ubifs_assert(!orphan->new); - ubifs_assert(orphan->del); + ubifs_assert(c, !orphan->new); + ubifs_assert(c, orphan->del); rb_erase(&orphan->rb, &c->orph_tree); list_del(&orphan->list); c->tot_orphans -= 1; diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index 3af4472061cc..984e30e83c0b 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -444,7 +444,7 @@ static void clean_buf(const struct ubifs_info *c, void **buf, int lnum, dbg_rcvry("cleaning corruption at %d:%d", lnum, *offs); - ubifs_assert(!(*offs & 7)); + ubifs_assert(c, !(*offs & 7)); empty_offs = ALIGN(*offs, c->min_io_size); pad_len = empty_offs - *offs; ubifs_pad(c, *buf, pad_len); @@ -644,7 +644,7 @@ struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum, if (IS_ERR(sleb)) return sleb; - ubifs_assert(len >= 8); + ubifs_assert(c, len >= 8); while (len >= 8) { dbg_scan("look at LEB %d:%d (%d bytes left)", lnum, offs, len); @@ -966,7 +966,7 @@ int ubifs_recover_inl_heads(struct ubifs_info *c, void *sbuf) { int err; - ubifs_assert(!c->ro_mount || c->remounting_rw); + ubifs_assert(c, !c->ro_mount || c->remounting_rw); dbg_rcvry("checking index head at %d:%d", c->ihead_lnum, c->ihead_offs); err = recover_head(c, c->ihead_lnum, c->ihead_offs, sbuf); @@ -1187,8 +1187,8 @@ int ubifs_rcvry_gc_commit(struct ubifs_info *c) return grab_empty_leb(c); } - ubifs_assert(!(lp.flags & LPROPS_INDEX)); - ubifs_assert(lp.free + lp.dirty >= wbuf->offs); + ubifs_assert(c, !(lp.flags & LPROPS_INDEX)); + ubifs_assert(c, lp.free + lp.dirty >= wbuf->offs); /* * We run the commit before garbage collection otherwise subsequent @@ -1216,7 +1216,7 @@ int ubifs_rcvry_gc_commit(struct ubifs_info *c) return err; } - ubifs_assert(err == LEB_RETAINED); + ubifs_assert(c, err == LEB_RETAINED); if (err != LEB_RETAINED) return -EINVAL; @@ -1507,7 +1507,7 @@ int ubifs_recover_size(struct ubifs_info *c) struct inode *inode; struct ubifs_inode *ui; - ubifs_assert(!e->inode); + ubifs_assert(c, !e->inode); inode = ubifs_iget(c->vfs_sb, e->inum); if (IS_ERR(inode)) diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c index 85c2a43082b7..4844538eb926 100644 --- a/fs/ubifs/replay.c +++ b/fs/ubifs/replay.c @@ -273,6 +273,7 @@ static int apply_replay_entry(struct ubifs_info *c, struct replay_entry *r) static int replay_entries_cmp(void *priv, struct list_head *a, struct list_head *b) { + struct ubifs_info *c = priv; struct replay_entry *ra, *rb; cond_resched(); @@ -281,7 +282,7 @@ static int replay_entries_cmp(void *priv, struct list_head *a, ra = list_entry(a, struct replay_entry, list); rb = list_entry(b, struct replay_entry, list); - ubifs_assert(ra->sqnum != rb->sqnum); + ubifs_assert(c, ra->sqnum != rb->sqnum); if (ra->sqnum > rb->sqnum) return 1; return -1; @@ -668,9 +669,9 @@ static int replay_bud(struct ubifs_info *c, struct bud_entry *b) goto out; } - ubifs_assert(ubifs_search_bud(c, lnum)); - ubifs_assert(sleb->endpt - offs >= used); - ubifs_assert(sleb->endpt % c->min_io_size == 0); + ubifs_assert(c, ubifs_search_bud(c, lnum)); + ubifs_assert(c, sleb->endpt - offs >= used); + ubifs_assert(c, sleb->endpt % c->min_io_size == 0); b->dirty = sleb->endpt - offs - used; b->free = c->leb_size - sleb->endpt; @@ -706,7 +707,7 @@ static int replay_buds(struct ubifs_info *c) if (err) return err; - ubifs_assert(b->sqnum > prev_sqnum); + ubifs_assert(c, b->sqnum > prev_sqnum); prev_sqnum = b->sqnum; } @@ -1067,7 +1068,7 @@ int ubifs_replay_journal(struct ubifs_info *c) c->bi.uncommitted_idx = atomic_long_read(&c->dirty_zn_cnt); c->bi.uncommitted_idx *= c->max_idx_node_sz; - ubifs_assert(c->bud_bytes <= c->max_bud_bytes || c->need_recovery); + ubifs_assert(c, c->bud_bytes <= c->max_bud_bytes || c->need_recovery); dbg_mnt("finished, log head LEB %d:%d, max_sqnum %llu, highest_inum %lu", c->lhead_lnum, c->lhead_offs, c->max_sqnum, (unsigned long)c->highest_inum); diff --git a/fs/ubifs/sb.c b/fs/ubifs/sb.c index 8c25081a5109..bf17f58908ff 100644 --- a/fs/ubifs/sb.c +++ b/fs/ubifs/sb.c @@ -85,7 +85,7 @@ static int create_default_filesystem(struct ubifs_info *c) long long tmp64, main_bytes; __le64 tmp_le64; __le32 tmp_le32; - struct timespec ts; + struct timespec64 ts; /* Some functions called from here depend on the @c->key_len filed */ c->key_len = UBIFS_SK_LEN; @@ -301,8 +301,8 @@ static int create_default_filesystem(struct ubifs_info *c) ino->creat_sqnum = cpu_to_le64(++c->max_sqnum); ino->nlink = cpu_to_le32(2); - ktime_get_real_ts(&ts); - ts = timespec_trunc(ts, DEFAULT_TIME_GRAN); + ktime_get_real_ts64(&ts); + ts = timespec64_trunc(ts, DEFAULT_TIME_GRAN); tmp_le64 = cpu_to_le64(ts.tv_sec); ino->atime_sec = tmp_le64; ino->ctime_sec = tmp_le64; @@ -563,7 +563,7 @@ int ubifs_read_superblock(struct ubifs_info *c) * due to the unavailability of time-travelling equipment. */ if (c->fmt_version > UBIFS_FORMAT_VERSION) { - ubifs_assert(!c->ro_media || c->ro_mount); + ubifs_assert(c, !c->ro_media || c->ro_mount); if (!c->ro_mount || c->ro_compat_version > UBIFS_RO_COMPAT_VERSION) { ubifs_err(c, "on-flash format version is w%d/r%d, but software only supports up to version w%d/r%d", @@ -705,9 +705,9 @@ static int fixup_leb(struct ubifs_info *c, int lnum, int len) { int err; - ubifs_assert(len >= 0); - ubifs_assert(len % c->min_io_size == 0); - ubifs_assert(len < c->leb_size); + ubifs_assert(c, len >= 0); + ubifs_assert(c, len % c->min_io_size == 0); + ubifs_assert(c, len < c->leb_size); if (len == 0) { dbg_mnt("unmap empty LEB %d", lnum); @@ -817,8 +817,8 @@ int ubifs_fixup_free_space(struct ubifs_info *c) int err; struct ubifs_sb_node *sup; - ubifs_assert(c->space_fixup); - ubifs_assert(!c->ro_mount); + ubifs_assert(c, c->space_fixup); + ubifs_assert(c, !c->ro_mount); ubifs_msg(c, "start fixing up free space"); diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c index 16f03d9929e5..ea88926163f4 100644 --- a/fs/ubifs/scan.c +++ b/fs/ubifs/scan.c @@ -176,7 +176,7 @@ void ubifs_end_scan(const struct ubifs_info *c, struct ubifs_scan_leb *sleb, int lnum, int offs) { dbg_scan("stop scanning LEB %d at offset %d", lnum, offs); - ubifs_assert(offs % c->min_io_size == 0); + ubifs_assert(c, offs % c->min_io_size == 0); sleb->endpt = ALIGN(offs, c->min_io_size); } diff --git a/fs/ubifs/shrinker.c b/fs/ubifs/shrinker.c index 9a9fb94a41c6..5eb5958723d4 100644 --- a/fs/ubifs/shrinker.c +++ b/fs/ubifs/shrinker.c @@ -71,10 +71,10 @@ static int shrink_tnc(struct ubifs_info *c, int nr, int age, int *contention) { int total_freed = 0; struct ubifs_znode *znode, *zprev; - int time = get_seconds(); + time64_t time = ktime_get_seconds(); - ubifs_assert(mutex_is_locked(&c->umount_mutex)); - ubifs_assert(mutex_is_locked(&c->tnc_mutex)); + ubifs_assert(c, mutex_is_locked(&c->umount_mutex)); + ubifs_assert(c, mutex_is_locked(&c->tnc_mutex)); if (!c->zroot.znode || atomic_long_read(&c->clean_zn_cnt) == 0) return 0; @@ -89,7 +89,7 @@ static int shrink_tnc(struct ubifs_info *c, int nr, int age, int *contention) * changed only when the 'c->tnc_mutex' is held. */ zprev = NULL; - znode = ubifs_tnc_levelorder_next(c->zroot.znode, NULL); + znode = ubifs_tnc_levelorder_next(c, c->zroot.znode, NULL); while (znode && total_freed < nr && atomic_long_read(&c->clean_zn_cnt) > 0) { int freed; @@ -125,7 +125,7 @@ static int shrink_tnc(struct ubifs_info *c, int nr, int age, int *contention) else c->zroot.znode = NULL; - freed = ubifs_destroy_tnc_subtree(znode); + freed = ubifs_destroy_tnc_subtree(c, znode); atomic_long_sub(freed, &ubifs_clean_zn_cnt); atomic_long_sub(freed, &c->clean_zn_cnt); total_freed += freed; @@ -136,7 +136,7 @@ static int shrink_tnc(struct ubifs_info *c, int nr, int age, int *contention) break; zprev = znode; - znode = ubifs_tnc_levelorder_next(c->zroot.znode, znode); + znode = ubifs_tnc_levelorder_next(c, c->zroot.znode, znode); cond_resched(); } diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index c5466c70d620..23e7042666a7 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -89,9 +89,9 @@ static int validate_inode(struct ubifs_info *c, const struct inode *inode) if (ui->xattr && !S_ISREG(inode->i_mode)) return 5; - if (!ubifs_compr_present(ui->compr_type)) { + if (!ubifs_compr_present(c, ui->compr_type)) { ubifs_warn(c, "inode %lu uses '%s' compression, but it was not compiled in", - inode->i_ino, ubifs_compr_name(ui->compr_type)); + inode->i_ino, ubifs_compr_name(c, ui->compr_type)); } err = dbg_check_dir(c, inode); @@ -296,7 +296,7 @@ static int ubifs_write_inode(struct inode *inode, struct writeback_control *wbc) struct ubifs_info *c = inode->i_sb->s_fs_info; struct ubifs_inode *ui = ubifs_inode(inode); - ubifs_assert(!ui->xattr); + ubifs_assert(c, !ui->xattr); if (is_bad_inode(inode)) return 0; @@ -349,7 +349,7 @@ static void ubifs_evict_inode(struct inode *inode) goto out; dbg_gen("inode %lu, mode %#x", inode->i_ino, (int)inode->i_mode); - ubifs_assert(!atomic_read(&inode->i_count)); + ubifs_assert(c, !atomic_read(&inode->i_count)); truncate_inode_pages_final(&inode->i_data); @@ -384,9 +384,10 @@ done: static void ubifs_dirty_inode(struct inode *inode, int flags) { + struct ubifs_info *c = inode->i_sb->s_fs_info; struct ubifs_inode *ui = ubifs_inode(inode); - ubifs_assert(mutex_is_locked(&ui->ui_mutex)); + ubifs_assert(c, mutex_is_locked(&ui->ui_mutex)); if (!ui->dirty) { ui->dirty = 1; dbg_gen("inode %lu", inode->i_ino); @@ -416,7 +417,7 @@ static int ubifs_statfs(struct dentry *dentry, struct kstatfs *buf) buf->f_namelen = UBIFS_MAX_NLEN; buf->f_fsid.val[0] = le32_to_cpu(uuid[0]) ^ le32_to_cpu(uuid[2]); buf->f_fsid.val[1] = le32_to_cpu(uuid[1]) ^ le32_to_cpu(uuid[3]); - ubifs_assert(buf->f_bfree <= c->block_cnt); + ubifs_assert(c, buf->f_bfree <= c->block_cnt); return 0; } @@ -441,9 +442,10 @@ static int ubifs_show_options(struct seq_file *s, struct dentry *root) if (c->mount_opts.override_compr) { seq_printf(s, ",compr=%s", - ubifs_compr_name(c->mount_opts.compr_type)); + ubifs_compr_name(c, c->mount_opts.compr_type)); } + seq_printf(s, ",assert=%s", ubifs_assert_action_name(c)); seq_printf(s, ",ubi=%d,vol=%d", c->vi.ubi_num, c->vi.vol_id); return 0; @@ -921,6 +923,7 @@ static int check_volume_empty(struct ubifs_info *c) * Opt_chk_data_crc: check CRCs when reading data nodes * Opt_no_chk_data_crc: do not check CRCs when reading data nodes * Opt_override_compr: override default compressor + * Opt_assert: set ubifs_assert() action * Opt_err: just end of array marker */ enum { @@ -931,6 +934,7 @@ enum { Opt_chk_data_crc, Opt_no_chk_data_crc, Opt_override_compr, + Opt_assert, Opt_ignore, Opt_err, }; @@ -945,6 +949,7 @@ static const match_table_t tokens = { {Opt_override_compr, "compr=%s"}, {Opt_ignore, "ubi=%s"}, {Opt_ignore, "vol=%s"}, + {Opt_assert, "assert=%s"}, {Opt_err, NULL}, }; @@ -1045,6 +1050,26 @@ static int ubifs_parse_options(struct ubifs_info *c, char *options, c->default_compr = c->mount_opts.compr_type; break; } + case Opt_assert: + { + char *act = match_strdup(&args[0]); + + if (!act) + return -ENOMEM; + if (!strcmp(act, "report")) + c->assert_action = ASSACT_REPORT; + else if (!strcmp(act, "read-only")) + c->assert_action = ASSACT_RO; + else if (!strcmp(act, "panic")) + c->assert_action = ASSACT_PANIC; + else { + ubifs_err(c, "unknown assert action \"%s\"", act); + kfree(act); + return -EINVAL; + } + kfree(act); + break; + } case Opt_ignore: break; default: @@ -1103,7 +1128,7 @@ static void destroy_journal(struct ubifs_info *c) */ static void bu_init(struct ubifs_info *c) { - ubifs_assert(c->bulk_read == 1); + ubifs_assert(c, c->bulk_read == 1); if (c->bu.buf) return; /* Already initialized */ @@ -1134,7 +1159,7 @@ again: */ static int check_free_space(struct ubifs_info *c) { - ubifs_assert(c->dark_wm > 0); + ubifs_assert(c, c->dark_wm > 0); if (c->lst.total_free + c->lst.total_dirty < c->dark_wm) { ubifs_err(c, "insufficient free space to mount in R/W mode"); ubifs_dump_budg(c, &c->bi); @@ -1234,9 +1259,9 @@ static int mount_ubifs(struct ubifs_info *c) * Make sure the compressor which is set as default in the superblock * or overridden by mount options is actually compiled in. */ - if (!ubifs_compr_present(c->default_compr)) { + if (!ubifs_compr_present(c, c->default_compr)) { ubifs_err(c, "'compressor \"%s\" is not compiled in", - ubifs_compr_name(c->default_compr)); + ubifs_compr_name(c, c->default_compr)); err = -ENOTSUPP; goto out_free; } @@ -1396,10 +1421,10 @@ static int mount_ubifs(struct ubifs_info *c) * the journal head LEBs may also be accounted as * "empty taken" if they are empty. */ - ubifs_assert(c->lst.taken_empty_lebs > 0); + ubifs_assert(c, c->lst.taken_empty_lebs > 0); } } else - ubifs_assert(c->lst.taken_empty_lebs > 0); + ubifs_assert(c, c->lst.taken_empty_lebs > 0); err = dbg_check_filesystem(c); if (err) @@ -1429,7 +1454,7 @@ static int mount_ubifs(struct ubifs_info *c) UBIFS_FORMAT_VERSION, UBIFS_RO_COMPAT_VERSION, c->uuid, c->big_lpt ? ", big LPT model" : ", small LPT model"); - dbg_gen("default compressor: %s", ubifs_compr_name(c->default_compr)); + dbg_gen("default compressor: %s", ubifs_compr_name(c, c->default_compr)); dbg_gen("data journal heads: %d", c->jhead_cnt - NONDATA_JHEADS_CNT); dbg_gen("log LEBs: %d (%d - %d)", @@ -1610,7 +1635,7 @@ static int ubifs_remount_rw(struct ubifs_info *c) goto out; } else { /* A readonly mount is not allowed to have orphans */ - ubifs_assert(c->tot_orphans == 0); + ubifs_assert(c, c->tot_orphans == 0); err = ubifs_clear_orphans(c); if (err) goto out; @@ -1727,8 +1752,8 @@ static void ubifs_remount_ro(struct ubifs_info *c) { int i, err; - ubifs_assert(!c->need_recovery); - ubifs_assert(!c->ro_mount); + ubifs_assert(c, !c->need_recovery); + ubifs_assert(c, !c->ro_mount); mutex_lock(&c->umount_mutex); if (c->bgt) { @@ -1778,9 +1803,9 @@ static void ubifs_put_super(struct super_block *sb) * to write them back because of I/O errors. */ if (!c->ro_error) { - ubifs_assert(c->bi.idx_growth == 0); - ubifs_assert(c->bi.dd_growth == 0); - ubifs_assert(c->bi.data_growth == 0); + ubifs_assert(c, c->bi.idx_growth == 0); + ubifs_assert(c, c->bi.dd_growth == 0); + ubifs_assert(c, c->bi.data_growth == 0); } /* @@ -1887,7 +1912,7 @@ static int ubifs_remount_fs(struct super_block *sb, int *flags, char *data) mutex_unlock(&c->bu_mutex); } - ubifs_assert(c->lst.taken_empty_lebs > 0); + ubifs_assert(c, c->lst.taken_empty_lebs > 0); return 0; } @@ -2002,6 +2027,7 @@ static struct ubifs_info *alloc_ubifs_info(struct ubi_volume_desc *ubi) INIT_LIST_HEAD(&c->orph_list); INIT_LIST_HEAD(&c->orph_new); c->no_chk_data_crc = 1; + c->assert_action = ASSACT_RO; c->highest_inum = UBIFS_FIRST_INO; c->lhead_lnum = c->ltail_lnum = UBIFS_LOG_LNUM; @@ -2053,7 +2079,9 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) if (c->max_inode_sz > MAX_LFS_FILESIZE) sb->s_maxbytes = c->max_inode_sz = MAX_LFS_FILESIZE; sb->s_op = &ubifs_super_operations; +#ifdef CONFIG_UBIFS_FS_XATTR sb->s_xattr = ubifs_xattr_handlers; +#endif #ifdef CONFIG_UBIFS_FS_ENCRYPTION sb->s_cop = &ubifs_crypt_operations; #endif @@ -2061,7 +2089,7 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) mutex_lock(&c->umount_mutex); err = mount_ubifs(c); if (err) { - ubifs_assert(err < 0); + ubifs_assert(c, err < 0); goto out_unlock; } @@ -2304,8 +2332,8 @@ late_initcall(ubifs_init); static void __exit ubifs_exit(void) { - ubifs_assert(list_empty(&ubifs_infos)); - ubifs_assert(atomic_long_read(&ubifs_clean_zn_cnt) == 0); + WARN_ON(list_empty(&ubifs_infos)); + WARN_ON(atomic_long_read(&ubifs_clean_zn_cnt) == 0); dbg_debugfs_exit(); ubifs_compressors_exit(); diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index 4a21e7f75e7a..bf416e512743 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -211,7 +211,7 @@ static struct ubifs_znode *copy_znode(struct ubifs_info *c, __set_bit(DIRTY_ZNODE, &zn->flags); __clear_bit(COW_ZNODE, &zn->flags); - ubifs_assert(!ubifs_zn_obsolete(znode)); + ubifs_assert(c, !ubifs_zn_obsolete(znode)); __set_bit(OBSOLETE_ZNODE, &znode->flags); if (znode->level != 0) { @@ -321,9 +321,9 @@ static int lnc_add(struct ubifs_info *c, struct ubifs_zbranch *zbr, void *lnc_node; const struct ubifs_dent_node *dent = node; - ubifs_assert(!zbr->leaf); - ubifs_assert(zbr->len != 0); - ubifs_assert(is_hash_key(c, &zbr->key)); + ubifs_assert(c, !zbr->leaf); + ubifs_assert(c, zbr->len != 0); + ubifs_assert(c, is_hash_key(c, &zbr->key)); err = ubifs_validate_entry(c, dent); if (err) { @@ -355,8 +355,8 @@ static int lnc_add_directly(struct ubifs_info *c, struct ubifs_zbranch *zbr, { int err; - ubifs_assert(!zbr->leaf); - ubifs_assert(zbr->len != 0); + ubifs_assert(c, !zbr->leaf); + ubifs_assert(c, zbr->len != 0); err = ubifs_validate_entry(c, node); if (err) { @@ -398,11 +398,11 @@ static int tnc_read_hashed_node(struct ubifs_info *c, struct ubifs_zbranch *zbr, { int err; - ubifs_assert(is_hash_key(c, &zbr->key)); + ubifs_assert(c, is_hash_key(c, &zbr->key)); if (zbr->leaf) { /* Read from the leaf node cache */ - ubifs_assert(zbr->len != 0); + ubifs_assert(c, zbr->len != 0); memcpy(node, zbr->leaf, zbr->len); return 0; } @@ -721,7 +721,7 @@ static int resolve_collision(struct ubifs_info *c, const union ubifs_key *key, while (1) { err = tnc_prev(c, zn, n); if (err == -ENOENT) { - ubifs_assert(*n == 0); + ubifs_assert(c, *n == 0); *n = -1; return 0; } @@ -761,12 +761,12 @@ static int resolve_collision(struct ubifs_info *c, const union ubifs_key *key, err = tnc_next(c, zn, n); if (err) { /* Should be impossible */ - ubifs_assert(0); + ubifs_assert(c, 0); if (err == -ENOENT) err = -EINVAL; return err; } - ubifs_assert(*n == 0); + ubifs_assert(c, *n == 0); *n = -1; } return 0; @@ -778,7 +778,7 @@ static int resolve_collision(struct ubifs_info *c, const union ubifs_key *key, return 0; if (err == NAME_MATCHES) return 1; - ubifs_assert(err == NAME_GREATER); + ubifs_assert(c, err == NAME_GREATER); } } else { int nn = *n; @@ -802,7 +802,7 @@ static int resolve_collision(struct ubifs_info *c, const union ubifs_key *key, *n = nn; if (err == NAME_MATCHES) return 1; - ubifs_assert(err == NAME_LESS); + ubifs_assert(c, err == NAME_LESS); } } } @@ -843,7 +843,7 @@ static int fallible_matches_name(struct ubifs_info *c, err = NOT_ON_MEDIA; goto out_free; } - ubifs_assert(err == 1); + ubifs_assert(c, err == 1); err = lnc_add_directly(c, zbr, dent); if (err) @@ -923,7 +923,7 @@ static int fallible_resolve_collision(struct ubifs_info *c, while (1) { err = tnc_prev(c, zn, n); if (err == -ENOENT) { - ubifs_assert(*n == 0); + ubifs_assert(c, *n == 0); *n = -1; break; } @@ -935,12 +935,12 @@ static int fallible_resolve_collision(struct ubifs_info *c, err = tnc_next(c, zn, n); if (err) { /* Should be impossible */ - ubifs_assert(0); + ubifs_assert(c, 0); if (err == -ENOENT) err = -EINVAL; return err; } - ubifs_assert(*n == 0); + ubifs_assert(c, *n == 0); *n = -1; } break; @@ -1100,8 +1100,8 @@ static struct ubifs_znode *dirty_cow_bottom_up(struct ubifs_info *c, struct ubifs_znode *zp; int *path = c->bottom_up_buf, p = 0; - ubifs_assert(c->zroot.znode); - ubifs_assert(znode); + ubifs_assert(c, c->zroot.znode); + ubifs_assert(c, znode); if (c->zroot.znode->level > BOTTOM_UP_HEIGHT) { kfree(c->bottom_up_buf); c->bottom_up_buf = kmalloc_array(c->zroot.znode->level, @@ -1120,7 +1120,7 @@ static struct ubifs_znode *dirty_cow_bottom_up(struct ubifs_info *c, if (!zp) break; n = znode->iip; - ubifs_assert(p < c->zroot.znode->level); + ubifs_assert(c, p < c->zroot.znode->level); path[p++] = n; if (!zp->cnext && ubifs_zn_dirty(znode)) break; @@ -1134,18 +1134,18 @@ static struct ubifs_znode *dirty_cow_bottom_up(struct ubifs_info *c, zp = znode->parent; if (zp) { - ubifs_assert(path[p - 1] >= 0); - ubifs_assert(path[p - 1] < zp->child_cnt); + ubifs_assert(c, path[p - 1] >= 0); + ubifs_assert(c, path[p - 1] < zp->child_cnt); zbr = &zp->zbranch[path[--p]]; znode = dirty_cow_znode(c, zbr); } else { - ubifs_assert(znode == c->zroot.znode); + ubifs_assert(c, znode == c->zroot.znode); znode = dirty_cow_znode(c, &c->zroot); } if (IS_ERR(znode) || !p) break; - ubifs_assert(path[p - 1] >= 0); - ubifs_assert(path[p - 1] < znode->child_cnt); + ubifs_assert(c, path[p - 1] >= 0); + ubifs_assert(c, path[p - 1] < znode->child_cnt); znode = znode->zbranch[path[p - 1]].znode; } @@ -1179,10 +1179,10 @@ int ubifs_lookup_level0(struct ubifs_info *c, const union ubifs_key *key, { int err, exact; struct ubifs_znode *znode; - unsigned long time = get_seconds(); + time64_t time = ktime_get_seconds(); dbg_tnck(key, "search key "); - ubifs_assert(key_type(c, key) < UBIFS_INVALID_KEY); + ubifs_assert(c, key_type(c, key) < UBIFS_INVALID_KEY); znode = c->zroot.znode; if (unlikely(!znode)) { @@ -1315,7 +1315,7 @@ static int lookup_level0_dirty(struct ubifs_info *c, const union ubifs_key *key, { int err, exact; struct ubifs_znode *znode; - unsigned long time = get_seconds(); + time64_t time = ktime_get_seconds(); dbg_tnck(key, "search and dirty key "); @@ -1658,9 +1658,9 @@ static int read_wbuf(struct ubifs_wbuf *wbuf, void *buf, int len, int lnum, int rlen, overlap; dbg_io("LEB %d:%d, length %d", lnum, offs, len); - ubifs_assert(wbuf && lnum >= 0 && lnum < c->leb_cnt && offs >= 0); - ubifs_assert(!(offs & 7) && offs < c->leb_size); - ubifs_assert(offs + len <= c->leb_size); + ubifs_assert(c, wbuf && lnum >= 0 && lnum < c->leb_cnt && offs >= 0); + ubifs_assert(c, !(offs & 7) && offs < c->leb_size); + ubifs_assert(c, offs + len <= c->leb_size); spin_lock(&wbuf->lock); overlap = (lnum == wbuf->lnum && offs + len > wbuf->offs); @@ -1824,7 +1824,7 @@ static int do_lookup_nm(struct ubifs_info *c, const union ubifs_key *key, goto out_unlock; } - ubifs_assert(n >= 0); + ubifs_assert(c, n >= 0); err = resolve_collision(c, key, &znode, &n, nm); dbg_tnc("rc returned %d, znode %p, n %d", err, znode, n); @@ -1922,7 +1922,7 @@ static int do_lookup_dh(struct ubifs_info *c, const union ubifs_key *key, struct ubifs_znode *znode; union ubifs_key start_key; - ubifs_assert(is_hash_key(c, key)); + ubifs_assert(c, is_hash_key(c, key)); lowest_dent_key(c, &start_key, key_inum(c, key)); @@ -1993,8 +1993,8 @@ static void correct_parent_keys(const struct ubifs_info *c, { union ubifs_key *key, *key1; - ubifs_assert(znode->parent); - ubifs_assert(znode->iip == 0); + ubifs_assert(c, znode->parent); + ubifs_assert(c, znode->iip == 0); key = &znode->zbranch[0].key; key1 = &znode->parent->zbranch[0].key; @@ -2011,6 +2011,7 @@ static void correct_parent_keys(const struct ubifs_info *c, /** * insert_zbranch - insert a zbranch into a znode. + * @c: UBIFS file-system description object * @znode: znode into which to insert * @zbr: zbranch to insert * @n: slot number to insert to @@ -2020,12 +2021,12 @@ static void correct_parent_keys(const struct ubifs_info *c, * zbranch has to be inserted to the @znode->zbranches[]' array at the @n-th * slot, zbranches starting from @n have to be moved right. */ -static void insert_zbranch(struct ubifs_znode *znode, +static void insert_zbranch(struct ubifs_info *c, struct ubifs_znode *znode, const struct ubifs_zbranch *zbr, int n) { int i; - ubifs_assert(ubifs_zn_dirty(znode)); + ubifs_assert(c, ubifs_zn_dirty(znode)); if (znode->level) { for (i = znode->child_cnt; i > n; i--) { @@ -2079,16 +2080,16 @@ static int tnc_insert(struct ubifs_info *c, struct ubifs_znode *znode, int i, keep, move, appending = 0; union ubifs_key *key = &zbr->key, *key1; - ubifs_assert(n >= 0 && n <= c->fanout); + ubifs_assert(c, n >= 0 && n <= c->fanout); /* Implement naive insert for now */ again: zp = znode->parent; if (znode->child_cnt < c->fanout) { - ubifs_assert(n != c->fanout); + ubifs_assert(c, n != c->fanout); dbg_tnck(key, "inserted at %d level %d, key ", n, znode->level); - insert_zbranch(znode, zbr, n); + insert_zbranch(c, znode, zbr, n); /* Ensure parent's key is correct */ if (n == 0 && zp && znode->iip == 0) @@ -2197,7 +2198,7 @@ do_split: /* Insert new key and branch */ dbg_tnck(key, "inserting at %d level %d, key ", n, zn->level); - insert_zbranch(zi, zbr, n); + insert_zbranch(c, zi, zbr, n); /* Insert new znode (produced by spitting) into the parent */ if (zp) { @@ -2495,8 +2496,8 @@ static int tnc_delete(struct ubifs_info *c, struct ubifs_znode *znode, int n) int i, err; /* Delete without merge for now */ - ubifs_assert(znode->level == 0); - ubifs_assert(n >= 0 && n < c->fanout); + ubifs_assert(c, znode->level == 0); + ubifs_assert(c, n >= 0 && n < c->fanout); dbg_tnck(&znode->zbranch[n].key, "deleting key "); zbr = &znode->zbranch[n]; @@ -2522,8 +2523,8 @@ static int tnc_delete(struct ubifs_info *c, struct ubifs_znode *znode, int n) */ do { - ubifs_assert(!ubifs_zn_obsolete(znode)); - ubifs_assert(ubifs_zn_dirty(znode)); + ubifs_assert(c, !ubifs_zn_obsolete(znode)); + ubifs_assert(c, ubifs_zn_dirty(znode)); zp = znode->parent; n = znode->iip; @@ -2545,7 +2546,7 @@ static int tnc_delete(struct ubifs_info *c, struct ubifs_znode *znode, int n) /* Remove from znode, entry n - 1 */ znode->child_cnt -= 1; - ubifs_assert(znode->level != 0); + ubifs_assert(c, znode->level != 0); for (i = n; i < znode->child_cnt; i++) { znode->zbranch[i] = znode->zbranch[i + 1]; if (znode->zbranch[i].znode) @@ -2578,8 +2579,8 @@ static int tnc_delete(struct ubifs_info *c, struct ubifs_znode *znode, int n) c->zroot.offs = zbr->offs; c->zroot.len = zbr->len; c->zroot.znode = znode; - ubifs_assert(!ubifs_zn_obsolete(zp)); - ubifs_assert(ubifs_zn_dirty(zp)); + ubifs_assert(c, !ubifs_zn_obsolete(zp)); + ubifs_assert(c, ubifs_zn_dirty(zp)); atomic_long_dec(&c->dirty_zn_cnt); if (zp->cnext) { @@ -2944,7 +2945,7 @@ struct ubifs_dent_node *ubifs_tnc_next_ent(struct ubifs_info *c, union ubifs_key *dkey; dbg_tnck(key, "key "); - ubifs_assert(is_hash_key(c, key)); + ubifs_assert(c, is_hash_key(c, key)); mutex_lock(&c->tnc_mutex); err = ubifs_lookup_level0(c, key, &znode, &n); @@ -3031,7 +3032,7 @@ static void tnc_destroy_cnext(struct ubifs_info *c) if (!c->cnext) return; - ubifs_assert(c->cmt_state == COMMIT_BROKEN); + ubifs_assert(c, c->cmt_state == COMMIT_BROKEN); cnext = c->cnext; do { struct ubifs_znode *znode = cnext; @@ -3053,8 +3054,8 @@ void ubifs_tnc_close(struct ubifs_info *c) long n, freed; n = atomic_long_read(&c->clean_zn_cnt); - freed = ubifs_destroy_tnc_subtree(c->zroot.znode); - ubifs_assert(freed == n); + freed = ubifs_destroy_tnc_subtree(c, c->zroot.znode); + ubifs_assert(c, freed == n); atomic_long_sub(n, &ubifs_clean_zn_cnt); } kfree(c->gap_lebs); @@ -3167,7 +3168,7 @@ static struct ubifs_znode *lookup_znode(struct ubifs_info *c, struct ubifs_znode *znode, *zn; int n, nn; - ubifs_assert(key_type(c, key) < UBIFS_INVALID_KEY); + ubifs_assert(c, key_type(c, key) < UBIFS_INVALID_KEY); /* * The arguments have probably been read off flash, so don't assume @@ -3206,7 +3207,7 @@ static struct ubifs_znode *lookup_znode(struct ubifs_info *c, if (IS_ERR(znode)) return znode; ubifs_search_zbranch(c, znode, key, &n); - ubifs_assert(n >= 0); + ubifs_assert(c, n >= 0); } if (znode->level == level + 1) break; @@ -3497,7 +3498,7 @@ int dbg_check_inode_size(struct ubifs_info *c, const struct inode *inode, if (err < 0) goto out_unlock; - ubifs_assert(err == 0); + ubifs_assert(c, err == 0); key = &znode->zbranch[n].key; if (!key_in_range(c, key, &from_key, &to_key)) goto out_unlock; diff --git a/fs/ubifs/tnc_commit.c b/fs/ubifs/tnc_commit.c index a9df94ad46a3..dba87d09b989 100644 --- a/fs/ubifs/tnc_commit.c +++ b/fs/ubifs/tnc_commit.c @@ -87,8 +87,8 @@ static int make_idx_node(struct ubifs_info *c, struct ubifs_idx_node *idx, atomic_long_dec(&c->dirty_zn_cnt); - ubifs_assert(ubifs_zn_dirty(znode)); - ubifs_assert(ubifs_zn_cow(znode)); + ubifs_assert(c, ubifs_zn_dirty(znode)); + ubifs_assert(c, ubifs_zn_cow(znode)); /* * Note, unlike 'write_index()' we do not add memory barriers here @@ -115,9 +115,9 @@ static int fill_gap(struct ubifs_info *c, int lnum, int gap_start, int gap_end, { int len, gap_remains, gap_pos, written, pad_len; - ubifs_assert((gap_start & 7) == 0); - ubifs_assert((gap_end & 7) == 0); - ubifs_assert(gap_end >= gap_start); + ubifs_assert(c, (gap_start & 7) == 0); + ubifs_assert(c, (gap_end & 7) == 0); + ubifs_assert(c, gap_end >= gap_start); gap_remains = gap_end - gap_start; if (!gap_remains) @@ -131,7 +131,7 @@ static int fill_gap(struct ubifs_info *c, int lnum, int gap_start, int gap_end, const int alen = ALIGN(len, 8); int err; - ubifs_assert(alen <= gap_remains); + ubifs_assert(c, alen <= gap_remains); err = make_idx_node(c, c->ileb_buf + gap_pos, znode, lnum, gap_pos, len); if (err) @@ -259,7 +259,7 @@ static int layout_leb_in_gaps(struct ubifs_info *c, int *p) struct ubifs_idx_node *idx; int in_use, level; - ubifs_assert(snod->type == UBIFS_IDX_NODE); + ubifs_assert(c, snod->type == UBIFS_IDX_NODE); idx = snod->node; key_read(c, ubifs_idx_key(c, idx), &snod->key); level = le16_to_cpu(idx->level); @@ -373,7 +373,7 @@ static int layout_in_gaps(struct ubifs_info *c, int cnt) p = c->gap_lebs; do { - ubifs_assert(p < c->gap_lebs + c->lst.idx_lebs); + ubifs_assert(c, p < c->gap_lebs + c->lst.idx_lebs); written = layout_leb_in_gaps(c, p); if (written < 0) { err = written; @@ -639,7 +639,7 @@ static int get_znodes_to_commit(struct ubifs_info *c) } cnt += 1; while (1) { - ubifs_assert(!ubifs_zn_cow(znode)); + ubifs_assert(c, !ubifs_zn_cow(znode)); __set_bit(COW_ZNODE, &znode->flags); znode->alt = 0; cnext = find_next_dirty(znode); @@ -652,7 +652,7 @@ static int get_znodes_to_commit(struct ubifs_info *c) cnt += 1; } dbg_cmt("committing %d znodes", cnt); - ubifs_assert(cnt == atomic_long_read(&c->dirty_zn_cnt)); + ubifs_assert(c, cnt == atomic_long_read(&c->dirty_zn_cnt)); return cnt; } @@ -760,7 +760,7 @@ int ubifs_tnc_start_commit(struct ubifs_info *c, struct ubifs_zbranch *zroot) err = layout_commit(c, no_space, cnt); if (err) goto out_free; - ubifs_assert(atomic_long_read(&c->dirty_zn_cnt) == 0); + ubifs_assert(c, atomic_long_read(&c->dirty_zn_cnt) == 0); err = free_unused_idx_lebs(c); if (err) goto out; @@ -781,7 +781,7 @@ int ubifs_tnc_start_commit(struct ubifs_info *c, struct ubifs_zbranch *zroot) * budgeting subsystem to assume the index is already committed, * even though it is not. */ - ubifs_assert(c->bi.min_idx_lebs == ubifs_calc_min_idx_lebs(c)); + ubifs_assert(c, c->bi.min_idx_lebs == ubifs_calc_min_idx_lebs(c)); c->bi.old_idx_sz = c->calc_idx_sz; c->bi.uncommitted_idx = 0; c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c); @@ -887,8 +887,8 @@ static int write_index(struct ubifs_info *c) /* Grab some stuff from znode while we still can */ cnext = znode->cnext; - ubifs_assert(ubifs_zn_dirty(znode)); - ubifs_assert(ubifs_zn_cow(znode)); + ubifs_assert(c, ubifs_zn_dirty(znode)); + ubifs_assert(c, ubifs_zn_cow(znode)); /* * It is important that other threads should see %DIRTY_ZNODE diff --git a/fs/ubifs/tnc_misc.c b/fs/ubifs/tnc_misc.c index 93f5b7859e6f..d90ee01076a9 100644 --- a/fs/ubifs/tnc_misc.c +++ b/fs/ubifs/tnc_misc.c @@ -31,19 +31,21 @@ /** * ubifs_tnc_levelorder_next - next TNC tree element in levelorder traversal. + * @c: UBIFS file-system description object * @zr: root of the subtree to traverse * @znode: previous znode * * This function implements levelorder TNC traversal. The LNC is ignored. * Returns the next element or %NULL if @znode is already the last one. */ -struct ubifs_znode *ubifs_tnc_levelorder_next(struct ubifs_znode *zr, +struct ubifs_znode *ubifs_tnc_levelorder_next(const struct ubifs_info *c, + struct ubifs_znode *zr, struct ubifs_znode *znode) { int level, iip, level_search = 0; struct ubifs_znode *zn; - ubifs_assert(zr); + ubifs_assert(c, zr); if (unlikely(!znode)) return zr; @@ -58,7 +60,7 @@ struct ubifs_znode *ubifs_tnc_levelorder_next(struct ubifs_znode *zr, iip = znode->iip; while (1) { - ubifs_assert(znode->level <= zr->level); + ubifs_assert(c, znode->level <= zr->level); /* * First walk up until there is a znode with next branch to @@ -85,7 +87,7 @@ struct ubifs_znode *ubifs_tnc_levelorder_next(struct ubifs_znode *zr, level_search = 1; iip = -1; znode = ubifs_tnc_find_child(zr, 0); - ubifs_assert(znode); + ubifs_assert(c, znode); } /* Switch to the next index */ @@ -111,7 +113,7 @@ struct ubifs_znode *ubifs_tnc_levelorder_next(struct ubifs_znode *zr, } if (zn) { - ubifs_assert(zn->level >= 0); + ubifs_assert(c, zn->level >= 0); return zn; } } @@ -140,7 +142,7 @@ int ubifs_search_zbranch(const struct ubifs_info *c, int uninitialized_var(cmp); const struct ubifs_zbranch *zbr = &znode->zbranch[0]; - ubifs_assert(end > beg); + ubifs_assert(c, end > beg); while (end > beg) { mid = (beg + end) >> 1; @@ -158,13 +160,13 @@ int ubifs_search_zbranch(const struct ubifs_info *c, *n = end - 1; /* The insert point is after *n */ - ubifs_assert(*n >= -1 && *n < znode->child_cnt); + ubifs_assert(c, *n >= -1 && *n < znode->child_cnt); if (*n == -1) - ubifs_assert(keys_cmp(c, key, &zbr[0].key) < 0); + ubifs_assert(c, keys_cmp(c, key, &zbr[0].key) < 0); else - ubifs_assert(keys_cmp(c, key, &zbr[*n].key) > 0); + ubifs_assert(c, keys_cmp(c, key, &zbr[*n].key) > 0); if (*n + 1 < znode->child_cnt) - ubifs_assert(keys_cmp(c, key, &zbr[*n + 1].key) < 0); + ubifs_assert(c, keys_cmp(c, key, &zbr[*n + 1].key) < 0); return 0; } @@ -195,16 +197,18 @@ struct ubifs_znode *ubifs_tnc_postorder_first(struct ubifs_znode *znode) /** * ubifs_tnc_postorder_next - next TNC tree element in postorder traversal. + * @c: UBIFS file-system description object * @znode: previous znode * * This function implements postorder TNC traversal. The LNC is ignored. * Returns the next element or %NULL if @znode is already the last one. */ -struct ubifs_znode *ubifs_tnc_postorder_next(struct ubifs_znode *znode) +struct ubifs_znode *ubifs_tnc_postorder_next(const struct ubifs_info *c, + struct ubifs_znode *znode) { struct ubifs_znode *zn; - ubifs_assert(znode); + ubifs_assert(c, znode); if (unlikely(!znode->parent)) return NULL; @@ -220,18 +224,20 @@ struct ubifs_znode *ubifs_tnc_postorder_next(struct ubifs_znode *znode) /** * ubifs_destroy_tnc_subtree - destroy all znodes connected to a subtree. + * @c: UBIFS file-system description object * @znode: znode defining subtree to destroy * * This function destroys subtree of the TNC tree. Returns number of clean * znodes in the subtree. */ -long ubifs_destroy_tnc_subtree(struct ubifs_znode *znode) +long ubifs_destroy_tnc_subtree(const struct ubifs_info *c, + struct ubifs_znode *znode) { struct ubifs_znode *zn = ubifs_tnc_postorder_first(znode); long clean_freed = 0; int n; - ubifs_assert(zn); + ubifs_assert(c, zn); while (1) { for (n = 0; n < zn->child_cnt; n++) { if (!zn->zbranch[n].znode) @@ -252,7 +258,7 @@ long ubifs_destroy_tnc_subtree(struct ubifs_znode *znode) return clean_freed; } - zn = ubifs_tnc_postorder_next(zn); + zn = ubifs_tnc_postorder_next(c, zn); } } @@ -410,7 +416,7 @@ struct ubifs_znode *ubifs_load_znode(struct ubifs_info *c, int err; struct ubifs_znode *znode; - ubifs_assert(!zbr->znode); + ubifs_assert(c, !zbr->znode); /* * A slab cache is not presently used for znodes because the znode size * depends on the fanout which is stored in the superblock. @@ -435,7 +441,7 @@ struct ubifs_znode *ubifs_load_znode(struct ubifs_info *c, zbr->znode = znode; znode->parent = parent; - znode->time = get_seconds(); + znode->time = ktime_get_seconds(); znode->iip = iip; return znode; diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 04bf84d71e7b..4368cde476b0 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -258,6 +258,18 @@ enum { LEB_RETAINED, }; +/* + * Action taken upon a failed ubifs_assert(). + * @ASSACT_REPORT: just report the failed assertion + * @ASSACT_RO: switch to read-only mode + * @ASSACT_PANIC: call BUG() and possible panic the kernel + */ +enum { + ASSACT_REPORT = 0, + ASSACT_RO, + ASSACT_PANIC, +}; + /** * struct ubifs_old_idx - index node obsoleted since last commit start. * @rb: rb-tree node @@ -758,7 +770,7 @@ struct ubifs_znode { struct ubifs_znode *parent; struct ubifs_znode *cnext; unsigned long flags; - unsigned long time; + time64_t time; int level; int child_cnt; int iip; @@ -1015,6 +1027,7 @@ struct ubifs_debug_info; * @bulk_read: enable bulk-reads * @default_compr: default compression algorithm (%UBIFS_COMPR_LZO, etc) * @rw_incompat: the media is not R/W compatible + * @assert_action: action to take when a ubifs_assert() fails * * @tnc_mutex: protects the Tree Node Cache (TNC), @zroot, @cnext, @enext, and * @calc_idx_sz @@ -1256,6 +1269,7 @@ struct ubifs_info { unsigned int bulk_read:1; unsigned int default_compr:2; unsigned int rw_incompat:1; + unsigned int assert_action:2; struct mutex tnc_mutex; struct ubifs_zbranch zroot; @@ -1608,14 +1622,17 @@ int ubifs_tnc_get_bu_keys(struct ubifs_info *c, struct bu_info *bu); int ubifs_tnc_bulk_read(struct ubifs_info *c, struct bu_info *bu); /* tnc_misc.c */ -struct ubifs_znode *ubifs_tnc_levelorder_next(struct ubifs_znode *zr, +struct ubifs_znode *ubifs_tnc_levelorder_next(const struct ubifs_info *c, + struct ubifs_znode *zr, struct ubifs_znode *znode); int ubifs_search_zbranch(const struct ubifs_info *c, const struct ubifs_znode *znode, const union ubifs_key *key, int *n); struct ubifs_znode *ubifs_tnc_postorder_first(struct ubifs_znode *znode); -struct ubifs_znode *ubifs_tnc_postorder_next(struct ubifs_znode *znode); -long ubifs_destroy_tnc_subtree(struct ubifs_znode *zr); +struct ubifs_znode *ubifs_tnc_postorder_next(const struct ubifs_info *c, + struct ubifs_znode *znode); +long ubifs_destroy_tnc_subtree(const struct ubifs_info *c, + struct ubifs_znode *zr); struct ubifs_znode *ubifs_load_znode(struct ubifs_info *c, struct ubifs_zbranch *zbr, struct ubifs_znode *parent, int iip); @@ -1698,7 +1715,7 @@ struct ubifs_nnode *ubifs_get_nnode(struct ubifs_info *c, int ubifs_read_nnode(struct ubifs_info *c, struct ubifs_nnode *parent, int iip); void ubifs_add_lpt_dirt(struct ubifs_info *c, int lnum, int dirty); void ubifs_add_nnode_dirt(struct ubifs_info *c, struct ubifs_nnode *nnode); -uint32_t ubifs_unpack_bits(uint8_t **addr, int *pos, int nrbits); +uint32_t ubifs_unpack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, int nrbits); struct ubifs_nnode *ubifs_first_nnode(struct ubifs_info *c, int *hght); /* Needed only in debugging code in lpt_commit.c */ int ubifs_unpack_nnode(const struct ubifs_info *c, void *buf, @@ -1755,7 +1772,13 @@ int ubifs_xattr_set(struct inode *host, const char *name, const void *value, size_t size, int flags, bool check_lock); ssize_t ubifs_xattr_get(struct inode *host, const char *name, void *buf, size_t size); + +#ifdef CONFIG_UBIFS_FS_XATTR void ubifs_evict_xattr_inode(struct ubifs_info *c, ino_t xattr_inum); +#else +static inline void ubifs_evict_xattr_inode(struct ubifs_info *c, + ino_t xattr_inum) { } +#endif #ifdef CONFIG_UBIFS_FS_SECURITY extern int ubifs_init_security(struct inode *dentry, struct inode *inode, @@ -1812,14 +1835,16 @@ static inline int ubifs_encrypt(const struct inode *inode, unsigned int in_len, unsigned int *out_len, int block) { - ubifs_assert(0); + struct ubifs_info *c = inode->i_sb->s_fs_info; + ubifs_assert(c, 0); return -EOPNOTSUPP; } static inline int ubifs_decrypt(const struct inode *inode, struct ubifs_data_node *dn, unsigned int *out_len, int block) { - ubifs_assert(0); + struct ubifs_info *c = inode->i_sb->s_fs_info; + ubifs_assert(c, 0); return -EOPNOTSUPP; } #else diff --git a/fs/ubifs/xattr.c b/fs/ubifs/xattr.c index 6f720fdf5020..61afdfee4b28 100644 --- a/fs/ubifs/xattr.c +++ b/fs/ubifs/xattr.c @@ -152,6 +152,12 @@ static int create_xattr(struct ubifs_info *c, struct inode *host, ui->data_len = size; mutex_lock(&host_ui->ui_mutex); + + if (!host->i_nlink) { + err = -ENOENT; + goto out_noent; + } + host->i_ctime = current_time(host); host_ui->xattr_cnt += 1; host_ui->xattr_size += CALC_DENT_SIZE(fname_len(nm)); @@ -184,6 +190,7 @@ out_cancel: host_ui->xattr_size -= CALC_XATTR_BYTES(size); host_ui->xattr_names -= fname_len(nm); host_ui->flags &= ~UBIFS_CRYPT_FL; +out_noent: mutex_unlock(&host_ui->ui_mutex); out_free: make_bad_inode(inode); @@ -216,7 +223,7 @@ static int change_xattr(struct ubifs_info *c, struct inode *host, struct ubifs_budget_req req = { .dirtied_ino = 2, .dirtied_ino_d = ALIGN(size, 8) + ALIGN(host_ui->data_len, 8) }; - ubifs_assert(ui->data_len == inode->i_size); + ubifs_assert(c, ui->data_len == inode->i_size); err = ubifs_budget_space(c, &req); if (err) return err; @@ -235,6 +242,12 @@ static int change_xattr(struct ubifs_info *c, struct inode *host, mutex_unlock(&ui->ui_mutex); mutex_lock(&host_ui->ui_mutex); + + if (!host->i_nlink) { + err = -ENOENT; + goto out_noent; + } + host->i_ctime = current_time(host); host_ui->xattr_size -= CALC_XATTR_BYTES(old_size); host_ui->xattr_size += CALC_XATTR_BYTES(size); @@ -256,6 +269,7 @@ static int change_xattr(struct ubifs_info *c, struct inode *host, out_cancel: host_ui->xattr_size -= CALC_XATTR_BYTES(size); host_ui->xattr_size += CALC_XATTR_BYTES(old_size); +out_noent: mutex_unlock(&host_ui->ui_mutex); make_bad_inode(inode); out_free: @@ -291,7 +305,7 @@ int ubifs_xattr_set(struct inode *host, const char *name, const void *value, int err; if (check_lock) - ubifs_assert(inode_is_locked(host)); + ubifs_assert(c, inode_is_locked(host)); if (size > UBIFS_MAX_INO_DATA) return -ERANGE; @@ -374,8 +388,8 @@ ssize_t ubifs_xattr_get(struct inode *host, const char *name, void *buf, } ui = ubifs_inode(inode); - ubifs_assert(inode->i_size == ui->data_len); - ubifs_assert(ubifs_inode(host)->xattr_size > ui->data_len); + ubifs_assert(c, inode->i_size == ui->data_len); + ubifs_assert(c, ubifs_inode(host)->xattr_size > ui->data_len); mutex_lock(&ui->ui_mutex); if (buf) { @@ -462,7 +476,7 @@ ssize_t ubifs_listxattr(struct dentry *dentry, char *buffer, size_t size) return err; } - ubifs_assert(written <= size); + ubifs_assert(c, written <= size); return written; } @@ -475,13 +489,19 @@ static int remove_xattr(struct ubifs_info *c, struct inode *host, struct ubifs_budget_req req = { .dirtied_ino = 2, .mod_dent = 1, .dirtied_ino_d = ALIGN(host_ui->data_len, 8) }; - ubifs_assert(ui->data_len == inode->i_size); + ubifs_assert(c, ui->data_len == inode->i_size); err = ubifs_budget_space(c, &req); if (err) return err; mutex_lock(&host_ui->ui_mutex); + + if (!host->i_nlink) { + err = -ENOENT; + goto out_noent; + } + host->i_ctime = current_time(host); host_ui->xattr_cnt -= 1; host_ui->xattr_size -= CALC_DENT_SIZE(fname_len(nm)); @@ -501,6 +521,7 @@ out_cancel: host_ui->xattr_size += CALC_DENT_SIZE(fname_len(nm)); host_ui->xattr_size += CALC_XATTR_BYTES(ui->data_len); host_ui->xattr_names += fname_len(nm); +out_noent: mutex_unlock(&host_ui->ui_mutex); ubifs_release_budget(c, &req); make_bad_inode(inode); @@ -538,7 +559,10 @@ static int ubifs_xattr_remove(struct inode *host, const char *name) union ubifs_key key; int err; - ubifs_assert(inode_is_locked(host)); + ubifs_assert(c, inode_is_locked(host)); + + if (!host->i_nlink) + return -ENOENT; if (fname_len(&nm) > UBIFS_MAX_NLEN) return -ENAMETOOLONG; @@ -561,7 +585,7 @@ static int ubifs_xattr_remove(struct inode *host, const char *name) goto out_free; } - ubifs_assert(inode->i_nlink == 1); + ubifs_assert(c, inode->i_nlink == 1); clear_nlink(inode); err = remove_xattr(c, host, inode, &nm); if (err) diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h index e811ef7b8350..b3353e21f3b3 100644 --- a/include/asm-generic/tlb.h +++ b/include/asm-generic/tlb.h @@ -15,6 +15,7 @@ #ifndef _ASM_GENERIC__TLB_H #define _ASM_GENERIC__TLB_H +#include <linux/mmu_notifier.h> #include <linux/swap.h> #include <asm/pgalloc.h> #include <asm/tlbflush.h> @@ -138,6 +139,16 @@ static inline void __tlb_reset_range(struct mmu_gather *tlb) } } +static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb) +{ + if (!tlb->end) + return; + + tlb_flush(tlb); + mmu_notifier_invalidate_range(tlb->mm, tlb->start, tlb->end); + __tlb_reset_range(tlb); +} + static inline void tlb_remove_page_size(struct mmu_gather *tlb, struct page *page, int page_size) { @@ -186,10 +197,8 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb, #define __tlb_end_vma(tlb, vma) \ do { \ - if (!tlb->fullmm && tlb->end) { \ - tlb_flush(tlb); \ - __tlb_reset_range(tlb); \ - } \ + if (!tlb->fullmm) \ + tlb_flush_mmu_tlbonly(tlb); \ } while (0) #ifndef tlb_end_vma @@ -303,14 +312,4 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb, #define tlb_migrate_finish(mm) do {} while (0) -/* - * Used to flush the TLB when page tables are removed, when lazy - * TLB mode may cause a CPU to retain intermediate translations - * pointing to about-to-be-freed page table memory. - */ -#ifndef HAVE_TLB_FLUSH_REMOVE_TABLES -#define tlb_flush_remove_tables(mm) do {} while (0) -#define tlb_flush_remove_tables_local(mm) do {} while (0) -#endif - #endif /* _ASM_GENERIC__TLB_H */ diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h index 2c005376ac0e..7138384e2ef9 100644 --- a/include/dt-bindings/bus/ti-sysc.h +++ b/include/dt-bindings/bus/ti-sysc.h @@ -15,6 +15,8 @@ /* SmartReflex sysc found on 36xx and later */ #define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) +#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) + /* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ #define SYSC_IDLE_FORCE 0 #define SYSC_IDLE_NO 1 diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h index 5e1061b15aed..d7549c57cac3 100644 --- a/include/dt-bindings/clock/dra7.h +++ b/include/dt-bindings/clock/dra7.h @@ -168,5 +168,6 @@ #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) #endif diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h deleted file mode 100644 index 842cdc0adff1..000000000000 --- a/include/dt-bindings/clock/exynos5440.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Hajda <a.hajda@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for Exynos5440 clock controller. -*/ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H -#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H - -#define CLK_XTAL 1 -#define CLK_ARM_CLK 2 -#define CLK_CPLLA 3 -#define CLK_CPLLB 4 -#define CLK_SPI_BAUD 16 -#define CLK_PB0_250 17 -#define CLK_PR0_250 18 -#define CLK_PR1_250 19 -#define CLK_B_250 20 -#define CLK_B_125 21 -#define CLK_B_200 22 -#define CLK_SATA 23 -#define CLK_USB 24 -#define CLK_GMAC0 25 -#define CLK_CS250 26 -#define CLK_PB0_250_O 27 -#define CLK_PR0_250_O 28 -#define CLK_PR1_250_O 29 -#define CLK_B_250_O 30 -#define CLK_B_125_O 31 -#define CLK_B_200_O 32 -#define CLK_SATA_O 33 -#define CLK_USB_O 34 -#define CLK_GMAC0_O 35 -#define CLK_CS250_O 36 - -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 37 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h new file mode 100644 index 000000000000..6f9aa7349cef --- /dev/null +++ b/include/dt-bindings/memory/mt2712-larb-port.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef __DTS_IOMMU_PORT_MT2712_H +#define __DTS_IOMMU_PORT_MT2712_H + +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 +#define M4U_LARB4_ID 4 +#define M4U_LARB5_ID 5 +#define M4U_LARB6_ID 6 +#define M4U_LARB7_ID 7 +#define M4U_LARB8_ID 8 +#define M4U_LARB9_ID 9 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) + +/* larb1 */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) + +/* larb2 */ +#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) + +/* larb3 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) + +/* larb4 */ +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) +#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) +#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) +#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) + +/* larb5 */ +#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) +#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) +#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) + +/* larb6 */ +#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) +#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) +#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) +#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) + +/* larb7 */ +#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) +#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) + +/* larb8 */ +#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) +#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) +#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) + +/* larb9 */ +#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) +#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) + +#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h new file mode 100644 index 000000000000..476c5fc873b6 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H + +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index 6aca5ce8a99a..931ab05f771d 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -47,8 +47,10 @@ #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ +#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ +#define AT91_PMC_KEY_MASK (0xff << 16) #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ @@ -155,6 +157,19 @@ #define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ +#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ +#define AT91_PMC_FSTT(n) BIT(n) +#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ +#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ +#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ +#define AT91_PMC_LPM BIT(20) /* Low-power Mode */ +#define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */ +#define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */ + +#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */ + +#define AT91_PMC_FS_INPUT_MASK 0x7ff + #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h index 90479a0f3986..3525c179698c 100644 --- a/include/linux/compiler_types.h +++ b/include/linux/compiler_types.h @@ -67,6 +67,18 @@ extern void __chk_io_ptr(const volatile void __iomem *); #endif /* + * Some architectures need to provide custom definitions of macros provided + * by linux/compiler-*.h, and can do so using asm/compiler.h. We include that + * conditionally rather than using an asm-generic wrapper in order to avoid + * build failures if any C compilation, which will include this file via an + * -include argument in c_flags, occurs prior to the asm-generic wrappers being + * generated. + */ +#ifdef CONFIG_HAVE_ARCH_COMPILER_H +#include <asm/compiler.h> +#endif + +/* * Generic compiler-independent macros required for kernel * build go below this comment. Actual compiler/compiler version * specific implementations come from the above header files diff --git a/include/linux/console.h b/include/linux/console.h index f59f3dbca65c..ec9bdb3d7bab 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -14,6 +14,7 @@ #ifndef _LINUX_CONSOLE_H_ #define _LINUX_CONSOLE_H_ 1 +#include <linux/atomic.h> #include <linux/types.h> struct vc_data; @@ -201,11 +202,14 @@ void vcs_make_sysfs(int index); void vcs_remove_sysfs(int index); /* Some debug stub to catch some of the obvious races in the VT code */ -#if 1 -#define WARN_CONSOLE_UNLOCKED() WARN_ON(!is_console_locked() && !oops_in_progress) -#else -#define WARN_CONSOLE_UNLOCKED() -#endif +#define WARN_CONSOLE_UNLOCKED() \ + WARN_ON(!atomic_read(&ignore_console_lock_warning) && \ + !is_console_locked() && !oops_in_progress) +/* + * Increment ignore_console_lock_warning if you need to quiet + * WARN_CONSOLE_UNLOCKED() for debugging purposes. + */ +extern atomic_t ignore_console_lock_warning; /* VESA Blanking Levels */ #define VESA_NO_BLANKING 0 diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index c49843c4d031..caf40ad0bbc6 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -144,6 +144,7 @@ enum cpuhp_state { CPUHP_AP_SMPBOOT_THREADS, CPUHP_AP_X86_VDSO_VMA_ONLINE, CPUHP_AP_IRQ_AFFINITY_ONLINE, + CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS, CPUHP_AP_PERF_ONLINE, CPUHP_AP_PERF_X86_ONLINE, CPUHP_AP_PERF_X86_UNCORE_ONLINE, diff --git a/include/linux/fb.h b/include/linux/fb.h index aa74a228bb92..3e7e75383d32 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -126,7 +126,7 @@ struct fb_cursor_user { /* The resolution of the passed in fb_info about to change */ #define FB_EVENT_MODE_CHANGE 0x01 -/* The display on this fb_info is beeing suspended, no access to the +/* The display on this fb_info is being suspended, no access to the * framebuffer is allowed any more after that call returns */ #define FB_EVENT_SUSPEND 0x02 @@ -159,9 +159,9 @@ struct fb_cursor_user { #define FB_EVENT_FB_UNBIND 0x0E /* CONSOLE-SPECIFIC: remap all consoles to new fb - for vga_switcheroo */ #define FB_EVENT_REMAP_ALL_CONSOLE 0x0F -/* A hardware display blank early change occured */ +/* A hardware display blank early change occurred */ #define FB_EARLY_EVENT_BLANK 0x10 -/* A hardware display blank revert early change occured */ +/* A hardware display blank revert early change occurred */ #define FB_R_EARLY_EVENT_BLANK 0x11 struct fb_event { @@ -650,6 +650,10 @@ extern struct fb_info *registered_fb[FB_MAX]; extern int num_registered_fb; extern struct class *fb_class; +#define for_each_registered_fb(i) \ + for (i = 0; i < FB_MAX; i++) \ + if (!registered_fb[i]) {} else + extern int lock_fb_info(struct fb_info *info); static inline void unlock_fb_info(struct fb_info *info) diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h index 4fd95dbeb52f..b065ef406770 100644 --- a/include/linux/lockd/lockd.h +++ b/include/linux/lockd/lockd.h @@ -299,7 +299,7 @@ int nlmsvc_unlock_all_by_ip(struct sockaddr *server_addr); static inline struct inode *nlmsvc_file_inode(struct nlm_file *file) { - return file_inode(file->f_file); + return locks_inode(file->f_file); } static inline int __nlm_privileged_request4(const struct sockaddr *sap) @@ -359,7 +359,7 @@ static inline int nlm_privileged_requester(const struct svc_rqst *rqstp) static inline int nlm_compare_locks(const struct file_lock *fl1, const struct file_lock *fl2) { - return file_inode(fl1->fl_file) == file_inode(fl2->fl_file) + return locks_inode(fl1->fl_file) == locks_inode(fl2->fl_file) && fl1->fl_pid == fl2->fl_pid && fl1->fl_owner == fl2->fl_owner && fl1->fl_start == fl2->fl_start diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index e06f5f79eaef..6c1ad160ed87 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -457,4 +457,7 @@ #define MCLK_DIR(x) (x == 1 ? IMX6UL_GPR1_SAI1_MCLK_DIR : x == 2 ? \ IMX6UL_GPR1_SAI2_MCLK_DIR : IMX6UL_GPR1_SAI3_MCLK_DIR) +/* For imx6sll iomux gpr register field define */ +#define IMX6SLL_GPR5_AFCG_X_BYPASS_MASK (0x1f << 11) + #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h index 57ffaa20d564..1b06f0b28453 100644 --- a/include/linux/nfs4.h +++ b/include/linux/nfs4.h @@ -374,6 +374,13 @@ enum lock_type4 { NFS4_WRITEW_LT = 4 }; +enum change_attr_type4 { + NFS4_CHANGE_TYPE_IS_MONOTONIC_INCR = 0, + NFS4_CHANGE_TYPE_IS_VERSION_COUNTER = 1, + NFS4_CHANGE_TYPE_IS_VERSION_COUNTER_NOPNFS = 2, + NFS4_CHANGE_TYPE_IS_TIME_METADATA = 3, + NFS4_CHANGE_TYPE_IS_UNDEFINED = 4 +}; /* Mandatory Attributes */ #define FATTR4_WORD0_SUPPORTED_ATTRS (1UL << 0) @@ -441,6 +448,7 @@ enum lock_type4 { #define FATTR4_WORD2_LAYOUT_BLKSIZE (1UL << 1) #define FATTR4_WORD2_MDSTHRESHOLD (1UL << 4) #define FATTR4_WORD2_CLONE_BLKSIZE (1UL << 13) +#define FATTR4_WORD2_CHANGE_ATTR_TYPE (1UL << 15) #define FATTR4_WORD2_SECURITY_LABEL (1UL << 16) #define FATTR4_WORD2_MODE_UMASK (1UL << 17) @@ -527,6 +535,7 @@ enum { NFSPROC4_CLNT_LAYOUTSTATS, NFSPROC4_CLNT_CLONE, NFSPROC4_CLNT_COPY, + NFSPROC4_CLNT_OFFLOAD_CANCEL, NFSPROC4_CLNT_LOOKUPP, }; diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 2f129bbfaae8..a0831e9d19c9 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -185,6 +185,17 @@ struct nfs_inode { struct inode vfs_inode; }; +struct nfs4_copy_state { + struct list_head copies; + nfs4_stateid stateid; + struct completion completion; + uint64_t count; + struct nfs_writeverf verf; + int error; + int flags; + struct nfs4_state *parent_state; +}; + /* * Access bit flags */ diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h index 74ae3e1d19a0..bf39d9c92201 100644 --- a/include/linux/nfs_fs_sb.h +++ b/include/linux/nfs_fs_sb.h @@ -28,7 +28,6 @@ struct nfs41_impl_id; struct nfs_client { refcount_t cl_count; atomic_t cl_mds_count; - seqcount_t cl_callback_count; int cl_cons_state; /* current construction state (-ve: init error) */ #define NFS_CS_READY 0 /* ready to be used */ #define NFS_CS_INITING 1 /* busy initialising */ @@ -122,6 +121,7 @@ struct nfs_client { #endif struct net *cl_net; + struct list_head pending_cb_stateids; }; /* @@ -209,6 +209,7 @@ struct nfs_server { struct list_head state_owners_lru; struct list_head layouts; struct list_head delegations; + struct list_head ss_copies; unsigned long mig_gen; unsigned long mig_status; @@ -256,5 +257,6 @@ struct nfs_server { #define NFS_CAP_LAYOUTSTATS (1U << 22) #define NFS_CAP_CLONE (1U << 23) #define NFS_CAP_COPY (1U << 24) +#define NFS_CAP_OFFLOAD_CANCEL (1U << 25) #endif diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index 712eed156d09..bd1c889a9ed9 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -271,7 +271,6 @@ struct nfs4_layoutget { struct nfs4_layoutget_args args; struct nfs4_layoutget_res res; struct rpc_cred *cred; - unsigned callback_count; gfp_t gfp_flags; }; @@ -1389,9 +1388,11 @@ struct nfs42_copy_args { u64 dst_pos; u64 count; + bool sync; }; struct nfs42_write_res { + nfs4_stateid stateid; u64 count; struct nfs_writeverf verifier; }; @@ -1404,6 +1405,18 @@ struct nfs42_copy_res { struct nfs_commitres commit_res; }; +struct nfs42_offload_status_args { + struct nfs4_sequence_args osa_seq_args; + struct nfs_fh *osa_src_fh; + nfs4_stateid osa_stateid; +}; + +struct nfs42_offload_status_res { + struct nfs4_sequence_res osr_seq_res; + uint64_t osr_count; + int osr_status; +}; + struct nfs42_seek_args { struct nfs4_sequence_args seq_args; diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/include/linux/platform_data/ams-delta-fiq.h index 6dfc3e1210a3..cf4589ccb720 100644 --- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h +++ b/include/linux/platform_data/ams-delta-fiq.h @@ -1,5 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + /* - * arch/arm/mach-omap1/include/ams-delta-fiq.h + * include/linux/platform_data/ams-delta-fiq.h * * Taken from the original Amstrad modifications to fiq.h * @@ -11,24 +13,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef __AMS_DELTA_FIQ_H -#define __AMS_DELTA_FIQ_H - -#include <mach/irqs.h> - -/* - * Interrupt number used for passing control from FIQ to IRQ. - * IRQ12, described as reserved, has been selected. - */ -#define INT_DEFERRED_FIQ INT_1510_RES12 -/* - * Base address of an interrupt handler that the INT_DEFERRED_FIQ belongs to. - */ -#if (INT_DEFERRED_FIQ < IH2_BASE) -#define DEFERRED_FIQ_IH_BASE OMAP_IH1_BASE -#else -#define DEFERRED_FIQ_IH_BASE OMAP_IH2_BASE -#endif +#ifndef __LINUX_PLATFORM_DATA_AMS_DELTA_FIQ_H +#define __LINUX_PLATFORM_DATA_AMS_DELTA_FIQ_H /* * These are the offsets from the beginning of the fiq_buffer. They are put here @@ -69,11 +55,4 @@ #define FIQ_CIRC_BUFF 30 /*Start of circular buffer */ -#ifndef __ASSEMBLER__ -extern unsigned int fiq_buffer[]; -extern unsigned char qwerty_fiqin_start, qwerty_fiqin_end; - -extern void __init ams_delta_init_fiq(void); -#endif - #endif diff --git a/include/linux/platform_data/mtd-davinci-aemif.h b/include/linux/platform_data/mtd-davinci-aemif.h index 97948ac2bb9b..a403dd51dacc 100644 --- a/include/linux/platform_data/mtd-davinci-aemif.h +++ b/include/linux/platform_data/mtd-davinci-aemif.h @@ -33,5 +33,4 @@ struct davinci_aemif_timing { u8 ta; }; -int davinci_aemif_setup(struct platform_device *pdev); #endif diff --git a/include/linux/platform_data/pm33xx.h b/include/linux/platform_data/pm33xx.h index f9bed2a0af9d..fbf5ed73c7cc 100644 --- a/include/linux/platform_data/pm33xx.h +++ b/include/linux/platform_data/pm33xx.h @@ -12,6 +12,29 @@ #include <linux/kbuild.h> #include <linux/types.h> +/* + * WFI Flags for sleep code control + * + * These flags allow PM code to exclude certain operations from happening + * in the low level ASM code found in sleep33xx.S and sleep43xx.S + * + * WFI_FLAG_FLUSH_CACHE: Flush the ARM caches and disable caching. Only + * needed when MPU will lose context. + * WFI_FLAG_SELF_REFRESH: Let EMIF place DDR memory into self-refresh and + * disable EMIF. + * WFI_FLAG_SAVE_EMIF: Save context of all EMIF registers and restore in + * resume path. Only needed if PER domain loses context + * and must also have WFI_FLAG_SELF_REFRESH set. + * WFI_FLAG_WAKE_M3: Disable MPU clock or clockdomain to cause wkup_m3 to + * execute when WFI instruction executes. + * WFI_FLAG_RTC_ONLY: Configure the RTC to enter RTC+DDR mode. + */ +#define WFI_FLAG_FLUSH_CACHE BIT(0) +#define WFI_FLAG_SELF_REFRESH BIT(1) +#define WFI_FLAG_SAVE_EMIF BIT(2) +#define WFI_FLAG_WAKE_M3 BIT(3) +#define WFI_FLAG_RTC_ONLY BIT(4) + #ifndef __ASSEMBLER__ struct am33xx_pm_sram_addr { void (*do_wfi)(void); @@ -19,12 +42,15 @@ struct am33xx_pm_sram_addr { unsigned long *resume_offset; unsigned long *emif_sram_table; unsigned long *ro_sram_data; + unsigned long resume_address; }; struct am33xx_pm_platform_data { int (*init)(void); - int (*soc_suspend)(unsigned int state, int (*fn)(unsigned long)); + int (*soc_suspend)(unsigned int state, int (*fn)(unsigned long), + unsigned long args); struct am33xx_pm_sram_addr *(*get_sram_addrs)(void); + void __iomem *(*get_rtc_base_addr)(void); }; struct am33xx_pm_sram_data { @@ -36,6 +62,7 @@ struct am33xx_pm_sram_data { struct am33xx_pm_ro_sram_data { u32 amx3_pm_sram_data_virt; u32 amx3_pm_sram_data_phys; + void __iomem *rtc_base_virt; } __packed __aligned(8); #endif /* __ASSEMBLER__ */ diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 990aad477458..2efa3470a451 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -14,6 +14,7 @@ enum ti_sysc_module_type { TI_SYSC_OMAP4_SR, TI_SYSC_OMAP4_MCASP, TI_SYSC_OMAP4_USB_HOST_FS, + TI_SYSC_DRA7_MCAN, }; struct ti_sysc_cookie { diff --git a/include/linux/soc/renesas/rcar-sysc.h b/include/linux/soc/renesas/rcar-sysc.h index 8a6086d2e9c3..00fae6fd234d 100644 --- a/include/linux/soc/renesas/rcar-sysc.h +++ b/include/linux/soc/renesas/rcar-sysc.h @@ -2,16 +2,7 @@ #ifndef __LINUX_SOC_RENESAS_RCAR_SYSC_H__ #define __LINUX_SOC_RENESAS_RCAR_SYSC_H__ -#include <linux/types.h> - -struct rcar_sysc_ch { - u16 chan_offs; - u8 chan_bit; - u8 isr_bit; -}; - -int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch); -int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch); -void rcar_sysc_init(phys_addr_t base, u32 syscier); +int rcar_sysc_power_down_cpu(unsigned int cpu); +int rcar_sysc_power_up_cpu(unsigned int cpu); #endif /* __LINUX_SOC_RENESAS_RCAR_SYSC_H__ */ diff --git a/include/linux/sunrpc/auth.h b/include/linux/sunrpc/auth.h index d9af474a857d..58a6765c1c5e 100644 --- a/include/linux/sunrpc/auth.h +++ b/include/linux/sunrpc/auth.h @@ -125,7 +125,8 @@ struct rpc_authops { struct module *owner; rpc_authflavor_t au_flavor; /* flavor (RPC_AUTH_*) */ char * au_name; - struct rpc_auth * (*create)(struct rpc_auth_create_args *, struct rpc_clnt *); + struct rpc_auth * (*create)(const struct rpc_auth_create_args *, + struct rpc_clnt *); void (*destroy)(struct rpc_auth *); int (*hash_cred)(struct auth_cred *, unsigned int); @@ -174,7 +175,7 @@ struct rpc_cred * rpc_lookup_generic_cred(struct auth_cred *, int, gfp_t); struct rpc_cred * rpc_lookup_machine_cred(const char *service_name); int rpcauth_register(const struct rpc_authops *); int rpcauth_unregister(const struct rpc_authops *); -struct rpc_auth * rpcauth_create(struct rpc_auth_create_args *, +struct rpc_auth * rpcauth_create(const struct rpc_auth_create_args *, struct rpc_clnt *); void rpcauth_release(struct rpc_auth *); rpc_authflavor_t rpcauth_get_pseudoflavor(rpc_authflavor_t, diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 9b11b6a0978c..73d5c4a870fa 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -156,6 +156,7 @@ int rpc_switch_client_transport(struct rpc_clnt *, void rpc_shutdown_client(struct rpc_clnt *); void rpc_release_client(struct rpc_clnt *); +void rpc_task_release_transport(struct rpc_task *); void rpc_task_release_client(struct rpc_task *); int rpcb_create_local(struct net *); diff --git a/include/linux/sunrpc/metrics.h b/include/linux/sunrpc/metrics.h index 9baed7b355b2..1b3751327575 100644 --- a/include/linux/sunrpc/metrics.h +++ b/include/linux/sunrpc/metrics.h @@ -82,7 +82,7 @@ void rpc_count_iostats(const struct rpc_task *, struct rpc_iostats *); void rpc_count_iostats_metrics(const struct rpc_task *, struct rpc_iostats *); -void rpc_print_iostats(struct seq_file *, struct rpc_clnt *); +void rpc_clnt_show_stats(struct seq_file *, struct rpc_clnt *); void rpc_free_iostats(struct rpc_iostats *); #else /* CONFIG_PROC_FS */ @@ -95,7 +95,7 @@ static inline void rpc_count_iostats_metrics(const struct rpc_task *task, { } -static inline void rpc_print_iostats(struct seq_file *seq, struct rpc_clnt *clnt) {} +static inline void rpc_clnt_show_stats(struct seq_file *seq, struct rpc_clnt *clnt) {} static inline void rpc_free_iostats(struct rpc_iostats *stats) {} #endif /* CONFIG_PROC_FS */ diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h index 574368e8a16f..73e130a840ce 100644 --- a/include/linux/sunrpc/svc.h +++ b/include/linux/sunrpc/svc.h @@ -496,9 +496,11 @@ void svc_reserve(struct svc_rqst *rqstp, int space); struct svc_pool * svc_pool_for_cpu(struct svc_serv *serv, int cpu); char * svc_print_addr(struct svc_rqst *, char *, size_t); unsigned int svc_fill_write_vector(struct svc_rqst *rqstp, + struct page **pages, struct kvec *first, size_t total); char *svc_fill_symlink_pathname(struct svc_rqst *rqstp, - struct kvec *first, size_t total); + struct kvec *first, void *p, + size_t total); #define RPC_MAX_ADDRBUFLEN (63U) diff --git a/include/linux/sunrpc/svcauth.h b/include/linux/sunrpc/svcauth.h index 7c3656505847..04e404a07882 100644 --- a/include/linux/sunrpc/svcauth.h +++ b/include/linux/sunrpc/svcauth.h @@ -31,6 +31,7 @@ struct svc_cred { /* name of form servicetype@hostname, passed down by * rpc.svcgssd, or computed from the above: */ char *cr_principal; + char *cr_targ_princ; struct gss_api_mech *cr_gss_mech; }; @@ -39,6 +40,7 @@ static inline void init_svc_cred(struct svc_cred *cred) cred->cr_group_info = NULL; cred->cr_raw_principal = NULL; cred->cr_principal = NULL; + cred->cr_targ_princ = NULL; cred->cr_gss_mech = NULL; } @@ -48,6 +50,7 @@ static inline void free_svc_cred(struct svc_cred *cred) put_group_info(cred->cr_group_info); kfree(cred->cr_raw_principal); kfree(cred->cr_principal); + kfree(cred->cr_targ_princ); gss_mech_put(cred->cr_gss_mech); init_svc_cred(cred); } diff --git a/include/linux/wkup_m3_ipc.h b/include/linux/wkup_m3_ipc.h index d6ba7d39a62f..e497e621dbb7 100644 --- a/include/linux/wkup_m3_ipc.h +++ b/include/linux/wkup_m3_ipc.h @@ -40,6 +40,12 @@ struct wkup_m3_ipc { struct mbox_chan *mbox; struct wkup_m3_ipc_ops *ops; + int is_rtc_only; +}; + +struct wkup_m3_wakeup_src { + int irq_nr; + char src[10]; }; struct wkup_m3_ipc_ops { @@ -48,8 +54,11 @@ struct wkup_m3_ipc_ops { int (*prepare_low_power)(struct wkup_m3_ipc *m3_ipc, int state); int (*finish_low_power)(struct wkup_m3_ipc *m3_ipc); int (*request_pm_status)(struct wkup_m3_ipc *m3_ipc); + const char *(*request_wake_src)(struct wkup_m3_ipc *m3_ipc); + void (*set_rtc_only)(struct wkup_m3_ipc *m3_ipc); }; struct wkup_m3_ipc *wkup_m3_ipc_get(void); void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc); +void wkup_m3_set_rtc_only_mode(void); #endif /* _LINUX_WKUP_M3_IPC_H */ diff --git a/include/rdma/ib_cache.h b/include/rdma/ib_cache.h index 3e11e7cc60b7..62e990b620aa 100644 --- a/include/rdma/ib_cache.h +++ b/include/rdma/ib_cache.h @@ -133,28 +133,4 @@ const struct ib_gid_attr *rdma_get_gid_attr(struct ib_device *device, void rdma_put_gid_attr(const struct ib_gid_attr *attr); void rdma_hold_gid_attr(const struct ib_gid_attr *attr); -/* - * This is to be removed. It only exists to make merging rdma and smc simpler. - */ -static inline __deprecated int ib_query_gid(struct ib_device *device, - u8 port_num, int index, - union ib_gid *gid, - struct ib_gid_attr *attr_out) -{ - const struct ib_gid_attr *attr; - - memset(attr_out, 0, sizeof(*attr_out)); - attr = rdma_get_gid_attr(device, port_num, index); - if (IS_ERR(attr)) - return PTR_ERR(attr); - - if (attr->ndev) - dev_hold(attr->ndev); - *attr_out = *attr; - - rdma_put_gid_attr(attr); - - return 0; -} - #endif /* _IB_CACHE_H */ diff --git a/include/soc/bcm2835/raspberrypi-firmware.h b/include/soc/bcm2835/raspberrypi-firmware.h index 8ee8991aa099..c4a5c9e9fb47 100644 --- a/include/soc/bcm2835/raspberrypi-firmware.h +++ b/include/soc/bcm2835/raspberrypi-firmware.h @@ -75,6 +75,7 @@ enum rpi_firmware_property_tag { RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020, RPI_FIRMWARE_GET_CUSTOMER_OTP = 0x00030021, RPI_FIRMWARE_GET_DOMAIN_STATE = 0x00030030, + RPI_FIRMWARE_GET_THROTTLED = 0x00030046, RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001, RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002, RPI_FIRMWARE_SET_VOLTAGE = 0x00038003, diff --git a/drivers/staging/fsl-mc/include/dpaa2-fd.h b/include/soc/fsl/dpaa2-fd.h index b55b89ba4eda..2576abaa7779 100644 --- a/drivers/staging/fsl-mc/include/dpaa2-fd.h +++ b/include/soc/fsl/dpaa2-fd.h @@ -67,6 +67,18 @@ struct dpaa2_fd { #define SG_FINAL_FLAG_MASK 0x1 #define SG_FINAL_FLAG_SHIFT 15 +/* Error bits in FD CTRL */ +#define FD_CTRL_ERR_MASK 0x000000FF +#define FD_CTRL_UFD 0x00000004 +#define FD_CTRL_SBE 0x00000008 +#define FD_CTRL_FLC 0x00000010 +#define FD_CTRL_FSE 0x00000020 +#define FD_CTRL_FAERR 0x00000040 + +/* Annotation bits in FD CTRL */ +#define FD_CTRL_PTA 0x00800000 +#define FD_CTRL_PTV1 0x00400000 + enum dpaa2_fd_format { dpaa2_fd_single = 0, dpaa2_fd_list, diff --git a/drivers/staging/fsl-mc/include/dpaa2-global.h b/include/soc/fsl/dpaa2-global.h index 9bc0713346a8..9bc0713346a8 100644 --- a/drivers/staging/fsl-mc/include/dpaa2-global.h +++ b/include/soc/fsl/dpaa2-global.h diff --git a/drivers/staging/fsl-mc/include/dpaa2-io.h b/include/soc/fsl/dpaa2-io.h index ab51e40d11db..ab51e40d11db 100644 --- a/drivers/staging/fsl-mc/include/dpaa2-io.h +++ b/include/soc/fsl/dpaa2-io.h diff --git a/include/uapi/mtd/ubi-user.h b/include/uapi/mtd/ubi-user.h index 5b04a494d139..aad3b6201fc0 100644 --- a/include/uapi/mtd/ubi-user.h +++ b/include/uapi/mtd/ubi-user.h @@ -285,6 +285,20 @@ struct ubi_attach_req { __s8 padding[10]; }; +/* + * UBI volume flags. + * + * @UBI_VOL_SKIP_CRC_CHECK_FLG: skip the CRC check done on a static volume at + * open time. Only valid for static volumes and + * should only be used if the volume user has a + * way to verify data integrity + */ +enum { + UBI_VOL_SKIP_CRC_CHECK_FLG = 0x1, +}; + +#define UBI_VOL_VALID_FLGS (UBI_VOL_SKIP_CRC_CHECK_FLG) + /** * struct ubi_mkvol_req - volume description data structure used in * volume creation requests. @@ -292,7 +306,7 @@ struct ubi_attach_req { * @alignment: volume alignment * @bytes: volume size in bytes * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME) - * @padding1: reserved for future, not used, has to be zeroed + * @flags: volume flags (%UBI_VOL_SKIP_CRC_CHECK_FLG) * @name_len: volume name length * @padding2: reserved for future, not used, has to be zeroed * @name: volume name @@ -321,7 +335,7 @@ struct ubi_mkvol_req { __s32 alignment; __s64 bytes; __s8 vol_type; - __s8 padding1; + __u8 flags; __s16 name_len; __s8 padding2[4]; char name[UBI_MAX_VOLUME_NAME + 1]; diff --git a/include/video/udlfb.h b/include/video/udlfb.h index 0cabe6b09095..3abd327bada6 100644 --- a/include/video/udlfb.h +++ b/include/video/udlfb.h @@ -20,7 +20,6 @@ struct dloarea { struct urb_node { struct list_head entry; struct dlfb_data *dlfb; - struct delayed_work release_urb_work; struct urb *urb; }; @@ -52,11 +51,14 @@ struct dlfb_data { int base8; u32 pseudo_palette[256]; int blank_mode; /*one of FB_BLANK_ */ + struct fb_ops ops; /* blit-only rendering path metrics, exposed through sysfs */ atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */ atomic_t bytes_identical; /* saved effort with backbuffer comparison */ atomic_t bytes_sent; /* to usb, after compression including overhead */ atomic_t cpu_kcycles_used; /* transpired during pixel processing */ + struct fb_var_screeninfo current_mode; + struct list_head deferred_free; }; #define NR_USB_REQUEST_I2C_SUB_IO 0x02 @@ -87,7 +89,7 @@ struct dlfb_data { #define MIN_RAW_PIX_BYTES 2 #define MIN_RAW_CMD_BYTES (RAW_HEADER_BYTES + MIN_RAW_PIX_BYTES) -#define DL_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */ +#define DL_DEFIO_WRITE_DELAY msecs_to_jiffies(HZ <= 300 ? 4 : 10) /* optimal value for 720p video */ #define DL_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */ /* remove these once align.h patch is taken into kernel */ diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index 918f386b2f6e..924e37fb1620 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -66,6 +66,9 @@ int console_printk[4] = { CONSOLE_LOGLEVEL_DEFAULT, /* default_console_loglevel */ }; +atomic_t ignore_console_lock_warning __read_mostly = ATOMIC_INIT(0); +EXPORT_SYMBOL(ignore_console_lock_warning); + /* * Low level drivers may need that to know if they can schedule in * their unblank() callback or not. So let's export it. diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig index c042a455afc6..5e3de28c7677 100644 --- a/kernel/trace/Kconfig +++ b/kernel/trace/Kconfig @@ -774,6 +774,18 @@ config TRACING_EVENTS_GPIO help Enable tracing events for gpio subsystem +config GCOV_PROFILE_FTRACE + bool "Enable GCOV profiling on ftrace subsystem" + depends on GCOV_KERNEL + help + Enable GCOV profiling on ftrace subsystem for checking + which functions/lines are tested. + + If unsure, say N. + + Note that on a kernel compiled with this config, ftrace will + run significantly slower. + endif # FTRACE endif # TRACING_SUPPORT diff --git a/kernel/trace/Makefile b/kernel/trace/Makefile index 98d53b39a8ee..f81dadbc7c4a 100644 --- a/kernel/trace/Makefile +++ b/kernel/trace/Makefile @@ -23,6 +23,11 @@ ifdef CONFIG_TRACING_BRANCHES KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING endif +# for GCOV coverage profiling +ifdef CONFIG_GCOV_PROFILE_FTRACE +GCOV_PROFILE := y +endif + CFLAGS_trace_benchmark.o := -I$(src) CFLAGS_trace_events_filter.o := -I$(src) diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c index 2bfb2bbeb3d2..c30032367aab 100644 --- a/kernel/trace/trace_kprobe.c +++ b/kernel/trace/trace_kprobe.c @@ -513,7 +513,14 @@ static bool within_notrace_func(struct trace_kprobe *tk) if (!addr || !kallsyms_lookup_size_offset(addr, &size, &offset)) return false; - return !ftrace_location_range(addr - offset, addr - offset + size); + /* Get the entry address of the target function */ + addr -= offset; + + /* + * Since ftrace_location_range() does inclusive range check, we need + * to subtract 1 byte from the end address. + */ + return !ftrace_location_range(addr, addr + size - 1); } #else #define within_notrace_func(tk) (false) diff --git a/mm/memory.c b/mm/memory.c index 42ebdc33268e..83aef222f11b 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -238,23 +238,13 @@ void arch_tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, __tlb_reset_range(tlb); } -static void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb) +static void tlb_flush_mmu_free(struct mmu_gather *tlb) { - if (!tlb->end) - return; + struct mmu_gather_batch *batch; - tlb_flush(tlb); - mmu_notifier_invalidate_range(tlb->mm, tlb->start, tlb->end); #ifdef CONFIG_HAVE_RCU_TABLE_FREE tlb_table_flush(tlb); #endif - __tlb_reset_range(tlb); -} - -static void tlb_flush_mmu_free(struct mmu_gather *tlb) -{ - struct mmu_gather_batch *batch; - for (batch = &tlb->local; batch && batch->nr; batch = batch->next) { free_pages_and_swap_cache(batch->pages, batch->nr); batch->nr = 0; @@ -326,20 +316,31 @@ bool __tlb_remove_page_size(struct mmu_gather *tlb, struct page *page, int page_ #ifdef CONFIG_HAVE_RCU_TABLE_FREE -static void tlb_remove_table_smp_sync(void *arg) +/* + * See the comment near struct mmu_table_batch. + */ + +/* + * If we want tlb_remove_table() to imply TLB invalidates. + */ +static inline void tlb_table_invalidate(struct mmu_gather *tlb) { - struct mm_struct __maybe_unused *mm = arg; +#ifdef CONFIG_HAVE_RCU_TABLE_INVALIDATE /* - * On most architectures this does nothing. Simply delivering the - * interrupt is enough to prevent races with software page table - * walking like that done in get_user_pages_fast. - * - * See the comment near struct mmu_table_batch. + * Invalidate page-table caches used by hardware walkers. Then we still + * need to RCU-sched wait while freeing the pages because software + * walkers can still be in-flight. */ - tlb_flush_remove_tables_local(mm); + tlb_flush_mmu_tlbonly(tlb); +#endif +} + +static void tlb_remove_table_smp_sync(void *arg) +{ + /* Simply deliver the interrupt */ } -static void tlb_remove_table_one(void *table, struct mmu_gather *tlb) +static void tlb_remove_table_one(void *table) { /* * This isn't an RCU grace period and hence the page-tables cannot be @@ -348,7 +349,7 @@ static void tlb_remove_table_one(void *table, struct mmu_gather *tlb) * It is however sufficient for software page-table walkers that rely on * IRQ disabling. See the comment near struct mmu_table_batch. */ - smp_call_function(tlb_remove_table_smp_sync, tlb->mm, 1); + smp_call_function(tlb_remove_table_smp_sync, NULL, 1); __tlb_remove_table(table); } @@ -369,9 +370,8 @@ void tlb_table_flush(struct mmu_gather *tlb) { struct mmu_table_batch **batch = &tlb->batch; - tlb_flush_remove_tables(tlb->mm); - if (*batch) { + tlb_table_invalidate(tlb); call_rcu_sched(&(*batch)->rcu, tlb_remove_table_rcu); *batch = NULL; } @@ -381,23 +381,16 @@ void tlb_remove_table(struct mmu_gather *tlb, void *table) { struct mmu_table_batch **batch = &tlb->batch; - /* - * When there's less then two users of this mm there cannot be a - * concurrent page-table walk. - */ - if (atomic_read(&tlb->mm->mm_users) < 2) { - __tlb_remove_table(table); - return; - } - if (*batch == NULL) { *batch = (struct mmu_table_batch *)__get_free_page(GFP_NOWAIT | __GFP_NOWARN); if (*batch == NULL) { - tlb_remove_table_one(table, tlb); + tlb_table_invalidate(tlb); + tlb_remove_table_one(table); return; } (*batch)->nr = 0; } + (*batch)->tables[(*batch)->nr++] = table; if ((*batch)->nr == MAX_TABLE_BATCH) tlb_table_flush(tlb); diff --git a/net/smc/smc_ib.c b/net/smc/smc_ib.c index 9bb5274a244e..e519ef29c0ff 100644 --- a/net/smc/smc_ib.c +++ b/net/smc/smc_ib.c @@ -145,17 +145,21 @@ out: static int smc_ib_fill_mac(struct smc_ib_device *smcibdev, u8 ibport) { - struct ib_gid_attr gattr; - union ib_gid gid; - int rc; + const struct ib_gid_attr *attr; + int rc = 0; - rc = ib_query_gid(smcibdev->ibdev, ibport, 0, &gid, &gattr); - if (rc || !gattr.ndev) + attr = rdma_get_gid_attr(smcibdev->ibdev, ibport, 0); + if (IS_ERR(attr)) return -ENODEV; - memcpy(smcibdev->mac[ibport - 1], gattr.ndev->dev_addr, ETH_ALEN); - dev_put(gattr.ndev); - return 0; + if (attr->ndev) + memcpy(smcibdev->mac[ibport - 1], attr->ndev->dev_addr, + ETH_ALEN); + else + rc = -ENODEV; + + rdma_put_gid_attr(attr); + return rc; } /* Create an identifier unique for this instance of SMC-R. @@ -180,29 +184,27 @@ bool smc_ib_port_active(struct smc_ib_device *smcibdev, u8 ibport) int smc_ib_determine_gid(struct smc_ib_device *smcibdev, u8 ibport, unsigned short vlan_id, u8 gid[], u8 *sgid_index) { - struct ib_gid_attr gattr; - union ib_gid _gid; + const struct ib_gid_attr *attr; int i; for (i = 0; i < smcibdev->pattr[ibport - 1].gid_tbl_len; i++) { - memset(&_gid, 0, SMC_GID_SIZE); - memset(&gattr, 0, sizeof(gattr)); - if (ib_query_gid(smcibdev->ibdev, ibport, i, &_gid, &gattr)) + attr = rdma_get_gid_attr(smcibdev->ibdev, ibport, i); + if (IS_ERR(attr)) continue; - if (!gattr.ndev) - continue; - if (((!vlan_id && !is_vlan_dev(gattr.ndev)) || - (vlan_id && is_vlan_dev(gattr.ndev) && - vlan_dev_vlan_id(gattr.ndev) == vlan_id)) && - gattr.gid_type == IB_GID_TYPE_IB) { + + if (attr->ndev && + ((!vlan_id && !is_vlan_dev(attr->ndev)) || + (vlan_id && is_vlan_dev(attr->ndev) && + vlan_dev_vlan_id(attr->ndev) == vlan_id)) && + attr->gid_type == IB_GID_TYPE_ROCE) { if (gid) - memcpy(gid, &_gid, SMC_GID_SIZE); + memcpy(gid, &attr->gid, SMC_GID_SIZE); if (sgid_index) - *sgid_index = i; - dev_put(gattr.ndev); + *sgid_index = attr->index; + rdma_put_gid_attr(attr); return 0; } - dev_put(gattr.ndev); + rdma_put_gid_attr(attr); } return -ENODEV; } diff --git a/net/sunrpc/auth.c b/net/sunrpc/auth.c index d2623b9f23d6..305ecea92170 100644 --- a/net/sunrpc/auth.c +++ b/net/sunrpc/auth.c @@ -50,7 +50,7 @@ static int param_set_hashtbl_sz(const char *val, const struct kernel_param *kp) if (!val) goto out_inval; ret = kstrtoul(val, 0, &num); - if (ret == -EINVAL) + if (ret) goto out_inval; nbits = fls(num - 1); if (nbits > MAX_HASHTABLE_BITS || nbits < 2) @@ -253,7 +253,7 @@ rpcauth_list_flavors(rpc_authflavor_t *array, int size) EXPORT_SYMBOL_GPL(rpcauth_list_flavors); struct rpc_auth * -rpcauth_create(struct rpc_auth_create_args *args, struct rpc_clnt *clnt) +rpcauth_create(const struct rpc_auth_create_args *args, struct rpc_clnt *clnt) { struct rpc_auth *auth; const struct rpc_authops *ops; diff --git a/net/sunrpc/auth_gss/auth_gss.c b/net/sunrpc/auth_gss/auth_gss.c index 0fc397fae42b..21c0aa0a0d1d 100644 --- a/net/sunrpc/auth_gss/auth_gss.c +++ b/net/sunrpc/auth_gss/auth_gss.c @@ -284,7 +284,12 @@ err: return p; } -#define UPCALL_BUF_LEN 128 +/* XXX: Need some documentation about why UPCALL_BUF_LEN is so small. + * Is user space expecting no more than UPCALL_BUF_LEN bytes? + * Note that there are now _two_ NI_MAXHOST sized data items + * being passed in this string. + */ +#define UPCALL_BUF_LEN 256 struct gss_upcall_msg { refcount_t count; @@ -456,18 +461,44 @@ static int gss_encode_v1_msg(struct gss_upcall_msg *gss_msg, buflen -= len; p += len; gss_msg->msg.len = len; + + /* + * target= is a full service principal that names the remote + * identity that we are authenticating to. + */ if (target_name) { len = scnprintf(p, buflen, "target=%s ", target_name); buflen -= len; p += len; gss_msg->msg.len += len; } - if (service_name != NULL) { - len = scnprintf(p, buflen, "service=%s ", service_name); + + /* + * gssd uses service= and srchost= to select a matching key from + * the system's keytab to use as the source principal. + * + * service= is the service name part of the source principal, + * or "*" (meaning choose any). + * + * srchost= is the hostname part of the source principal. When + * not provided, gssd uses the local hostname. + */ + if (service_name) { + char *c = strchr(service_name, '@'); + + if (!c) + len = scnprintf(p, buflen, "service=%s ", + service_name); + else + len = scnprintf(p, buflen, + "service=%.*s srchost=%s ", + (int)(c - service_name), + service_name, c + 1); buflen -= len; p += len; gss_msg->msg.len += len; } + if (mech->gm_upcall_enctypes) { len = scnprintf(p, buflen, "enctypes=%s ", mech->gm_upcall_enctypes); @@ -985,7 +1016,7 @@ static void gss_pipe_free(struct gss_pipe *p) * parameters based on the input flavor (which must be a pseudoflavor) */ static struct gss_auth * -gss_create_new(struct rpc_auth_create_args *args, struct rpc_clnt *clnt) +gss_create_new(const struct rpc_auth_create_args *args, struct rpc_clnt *clnt) { rpc_authflavor_t flavor = args->pseudoflavor; struct gss_auth *gss_auth; @@ -1132,7 +1163,7 @@ gss_destroy(struct rpc_auth *auth) * (which is guaranteed to last as long as any of its descendants). */ static struct gss_auth * -gss_auth_find_or_add_hashed(struct rpc_auth_create_args *args, +gss_auth_find_or_add_hashed(const struct rpc_auth_create_args *args, struct rpc_clnt *clnt, struct gss_auth *new) { @@ -1169,7 +1200,8 @@ out: } static struct gss_auth * -gss_create_hashed(struct rpc_auth_create_args *args, struct rpc_clnt *clnt) +gss_create_hashed(const struct rpc_auth_create_args *args, + struct rpc_clnt *clnt) { struct gss_auth *gss_auth; struct gss_auth *new; @@ -1188,7 +1220,7 @@ out: } static struct rpc_auth * -gss_create(struct rpc_auth_create_args *args, struct rpc_clnt *clnt) +gss_create(const struct rpc_auth_create_args *args, struct rpc_clnt *clnt) { struct gss_auth *gss_auth; struct rpc_xprt_switch *xps = rcu_access_pointer(clnt->cl_xpi.xpi_xpswitch); @@ -1571,7 +1603,7 @@ static int gss_cred_is_negative_entry(struct rpc_cred *cred) if (test_bit(RPCAUTH_CRED_NEGATIVE, &cred->cr_flags)) { unsigned long now = jiffies; unsigned long begin, expire; - struct gss_cred *gss_cred; + struct gss_cred *gss_cred; gss_cred = container_of(cred, struct gss_cred, gc_base); begin = gss_cred->gc_upcall_timestamp; diff --git a/net/sunrpc/auth_gss/gss_generic_token.c b/net/sunrpc/auth_gss/gss_generic_token.c index 254defe446a7..fe97f3106536 100644 --- a/net/sunrpc/auth_gss/gss_generic_token.c +++ b/net/sunrpc/auth_gss/gss_generic_token.c @@ -231,4 +231,3 @@ g_verify_token_header(struct xdr_netobj *mech, int *body_size, } EXPORT_SYMBOL_GPL(g_verify_token_header); - diff --git a/net/sunrpc/auth_gss/gss_krb5_crypto.c b/net/sunrpc/auth_gss/gss_krb5_crypto.c index 8654494b4d0a..0220e1ca5280 100644 --- a/net/sunrpc/auth_gss/gss_krb5_crypto.c +++ b/net/sunrpc/auth_gss/gss_krb5_crypto.c @@ -169,7 +169,7 @@ make_checksum_hmac_md5(struct krb5_ctx *kctx, char *header, int hdrlen, struct scatterlist sg[1]; int err = -1; u8 *checksumdata; - u8 rc4salt[4]; + u8 *rc4salt; struct crypto_ahash *md5; struct crypto_ahash *hmac_md5; struct ahash_request *req; @@ -183,14 +183,18 @@ make_checksum_hmac_md5(struct krb5_ctx *kctx, char *header, int hdrlen, return GSS_S_FAILURE; } + rc4salt = kmalloc_array(4, sizeof(*rc4salt), GFP_NOFS); + if (!rc4salt) + return GSS_S_FAILURE; + if (arcfour_hmac_md5_usage_to_salt(usage, rc4salt)) { dprintk("%s: invalid usage value %u\n", __func__, usage); - return GSS_S_FAILURE; + goto out_free_rc4salt; } checksumdata = kmalloc(GSS_KRB5_MAX_CKSUM_LEN, GFP_NOFS); if (!checksumdata) - return GSS_S_FAILURE; + goto out_free_rc4salt; md5 = crypto_alloc_ahash("md5", 0, CRYPTO_ALG_ASYNC); if (IS_ERR(md5)) @@ -258,6 +262,8 @@ out_free_md5: crypto_free_ahash(md5); out_free_cksum: kfree(checksumdata); +out_free_rc4salt: + kfree(rc4salt); return err ? GSS_S_FAILURE : 0; } @@ -373,7 +379,6 @@ make_checksum_v2(struct krb5_ctx *kctx, char *header, int hdrlen, struct scatterlist sg[1]; int err = -1; u8 *checksumdata; - unsigned int checksumlen; if (kctx->gk5e->keyed_cksum == 0) { dprintk("%s: expected keyed hash for %s\n", @@ -393,7 +398,6 @@ make_checksum_v2(struct krb5_ctx *kctx, char *header, int hdrlen, tfm = crypto_alloc_ahash(kctx->gk5e->cksum_name, 0, CRYPTO_ALG_ASYNC); if (IS_ERR(tfm)) goto out_free_cksum; - checksumlen = crypto_ahash_digestsize(tfm); req = ahash_request_alloc(tfm, GFP_NOFS); if (!req) @@ -1077,4 +1081,3 @@ out_err: dprintk("%s: returning %d\n", __func__, err); return err; } - diff --git a/net/sunrpc/auth_gss/gss_krb5_keys.c b/net/sunrpc/auth_gss/gss_krb5_keys.c index 870133146026..f7fe2d2b851f 100644 --- a/net/sunrpc/auth_gss/gss_krb5_keys.c +++ b/net/sunrpc/auth_gss/gss_krb5_keys.c @@ -324,4 +324,3 @@ u32 gss_krb5_aes_make_key(const struct gss_krb5_enctype *gk5e, err_out: return ret; } - diff --git a/net/sunrpc/auth_gss/gss_krb5_seal.c b/net/sunrpc/auth_gss/gss_krb5_seal.c index 94a2b3f082a8..eaad9bc7a0bd 100644 --- a/net/sunrpc/auth_gss/gss_krb5_seal.c +++ b/net/sunrpc/auth_gss/gss_krb5_seal.c @@ -229,4 +229,3 @@ gss_get_mic_kerberos(struct gss_ctx *gss_ctx, struct xdr_buf *text, return gss_get_mic_v2(ctx, text, token); } } - diff --git a/net/sunrpc/auth_gss/gss_krb5_unseal.c b/net/sunrpc/auth_gss/gss_krb5_unseal.c index b601a73cc9db..ef2b25b86d2f 100644 --- a/net/sunrpc/auth_gss/gss_krb5_unseal.c +++ b/net/sunrpc/auth_gss/gss_krb5_unseal.c @@ -225,4 +225,3 @@ gss_verify_mic_kerberos(struct gss_ctx *gss_ctx, return gss_verify_mic_v2(ctx, message_buffer, read_token); } } - diff --git a/net/sunrpc/auth_gss/gss_krb5_wrap.c b/net/sunrpc/auth_gss/gss_krb5_wrap.c index a737c2da0837..39a2e672900b 100644 --- a/net/sunrpc/auth_gss/gss_krb5_wrap.c +++ b/net/sunrpc/auth_gss/gss_krb5_wrap.c @@ -440,7 +440,6 @@ static u32 gss_wrap_kerberos_v2(struct krb5_ctx *kctx, u32 offset, struct xdr_buf *buf, struct page **pages) { - int blocksize; u8 *ptr, *plainhdr; s32 now; u8 flags = 0x00; @@ -473,7 +472,6 @@ gss_wrap_kerberos_v2(struct krb5_ctx *kctx, u32 offset, *ptr++ = 0xff; be16ptr = (__be16 *)ptr; - blocksize = crypto_skcipher_blocksize(kctx->acceptor_enc); *be16ptr++ = 0; /* "inner" token header always uses 0 for RRC */ *be16ptr++ = 0; @@ -623,4 +621,3 @@ gss_unwrap_kerberos(struct gss_ctx *gctx, int offset, struct xdr_buf *buf) return gss_unwrap_kerberos_v2(kctx, offset, buf); } } - diff --git a/net/sunrpc/auth_gss/gss_rpc_upcall.c b/net/sunrpc/auth_gss/gss_rpc_upcall.c index 1c7c49dbf8ba..73dcda060335 100644 --- a/net/sunrpc/auth_gss/gss_rpc_upcall.c +++ b/net/sunrpc/auth_gss/gss_rpc_upcall.c @@ -234,6 +234,35 @@ static int gssp_alloc_receive_pages(struct gssx_arg_accept_sec_context *arg) return 0; } +static char *gssp_stringify(struct xdr_netobj *netobj) +{ + return kstrndup(netobj->data, netobj->len, GFP_KERNEL); +} + +static void gssp_hostbased_service(char **principal) +{ + char *c; + + if (!*principal) + return; + + /* terminate and remove realm part */ + c = strchr(*principal, '@'); + if (c) { + *c = '\0'; + + /* change service-hostname delimiter */ + c = strchr(*principal, '/'); + if (c) + *c = '@'; + } + if (!c) { + /* not a service principal */ + kfree(*principal); + *principal = NULL; + } +} + /* * Public functions */ @@ -262,6 +291,7 @@ int gssp_accept_sec_context_upcall(struct net *net, */ .exported_context_token.len = GSSX_max_output_handle_sz, .mech.len = GSS_OID_MAX_LEN, + .targ_name.display_name.len = GSSX_max_princ_sz, .src_name.display_name.len = GSSX_max_princ_sz }; struct gssx_res_accept_sec_context res = { @@ -275,6 +305,7 @@ int gssp_accept_sec_context_upcall(struct net *net, .rpc_cred = NULL, /* FIXME ? */ }; struct xdr_netobj client_name = { 0 , NULL }; + struct xdr_netobj target_name = { 0, NULL }; int ret; if (data->in_handle.len != 0) @@ -285,8 +316,6 @@ int gssp_accept_sec_context_upcall(struct net *net, if (ret) return ret; - /* use nfs/ for targ_name ? */ - ret = gssp_call(net, &msg); gssp_free_receive_pages(&arg); @@ -304,6 +333,7 @@ int gssp_accept_sec_context_upcall(struct net *net, kfree(rctxh.mech.data); } client_name = rctxh.src_name.display_name; + target_name = rctxh.targ_name.display_name; } if (res.options.count == 1) { @@ -325,32 +355,22 @@ int gssp_accept_sec_context_upcall(struct net *net, } /* convert to GSS_NT_HOSTBASED_SERVICE form and set into creds */ - if (data->found_creds && client_name.data != NULL) { - char *c; - - data->creds.cr_raw_principal = kstrndup(client_name.data, - client_name.len, GFP_KERNEL); - - data->creds.cr_principal = kstrndup(client_name.data, - client_name.len, GFP_KERNEL); - if (data->creds.cr_principal) { - /* terminate and remove realm part */ - c = strchr(data->creds.cr_principal, '@'); - if (c) { - *c = '\0'; - - /* change service-hostname delimiter */ - c = strchr(data->creds.cr_principal, '/'); - if (c) *c = '@'; - } - if (!c) { - /* not a service principal */ - kfree(data->creds.cr_principal); - data->creds.cr_principal = NULL; - } + if (data->found_creds) { + if (client_name.data) { + data->creds.cr_raw_principal = + gssp_stringify(&client_name); + data->creds.cr_principal = + gssp_stringify(&client_name); + gssp_hostbased_service(&data->creds.cr_principal); + } + if (target_name.data) { + data->creds.cr_targ_princ = + gssp_stringify(&target_name); + gssp_hostbased_service(&data->creds.cr_targ_princ); } } kfree(client_name.data); + kfree(target_name.data); return ret; } diff --git a/net/sunrpc/auth_gss/svcauth_gss.c b/net/sunrpc/auth_gss/svcauth_gss.c index 5089dbb96d58..860f2a1bbb67 100644 --- a/net/sunrpc/auth_gss/svcauth_gss.c +++ b/net/sunrpc/auth_gss/svcauth_gss.c @@ -1389,7 +1389,7 @@ static void destroy_use_gss_proxy_proc_entry(struct net *net) struct sunrpc_net *sn = net_generic(net, sunrpc_net_id); if (sn->use_gssp_proc) { - remove_proc_entry("use-gss-proxy", sn->proc_net_rpc); + remove_proc_entry("use-gss-proxy", sn->proc_net_rpc); clear_gssp_clnt(sn); } } diff --git a/net/sunrpc/auth_null.c b/net/sunrpc/auth_null.c index 75d72e109a04..4b48228ee8c7 100644 --- a/net/sunrpc/auth_null.c +++ b/net/sunrpc/auth_null.c @@ -19,7 +19,7 @@ static struct rpc_auth null_auth; static struct rpc_cred null_cred; static struct rpc_auth * -nul_create(struct rpc_auth_create_args *args, struct rpc_clnt *clnt) +nul_create(const struct rpc_auth_create_args *args, struct rpc_clnt *clnt) { atomic_inc(&null_auth.au_count); return &null_auth; diff --git a/net/sunrpc/auth_unix.c b/net/sunrpc/auth_unix.c index dafd6b870ba3..185e56d4f9ae 100644 --- a/net/sunrpc/auth_unix.c +++ b/net/sunrpc/auth_unix.c @@ -30,7 +30,7 @@ static struct rpc_auth unix_auth; static const struct rpc_credops unix_credops; static struct rpc_auth * -unx_create(struct rpc_auth_create_args *args, struct rpc_clnt *clnt) +unx_create(const struct rpc_auth_create_args *args, struct rpc_clnt *clnt) { dprintk("RPC: creating UNIX authenticator for client %p\n", clnt); diff --git a/net/sunrpc/backchannel_rqst.c b/net/sunrpc/backchannel_rqst.c index c2c68a15b59d..3c15a99b9700 100644 --- a/net/sunrpc/backchannel_rqst.c +++ b/net/sunrpc/backchannel_rqst.c @@ -362,4 +362,3 @@ void xprt_complete_bc_request(struct rpc_rqst *req, uint32_t copied) wake_up(&bc_serv->sv_cb_waitq); spin_unlock(&bc_serv->sv_cb_lock); } - diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c index d839c33ae7d9..8ea2f5fadd96 100644 --- a/net/sunrpc/clnt.c +++ b/net/sunrpc/clnt.c @@ -892,7 +892,7 @@ rpc_free_client(struct rpc_clnt *clnt) /* * Free an RPC client */ -static struct rpc_clnt * +static struct rpc_clnt * rpc_free_auth(struct rpc_clnt *clnt) { if (clnt->cl_auth == NULL) @@ -965,10 +965,20 @@ out: } EXPORT_SYMBOL_GPL(rpc_bind_new_program); +void rpc_task_release_transport(struct rpc_task *task) +{ + struct rpc_xprt *xprt = task->tk_xprt; + + if (xprt) { + task->tk_xprt = NULL; + xprt_put(xprt); + } +} +EXPORT_SYMBOL_GPL(rpc_task_release_transport); + void rpc_task_release_client(struct rpc_task *task) { struct rpc_clnt *clnt = task->tk_client; - struct rpc_xprt *xprt = task->tk_xprt; if (clnt != NULL) { /* Remove from client task list */ @@ -979,12 +989,14 @@ void rpc_task_release_client(struct rpc_task *task) rpc_release_client(clnt); } + rpc_task_release_transport(task); +} - if (xprt != NULL) { - task->tk_xprt = NULL; - - xprt_put(xprt); - } +static +void rpc_task_set_transport(struct rpc_task *task, struct rpc_clnt *clnt) +{ + if (!task->tk_xprt) + task->tk_xprt = xprt_iter_get_next(&clnt->cl_xpi); } static @@ -992,8 +1004,7 @@ void rpc_task_set_client(struct rpc_task *task, struct rpc_clnt *clnt) { if (clnt != NULL) { - if (task->tk_xprt == NULL) - task->tk_xprt = xprt_iter_get_next(&clnt->cl_xpi); + rpc_task_set_transport(task, clnt); task->tk_client = clnt; atomic_inc(&clnt->cl_count); if (clnt->cl_softrtry) @@ -1512,6 +1523,7 @@ call_start(struct rpc_task *task) clnt->cl_program->version[clnt->cl_vers]->counts[idx]++; clnt->cl_stats->rpccnt++; task->tk_action = call_reserve; + rpc_task_set_transport(task, clnt); } /* diff --git a/net/sunrpc/rpcb_clnt.c b/net/sunrpc/rpcb_clnt.c index c526f8fb37c9..c7872bc13860 100644 --- a/net/sunrpc/rpcb_clnt.c +++ b/net/sunrpc/rpcb_clnt.c @@ -213,7 +213,7 @@ static void rpcb_set_local(struct net *net, struct rpc_clnt *clnt, sn->rpcb_local_clnt = clnt; sn->rpcb_local_clnt4 = clnt4; sn->rpcb_is_af_local = is_af_local ? 1 : 0; - smp_wmb(); + smp_wmb(); sn->rpcb_users = 1; dprintk("RPC: created new rpcb local clients (rpcb_local_clnt: " "%p, rpcb_local_clnt4: %p) for net %x%s\n", diff --git a/net/sunrpc/stats.c b/net/sunrpc/stats.c index f68aa46c9dd7..71166b393732 100644 --- a/net/sunrpc/stats.c +++ b/net/sunrpc/stats.c @@ -208,13 +208,39 @@ static void _print_name(struct seq_file *seq, unsigned int op, seq_printf(seq, "\t%12u: ", op); } -void rpc_print_iostats(struct seq_file *seq, struct rpc_clnt *clnt) +static void _add_rpc_iostats(struct rpc_iostats *a, struct rpc_iostats *b) +{ + a->om_ops += b->om_ops; + a->om_ntrans += b->om_ntrans; + a->om_timeouts += b->om_timeouts; + a->om_bytes_sent += b->om_bytes_sent; + a->om_bytes_recv += b->om_bytes_recv; + a->om_queue = ktime_add(a->om_queue, b->om_queue); + a->om_rtt = ktime_add(a->om_rtt, b->om_rtt); + a->om_execute = ktime_add(a->om_execute, b->om_execute); +} + +static void _print_rpc_iostats(struct seq_file *seq, struct rpc_iostats *stats, + int op, const struct rpc_procinfo *procs) +{ + _print_name(seq, op, procs); + seq_printf(seq, "%lu %lu %lu %Lu %Lu %Lu %Lu %Lu\n", + stats->om_ops, + stats->om_ntrans, + stats->om_timeouts, + stats->om_bytes_sent, + stats->om_bytes_recv, + ktime_to_ms(stats->om_queue), + ktime_to_ms(stats->om_rtt), + ktime_to_ms(stats->om_execute)); +} + +void rpc_clnt_show_stats(struct seq_file *seq, struct rpc_clnt *clnt) { - struct rpc_iostats *stats = clnt->cl_metrics; struct rpc_xprt *xprt; unsigned int op, maxproc = clnt->cl_maxproc; - if (!stats) + if (!clnt->cl_metrics) return; seq_printf(seq, "\tRPC iostats version: %s ", RPC_IOSTATS_VERS); @@ -229,20 +255,18 @@ void rpc_print_iostats(struct seq_file *seq, struct rpc_clnt *clnt) seq_printf(seq, "\tper-op statistics\n"); for (op = 0; op < maxproc; op++) { - struct rpc_iostats *metrics = &stats[op]; - _print_name(seq, op, clnt->cl_procinfo); - seq_printf(seq, "%lu %lu %lu %Lu %Lu %Lu %Lu %Lu\n", - metrics->om_ops, - metrics->om_ntrans, - metrics->om_timeouts, - metrics->om_bytes_sent, - metrics->om_bytes_recv, - ktime_to_ms(metrics->om_queue), - ktime_to_ms(metrics->om_rtt), - ktime_to_ms(metrics->om_execute)); + struct rpc_iostats stats = {}; + struct rpc_clnt *next = clnt; + do { + _add_rpc_iostats(&stats, &next->cl_metrics[op]); + if (next == next->cl_parent) + break; + next = next->cl_parent; + } while (next); + _print_rpc_iostats(seq, &stats, op, clnt->cl_procinfo); } } -EXPORT_SYMBOL_GPL(rpc_print_iostats); +EXPORT_SYMBOL_GPL(rpc_clnt_show_stats); /* * Register/unregister RPC proc files @@ -310,4 +334,3 @@ void rpc_proc_exit(struct net *net) dprintk("RPC: unregistering /proc/net/rpc\n"); remove_proc_entry("rpc", net->proc_net); } - diff --git a/net/sunrpc/sunrpc.h b/net/sunrpc/sunrpc.h index 09a0315ea77b..c9bacb3c930f 100644 --- a/net/sunrpc/sunrpc.h +++ b/net/sunrpc/sunrpc.h @@ -57,4 +57,3 @@ int svc_send_common(struct socket *sock, struct xdr_buf *xdr, int rpc_clients_notifier_register(void); void rpc_clients_notifier_unregister(void); #endif /* _NET_SUNRPC_SUNRPC_H */ - diff --git a/net/sunrpc/svc.c b/net/sunrpc/svc.c index 30a4226baf03..d13e05f1a990 100644 --- a/net/sunrpc/svc.c +++ b/net/sunrpc/svc.c @@ -1537,16 +1537,16 @@ EXPORT_SYMBOL_GPL(svc_max_payload); /** * svc_fill_write_vector - Construct data argument for VFS write call * @rqstp: svc_rqst to operate on + * @pages: list of pages containing data payload * @first: buffer containing first section of write payload * @total: total number of bytes of write payload * - * Returns the number of elements populated in the data argument array. + * Fills in rqstp::rq_vec, and returns the number of elements. */ -unsigned int svc_fill_write_vector(struct svc_rqst *rqstp, struct kvec *first, - size_t total) +unsigned int svc_fill_write_vector(struct svc_rqst *rqstp, struct page **pages, + struct kvec *first, size_t total) { struct kvec *vec = rqstp->rq_vec; - struct page **pages; unsigned int i; /* Some types of transport can present the write payload @@ -1560,14 +1560,11 @@ unsigned int svc_fill_write_vector(struct svc_rqst *rqstp, struct kvec *first, ++i; } - WARN_ON_ONCE(rqstp->rq_arg.page_base != 0); - pages = rqstp->rq_arg.pages; while (total) { vec[i].iov_base = page_address(*pages); vec[i].iov_len = min_t(size_t, total, PAGE_SIZE); total -= vec[i].iov_len; ++i; - ++pages; } @@ -1580,65 +1577,48 @@ EXPORT_SYMBOL_GPL(svc_fill_write_vector); * svc_fill_symlink_pathname - Construct pathname argument for VFS symlink call * @rqstp: svc_rqst to operate on * @first: buffer containing first section of pathname + * @p: buffer containing remaining section of pathname * @total: total length of the pathname argument * - * Returns pointer to a NUL-terminated string, or an ERR_PTR. The buffer is - * released automatically when @rqstp is recycled. + * The VFS symlink API demands a NUL-terminated pathname in mapped memory. + * Returns pointer to a NUL-terminated string, or an ERR_PTR. Caller must free + * the returned string. */ char *svc_fill_symlink_pathname(struct svc_rqst *rqstp, struct kvec *first, - size_t total) + void *p, size_t total) { - struct xdr_buf *arg = &rqstp->rq_arg; - struct page **pages; - char *result; - - /* VFS API demands a NUL-terminated pathname. This function - * uses a page from @rqstp as the pathname buffer, to enable - * direct placement. Thus the total buffer size is PAGE_SIZE. - * Space in this buffer for NUL-termination requires that we - * cap the size of the returned symlink pathname just a - * little early. - */ - if (total > PAGE_SIZE - 1) - return ERR_PTR(-ENAMETOOLONG); + size_t len, remaining; + char *result, *dst; - /* Some types of transport can present the pathname entirely - * in rq_arg.pages. If not, then copy the pathname into one - * page. - */ - pages = arg->pages; - WARN_ON_ONCE(arg->page_base != 0); - if (first->iov_base == 0) { - result = page_address(*pages); - result[total] = '\0'; - } else { - size_t len, remaining; - char *dst; + result = kmalloc(total + 1, GFP_KERNEL); + if (!result) + return ERR_PTR(-ESERVERFAULT); - result = page_address(*(rqstp->rq_next_page++)); - dst = result; - remaining = total; + dst = result; + remaining = total; - len = min_t(size_t, total, first->iov_len); + len = min_t(size_t, total, first->iov_len); + if (len) { memcpy(dst, first->iov_base, len); dst += len; remaining -= len; + } - /* No more than one page left */ - if (remaining) { - len = min_t(size_t, remaining, PAGE_SIZE); - memcpy(dst, page_address(*pages), len); - dst += len; - } - - *dst = '\0'; + if (remaining) { + len = min_t(size_t, remaining, PAGE_SIZE); + memcpy(dst, p, len); + dst += len; } - /* Sanity check: we don't allow the pathname argument to + *dst = '\0'; + + /* Sanity check: Linux doesn't allow the pathname argument to * contain a NUL byte. */ - if (strlen(result) != total) + if (strlen(result) != total) { + kfree(result); return ERR_PTR(-EINVAL); + } return result; } EXPORT_SYMBOL_GPL(svc_fill_symlink_pathname); diff --git a/net/sunrpc/xprt.c b/net/sunrpc/xprt.c index 3fabf9f6a0f9..a8db2e3f8904 100644 --- a/net/sunrpc/xprt.c +++ b/net/sunrpc/xprt.c @@ -880,7 +880,7 @@ static void xprt_wait_on_pinned_rqst(struct rpc_rqst *req) __must_hold(&req->rq_xprt->recv_lock) { struct rpc_task *task = req->rq_task; - + if (task && test_bit(RPC_TASK_MSG_RECV, &task->tk_runstate)) { spin_unlock(&req->rq_xprt->recv_lock); set_bit(RPC_TASK_MSG_RECV_WAIT, &task->tk_runstate); diff --git a/net/sunrpc/xprtrdma/svc_rdma.c b/net/sunrpc/xprtrdma/svc_rdma.c index 357ba90c382d..134bef6a451e 100644 --- a/net/sunrpc/xprtrdma/svc_rdma.c +++ b/net/sunrpc/xprtrdma/svc_rdma.c @@ -94,7 +94,6 @@ static int read_reset_stat(struct ctl_table *table, int write, atomic_set(stat, 0); else { char str_buf[32]; - char *data; int len = snprintf(str_buf, 32, "%d\n", atomic_read(stat)); if (len >= 32) return -EFAULT; @@ -103,7 +102,6 @@ static int read_reset_stat(struct ctl_table *table, int write, *lenp = 0; return 0; } - data = &str_buf[*ppos]; len -= *ppos; if (len > *lenp) len = *lenp; diff --git a/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c b/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c index 2ef75e885411..b24d5b8f2fee 100644 --- a/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c +++ b/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c @@ -365,9 +365,6 @@ static void svc_rdma_build_arg_xdr(struct svc_rqst *rqstp, arg->page_base = 0; arg->buflen = ctxt->rc_byte_len; arg->len = ctxt->rc_byte_len; - - rqstp->rq_respages = &rqstp->rq_pages[0]; - rqstp->rq_next_page = rqstp->rq_respages + 1; } /* This accommodates the largest possible Write chunk, @@ -729,6 +726,12 @@ int svc_rdma_recvfrom(struct svc_rqst *rqstp) svc_rdma_build_arg_xdr(rqstp, ctxt); + /* Prevent svc_xprt_release from releasing pages in rq_pages + * if we return 0 or an error. + */ + rqstp->rq_respages = rqstp->rq_pages; + rqstp->rq_next_page = rqstp->rq_respages; + p = (__be32 *)rqstp->rq_arg.head[0].iov_base; ret = svc_rdma_xdr_decode_req(&rqstp->rq_arg); if (ret < 0) diff --git a/net/sunrpc/xprtrdma/svc_rdma_rw.c b/net/sunrpc/xprtrdma/svc_rdma_rw.c index 04cb3363172a..dc1951759a8e 100644 --- a/net/sunrpc/xprtrdma/svc_rdma_rw.c +++ b/net/sunrpc/xprtrdma/svc_rdma_rw.c @@ -680,6 +680,7 @@ static int svc_rdma_build_read_chunk(struct svc_rqst *rqstp, struct svc_rdma_read_info *info, __be32 *p) { + unsigned int i; int ret; ret = -EINVAL; @@ -702,6 +703,12 @@ static int svc_rdma_build_read_chunk(struct svc_rqst *rqstp, info->ri_chunklen += rs_length; } + /* Pages under I/O have been copied to head->rc_pages. + * Prevent their premature release by svc_xprt_release() . + */ + for (i = 0; i < info->ri_readctxt->rc_page_count; i++) + rqstp->rq_pages[i] = NULL; + return ret; } @@ -817,7 +824,6 @@ int svc_rdma_recv_read_chunk(struct svcxprt_rdma *rdma, struct svc_rqst *rqstp, struct svc_rdma_recv_ctxt *head, __be32 *p) { struct svc_rdma_read_info *info; - struct page **page; int ret; /* The request (with page list) is constructed in @@ -844,27 +850,15 @@ int svc_rdma_recv_read_chunk(struct svcxprt_rdma *rdma, struct svc_rqst *rqstp, ret = svc_rdma_build_normal_read_chunk(rqstp, info, p); else ret = svc_rdma_build_pz_read_chunk(rqstp, info, p); - - /* Mark the start of the pages that can be used for the reply */ - if (info->ri_pageoff > 0) - info->ri_pageno++; - rqstp->rq_respages = &rqstp->rq_pages[info->ri_pageno]; - rqstp->rq_next_page = rqstp->rq_respages + 1; - if (ret < 0) - goto out; + goto out_err; ret = svc_rdma_post_chunk_ctxt(&info->ri_cc); - -out: - /* Read sink pages have been moved from rqstp->rq_pages to - * head->rc_arg.pages. Force svc_recv to refill those slots - * in rq_pages. - */ - for (page = rqstp->rq_pages; page < rqstp->rq_respages; page++) - *page = NULL; - if (ret < 0) - svc_rdma_read_info_free(info); + goto out_err; + return 0; + +out_err: + svc_rdma_read_info_free(info); return ret; } diff --git a/net/sunrpc/xprtrdma/svc_rdma_sendto.c b/net/sunrpc/xprtrdma/svc_rdma_sendto.c index ffef0c508f1a..8602a5f1b515 100644 --- a/net/sunrpc/xprtrdma/svc_rdma_sendto.c +++ b/net/sunrpc/xprtrdma/svc_rdma_sendto.c @@ -656,7 +656,9 @@ static void svc_rdma_save_io_pages(struct svc_rqst *rqstp, ctxt->sc_pages[i] = rqstp->rq_respages[i]; rqstp->rq_respages[i] = NULL; } - rqstp->rq_next_page = rqstp->rq_respages + 1; + + /* Prevent svc_xprt_release from releasing pages in rq_pages */ + rqstp->rq_next_page = rqstp->rq_respages; } /* Prepare the portion of the RPC Reply that will be transmitted diff --git a/net/sunrpc/xprtrdma/svc_rdma_transport.c b/net/sunrpc/xprtrdma/svc_rdma_transport.c index 547b2cdf1427..2848cafd4a17 100644 --- a/net/sunrpc/xprtrdma/svc_rdma_transport.c +++ b/net/sunrpc/xprtrdma/svc_rdma_transport.c @@ -296,7 +296,6 @@ static int rdma_listen_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event) { struct sockaddr *sap = (struct sockaddr *)&cma_id->route.addr.src_addr; - int ret = 0; trace_svcrdma_cm_event(event, sap); @@ -315,7 +314,7 @@ static int rdma_listen_handler(struct rdma_cm_id *cma_id, break; } - return ret; + return 0; } static int rdma_cma_handler(struct rdma_cm_id *cma_id, diff --git a/net/sunrpc/xprtrdma/verbs.c b/net/sunrpc/xprtrdma/verbs.c index 5efeba08918b..956a5ea47b58 100644 --- a/net/sunrpc/xprtrdma/verbs.c +++ b/net/sunrpc/xprtrdma/verbs.c @@ -280,7 +280,6 @@ rpcrdma_conn_upcall(struct rdma_cm_id *id, struct rdma_cm_event *event) ++xprt->rx_xprt.connect_cookie; connstate = -ECONNABORTED; connected: - xprt->rx_buf.rb_credits = 1; ep->rep_connected = connstate; rpcrdma_conn_func(ep); wake_up_all(&ep->rep_connect_wait); @@ -755,6 +754,7 @@ retry: } ep->rep_connected = 0; + rpcrdma_post_recvs(r_xprt, true); rc = rdma_connect(ia->ri_id, &ep->rep_remote_cma); if (rc) { @@ -773,8 +773,6 @@ retry: dprintk("RPC: %s: connected\n", __func__); - rpcrdma_post_recvs(r_xprt, true); - out: if (rc) ep->rep_connected = rc; @@ -1171,6 +1169,7 @@ rpcrdma_buffer_create(struct rpcrdma_xprt *r_xprt) list_add(&req->rl_list, &buf->rb_send_bufs); } + buf->rb_credits = 1; buf->rb_posted_receives = 0; INIT_LIST_HEAD(&buf->rb_recv_bufs); diff --git a/net/sunrpc/xprtsock.c b/net/sunrpc/xprtsock.c index 9e1c5024aba9..6b7539c0466e 100644 --- a/net/sunrpc/xprtsock.c +++ b/net/sunrpc/xprtsock.c @@ -3375,4 +3375,3 @@ module_param_named(tcp_max_slot_table_entries, xprt_max_tcp_slot_table_entries, max_slot_table_size, 0644); module_param_named(udp_slot_table_entries, xprt_udp_slot_table_entries, slot_table_size, 0644); - diff --git a/sound/ac97/bus.c b/sound/ac97/bus.c index 7a0dfca03a57..9f0c480489ef 100644 --- a/sound/ac97/bus.c +++ b/sound/ac97/bus.c @@ -529,7 +529,7 @@ static int ac97_bus_remove(struct device *dev) int ret; ret = pm_runtime_get_sync(dev); - if (ret) + if (ret < 0) return ret; ret = adrv->remove(adev); @@ -537,6 +537,8 @@ static int ac97_bus_remove(struct device *dev) if (ret == 0) ac97_put_disable_clk(adev); + pm_runtime_disable(dev); + return ret; } diff --git a/sound/ac97/snd_ac97_compat.c b/sound/ac97/snd_ac97_compat.c index 61544e0d8de4..8bab44f74bb8 100644 --- a/sound/ac97/snd_ac97_compat.c +++ b/sound/ac97/snd_ac97_compat.c @@ -15,6 +15,11 @@ #include "ac97_core.h" +static void compat_ac97_release(struct device *dev) +{ + kfree(to_ac97_t(dev)); +} + static void compat_ac97_reset(struct snd_ac97 *ac97) { struct ac97_codec_device *adev = to_ac97_device(ac97->private_data); @@ -65,21 +70,31 @@ static struct snd_ac97_bus compat_soc_ac97_bus = { struct snd_ac97 *snd_ac97_compat_alloc(struct ac97_codec_device *adev) { struct snd_ac97 *ac97; + int ret; ac97 = kzalloc(sizeof(struct snd_ac97), GFP_KERNEL); if (ac97 == NULL) return ERR_PTR(-ENOMEM); - ac97->dev = adev->dev; ac97->private_data = adev; ac97->bus = &compat_soc_ac97_bus; + + ac97->dev.parent = &adev->dev; + ac97->dev.release = compat_ac97_release; + dev_set_name(&ac97->dev, "%s-compat", dev_name(&adev->dev)); + ret = device_register(&ac97->dev); + if (ret) { + put_device(&ac97->dev); + return ERR_PTR(ret); + } + return ac97; } EXPORT_SYMBOL_GPL(snd_ac97_compat_alloc); void snd_ac97_compat_release(struct snd_ac97 *ac97) { - kfree(ac97); + device_unregister(&ac97->dev); } EXPORT_SYMBOL_GPL(snd_ac97_compat_release); diff --git a/sound/core/seq/seq_virmidi.c b/sound/core/seq/seq_virmidi.c index a2f1c6b58693..cb988efd1ed0 100644 --- a/sound/core/seq/seq_virmidi.c +++ b/sound/core/seq/seq_virmidi.c @@ -149,8 +149,9 @@ static void snd_vmidi_output_work(struct work_struct *work) /* discard the outputs in dispatch mode unless subscribed */ if (vmidi->seq_mode == SNDRV_VIRMIDI_SEQ_DISPATCH && !(vmidi->rdev->flags & SNDRV_VIRMIDI_SUBSCRIBE)) { - while (!snd_rawmidi_transmit_empty(substream)) - snd_rawmidi_transmit_ack(substream, 1); + char buf[32]; + while (snd_rawmidi_transmit(substream, buf, sizeof(buf)) > 0) + ; /* ignored */ return; } diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index b20974ef1e13..1d117f00d04d 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -5494,6 +5494,7 @@ enum { ALC255_FIXUP_DUMMY_LINEOUT_VERB, ALC255_FIXUP_DELL_HEADSET_MIC, ALC295_FIXUP_HP_X360, + ALC221_FIXUP_HP_HEADSET_MIC, }; static const struct hda_fixup alc269_fixups[] = { @@ -6351,7 +6352,16 @@ static const struct hda_fixup alc269_fixups[] = { .v.func = alc295_fixup_hp_top_speakers, .chained = true, .chain_id = ALC269_FIXUP_HP_MUTE_LED_MIC3 - } + }, + [ALC221_FIXUP_HP_HEADSET_MIC] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x19, 0x0181313f}, + { } + }, + .chained = true, + .chain_id = ALC269_FIXUP_HEADSET_MIC + }, }; static const struct snd_pci_quirk alc269_fixup_tbl[] = { @@ -6777,6 +6787,12 @@ static const struct hda_model_fixup alc269_fixup_models[] = { {0x21, 0x03211020} static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = { + SND_HDA_PIN_QUIRK(0x10ec0221, 0x103c, "HP Workstation", ALC221_FIXUP_HP_HEADSET_MIC, + {0x14, 0x01014020}, + {0x17, 0x90170110}, + {0x18, 0x02a11030}, + {0x19, 0x0181303F}, + {0x21, 0x0221102f}), SND_HDA_PIN_QUIRK(0x10ec0255, 0x1025, "Acer", ALC255_FIXUP_ACER_MIC_NO_PRESENCE, {0x12, 0x90a601c0}, {0x14, 0x90171120}, |