diff options
228 files changed, 3869 insertions, 4298 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt index f35b77920786..0ce6665df4a2 100644 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -8,7 +8,7 @@ control module driver itself. See [2] for documentation about clock/clockdomain nodes. -[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml [2] Documentation/devicetree/bindings/clock/ti/* Required properties: diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt deleted file mode 100644 index 966514744df4..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Oxford Semiconductor OXNAS SoC GPIO Controller - -Please refer to gpio.txt for generic information regarding GPIO bindings. - -Required properties: - - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio" - - reg: Base address and length for the device. - - interrupts: The port interrupt shared by all pins. - - gpio-controller: Marks the port as GPIO controller. - - #gpio-cells: Two. The first cell is the pin number and - the second cell is used to specify the gpio polarity as defined in - defined in <dt-bindings/gpio/gpio.h>: - 0 = GPIO_ACTIVE_HIGH - 1 = GPIO_ACTIVE_LOW - - interrupt-controller: Marks the device node as an interrupt controller. - - #interrupt-cells: Two. The first cell is the GPIO number and second cell - is used to specify the trigger type as defined in - <dt-bindings/interrupt-controller/irq.h>: - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING - IRQ_TYPE_EDGE_BOTH - - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the - gpio base and count, should be in the format of numeric-gpio-range as - specified in the gpio.txt file. - -Example: - -gpio0: gpio@0 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x000000 0x100000>; - interrupts = <21>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pinctrl 0 0 32>; -}; - -keys { - ... - - button-esc { - label = "ESC"; - linux,code = <1>; - gpios = <&gpio0 12 0>; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml index 99080c9eaac3..4e7a456ea4cc 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml @@ -15,6 +15,7 @@ allOf: properties: compatible: enum: + - amlogic,c3-periphs-pinctrl - amlogic,meson-a1-periphs-pinctrl - amlogic,meson-s4-periphs-pinctrl @@ -36,6 +37,10 @@ patternProperties: - const: mux - const: gpio + gpio-line-names: + minItems: 62 # A1 + maxItems: 82 # S4 + unevaluatedProperties: type: object $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml index a7b29ef0bab6..e707c222a07f 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml @@ -41,6 +41,13 @@ $defs: gpio-ranges: maxItems: 1 + patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + + required: + - gpio-hog + required: - reg - reg-names diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml index 7c9c94ec5b7b..0942ea60c6cd 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml @@ -36,6 +36,9 @@ patternProperties: - const: ds - const: gpio + gpio-line-names: + maxItems: 15 + unevaluatedProperties: type: object $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml index 4bcb8b60420f..e3c8bde30559 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml @@ -38,6 +38,9 @@ patternProperties: - const: mux - const: ds + gpio-line-names: + maxItems: 85 + unevaluatedProperties: type: object $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml index 32d99c9b6afc..c1b03147e8ec 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml @@ -44,6 +44,10 @@ patternProperties: - const: pull - const: gpio + gpio-line-names: + minItems: 11 # GXL + maxItems: 16 # Meson8 + unevaluatedProperties: type: object $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml index d0441051f34a..4ec85b8248fa 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml @@ -45,6 +45,10 @@ patternProperties: - const: pull-enable - const: gpio + gpio-line-names: + minItems: 86 # AXG + maxItems: 120 # Meson8 + unevaluatedProperties: type: object $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml index bef85c25cdef..37c0a74c7c01 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml @@ -25,30 +25,32 @@ properties: reg: maxItems: 2 -patternProperties: - '^.*$': - if: - type: object - then: - patternProperties: - "^function|groups$": - $ref: /schemas/types.yaml#/definitions/string - enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, - ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, - EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0, - GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, - I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK, - MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, - NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, - NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, - PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, - RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, - RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD, - SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO, - SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU, - SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, - TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM, - VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2] +additionalProperties: + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + pins: true + bias-disable: true + + patternProperties: + "^function|groups$": + enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, + ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, + EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0, + GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, + I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK, + MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, + NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, + NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, + PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, + RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, + RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD, + SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU, + SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, + TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM, + VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2] allOf: - $ref: pinctrl.yaml# @@ -56,8 +58,6 @@ allOf: required: - compatible -additionalProperties: false - examples: - | syscon: scu@1e6e2000 { diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index 14c391f16899..863da5d80826 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -37,32 +37,34 @@ properties: 0: compatible with "aspeed,ast2500-gfx", "syscon" 1: compatible with "aspeed,ast2500-lhc", "syscon" -patternProperties: - '^.*$': - if: - type: object - then: - patternProperties: - "^function|groups$": - $ref: /schemas/types.yaml#/definitions/string - enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, - ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, - ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2, - GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5, - I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC, - LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK, - MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, - NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, - NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0, - PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, - RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, - SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1, - SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO, - SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG, - SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3, - TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6, - USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS, - VGAVS, VPI24, VPO, WDTRST1, WDTRST2] +additionalProperties: + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + pins: true + bias-disable: true + + patternProperties: + "^function|groups$": + enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, + ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, + ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2, + GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5, + I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC, + LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK, + MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, + NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, + NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0, + PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, + RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, + SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1, + SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG, + SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3, + TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6, + USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS, + VGAVS, VPI24, VPO, WDTRST1, WDTRST2] allOf: - $ref: pinctrl.yaml# @@ -71,8 +73,6 @@ required: - compatible - aspeed,external-nodes -additionalProperties: false - examples: - | #include <dt-bindings/clock/aspeed-clock.h> diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index 859a1889dc1e..612464aef98b 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -23,65 +23,65 @@ properties: compatible: const: aspeed,ast2600-pinctrl -patternProperties: - '^.*$': - if: - type: object - then: - properties: - function: - $ref: /schemas/types.yaml#/definitions/string - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2, - ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT, - FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, - GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, - GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, - I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, - I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, - MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, - NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, - NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, - NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11, - PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8, - PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, - RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14, - SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, - SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO, - SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, - SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14, - TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, - THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, - UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP, - USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ] - - groups: - $ref: /schemas/types.yaml#/definitions/string - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2, - ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4, - EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, - GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, - GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, - I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, - I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, - LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, - MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, - NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, - NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, - OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, - PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, - PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1, - QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, - RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1, - SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, - SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, - SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2, - SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, - SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, - TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, - TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, - TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, - UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, - WDTRST3, WDTRST4] +additionalProperties: + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2, + ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT, + FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, + GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, + GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, + I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, + I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, + MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, + NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, + NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, + NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11, + PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8, + PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, + RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14, + SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, + SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, + SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14, + TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, + THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, + UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP, + USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ] + + groups: + enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2, + ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4, + EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, + GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, + GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, + I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, + I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, + LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, + MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, + NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, + NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, + OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, + PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, + PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1, + QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, + RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1, + SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, + SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, + SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2, + SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, + SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, + TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, + TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, + TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, + UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, + WDTRST3, WDTRST4] + + pins: true + bias-disable: true allOf: - $ref: pinctrl.yaml# @@ -89,8 +89,6 @@ allOf: required: - compatible -additionalProperties: false - examples: - | syscon: scu@1e6e2000 { diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt deleted file mode 100644 index e047a198db38..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt +++ /dev/null @@ -1,461 +0,0 @@ -Broadcom BCM281xx Pin Controller - -This is a pin controller for the Broadcom BCM281xx SoC family, which includes -BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs. - -=== Pin Controller Node === - -Required Properties: - -- compatible: Must be "brcm,bcm11351-pinctrl" -- reg: Base address of the PAD Controller register block and the size - of the block. - -For example, the following is the bare minimum node: - - pinctrl@35004800 { - compatible = "brcm,bcm11351-pinctrl"; - reg = <0x35004800 0x430>; - }; - -As a pin controller device, in addition to the required properties, this node -should also contain the pin configuration nodes that client devices reference, -if any. - -=== Pin Configuration Node === - -Each pin configuration node is a sub-node of the pin controller node and is a -container of an arbitrary number of subnodes, called pin group nodes in this -document. - -Please refer to the pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the definition of a -"pin configuration node". - -=== Pin Group Node === - -A pin group node specifies the desired pin mux and/or pin configuration for an -arbitrary number of pins. The name of the pin group node is optional and not -used. - -A pin group node only affects the properties specified in the node, and has no -effect on any properties that are omitted. - -The pin group node accepts a subset of the generic pin config properties. For -details generic pin config properties, please refer to pinctrl-bindings.txt -and <include/linux/pinctrl/pinconfig-generic.h>. - -Each pin controlled by this pin controller belong to one of three types: -Standard, I2C, and HDMI. Each type accepts a different set of pin config -properties. A list of pins and their types is provided below. - -Required Properties (applicable to all pins): - -- pins: Multiple strings. Specifies the name(s) of one or more pins to - be configured by this node. - -Optional Properties (for standard pins): - -- function: String. Specifies the pin mux selection. Values - must be one of: "alt1", "alt2", "alt3", "alt4" -- input-schmitt-enable: No arguments. Enable schmitt-trigger mode. -- input-schmitt-disable: No arguments. Disable schmitt-trigger mode. -- bias-pull-up: No arguments. Pull up on pin. -- bias-pull-down: No arguments. Pull down on pin. -- bias-disable: No arguments. Disable pin bias. -- slew-rate: Integer. Meaning depends on configured pin mux: - *_SCL or *_SDA: - 0: Standard(100kbps)& Fast(400kbps) mode - 1: Highspeed (3.4Mbps) mode - IC_DM or IC_DP: - 0: normal slew rate - 1: fast slew rate - Otherwise: - 0: fast slew rate - 1: normal slew rate -- input-enable: No arguments. Enable input (does not affect - output.) -- input-disable: No arguments. Disable input (does not affect - output.) -- drive-strength: Integer. Drive strength in mA. Valid values are - 2, 4, 6, 8, 10, 12, 14, 16 mA. - -Optional Properties (for I2C pins): - -- function: String. Specifies the pin mux selection. Values - must be one of: "alt1", "alt2", "alt3", "alt4" -- bias-pull-up: Integer. Pull up strength in Ohm. There are 3 - pull-up resistors (1.2k, 1.8k, 2.7k) available - in parallel for I2C pins, so the valid values - are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. -- bias-disable: No arguments. Disable pin bias. -- slew-rate: Integer. Meaning depends on configured pin mux: - *_SCL or *_SDA: - 0: Standard(100kbps)& Fast(400kbps) mode - 1: Highspeed (3.4Mbps) mode - IC_DM or IC_DP: - 0: normal slew rate - 1: fast slew rate - Otherwise: - 0: fast slew rate - 1: normal slew rate -- input-enable: No arguments. Enable input (does not affect - output.) -- input-disable: No arguments. Disable input (does not affect - output.) - -Optional Properties (for HDMI pins): - -- function: String. Specifies the pin mux selection. Values - must be one of: "alt1", "alt2", "alt3", "alt4" -- slew-rate: Integer. Controls slew rate. - 0: Standard(100kbps)& Fast(400kbps) mode - 1: Highspeed (3.4Mbps) mode -- input-enable: No arguments. Enable input (does not affect - output.) -- input-disable: No arguments. Disable input (does not affect - output.) - -Example: -// pin controller node -pinctrl@35004800 { - compatible = "brcm,bcm11351-pinctrl"; - reg = <0x35004800 0x430>; - - // pin configuration node - dev_a_default: dev_a_active { - //group node defining 1 standard pin - grp_1 { - pins = "std_pin1"; - function = "alt1"; - input-schmitt-enable; - bias-disable; - slew-rate = <1>; - drive-strength = <4>; - }; - - // group node defining 2 I2C pins - grp_2 { - pins = "i2c_pin1", "i2c_pin2"; - function = "alt2"; - bias-pull-up = <720>; - input-enable; - }; - - // group node defining 2 HDMI pins - grp_3 { - pins = "hdmi_pin1", "hdmi_pin2"; - function = "alt3"; - slew-rate = <1>; - }; - - // other pin group nodes - ... - }; - - // other pin configuration nodes - ... -}; - -In the example above, "dev_a_active" is a pin configuration node with a number -of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in -the "pins" property. Thus, the remaining properties in the "grp_1" node applies -only to this pin, including the following settings: - - setting pinmux to "alt1" - - enabling schmitt-trigger (hystersis) mode - - disabling pin bias - - setting the slew-rate to 1 - - setting the drive strength to 4 mA -Note that neither "input-enable" nor "input-disable" was specified - the pinctrl -subsystem will therefore leave this property unchanged from whatever state it -was in before applying these changes. - -The "pins" property in the pin group node "grp_2" specifies two pins - -"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node, -therefore, applies to both of these pins. The properties include: - - setting pinmux to "alt2" - - setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors - in parallel) - - enabling both pins' input -"slew-rate" is not specified in this pin group node, so the slew-rate for these -pins are left as-is. - -Finally, "grp_3" defines two HDMI pins. The following properties are applied to -both pins: - - setting pinmux to "alt3" - - setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps - Highspeed mode -The input is neither enabled or disabled, and is left untouched. - -=== Pin Names and Type === - -The following are valid pin names and their pin types: - - "adcsync", Standard - "bat_rm", Standard - "bsc1_scl", I2C - "bsc1_sda", I2C - "bsc2_scl", I2C - "bsc2_sda", I2C - "classgpwr", Standard - "clk_cx8", Standard - "clkout_0", Standard - "clkout_1", Standard - "clkout_2", Standard - "clkout_3", Standard - "clkreq_in_0", Standard - "clkreq_in_1", Standard - "cws_sys_req1", Standard - "cws_sys_req2", Standard - "cws_sys_req3", Standard - "digmic1_clk", Standard - "digmic1_dq", Standard - "digmic2_clk", Standard - "digmic2_dq", Standard - "gpen13", Standard - "gpen14", Standard - "gpen15", Standard - "gpio00", Standard - "gpio01", Standard - "gpio02", Standard - "gpio03", Standard - "gpio04", Standard - "gpio05", Standard - "gpio06", Standard - "gpio07", Standard - "gpio08", Standard - "gpio09", Standard - "gpio10", Standard - "gpio11", Standard - "gpio12", Standard - "gpio13", Standard - "gpio14", Standard - "gps_pablank", Standard - "gps_tmark", Standard - "hdmi_scl", HDMI - "hdmi_sda", HDMI - "ic_dm", Standard - "ic_dp", Standard - "kp_col_ip_0", Standard - "kp_col_ip_1", Standard - "kp_col_ip_2", Standard - "kp_col_ip_3", Standard - "kp_row_op_0", Standard - "kp_row_op_1", Standard - "kp_row_op_2", Standard - "kp_row_op_3", Standard - "lcd_b_0", Standard - "lcd_b_1", Standard - "lcd_b_2", Standard - "lcd_b_3", Standard - "lcd_b_4", Standard - "lcd_b_5", Standard - "lcd_b_6", Standard - "lcd_b_7", Standard - "lcd_g_0", Standard - "lcd_g_1", Standard - "lcd_g_2", Standard - "lcd_g_3", Standard - "lcd_g_4", Standard - "lcd_g_5", Standard - "lcd_g_6", Standard - "lcd_g_7", Standard - "lcd_hsync", Standard - "lcd_oe", Standard - "lcd_pclk", Standard - "lcd_r_0", Standard - "lcd_r_1", Standard - "lcd_r_2", Standard - "lcd_r_3", Standard - "lcd_r_4", Standard - "lcd_r_5", Standard - "lcd_r_6", Standard - "lcd_r_7", Standard - "lcd_vsync", Standard - "mdmgpio0", Standard - "mdmgpio1", Standard - "mdmgpio2", Standard - "mdmgpio3", Standard - "mdmgpio4", Standard - "mdmgpio5", Standard - "mdmgpio6", Standard - "mdmgpio7", Standard - "mdmgpio8", Standard - "mphi_data_0", Standard - "mphi_data_1", Standard - "mphi_data_2", Standard - "mphi_data_3", Standard - "mphi_data_4", Standard - "mphi_data_5", Standard - "mphi_data_6", Standard - "mphi_data_7", Standard - "mphi_data_8", Standard - "mphi_data_9", Standard - "mphi_data_10", Standard - "mphi_data_11", Standard - "mphi_data_12", Standard - "mphi_data_13", Standard - "mphi_data_14", Standard - "mphi_data_15", Standard - "mphi_ha0", Standard - "mphi_hat0", Standard - "mphi_hat1", Standard - "mphi_hce0_n", Standard - "mphi_hce1_n", Standard - "mphi_hrd_n", Standard - "mphi_hwr_n", Standard - "mphi_run0", Standard - "mphi_run1", Standard - "mtx_scan_clk", Standard - "mtx_scan_data", Standard - "nand_ad_0", Standard - "nand_ad_1", Standard - "nand_ad_2", Standard - "nand_ad_3", Standard - "nand_ad_4", Standard - "nand_ad_5", Standard - "nand_ad_6", Standard - "nand_ad_7", Standard - "nand_ale", Standard - "nand_cen_0", Standard - "nand_cen_1", Standard - "nand_cle", Standard - "nand_oen", Standard - "nand_rdy_0", Standard - "nand_rdy_1", Standard - "nand_wen", Standard - "nand_wp", Standard - "pc1", Standard - "pc2", Standard - "pmu_int", Standard - "pmu_scl", I2C - "pmu_sda", I2C - "rfst2g_mtsloten3g", Standard - "rgmii_0_rx_ctl", Standard - "rgmii_0_rxc", Standard - "rgmii_0_rxd_0", Standard - "rgmii_0_rxd_1", Standard - "rgmii_0_rxd_2", Standard - "rgmii_0_rxd_3", Standard - "rgmii_0_tx_ctl", Standard - "rgmii_0_txc", Standard - "rgmii_0_txd_0", Standard - "rgmii_0_txd_1", Standard - "rgmii_0_txd_2", Standard - "rgmii_0_txd_3", Standard - "rgmii_1_rx_ctl", Standard - "rgmii_1_rxc", Standard - "rgmii_1_rxd_0", Standard - "rgmii_1_rxd_1", Standard - "rgmii_1_rxd_2", Standard - "rgmii_1_rxd_3", Standard - "rgmii_1_tx_ctl", Standard - "rgmii_1_txc", Standard - "rgmii_1_txd_0", Standard - "rgmii_1_txd_1", Standard - "rgmii_1_txd_2", Standard - "rgmii_1_txd_3", Standard - "rgmii_gpio_0", Standard - "rgmii_gpio_1", Standard - "rgmii_gpio_2", Standard - "rgmii_gpio_3", Standard - "rtxdata2g_txdata3g1", Standard - "rtxen2g_txdata3g2", Standard - "rxdata3g0", Standard - "rxdata3g1", Standard - "rxdata3g2", Standard - "sdio1_clk", Standard - "sdio1_cmd", Standard - "sdio1_data_0", Standard - "sdio1_data_1", Standard - "sdio1_data_2", Standard - "sdio1_data_3", Standard - "sdio4_clk", Standard - "sdio4_cmd", Standard - "sdio4_data_0", Standard - "sdio4_data_1", Standard - "sdio4_data_2", Standard - "sdio4_data_3", Standard - "sim_clk", Standard - "sim_data", Standard - "sim_det", Standard - "sim_resetn", Standard - "sim2_clk", Standard - "sim2_data", Standard - "sim2_det", Standard - "sim2_resetn", Standard - "sri_c", Standard - "sri_d", Standard - "sri_e", Standard - "ssp_extclk", Standard - "ssp0_clk", Standard - "ssp0_fs", Standard - "ssp0_rxd", Standard - "ssp0_txd", Standard - "ssp2_clk", Standard - "ssp2_fs_0", Standard - "ssp2_fs_1", Standard - "ssp2_fs_2", Standard - "ssp2_fs_3", Standard - "ssp2_rxd_0", Standard - "ssp2_rxd_1", Standard - "ssp2_txd_0", Standard - "ssp2_txd_1", Standard - "ssp3_clk", Standard - "ssp3_fs", Standard - "ssp3_rxd", Standard - "ssp3_txd", Standard - "ssp4_clk", Standard - "ssp4_fs", Standard - "ssp4_rxd", Standard - "ssp4_txd", Standard - "ssp5_clk", Standard - "ssp5_fs", Standard - "ssp5_rxd", Standard - "ssp5_txd", Standard - "ssp6_clk", Standard - "ssp6_fs", Standard - "ssp6_rxd", Standard - "ssp6_txd", Standard - "stat_1", Standard - "stat_2", Standard - "sysclken", Standard - "traceclk", Standard - "tracedt00", Standard - "tracedt01", Standard - "tracedt02", Standard - "tracedt03", Standard - "tracedt04", Standard - "tracedt05", Standard - "tracedt06", Standard - "tracedt07", Standard - "tracedt08", Standard - "tracedt09", Standard - "tracedt10", Standard - "tracedt11", Standard - "tracedt12", Standard - "tracedt13", Standard - "tracedt14", Standard - "tracedt15", Standard - "txdata3g0", Standard - "txpwrind", Standard - "uartb1_ucts", Standard - "uartb1_urts", Standard - "uartb1_urxd", Standard - "uartb1_utxd", Standard - "uartb2_urxd", Standard - "uartb2_utxd", Standard - "uartb3_ucts", Standard - "uartb3_urts", Standard - "uartb3_urxd", Standard - "uartb3_utxd", Standard - "uartb4_ucts", Standard - "uartb4_urts", Standard - "uartb4_urxd", Standard - "uartb4_utxd", Standard - "vc_cam1_scl", I2C - "vc_cam1_sda", I2C - "vc_cam2_scl", I2C - "vc_cam2_sda", I2C - "vc_cam3_scl", I2C - "vc_cam3_sda", I2C diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml new file mode 100644 index 000000000000..90c275295199 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml @@ -0,0 +1,259 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM281xx pin controller + +maintainers: + - Florian Fainelli <florian.fainelli@broadcom.com> + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: brcm,bcm11351-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '-grp[0-9]$': + type: object + unevaluatedProperties: false + + properties: + pins: + description: + Specifies the name(s) of one or more pins to be configured by + this node. + items: + enum: [ adcsync, bat_rm, bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, + classgpwr, clk_cx8, clkout_0, clkout_1, clkout_2, + clkout_3, clkreq_in_0, clkreq_in_1, cws_sys_req1, + cws_sys_req2, cws_sys_req3, digmic1_clk, digmic1_dq, + digmic2_clk, digmic2_dq, gpen13, gpen14, gpen15, gpio00, + gpio01, gpio02, gpio03, gpio04, gpio05, gpio06, gpio07, + gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, gpio14, + gps_pablank, gps_tmark, hdmi_scl, hdmi_sda, ic_dm, ic_dp, + kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3, + kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3, + lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5, + lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3, + lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, lcd_oe, + lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, lcd_r_3, lcd_r_4, + lcd_r_5, lcd_r_6, lcd_r_7, lcd_vsync, mdmgpio0, mdmgpio1, + mdmgpio2, mdmgpio3, mdmgpio4, mdmgpio5, mdmgpio6, + mdmgpio7, mdmgpio8, mphi_data_0, mphi_data_1, mphi_data_2, + mphi_data_3, mphi_data_4, mphi_data_5, mphi_data_6, + mphi_data_7, mphi_data_8, mphi_data_9, mphi_data_10, + mphi_data_11, mphi_data_12, mphi_data_13, mphi_data_14, + mphi_data_15, mphi_ha0, mphi_hat0, mphi_hat1, mphi_hce0_n, + mphi_hce1_n, mphi_hrd_n, mphi_hwr_n, mphi_run0, mphi_run1, + mtx_scan_clk, mtx_scan_data, nand_ad_0, nand_ad_1, + nand_ad_2, nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6, + nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, nand_cle, + nand_oen, nand_rdy_0, nand_rdy_1, nand_wen, nand_wp, pc1, + pc2, pmu_int, pmu_scl, pmu_sda, rfst2g_mtsloten3g, + rgmii_0_rx_ctl, rgmii_0_rxc, rgmii_0_rxd_0, rgmii_0_rxd_1, + rgmii_0_rxd_2, rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc, + rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2, + rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, rgmii_1_rxd_0, + rgmii_1_rxd_1, rgmii_1_rxd_2, rgmii_1_rxd_3, + rgmii_1_tx_ctl, rgmii_1_txc, rgmii_1_txd_0, rgmii_1_txd_1, + rgmii_1_txd_2, rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1, + rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1, + rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2, + sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1, + sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd, + sdio4_data_0, sdio4_data_1, sdio4_data_2, sdio4_data_3, + sim_clk, sim_data, sim_det, sim_resetn, sim2_clk, + sim2_data, sim2_det, sim2_resetn, sri_c, sri_d, sri_e, + ssp_extclk, ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, + ssp2_clk, ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3, + ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, ssp3_clk, + ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, ssp4_fs, ssp4_rxd, + ssp4_txd, ssp5_clk, ssp5_fs, ssp5_rxd, ssp5_txd, ssp6_clk, + ssp6_fs, ssp6_rxd, ssp6_txd, stat_1, stat_2, sysclken, + traceclk, tracedt00, tracedt01, tracedt02, tracedt03, + tracedt04, tracedt05, tracedt06, tracedt07, tracedt08 + tracedt09, tracedt10, tracedt11, tracedt12, tracedt13 + tracedt14, tracedt15, txdata3g0, txpwrind, uartb1_ucts, + uartb1_urts, uartb1_urxd, uartb1_utxd, uartb2_urxd, + uartb2_utxd, uartb3_ucts, uartb3_urts, uartb3_urxd, + uartb3_utxd, uartb4_ucts, uartb4_urts, uartb4_urxd, + uartb4_utxd, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl, + vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ] + + function: + description: + Specifies the pin mux selection. + enum: [ alt1, alt2, alt3, alt4 ] + + slew-rate: + description: | + Meaning depends on configured pin mux: + *_scl or *_sda: + 0: Standard (100 kbps) & Fast (400 kbps) mode + 1: Highspeed (3.4 Mbps) mode + ic_dm or ic_dp: + 0: normal slew rate + 1: fast slew rate + Otherwise: + 0: fast slew rate + 1: normal slew rate + + bias-disable: true + input-disable: true + input-enable: true + + required: + - pins + + allOf: + - $ref: pincfg-node.yaml# + + # Optional properties for standard pins + - if: + properties: + pins: + contains: + enum: [ adcsync, bat_rm, classgpwr, clk_cx8, clkout_0, + clkout_1, clkout_2, clkout_3, clkreq_in_0, + clkreq_in_1, cws_sys_req1, cws_sys_req2, + cws_sys_req3, digmic1_clk, digmic1_dq, digmic2_clk, + digmic2_dq, gpen13, gpen14, gpen15, gpio00, gpio01, + gpio02, gpio03, gpio04, gpio05, gpio06, gpio07, + gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, + gpio14, gps_pablank, gps_tmark, ic_dm, ic_dp, + kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3, + kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3, + lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5, + lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3, + lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, + lcd_oe, lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, + lcd_r_3, lcd_r_4, lcd_r_5, lcd_r_6, lcd_r_7, + lcd_vsync, mdmgpio0, mdmgpio1, mdmgpio2, mdmgpio3, + mdmgpio4, mdmgpio5, mdmgpio6, mdmgpio7, mdmgpio8, + mphi_data_0, mphi_data_1, mphi_data_2, mphi_data_3, + mphi_data_4, mphi_data_5, mphi_data_6, mphi_data_7, + mphi_data_8, mphi_data_9, mphi_data_10, + mphi_data_11, mphi_data_12, mphi_data_13, + mphi_data_14, mphi_data_15, mphi_ha0, mphi_hat0, + mphi_hat1, mphi_hce0_n, mphi_hce1_n, mphi_hrd_n, + mphi_hwr_n, mphi_run0, mphi_run1, mtx_scan_clk, + mtx_scan_data, nand_ad_0, nand_ad_1, nand_ad_2, + nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6, + nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, + nand_cle, nand_oen, nand_rdy_0, nand_rdy_1, + nand_wen, nand_wp, pc1, pc2, pmu_int, + rfst2g_mtsloten3g, rgmii_0_rx_ctl, rgmii_0_rxc, + rgmii_0_rxd_0, rgmii_0_rxd_1, rgmii_0_rxd_2, + rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc, + rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2, + rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, + rgmii_1_rxd_0, rgmii_1_rxd_1, rgmii_1_rxd_2, + rgmii_1_rxd_3, rgmii_1_tx_ctl, rgmii_1_txc, + rgmii_1_txd_0, rgmii_1_txd_1, rgmii_1_txd_2, + rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1, + rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1, + rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2, + sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1, + sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd, + sdio4_data_0, sdio4_data_1, sdio4_data_2, + sdio4_data_3, sim_clk, sim_data, sim_det, + sim_resetn, sim2_clk, sim2_data, sim2_det, + sim2_resetn, sri_c, sri_d, sri_e, ssp_extclk, + ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, ssp2_clk, + ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3, + ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, + ssp3_clk, ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, + ssp4_fs, ssp4_rxd, ssp4_txd, ssp5_clk, ssp5_fs, + ssp5_rxd, ssp5_txd, ssp6_clk, ssp6_fs, ssp6_rxd, + ssp6_txd, stat_1, stat_2, sysclken, traceclk, + tracedt00, tracedt01, tracedt02, tracedt03, + tracedt04, tracedt05, tracedt06, tracedt07, + tracedt08, tracedt09, tracedt10, tracedt11, + tracedt12, tracedt13, tracedt14, tracedt15, + txdata3g0, txpwrind, uartb1_ucts, uartb1_urts, + uartb1_urxd, uartb1_utxd, uartb2_urxd, uartb2_utxd, + uartb3_ucts, uartb3_urts, uartb3_urxd, uartb3_utxd, + uartb4_ucts, uartb4_urts, uartb4_urxd, uartb4_utxd ] + then: + properties: + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + input-schmitt-enable: true + input-schmitt-disable: true + + # Optional properties for I2C pins + - if: + properties: + pins: + contains: + enum: [ bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, pmu_scl, + pmu_sda, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl, + vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ] + then: + properties: + bias-pull-up: + description: + There are 3 pull-up resistors (1.2k, 1.8k, 2.7k) available + in parallel for I2C pins. + enum: [ 568, 720, 831, 1080, 1200, 1800, 2700 ] + + bias-disable: true + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@35004800 { + compatible = "brcm,bcm11351-pinctrl"; + reg = <0x35004800 0x430>; + + dev-a-active-pins { + /* group node defining 1 standard pin */ + std-grp0 { + pins = "gpio00"; + function = "alt1"; + input-schmitt-enable; + bias-disable; + slew-rate = <1>; + drive-strength = <4>; + }; + + /* group node defining 2 I2C pins */ + i2c-grp0 { + pins = "bsc1_scl", "bsc1_sda"; + function = "alt2"; + bias-pull-up = <720>; + input-enable; + }; + + /* group node defining 2 HDMI pins */ + hdmi-grp0 { + pins = "hdmi_scl", "hdmi_sda"; + function = "alt3"; + slew-rate = <1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml b/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml index 222d57541b65..7f30ec2f1e54 100644 --- a/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml +++ b/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml @@ -51,6 +51,10 @@ properties: description: Optional power supply. + reset-gpios: + description: GPIO connected to the XRES pin + maxItems: 1 + patternProperties: '-pins$': type: object diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml index 35723966b70a..890961826c6f 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml @@ -135,7 +135,6 @@ additionalProperties: - $ref: pinmux-node.yaml# properties: - phandle: true function: true groups: true pins: true @@ -147,8 +146,6 @@ additionalProperties: additionalProperties: false - type: object - properties: - phandle: true additionalProperties: type: object allOf: @@ -156,7 +153,6 @@ additionalProperties: - $ref: pinmux-node.yaml# properties: - phandle: true function: true groups: true pins: true diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml index 065dedb3573a..1690c0ef553a 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml @@ -22,8 +22,6 @@ properties: patternProperties: "^pinmux(-[a-z0-9-_]+)?$": type: object - properties: - phandle: true # pin groups additionalProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml index f924652bef0d..9b7368bd3862 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml @@ -32,8 +32,6 @@ properties: patternProperties: "^pinmux(-[a-z0-9-_]+)?$": type: object - properties: - phandle: true # pin groups additionalProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml index 60a4bdf01bf2..87b6f4f42f25 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml @@ -23,8 +23,6 @@ properties: patternProperties: "^pinmux(-[a-z0-9-_]+)?$": type: object - properties: - phandle: true # pin groups additionalProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml index 432ea40209a8..63cd743a30e0 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml @@ -24,8 +24,6 @@ properties: patternProperties: "^pinmux(-[a-z0-9-_]+)?$": type: object - properties: - phandle: true # pin groups additionalProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml index 28ae2e6d0cbc..e99387a6da5e 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml @@ -22,8 +22,6 @@ properties: patternProperties: "^pinmux(-[a-z0-9-_]+)?$": type: object - properties: - phandle: true # pin groups additionalProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml index c0eda7848767..36c8f3301a8f 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml @@ -22,8 +22,6 @@ properties: patternProperties: "^pinmux(-[a-z0-9-_]+)?$": type: object - properties: - phandle: true # pin groups additionalProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt deleted file mode 100644 index b1159434f593..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Oxford Semiconductor OXNAS SoC Family Pin Controller - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -OXNAS 'pin configuration node' is a node of a group of pins which can be -used for a specific device or function. This node represents configurations of -pins, optional function, and optional mux related configuration. - -Required properties for pin controller node: - - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl" - - oxsemi,sys-ctrl: a phandle to the system controller syscon node - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - function: Mux function for the specified pins. - - bias-pull-up: Enable weak pull-up. - -Example: - -pinctrl: pinctrl { - compatible = "oxsemi,ox810se-pinctrl"; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - pinctrl_uart2: pinctrl_uart2 { - uart2a { - pins = "gpio31"; - function = "fct3"; - }; - uart2b { - pins = "gpio32"; - function = "fct3"; - }; - }; -}; - -uart2: serial@900000 { - compatible = "ns16550a"; - reg = <0x900000 0x100000>; - clocks = <&sysclk>; - interrupts = <29>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - resets = <&reset 22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt deleted file mode 100644 index bfd222b05495..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ /dev/null @@ -1,262 +0,0 @@ -One-register-per-pin type device tree based pinctrl driver - -Required properties: -- compatible : "pinctrl-single" or "pinconf-single". - "pinctrl-single" means that pinconf isn't supported. - "pinconf-single" means that generic pinconf is supported. - -- reg : offset and length of the register set for the mux registers - -- #pinctrl-cells : number of cells in addition to the index, set to 1 - or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits - -- pinctrl-single,register-width : pinmux register access width in bits - -- pinctrl-single,function-mask : mask of allowed pinmux function bits - in the pinmux register - -Optional properties: -- pinctrl-single,function-off : function off mode for disabled state if - available and same for all registers; if not specified, disabling of - pin functions is ignored - -- pinctrl-single,bit-per-mux : boolean to indicate that one register controls - more than one pin, for which "pinctrl-single,function-mask" property specifies - position mask of pin. - -- pinctrl-single,drive-strength : array of value that are used to configure - drive strength in the pinmux register. They're value of drive strength - current and drive strength mask. - - /* drive strength current, mask */ - pinctrl-single,power-source = <0x30 0xf0>; - -- pinctrl-single,bias-pullup : array of value that are used to configure the - input bias pullup in the pinmux register. - - /* input, enabled pullup bits, disabled pullup bits, mask */ - pinctrl-single,bias-pullup = <0 1 0 1>; - -- pinctrl-single,bias-pulldown : array of value that are used to configure the - input bias pulldown in the pinmux register. - - /* input, enabled pulldown bits, disabled pulldown bits, mask */ - pinctrl-single,bias-pulldown = <2 2 0 2>; - - * Two bits to control input bias pullup and pulldown: User should use - pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means - pullup, and the other one bit means pulldown. - * Three bits to control input bias enable, pullup and pulldown. User should - use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias - enable bit should be included in pullup or pulldown bits. - * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as - pinctrl-single,bias-disable. Because pinctrl single driver could implement - it by calling pulldown, pullup disabled. - -- pinctrl-single,input-schmitt : array of value that are used to configure - input schmitt in the pinmux register. In some silicons, there're two input - schmitt value (rising-edge & falling-edge) in the pinmux register. - - /* input schmitt value, mask */ - pinctrl-single,input-schmitt = <0x30 0x70>; - -- pinctrl-single,input-schmitt-enable : array of value that are used to - configure input schmitt enable or disable in the pinmux register. - - /* input, enable bits, disable bits, mask */ - pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; - -- pinctrl-single,low-power-mode : array of value that are used to configure - low power mode of this pin. For some silicons, the low power mode will - control the output of the pin when the pad including the pin enter low - power mode. - /* low power mode value, mask */ - pinctrl-single,low-power-mode = <0x288 0x388>; - -- pinctrl-single,gpio-range : list of value that are used to configure a GPIO - range. They're value of subnode phandle, pin base in pinctrl device, pin - number in this range, GPIO function value of this GPIO range. - The number of parameters is depend on #pinctrl-single,gpio-range-cells - property. - - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>; - -- interrupt-controller : standard interrupt controller binding if using - interrupts for wake-up events for example. In this case pinctrl-single - is set up as a chained interrupt controller and the wake-up interrupts - can be requested by the drivers using request_irq(). - -- #interrupt-cells : standard interrupt binding if using interrupts - -This driver assumes that there is only one register for each pin (unless the -pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as -specified in the pinctrl-bindings.txt document in this directory. - -The pin configuration nodes for pinctrl-single are specified as pinctrl -register offset and values using pinctrl-single,pins. Only the bits specified -in pinctrl-single,function-mask are updated. - -When #pinctrl-cells = 1, then setting a pin for a device could be done with: - - pinctrl-single,pins = <0xdc 0x118>; - -Where 0xdc is the offset from the pinctrl register base address for the device -pinctrl register, and 0x118 contains the desired value of the pinctrl register. - -When #pinctrl-cells = 2, then setting a pin for a device could be done with: - - pinctrl-single,pins = <0xdc 0x30 0x07>; - -Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value. -These two values are OR'd together to produce the value stored at offset 0xdc. -See the device example and static board pins example below for more information. - -In case when one register changes more than one pin's mux the -pinctrl-single,bits need to be used which takes three parameters: - - pinctrl-single,bits = <0xdc 0x18 0xff>; - -Where 0xdc is the offset from the pinctrl register base address for the -device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to -be used when applying this change to the register. - - -Optional sub-node: In case some pins could be configured as GPIO in the pinmux -register, those pins could be defined as a GPIO range. This sub-node is required -by pinctrl-single,gpio-range property. - -Required properties in sub-node: -- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in - pinctrl-single,gpio-range property. - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - -Example: - -/* SoC common file */ - -/* first controller instance for pins in core domain */ -pmx_core: pinmux@4a100040 { - compatible = "pinctrl-single"; - reg = <0x4a100040 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xffff>; -}; - -/* second controller instance for pins in wkup domain */ -pmx_wkup: pinmux@4a31e040 { - compatible = "pinctrl-single"; - reg = <0x4a31e040 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xffff>; -}; - -control_devconf0: pinmux@48002274 { - compatible = "pinctrl-single"; - reg = <0x48002274 4>; /* Single register */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x5F>; -}; - -/* third controller instance for pins in gpio domain */ -pmx_gpio: pinmux@d401e000 { - compatible = "pinconf-single"; - reg = <0xd401e000 0x0330>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - - /* sparse GPIO range could be supported */ - pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>, - <&range 12 1 0>, <&range 13 29 1>, - <&range 43 1 0>, <&range 44 49 1>, - <&range 94 1 1>, <&range 96 2 1>; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - - -/* board specific .dts file */ - -&pmx_core { - - /* - * map all board specific static pins enabled by the pinctrl driver - * itself during the boot (or just set them up in the bootloader) - */ - pinctrl-names = "default"; - pinctrl-0 = <&board_pins>; - - board_pins: pinmux_board_pins { - pinctrl-single,pins = < - 0x6c 0xf - 0x6e 0xf - 0x70 0xf - 0x72 0xf - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <0 2 2>; - pinctrl-single,bias-pullup = <0 1 1>; - }; - - /* map uart2 pins */ - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0xd8 0x118 - 0xda 0 - 0xdc 0x118 - 0xde 0 - >; - }; -}; - -&control_devconf0 { - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,bits = < - 0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */ - >; - }; - - mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins { - pinctrl-single,bits = < - 0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */ - >; - }; - -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml new file mode 100644 index 000000000000..45a307d3ce16 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -0,0 +1,207 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Pin Controller with a Single Register for One or More Pins + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: + Some pin controller devices use a single register for one or more pins. The + range of pin control registers can vary from one to many for each controller + instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this + kind of pin controller instances. + +properties: + compatible: + oneOf: + - enum: + - pinctrl-single + - pinconf-single + - items: + - enum: + - ti,am437-padconf + - ti,am654-padconf + - ti,dra7-padconf + - ti,omap2420-padconf + - ti,omap2430-padconf + - ti,omap3-padconf + - ti,omap4-padconf + - ti,omap5-padconf + - const: pinctrl-single + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pinctrl-cells': + description: + Number of cells. Usually 2, consisting of register offset, pin configuration + value, and pinmux mode. Some controllers may use 1 for just offset and value. + enum: [ 1, 2 ] + + pinctrl-single,bit-per-mux: + description: Optional flag to indicate register controls more than one pin + type: boolean + + pinctrl-single,function-mask: + description: Mask of the allowed register bits + $ref: /schemas/types.yaml#/definitions/uint32 + + pinctrl-single,function-off: + description: Optional function off mode for disabled state + $ref: /schemas/types.yaml#/definitions/uint32 + + pinctrl-single,register-width: + description: Width of pin specific bits in the register + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 8, 16, 32 ] + + pinctrl-single,gpio-range: + description: Optional list of pin base, nr pins & gpio function + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of a gpio-range node + - description: pin base + - description: number of pins + - description: gpio function + + '#gpio-range-cells': + description: No longer needed, may exist in older files for gpio-ranges + deprecated: true + const: 3 + + gpio-range: + description: Optional node for gpio range cells + type: object + additionalProperties: false + properties: + '#pinctrl-single,gpio-range-cells': + description: Number of gpio range cells + const: 3 + $ref: /schemas/types.yaml#/definitions/uint32 + +patternProperties: + '-pins(-[0-9]+)?$|-pin$': + description: + Pin group node name using naming ending in -pins followed by an optional + instance number + type: object + additionalProperties: false + + properties: + pinctrl-single,pins: + description: + Array of pins as described in pinmux-node.yaml for pinctrl-pin-array + $ref: /schemas/types.yaml#/definitions/uint32-array + + pinctrl-single,bits: + description: Register bit configuration for pinctrl-single,bit-per-mux + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: register offset + - description: value + - description: pin bitmask in the register + + pinctrl-single,bias-pullup: + description: Optional bias pull up configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enabled pull up bits + - description: disabled pull up bits + - description: bias pull up mask + + pinctrl-single,bias-pulldown: + description: Optional bias pull down configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enabled pull down bits + - description: disabled pull down bits + - description: bias pull down mask + + pinctrl-single,drive-strength: + description: Optional drive strength configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: drive strength current + - description: drive strength mask + + pinctrl-single,input-schmitt: + description: Optional input schmitt configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enable bits + - description: disable bits + - description: input schmitt mask + + pinctrl-single,low-power-mode: + description: Optional low power mode configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: low power mode value + - description: low power mode mask + + pinctrl-single,slew-rate: + description: Optional slew rate configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: slew rate + - description: slew rate mask + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - pinctrl-single,register-width + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + pinmux@4a100040 { + compatible = "pinctrl-single"; + reg = <0x4a100040 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xffff>; + pinctrl-single,gpio-range = <&range 0 3 0>; + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + uart2-pins { + pinctrl-single,pins = + <0xd8 0x118>, + <0xda 0>, + <0xdc 0x118>, + <0xde 0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 8aaf50181cef..3f8ad07c7cfd 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -26,6 +26,7 @@ properties: - qcom,pm6350-gpio - qcom,pm7250b-gpio - qcom,pm7325-gpio + - qcom,pm7550ba-gpio - qcom,pm8005-gpio - qcom,pm8008-gpio - qcom,pm8018-gpio @@ -53,6 +54,8 @@ properties: - qcom,pm8994-gpio - qcom,pm8998-gpio - qcom,pma8084-gpio + - qcom,pmc8180-gpio + - qcom,pmc8180c-gpio - qcom,pmi632-gpio - qcom,pmi8950-gpio - qcom,pmi8994-gpio @@ -68,6 +71,7 @@ properties: - qcom,pms405-gpio - qcom,pmx55-gpio - qcom,pmx65-gpio + - qcom,pmx75-gpio - enum: - qcom,spmi-gpio @@ -172,6 +176,7 @@ allOf: compatible: contains: enum: + - qcom,pm7550ba-gpio - qcom,pm8226-gpio - qcom,pm8350b-gpio - qcom,pm8550ve-gpio @@ -301,6 +306,7 @@ allOf: contains: enum: - qcom,pmx65-gpio + - qcom,pmx75-gpio then: properties: gpio-line-names: @@ -413,6 +419,7 @@ $defs: - gpio1-gpio9 for pm6350 - gpio1-gpio12 for pm7250b - gpio1-gpio10 for pm7325 + - gpio1-gpio8 for pm7550ba - gpio1-gpio4 for pm8005 - gpio1-gpio2 for pm8008 - gpio1-gpio6 for pm8018 @@ -456,6 +463,7 @@ $defs: - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 and gpio11) - gpio1-gpio16 for pmx65 + - gpio1-gpio16 for pmx75 items: pattern: "^gpio([0-9]+)$" diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml index fa51fa9536f7..00c5a00e35fc 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -17,11 +17,6 @@ properties: compatible: const: qcom,sc7280-lpass-lpi-pinctrl - qcom,adsp-bypass-mode: - description: - Tells ADSP is in bypass mode. - type: boolean - reg: maxItems: 2 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..abac3311fc55 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 SoC LPASS LPI TLMM + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM6115 SoC. + +properties: + compatible: + const: qcom,sm6115-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Audio voting clock + + clock-names: + items: + - const: audio + + gpio-controller: true + + "#gpio-cells": + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6115-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6115-lpass-state" + additionalProperties: false + +$defs: + qcom-sm6115-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-8])$" + + function: + enum: [ dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, gpio, i2s1_clk, + i2s1_data, i2s1_ws, i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, + i2s3_data, i2s3_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_mclk ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-bus-hold: true + bias-pull-down: true + bias-pull-up: true + bias-disable: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + + lpass_tlmm: pinctrl@a7c0000 { + compatible = "qcom,sm6115-lpass-lpi-pinctrl"; + reg = <0x0a7c0000 0x20000>, + <0x0a950000 0x10000>; + clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 19>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..2e65ae08dd21 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM8350 SoC. + +properties: + compatible: + const: qcom,sm8350-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + "#gpio-cells": + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8350-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8350-lpass-state" + additionalProperties: false + +$defs: + qcom-sm8350-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk, + i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk, + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-bus-hold: true + bias-pull-down: true + bias-pull-up: true + bias-disable: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8350-lpass-lpi-pinctrl"; + reg = <0x033c0000 0x20000>, + <0x03550000 0x10000>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml index 0fc3c0f52c19..181cd1676c0a 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -107,7 +107,6 @@ additionalProperties: Client device subnodes use below standard properties. properties: - phandle: true function: true groups: true pins: true @@ -127,9 +126,6 @@ additionalProperties: additionalProperties: false - type: object - properties: - phandle: true - additionalProperties: $ref: "#/additionalProperties/anyOf/0" diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml index 83800fcf0ce4..2bd7d47d0fdb 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml @@ -108,7 +108,6 @@ additionalProperties: Integers values in "pinmux" argument list are assembled as: ((PORT * 16 + PIN) | MUX_FUNC << 16) - phandle: true input-enable: true output-enable: true @@ -118,9 +117,6 @@ additionalProperties: additionalProperties: false - type: object - properties: - phandle: true - additionalProperties: $ref: "#/additionalProperties/anyOf/0" diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml index 37173a64fed2..8271e7b2c162 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml @@ -37,40 +37,37 @@ properties: gpio-ranges: maxItems: 1 -patternProperties: - "^.*$": - if: - type: object - then: - allOf: - - $ref: pincfg-node.yaml# - - $ref: pinmux-node.yaml# +additionalProperties: + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + The child nodes of the pin controller designate pins to be used for + specific peripheral functions or as GPIO. + + A pin multiplexing sub-node describes how to configure a set of + (or a single) pin in some desired alternate function mode. + The values for the pinmux properties are a combination of port name, + pin number and the desired function index. Use the RZA2_PINMUX macro + located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily + define these. + For assigning GPIO pins, use the macro RZA2_PIN also in + to express the desired port pin. + + properties: + pinmux: description: - The child nodes of the pin controller designate pins to be used for - specific peripheral functions or as GPIO. + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZA2_PINMUX() + helper macro in r7s9210-pinctrl.h. - A pin multiplexing sub-node describes how to configure a set of - (or a single) pin in some desired alternate function mode. - The values for the pinmux properties are a combination of port name, - pin number and the desired function index. Use the RZA2_PINMUX macro - located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily - define these. - For assigning GPIO pins, use the macro RZA2_PIN also in - to express the desired port pin. + required: + - pinmux - properties: - phandle: true - - pinmux: - description: - Values are constructed from GPIO port number, pin number, and - alternate function configuration number using the RZA2_PINMUX() - helper macro in r7s9210-pinctrl.h. - - required: - - pinmux - - additionalProperties: false + additionalProperties: false allOf: - $ref: pinctrl.yaml# @@ -82,8 +79,6 @@ required: - '#gpio-cells' - gpio-ranges -additionalProperties: false - examples: - | #include <dt-bindings/pinctrl/r7s9210-pinctrl.h> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 9ce1a07fc015..145c5442f268 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -83,7 +83,6 @@ additionalProperties: Client device subnodes use below standard properties. properties: - phandle: true pinmux: description: Values are constructed from GPIO port number, pin number, and @@ -106,9 +105,6 @@ additionalProperties: line-name: true - type: object - properties: - phandle: true - additionalProperties: $ref: "#/additionalProperties/anyOf/0" diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml index 19d4d2facfb4..816688580e33 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml @@ -74,7 +74,6 @@ additionalProperties: offset by 10. Additional identifiers are provided to specify the MDIO source peripheral. - phandle: true bias-disable: true bias-pull-up: description: Pull up the pin with 50 kOhm @@ -91,9 +90,6 @@ additionalProperties: $ref: "#/additionalProperties/anyOf/0" - type: object - properties: - phandle: true - additionalProperties: $ref: "#/additionalProperties/anyOf/0" diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml index c87161f2954f..cb81a17bd0b1 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml @@ -63,7 +63,6 @@ additionalProperties: Client device subnodes use below standard properties. properties: - phandle: true pinmux: description: Values are constructed from GPIO port number, pin number, and @@ -87,9 +86,6 @@ additionalProperties: line-name: true - type: object - properties: - phandle: true - additionalProperties: $ref: "#/additionalProperties/anyOf/0" diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml index a6f34df82e90..880da721a927 100644 --- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -32,7 +32,6 @@ additionalProperties: - $ref: pinmux-node.yaml# properties: - phandle: true function: true groups: true pins: true @@ -49,7 +48,6 @@ additionalProperties: - $ref: pinmux-node.yaml# properties: - phandle: true function: true groups: true pins: true diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt deleted file mode 100644 index 88c80273da91..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt +++ /dev/null @@ -1,13 +0,0 @@ -OMAP Pinctrl definitions - -Required properties: -- compatible : Should be one of: - "ti,omap2420-padconf" - OMAP2420 compatible pinctrl - "ti,omap2430-padconf" - OMAP2430 compatible pinctrl - "ti,omap3-padconf" - OMAP3 compatible pinctrl - "ti,omap4-padconf" - OMAP4 compatible pinctrl - "ti,omap5-padconf" - OMAP5 compatible pinctrl - "ti,dra7-padconf" - DRA7 compatible pinctrl - "ti,am437-padconf" - AM437x compatible pinctrl - -See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details. diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index 24ad0614e61b..01b6f2b57843 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -273,6 +273,10 @@ patternProperties: slew-rate: enum: [0, 1] + output-enable: + description: + This will internally disable the tri-state for MIO pins. + drive-strength: description: Selects the drive strength for MIO pins, in mA. diff --git a/arch/arm/boot/dts/st/ste-href520-tvk.dts b/arch/arm/boot/dts/st/ste-href520-tvk.dts index 4201547c5988..7f661f8f13ad 100644 --- a/arch/arm/boot/dts/st/ste-href520-tvk.dts +++ b/arch/arm/boot/dts/st/ste-href520-tvk.dts @@ -28,7 +28,7 @@ 2900000 0x0>; gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts index dfc933214c1a..a29e345a43d3 100644 --- a/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts +++ b/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts @@ -27,7 +27,7 @@ 2900000 0x0>; gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; - enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; enable-active-high; }; diff --git a/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts index 75506339a93c..1968bd143114 100644 --- a/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts +++ b/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts @@ -27,7 +27,7 @@ 2900000 0x0>; gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; - enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; diff --git a/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts index 52c56ed17ae6..7a5b6aa1db5b 100644 --- a/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts +++ b/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts @@ -29,7 +29,7 @@ 2900000 0x0>; gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts index 2db2f8be8b03..d5af3f375161 100644 --- a/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts +++ b/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts @@ -29,7 +29,7 @@ 2900000 0x0>; gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/ste-snowball.dts b/arch/arm/boot/dts/st/ste-snowball.dts index 9a3d6546399d..27c2ec51e732 100644 --- a/arch/arm/boot/dts/st/ste-snowball.dts +++ b/arch/arm/boot/dts/st/ste-snowball.dts @@ -229,7 +229,7 @@ /* GPIO228 SD_SEL */ gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; /* GPIO217 MMC_EN */ - enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 6d39faba7c3f..ff68b911b729 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/clock/g12a-aoclkc.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h> #include <dt-bindings/reset/amlogic,meson-g12a-reset.h> #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 8237aa1f05e9..7ca904f5acbb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -343,7 +343,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi index 86adc1423385..995ce10d5c81 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -201,7 +201,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index 42f30112b56a..0a6a12808568 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -325,7 +325,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index 276e95b34022..eed2a23047ca 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -380,7 +380,7 @@ compatible = "rockchip,rk818"; reg = <0x1c>; interrupt-parent = <&gpio_intc>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */ + interrupts = <IRQID_GPIOAO_7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */ #clock-cells = <1>; vcc1-supply = <&vdd_sys>; @@ -519,7 +519,7 @@ reg = <0x20>; interrupt-parent = <&gpio_intc>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */ + interrupts = <IRQID_GPIOAO_5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */ vcc1-supply = <&vdd_sys>; vcc2-supply = <&vdd_sys>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index 08fde513bac9..91c9769fda20 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -184,7 +184,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi index b40d2c1002c9..ac8b7178257e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi @@ -269,7 +269,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts index 7991fafed05c..9b2eb6e42651 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts @@ -99,7 +99,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index 17045ff81c69..62404743e62d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -45,7 +45,7 @@ linux,code = <BTN_1>; gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + interrupts = <IRQID_GPIOAO_3 IRQ_TYPE_EDGE_BOTH>; }; }; @@ -217,7 +217,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts index 85d7e7110596..e6e9410d40cb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts @@ -99,7 +99,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index cdb80e0a7718..1db2327bbd13 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -282,7 +282,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index cf4f78e6bd21..095579c55f18 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -53,7 +53,7 @@ linux,code = <BTN_0>; gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; - interrupts = <34 IRQ_TYPE_EDGE_BOTH>; + interrupts = <IRQID_GPIOH_6 IRQ_TYPE_EDGE_BOTH>; }; key-2 { @@ -61,7 +61,7 @@ linux,code = <BTN_1>; gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; - interrupts = <35 IRQ_TYPE_EDGE_BOTH>; + interrupts = <IRQID_GPIOH_7 IRQ_TYPE_EDGE_BOTH>; }; key-3 { @@ -69,7 +69,7 @@ linux,code = <BTN_2>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; + interrupts = <IRQID_GPIOAO_2 IRQ_TYPE_EDGE_BOTH>; }; key-mic-mute { @@ -78,7 +78,7 @@ linux,input-type = <EV_SW>; gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; - interrupts = <99 IRQ_TYPE_EDGE_BOTH>; + interrupts = <IRQID_GPIOE_2 IRQ_TYPE_EDGE_BOTH>; }; key-power { @@ -86,7 +86,7 @@ linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + interrupts = <IRQID_GPIOAO_3 IRQ_TYPE_EDGE_BOTH>; }; }; @@ -582,7 +582,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; interrupt-parent = <&gpio_intc>; - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <IRQID_GPIOX_18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wakeup"; shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; max-speed = <2000000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts index fda0630c235b..fc9b961133cd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts @@ -99,7 +99,7 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index eb9ad5ae393f..4cc1ac7f76ed 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -340,6 +340,8 @@ int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, static u32 pm_api_version; static u32 pm_tz_version; +static u32 pm_family_code; +static u32 pm_sub_family_code; int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) { @@ -406,6 +408,39 @@ int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) EXPORT_SYMBOL_GPL(zynqmp_pm_get_chipid); /** + * zynqmp_pm_get_family_info() - Get family info of platform + * @family: Returned family code value + * @subfamily: Returned sub-family code value + * + * Return: Returns status, either success or error+reason + */ +static int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 idcode; + int ret; + + /* Check is family or sub-family code already received */ + if (pm_family_code && pm_sub_family_code) { + *family = pm_family_code; + *subfamily = pm_sub_family_code; + return 0; + } + + ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload); + if (ret < 0) + return ret; + + idcode = ret_payload[1]; + pm_family_code = FIELD_GET(FAMILY_CODE_MASK, idcode); + pm_sub_family_code = FIELD_GET(SUB_FAMILY_CODE_MASK, idcode); + *family = pm_family_code; + *subfamily = pm_sub_family_code; + + return 0; +} + +/** * zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version * @version: Returned version value * @@ -1122,6 +1157,15 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_config); int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 value) { + int ret; + + if (pm_family_code == ZYNQMP_FAMILY_CODE && + param == PM_PINCTRL_CONFIG_TRI_STATE) { + ret = zynqmp_pm_feature(PM_PINCTRL_CONFIG_PARAM_SET); + if (ret < PM_PINCTRL_PARAM_SET_VERSION) + return -EOPNOTSUPP; + } + return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, pin, param, value, 0, NULL); } @@ -1920,6 +1964,11 @@ static int zynqmp_firmware_probe(struct platform_device *pdev) pr_info("%s Platform Management API v%d.%d\n", __func__, pm_api_version >> 16, pm_api_version & 0xFFFF); + /* Get the Family code and sub family code of platform */ + ret = zynqmp_pm_get_family_info(&pm_family_code, &pm_sub_family_code); + if (ret < 0) + return ret; + /* Check trustzone version number */ ret = zynqmp_pm_get_trustzone_version(&pm_tz_version); if (ret) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 57d57af1f624..7dfb7190580e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -355,17 +355,6 @@ config PINCTRL_OCELOT If conpiled as a module, the module name will be pinctrl-ocelot. -config PINCTRL_OXNAS - bool - depends on OF - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB - select OF_GPIO - select GPIOLIB_IRQCHIP - select MFD_SYSCON - config PINCTRL_PALMAS tristate "Pinctrl driver for the PALMAS Series MFD devices" depends on OF && MFD_PALMAS diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 482b391b5deb..dd6cda270294 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o -obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index cc3eb7409ab3..bc7bb9876e57 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -21,8 +21,8 @@ #include <linux/io.h> #include <linux/ioport.h> #include <linux/kernel.h> -#include <linux/of_device.h> -#include <linux/of_irq.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/seq_file.h> #include <linux/slab.h> @@ -891,10 +891,8 @@ static int iproc_gpio_probe(struct platform_device *pdev) } ret = gpiochip_add_data(gc, chip); - if (ret < 0) { - dev_err(dev, "unable to add GPIO chip\n"); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "unable to add GPIO chip\n"); if (!no_pinconf) { ret = iproc_gpio_register_pinconf(chip); diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 5045a7e57f1d..84af6aae36d1 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -15,12 +15,11 @@ #include <linux/io.h> #include <linux/ioport.h> #include <linux/kernel.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_irq.h> +#include <linux/of.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> #include <linux/slab.h> #include "../pinctrl-utils.h" @@ -686,10 +685,8 @@ static int nsp_gpio_probe(struct platform_device *pdev) } ret = devm_gpiochip_add_data(dev, gc, chip); - if (ret < 0) { - dev_err(dev, "unable to add GPIO chip\n"); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "unable to add GPIO chip\n"); ret = nsp_gpio_register_pinconf(chip); if (ret) { diff --git a/drivers/pinctrl/berlin/pinctrl-as370.c b/drivers/pinctrl/berlin/pinctrl-as370.c index 9dfdc275ee33..b631c14813a7 100644 --- a/drivers/pinctrl/berlin/pinctrl-as370.c +++ b/drivers/pinctrl/berlin/pinctrl-as370.c @@ -341,8 +341,7 @@ static int as370_pinctrl_probe(struct platform_device *pdev) if (!rmconfig) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 401886c81344..e9dc9638120a 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -205,6 +205,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin) { struct pin_desc *pindesc; + int error; pindesc = pin_desc_get(pctldev, pin->number); if (pindesc) { @@ -226,18 +227,25 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, } else { pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number); if (!pindesc->name) { - kfree(pindesc); - return -ENOMEM; + error = -ENOMEM; + goto failed; } pindesc->dynamic_name = true; } pindesc->drv_data = pin->drv_data; - radix_tree_insert(&pctldev->pin_desc_tree, pin->number, pindesc); + error = radix_tree_insert(&pctldev->pin_desc_tree, pin->number, pindesc); + if (error) + goto failed; + pr_debug("registered pin %d (%s) on %s\n", pin->number, pindesc->name, pctldev->desc->name); return 0; + +failed: + kfree(pindesc); + return error; } static int pinctrl_register_pins(struct pinctrl_dev *pctldev, @@ -633,7 +641,7 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name, int *pins, int num_pins, void *data) { struct group_desc *group; - int selector; + int selector, error; if (!name) return -EINVAL; @@ -653,7 +661,9 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name, group->num_pins = num_pins; group->data = data; - radix_tree_insert(&pctldev->pin_group_tree, selector, group); + error = radix_tree_insert(&pctldev->pin_group_tree, selector, group); + if (error) + return error; pctldev->num_groups++; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 93ffb5fc04e7..9bc16943014f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -14,7 +14,7 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/seq_file.h> #include <linux/slab.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index 3726c0ac2560..90c696046b38 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -15,7 +15,8 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <linux/seq_file.h> #include <linux/slab.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c index 144020764a4b..0404efbf2a86 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx23.c +++ b/drivers/pinctrl/freescale/pinctrl-imx23.c @@ -6,7 +6,8 @@ // Copyright 2012 Freescale Semiconductor, Inc. #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-mxs.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c index 51748da1668f..d2b0b6aad306 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx25.c +++ b/drivers/pinctrl/freescale/pinctrl-imx25.c @@ -14,8 +14,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c index 67e7105be4f3..1738df461235 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx27.c +++ b/drivers/pinctrl/freescale/pinctrl-imx27.c @@ -9,8 +9,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx1.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c index 13730dd193f1..eb847151713a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx28.c +++ b/drivers/pinctrl/freescale/pinctrl-imx28.c @@ -6,7 +6,8 @@ // Copyright 2012 Freescale Semiconductor, Inc. #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-mxs.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c index c8671ad5214c..1546517d8110 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx35.c +++ b/drivers/pinctrl/freescale/pinctrl-imx35.c @@ -12,8 +12,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c index a245b4011c00..9b044aee4f7c 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx50.c +++ b/drivers/pinctrl/freescale/pinctrl-imx50.c @@ -9,8 +9,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c index 307cf5fe4d15..e580c022bebe 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx51.c +++ b/drivers/pinctrl/freescale/pinctrl-imx51.c @@ -10,8 +10,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c index 02bf3bda69ac..1034192ab410 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx53.c +++ b/drivers/pinctrl/freescale/pinctrl-imx53.c @@ -10,8 +10,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c index 2b6d5141a477..09542fdcd405 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c @@ -8,8 +8,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c index a7507def26a9..ae5cec74a3e8 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6q.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c @@ -10,8 +10,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c index 236f3bf120c2..3111f50263f6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c @@ -8,8 +8,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sll.c b/drivers/pinctrl/freescale/pinctrl-imx6sll.c index dfefcecbe072..72a7214811ab 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sll.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sll.c @@ -7,8 +7,8 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c index b7b97c274dcc..aa76bc6d7402 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c @@ -8,8 +8,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c index 3b8747482e36..9cb02444f8aa 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c @@ -9,7 +9,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index 4126387344cb..8acf2b73aefa 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -9,7 +9,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c index 1915378d92b2..ba0ef1ea5722 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c @@ -8,9 +8,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c index f947b1d0d1aa..7dec709ebd9a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -8,10 +8,10 @@ #include <linux/firmware/imx/sci.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mm.c b/drivers/pinctrl/freescale/pinctrl-imx8mm.c index 39dc73281ce6..47d14902a01a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mm.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mm.c @@ -6,7 +6,7 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mq.c b/drivers/pinctrl/freescale/pinctrl-imx8mq.c index 3ed3c98bcedb..529eebe46298 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mq.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mq.c @@ -8,10 +8,10 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c index 0a0acc0038d0..37ef3229231b 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c @@ -10,10 +10,11 @@ #include <linux/firmware/imx/sci.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c index f8572597a54e..2e86ca9fc7ac 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c @@ -6,10 +6,10 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx93.c b/drivers/pinctrl/freescale/pinctrl-imx93.c index 91b3ee1e6fa9..5977dda3b759 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx93.c +++ b/drivers/pinctrl/freescale/pinctrl-imx93.c @@ -6,10 +6,10 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c index def683839ebe..f6435227d4fb 100644 --- a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c @@ -6,7 +6,7 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c b/drivers/pinctrl/freescale/pinctrl-imxrt1170.c index 5da1545fde91..d8857f329e25 100644 --- a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1170.c @@ -6,7 +6,7 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index 700e5a136814..76adcc5abdec 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -7,8 +7,8 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-imx.h" diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index b3ec00624416..d66f4f6932d8 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -1,11 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 # Intel pin control drivers menu "Intel pinctrl drivers" - depends on X86 || COMPILE_TEST + depends on ACPI && (X86 || COMPILE_TEST) config PINCTRL_BAYTRAIL bool "Intel Baytrail GPIO pin control" - depends on ACPI select PINCTRL_INTEL help driver for memory mapped GPIO functionality on Intel Baytrail @@ -17,7 +16,6 @@ config PINCTRL_BAYTRAIL config PINCTRL_CHERRYVIEW tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help Cherryview/Braswell pinctrl driver provides an interface that @@ -25,39 +23,12 @@ config PINCTRL_CHERRYVIEW config PINCTRL_LYNXPOINT tristate "Intel Lynxpoint pinctrl and GPIO driver" - depends on ACPI - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB - select GPIOLIB_IRQCHIP + select PINCTRL_INTEL help Lynxpoint is the PCH of Intel Haswell. This pinctrl driver provides an interface that allows configuring of PCH pins and using them as GPIOs. -config PINCTRL_MERRIFIELD - tristate "Intel Merrifield pinctrl driver" - depends on X86_INTEL_MID - select PINMUX - select PINCONF - select GENERIC_PINCONF - help - Merrifield Family-Level Interface Shim (FLIS) driver provides an - interface that allows configuring of SoC pins and using them as - GPIOs. - -config PINCTRL_MOOREFIELD - tristate "Intel Moorefield pinctrl driver" - depends on X86_INTEL_MID - select PINMUX - select PINCONF - select GENERIC_PINCONF - help - Moorefield Family-Level Interface Shim (FLIS) driver provides an - interface that allows configuring of SoC pins and using them as - GPIOs. - config PINCTRL_INTEL tristate select PINMUX @@ -68,7 +39,6 @@ config PINCTRL_INTEL config PINCTRL_ALDERLAKE tristate "Intel Alder Lake pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -76,7 +46,6 @@ config PINCTRL_ALDERLAKE config PINCTRL_BROXTON tristate "Intel Broxton pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help Broxton pinctrl driver provides an interface that allows @@ -84,7 +53,6 @@ config PINCTRL_BROXTON config PINCTRL_CANNONLAKE tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -92,7 +60,6 @@ config PINCTRL_CANNONLAKE config PINCTRL_CEDARFORK tristate "Intel Cedar Fork pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -100,7 +67,6 @@ config PINCTRL_CEDARFORK config PINCTRL_DENVERTON tristate "Intel Denverton pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -108,7 +74,6 @@ config PINCTRL_DENVERTON config PINCTRL_ELKHARTLAKE tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -116,7 +81,6 @@ config PINCTRL_ELKHARTLAKE config PINCTRL_EMMITSBURG tristate "Intel Emmitsburg pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -124,7 +88,6 @@ config PINCTRL_EMMITSBURG config PINCTRL_GEMINILAKE tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -132,7 +95,6 @@ config PINCTRL_GEMINILAKE config PINCTRL_ICELAKE tristate "Intel Ice Lake PCH pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -140,7 +102,6 @@ config PINCTRL_ICELAKE config PINCTRL_JASPERLAKE tristate "Intel Jasper Lake PCH pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -148,7 +109,6 @@ config PINCTRL_JASPERLAKE config PINCTRL_LAKEFIELD tristate "Intel Lakefield SoC pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -156,7 +116,6 @@ config PINCTRL_LAKEFIELD config PINCTRL_LEWISBURG tristate "Intel Lewisburg pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -164,7 +123,6 @@ config PINCTRL_LEWISBURG config PINCTRL_METEORLAKE tristate "Intel Meteor Lake pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -172,7 +130,6 @@ config PINCTRL_METEORLAKE config PINCTRL_SUNRISEPOINT tristate "Intel Sunrisepoint pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver @@ -181,10 +138,10 @@ config PINCTRL_SUNRISEPOINT config PINCTRL_TIGERLAKE tristate "Intel Tiger Lake pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring of Intel Tiger Lake PCH pins and using them as GPIOs. +source "drivers/pinctrl/intel/Kconfig.tng" endmenu diff --git a/drivers/pinctrl/intel/Kconfig.tng b/drivers/pinctrl/intel/Kconfig.tng new file mode 100644 index 000000000000..6f88a64d260c --- /dev/null +++ b/drivers/pinctrl/intel/Kconfig.tng @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Intel Tangier and compatible pin control drivers + +if X86_INTEL_MID || COMPILE_TEST + +config PINCTRL_TANGIER + tristate + select PINMUX + select PINCONF + select GENERIC_PINCONF + help + This is a library driver for Intel Tangier pin controller and to + be selected and used by respective compatible platform drivers. + + If built as a module its name will be pinctrl-tangier. + +config PINCTRL_MERRIFIELD + tristate "Intel Merrifield pinctrl driver" + select PINCTRL_TANGIER + help + Intel Merrifield Family-Level Interface Shim (FLIS) driver provides + an interface that allows configuring of SoC pins and using them as + GPIOs. + +config PINCTRL_MOOREFIELD + tristate "Intel Moorefield pinctrl driver" + select PINCTRL_TANGIER + help + Intel Moorefield Family-Level Interface Shim (FLIS) driver provides + an interface that allows configuring of SoC pins and using them as + GPIOs. + +endif diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 906dd6c8d837..f6d30f2d973a 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o +obj-$(CONFIG_PINCTRL_TANGIER) += pinctrl-tangier.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c index 55bbfd647ba4..4a37dc273d63 100644 --- a/drivers/pinctrl/intel/pinctrl-alderlake.c +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -748,3 +748,4 @@ module_platform_driver(adl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 27aef62fc7c0..faa8b7ff5bcf 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -13,6 +13,7 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/module.h> #include <linux/types.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> @@ -551,25 +552,10 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = { static DEFINE_RAW_SPINLOCK(byt_lock); -static struct intel_community *byt_get_community(struct intel_pinctrl *vg, - unsigned int pin) -{ - struct intel_community *comm; - int i; - - for (i = 0; i < vg->ncommunities; i++) { - comm = vg->communities + i; - if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) - return comm; - } - - return NULL; -} - static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, int reg) { - struct intel_community *comm = byt_get_community(vg, offset); + struct intel_community *comm = intel_get_community(vg, offset); u32 reg_offset; if (!comm) @@ -591,68 +577,12 @@ static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, return comm->pad_regs + reg_offset + reg; } -static int byt_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - return vg->soc->ngroups; -} - -static const char *byt_get_group_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - return vg->soc->groups[selector].grp.name; -} - -static int byt_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int selector, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - *pins = vg->soc->groups[selector].grp.pins; - *num_pins = vg->soc->groups[selector].grp.npins; - - return 0; -} - static const struct pinctrl_ops byt_pinctrl_ops = { - .get_groups_count = byt_get_groups_count, - .get_group_name = byt_get_group_name, - .get_group_pins = byt_get_group_pins, + .get_groups_count = intel_get_groups_count, + .get_group_name = intel_get_group_name, + .get_group_pins = intel_get_group_pins, }; -static int byt_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - return vg->soc->nfunctions; -} - -static const char *byt_get_function_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - return vg->soc->functions[selector].func.name; -} - -static int byt_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int selector, - const char * const **groups, - unsigned int *ngroups) -{ - struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - - *groups = vg->soc->functions[selector].func.groups; - *ngroups = vg->soc->functions[selector].func.ngroups; - - return 0; -} - static void byt_set_group_simple_mux(struct intel_pinctrl *vg, const struct intel_pingroup group, unsigned int func) @@ -851,9 +781,9 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, } static const struct pinmux_ops byt_pinmux_ops = { - .get_functions_count = byt_get_functions_count, - .get_function_name = byt_get_function_name, - .get_function_groups = byt_get_function_groups, + .get_functions_count = intel_get_functions_count, + .get_function_name = intel_get_function_name, + .get_function_groups = intel_get_function_groups, .set_mux = byt_set_mux, .gpio_request_enable = byt_gpio_request_enable, .gpio_disable_free = byt_gpio_disable_free, @@ -995,8 +925,8 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); + u32 conf, val, db_pulse, debounce; unsigned long flags; - u32 conf, val, debounce; int i, ret = 0; raw_spin_lock_irqsave(&byt_lock, flags); @@ -1053,8 +983,6 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, break; case PIN_CONFIG_INPUT_DEBOUNCE: - debounce = readl(db_reg); - if (arg) conf |= BYT_DEBOUNCE_EN; else @@ -1062,32 +990,25 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, switch (arg) { case 375: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_375US; + db_pulse = BYT_DEBOUNCE_PULSE_375US; break; case 750: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_750US; + db_pulse = BYT_DEBOUNCE_PULSE_750US; break; case 1500: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_1500US; + db_pulse = BYT_DEBOUNCE_PULSE_1500US; break; case 3000: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_3MS; + db_pulse = BYT_DEBOUNCE_PULSE_3MS; break; case 6000: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_6MS; + db_pulse = BYT_DEBOUNCE_PULSE_6MS; break; case 12000: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_12MS; + db_pulse = BYT_DEBOUNCE_PULSE_12MS; break; case 24000: - debounce &= ~BYT_DEBOUNCE_PULSE_MASK; - debounce |= BYT_DEBOUNCE_PULSE_24MS; + db_pulse = BYT_DEBOUNCE_PULSE_24MS; break; default: if (arg) @@ -1095,8 +1016,13 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, break; } - if (!ret) - writel(debounce, db_reg); + if (ret) + break; + + debounce = readl(db_reg); + debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse; + writel(debounce, db_reg); + break; default: ret = -ENOTSUPP; @@ -1265,7 +1191,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) val = readl(val_reg); raw_spin_unlock_irqrestore(&byt_lock, flags); - comm = byt_get_community(vg, pin); + comm = intel_get_community(vg, pin); if (!comm) { seq_printf(s, "Pin %i: can't retrieve community\n", pin); continue; @@ -1733,7 +1659,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM_SLEEP static int byt_gpio_suspend(struct device *dev) { struct intel_pinctrl *vg = dev_get_drvdata(dev); @@ -1817,9 +1742,7 @@ static int byt_gpio_resume(struct device *dev) raw_spin_unlock_irqrestore(&byt_lock, flags); return 0; } -#endif -#ifdef CONFIG_PM static int byt_gpio_runtime_suspend(struct device *dev) { return 0; @@ -1829,19 +1752,17 @@ static int byt_gpio_runtime_resume(struct device *dev) { return 0; } -#endif static const struct dev_pm_ops byt_gpio_pm_ops = { - SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) - SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, - NULL) + LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) + RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL) }; static struct platform_driver byt_gpio_driver = { .probe = byt_pinctrl_probe, .driver = { .name = "byt_gpio", - .pm = &byt_gpio_pm_ops, + .pm = pm_ptr(&byt_gpio_pm_ops), .acpi_match_table = byt_gpio_acpi_match, .suppress_bind_attrs = true, }, @@ -1852,3 +1773,5 @@ static int __init byt_gpio_init(void) return platform_driver_register(&byt_gpio_driver); } subsys_initcall(byt_gpio_init); + +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c index 77e921b2178d..4d5ddb297909 100644 --- a/drivers/pinctrl/intel/pinctrl-broxton.c +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -1028,3 +1028,4 @@ MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:apollolake-pinctrl"); MODULE_ALIAS("platform:broxton-pinctrl"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index 88142ec57b25..95976abfb785 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -834,9 +834,9 @@ static struct platform_driver cnl_pinctrl_driver = { .pm = &cnl_pinctrl_pm_ops, }, }; - module_platform_driver(cnl_pinctrl_driver); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c index 2ab52b1fbc59..a20465eb2dc6 100644 --- a/drivers/pinctrl/intel/pinctrl-cedarfork.c +++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c @@ -351,3 +351,4 @@ module_exit(cdf_pinctrl_exit); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index eee0f9bc3d32..81ee949b946d 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -617,31 +617,6 @@ static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK; } -static int chv_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->ngroups; -} - -static const char *chv_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->groups[group].grp.name; -} - -static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, - const unsigned int **pins, unsigned int *npins) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *pins = pctrl->soc->groups[group].grp.pins; - *npins = pctrl->soc->groups[group].grp.npins; - return 0; -} - static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int offset) { @@ -676,39 +651,12 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, } static const struct pinctrl_ops chv_pinctrl_ops = { - .get_groups_count = chv_get_groups_count, - .get_group_name = chv_get_group_name, - .get_group_pins = chv_get_group_pins, + .get_groups_count = intel_get_groups_count, + .get_group_name = intel_get_group_name, + .get_group_pins = intel_get_group_pins, .pin_dbg_show = chv_pin_dbg_show, }; -static int chv_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->nfunctions; -} - -static const char *chv_get_function_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->functions[function].func.name; -} - -static int chv_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const ngroups) -{ - struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctrl->soc->functions[function].func.groups; - *ngroups = pctrl->soc->functions[function].func.ngroups; - return 0; -} - static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { @@ -884,9 +832,9 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, } static const struct pinmux_ops chv_pinmux_ops = { - .get_functions_count = chv_get_functions_count, - .get_function_name = chv_get_function_name, - .get_function_groups = chv_get_function_groups, + .get_functions_count = intel_get_functions_count, + .get_function_name = intel_get_function_name, + .get_function_groups = intel_get_function_groups, .set_mux = chv_pinmux_set_mux, .gpio_request_enable = chv_gpio_request_enable, .gpio_disable_free = chv_gpio_disable_free, @@ -1118,7 +1066,7 @@ static int chv_config_group_get(struct pinctrl_dev *pctldev, unsigned int npins; int ret; - ret = chv_get_group_pins(pctldev, group, &pins, &npins); + ret = intel_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; @@ -1137,7 +1085,7 @@ static int chv_config_group_set(struct pinctrl_dev *pctldev, unsigned int npins; int i, ret; - ret = chv_get_group_pins(pctldev, group, &pins, &npins); + ret = intel_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; @@ -1701,7 +1649,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev) struct intel_community_context *cctx; struct intel_community *community; struct device *dev = &pdev->dev; - struct acpi_device *adev = ACPI_COMPANION(dev); struct intel_pinctrl *pctrl; acpi_status status; unsigned int i; @@ -1769,7 +1716,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev) if (ret) return ret; - status = acpi_install_address_space_handler(adev->handle, + status = acpi_install_address_space_handler(ACPI_HANDLE(dev), community->acpi_space_id, chv_pinctrl_mmio_access_handler, NULL, pctrl); @@ -1786,14 +1733,13 @@ static int chv_pinctrl_remove(struct platform_device *pdev) struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); const struct intel_community *community = &pctrl->communities[0]; - acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), + acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev), community->acpi_space_id, chv_pinctrl_mmio_access_handler); return 0; } -#ifdef CONFIG_PM_SLEEP static int chv_pinctrl_suspend_noirq(struct device *dev) { struct intel_pinctrl *pctrl = dev_get_drvdata(dev); @@ -1877,12 +1823,9 @@ static int chv_pinctrl_resume_noirq(struct device *dev) return 0; } -#endif -static const struct dev_pm_ops chv_pinctrl_pm_ops = { - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, - chv_pinctrl_resume_noirq) -}; +static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops, + chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq); static const struct acpi_device_id chv_pinctrl_acpi_match[] = { { "INT33FF", (kernel_ulong_t)chv_soc_data }, @@ -1895,7 +1838,7 @@ static struct platform_driver chv_pinctrl_driver = { .remove = chv_pinctrl_remove, .driver = { .name = "cherryview-pinctrl", - .pm = &chv_pinctrl_pm_ops, + .pm = pm_sleep_ptr(&chv_pinctrl_pm_ops), .acpi_match_table = chv_pinctrl_acpi_match, }, }; @@ -1915,3 +1858,4 @@ module_exit(chv_pinctrl_exit); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c index c1a9db091c6e..0c4694cfa594 100644 --- a/drivers/pinctrl/intel/pinctrl-denverton.c +++ b/drivers/pinctrl/intel/pinctrl-denverton.c @@ -281,3 +281,4 @@ module_exit(dnv_pinctrl_exit); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c index 64b1997df0be..81581ab85316 100644 --- a/drivers/pinctrl/intel/pinctrl-elkhartlake.c +++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c @@ -495,9 +495,9 @@ static struct platform_driver ehl_pinctrl_driver = { .pm = &ehl_pinctrl_pm_ops, }, }; - module_platform_driver(ehl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-emmitsburg.c b/drivers/pinctrl/intel/pinctrl-emmitsburg.c index cc8f0baabc91..099ec8351d5f 100644 --- a/drivers/pinctrl/intel/pinctrl-emmitsburg.c +++ b/drivers/pinctrl/intel/pinctrl-emmitsburg.c @@ -368,9 +368,9 @@ static struct platform_driver ebg_pinctrl_driver = { .pm = &ebg_pinctrl_pm_ops, }, }; - module_platform_driver(ebg_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_DESCRIPTION("Intel Emmitsburg PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-geminilake.c b/drivers/pinctrl/intel/pinctrl-geminilake.c index 918cc9f261cf..9effa06b61e9 100644 --- a/drivers/pinctrl/intel/pinctrl-geminilake.c +++ b/drivers/pinctrl/intel/pinctrl-geminilake.c @@ -473,3 +473,4 @@ module_exit(glk_pinctrl_exit); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 1c64b4a1c491..300e1538c8d0 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -685,10 +685,10 @@ static struct platform_driver icl_pinctrl_driver = { .pm = &icl_pinctrl_pm_ops, }, }; - module_platform_driver(icl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 64c3e62b4348..3be04ab760d3 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -107,8 +107,7 @@ struct intel_community_context { #define pin_to_padno(c, p) ((p) - (c)->pin_base) #define padgroup_offset(g, p) ((p) - (g)->base) -static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, - unsigned int pin) +struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin) { struct intel_community *community; int i; @@ -123,6 +122,7 @@ static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); return NULL; } +EXPORT_SYMBOL_NS_GPL(intel_get_community, PINCTRL_INTEL); static const struct intel_padgroup * intel_community_get_padgroup(const struct intel_community *community, @@ -276,23 +276,24 @@ static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); } -static int intel_get_groups_count(struct pinctrl_dev *pctldev) +int intel_get_groups_count(struct pinctrl_dev *pctldev) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->ngroups; } +EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, PINCTRL_INTEL); -static const char *intel_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) +const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->groups[group].grp.name; } +EXPORT_SYMBOL_NS_GPL(intel_get_group_name, PINCTRL_INTEL); -static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, - const unsigned int **pins, unsigned int *npins) +int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -300,6 +301,7 @@ static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, *npins = pctrl->soc->groups[group].grp.npins; return 0; } +EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, PINCTRL_INTEL); static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) @@ -359,25 +361,24 @@ static const struct pinctrl_ops intel_pinctrl_ops = { .pin_dbg_show = intel_pin_dbg_show, }; -static int intel_get_functions_count(struct pinctrl_dev *pctldev) +int intel_get_functions_count(struct pinctrl_dev *pctldev) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->nfunctions; } +EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, PINCTRL_INTEL); -static const char *intel_get_function_name(struct pinctrl_dev *pctldev, - unsigned int function) +const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->functions[function].func.name; } +EXPORT_SYMBOL_NS_GPL(intel_get_function_name, PINCTRL_INTEL); -static int intel_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const ngroups) +int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, + const char * const **groups, unsigned int * const ngroups) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -385,6 +386,7 @@ static int intel_get_function_groups(struct pinctrl_dev *pctldev, *ngroups = pctrl->soc->functions[function].func.ngroups; return 0; } +EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, PINCTRL_INTEL); static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) @@ -1666,7 +1668,7 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev) return intel_pinctrl_probe(pdev, data); } -EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); +EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, PINCTRL_INTEL); int intel_pinctrl_probe_by_uid(struct platform_device *pdev) { @@ -1678,7 +1680,7 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev) return intel_pinctrl_probe(pdev, data); } -EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); +EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, PINCTRL_INTEL); const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) { @@ -1710,7 +1712,7 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_ return data ?: ERR_PTR(-ENODATA); } -EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); +EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL); #ifdef CONFIG_PM_SLEEP static bool __intel_gpio_is_direct_irq(u32 value) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 1faf2ada480a..cee512f97b56 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -266,4 +266,16 @@ const struct dev_pm_ops _name = { \ intel_pinctrl_resume_noirq) \ } +struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin); + +int intel_get_groups_count(struct pinctrl_dev *pctldev); +const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group); +int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins); + +int intel_get_functions_count(struct pinctrl_dev *pctldev); +const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function); +int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, + const char * const **groups, unsigned int * const ngroups); + #endif /* PINCTRL_INTEL_H */ diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c index 086ab7fe08dd..50f137deed9c 100644 --- a/drivers/pinctrl/intel/pinctrl-jasperlake.c +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -341,3 +341,4 @@ module_platform_driver(jsl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-lakefield.c b/drivers/pinctrl/intel/pinctrl-lakefield.c index 8dac2d6012b1..0b94e11b78ac 100644 --- a/drivers/pinctrl/intel/pinctrl-lakefield.c +++ b/drivers/pinctrl/intel/pinctrl-lakefield.c @@ -362,3 +362,4 @@ module_platform_driver(lkf_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_DESCRIPTION("Intel Lakefield PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-lewisburg.c b/drivers/pinctrl/intel/pinctrl-lewisburg.c index 7aac1bbde2e9..aa725a5d62b9 100644 --- a/drivers/pinctrl/intel/pinctrl-lewisburg.c +++ b/drivers/pinctrl/intel/pinctrl-lewisburg.c @@ -317,9 +317,9 @@ static struct platform_driver lbg_pinctrl_driver = { .pm = &lbg_pinctrl_pm_ops, }, }; - module_platform_driver(lbg_pinctrl_driver); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Lewisburg pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index cdace55aaeac..c3732a9f0658 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -206,21 +206,6 @@ static const struct intel_pinctrl_soc_data lptlp_soc_data = { * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. */ -static struct intel_community *lp_get_community(struct intel_pinctrl *lg, - unsigned int pin) -{ - struct intel_community *comm; - int i; - - for (i = 0; i < lg->ncommunities; i++) { - comm = &lg->communities[i]; - if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) - return comm; - } - - return NULL; -} - static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, int reg) { @@ -228,7 +213,7 @@ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, struct intel_community *comm; int reg_offset; - comm = lp_get_community(lg, offset); + comm = intel_get_community(lg, offset); if (!comm) return NULL; @@ -272,34 +257,6 @@ static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) return false; } -static int lp_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - return lg->soc->ngroups; -} - -static const char *lp_get_group_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - return lg->soc->groups[selector].grp.name; -} - -static int lp_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int selector, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - *pins = lg->soc->groups[selector].grp.pins; - *num_pins = lg->soc->groups[selector].grp.npins; - - return 0; -} - static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) { @@ -323,40 +280,12 @@ static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, } static const struct pinctrl_ops lptlp_pinctrl_ops = { - .get_groups_count = lp_get_groups_count, - .get_group_name = lp_get_group_name, - .get_group_pins = lp_get_group_pins, + .get_groups_count = intel_get_groups_count, + .get_group_name = intel_get_group_name, + .get_group_pins = intel_get_group_pins, .pin_dbg_show = lp_pin_dbg_show, }; -static int lp_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - return lg->soc->nfunctions; -} - -static const char *lp_get_function_name(struct pinctrl_dev *pctldev, - unsigned int selector) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - return lg->soc->functions[selector].func.name; -} - -static int lp_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int selector, - const char * const **groups, - unsigned int *ngroups) -{ - struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - - *groups = lg->soc->functions[selector].func.groups; - *ngroups = lg->soc->functions[selector].func.ngroups; - - return 0; -} - static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { @@ -481,9 +410,9 @@ static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, } static const struct pinmux_ops lptlp_pinmux_ops = { - .get_functions_count = lp_get_functions_count, - .get_function_name = lp_get_function_name, - .get_function_groups = lp_get_function_groups, + .get_functions_count = intel_get_functions_count, + .get_function_name = intel_get_function_name, + .get_function_groups = intel_get_function_groups, .set_mux = lp_pinmux_set_mux, .gpio_request_enable = lp_gpio_request_enable, .gpio_disable_free = lp_gpio_disable_free, @@ -948,9 +877,8 @@ static int lp_gpio_resume(struct device *dev) } static const struct dev_pm_ops lp_gpio_pm_ops = { - .runtime_suspend = lp_gpio_runtime_suspend, - .runtime_resume = lp_gpio_runtime_resume, - .resume = lp_gpio_resume, + SYSTEM_SLEEP_PM_OPS(NULL, lp_gpio_resume) + RUNTIME_PM_OPS(lp_gpio_runtime_suspend, lp_gpio_runtime_resume, NULL) }; static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { @@ -965,7 +893,7 @@ static struct platform_driver lp_gpio_driver = { .remove = lp_gpio_remove, .driver = { .name = "lp_gpio", - .pm = &lp_gpio_pm_ops, + .pm = pm_ptr(&lp_gpio_pm_ops), .acpi_match_table = lynxpoint_gpio_acpi_match, }, }; @@ -987,3 +915,4 @@ MODULE_AUTHOR("Andy Shevchenko (Intel)"); MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:lp_gpio"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index fb6de38b1c50..d809680a09c9 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -6,85 +6,17 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/bits.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/module.h> +#include <linux/init.h> +#include <linux/kernel.h> #include <linux/mod_devicetable.h> +#include <linux/module.h> #include <linux/platform_device.h> -#include <linux/seq_file.h> +#include <linux/types.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> #include "pinctrl-intel.h" - -#define MRFLD_FAMILY_NR 64 -#define MRFLD_FAMILY_LEN 0x400 - -#define SLEW_OFFSET 0x000 -#define BUFCFG_OFFSET 0x100 -#define MISC_OFFSET 0x300 - -#define BUFCFG_PINMODE_SHIFT 0 -#define BUFCFG_PINMODE_MASK GENMASK(2, 0) -#define BUFCFG_PINMODE_GPIO 0 -#define BUFCFG_PUPD_VAL_SHIFT 4 -#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) -#define BUFCFG_PUPD_VAL_2K 0 -#define BUFCFG_PUPD_VAL_20K 1 -#define BUFCFG_PUPD_VAL_50K 2 -#define BUFCFG_PUPD_VAL_910 3 -#define BUFCFG_PU_EN BIT(8) -#define BUFCFG_PD_EN BIT(9) -#define BUFCFG_Px_EN_MASK GENMASK(9, 8) -#define BUFCFG_SLEWSEL BIT(10) -#define BUFCFG_OVINEN BIT(12) -#define BUFCFG_OVINEN_EN BIT(13) -#define BUFCFG_OVINEN_MASK GENMASK(13, 12) -#define BUFCFG_OVOUTEN BIT(14) -#define BUFCFG_OVOUTEN_EN BIT(15) -#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) -#define BUFCFG_INDATAOV_VAL BIT(16) -#define BUFCFG_INDATAOV_EN BIT(17) -#define BUFCFG_INDATAOV_MASK GENMASK(17, 16) -#define BUFCFG_OUTDATAOV_VAL BIT(18) -#define BUFCFG_OUTDATAOV_EN BIT(19) -#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) -#define BUFCFG_OD_EN BIT(21) - -/** - * struct mrfld_family - Intel pin family description - * @barno: MMIO BAR number where registers for this family reside - * @pin_base: Starting pin of pins in this family - * @npins: Number of pins in this family - * @protected: True if family is protected by access - * @regs: family specific common registers - */ -struct mrfld_family { - unsigned int barno; - unsigned int pin_base; - size_t npins; - bool protected; - void __iomem *regs; -}; - -#define MRFLD_FAMILY(b, s, e) \ - { \ - .barno = (b), \ - .pin_base = (s), \ - .npins = (e) - (s) + 1, \ - } - -#define MRFLD_FAMILY_PROTECTED(b, s, e) \ - { \ - .barno = (b), \ - .pin_base = (s), \ - .npins = (e) - (s) + 1, \ - .protected = true, \ - } +#include "pinctrl-tangier.h" static const struct pinctrl_pin_desc mrfld_pins[] = { /* Family 0: OCP2SSC (0 pins) */ @@ -389,587 +321,43 @@ static const struct intel_function mrfld_functions[] = { FUNCTION("pwm3", mrfld_pwm3_groups), }; -static const struct mrfld_family mrfld_families[] = { - MRFLD_FAMILY(1, 0, 12), - MRFLD_FAMILY(2, 13, 36), - MRFLD_FAMILY(3, 37, 56), - MRFLD_FAMILY(4, 57, 64), - MRFLD_FAMILY(5, 65, 78), - MRFLD_FAMILY(6, 79, 100), - MRFLD_FAMILY_PROTECTED(7, 101, 114), - MRFLD_FAMILY(8, 115, 126), - MRFLD_FAMILY(9, 127, 145), - MRFLD_FAMILY(10, 146, 157), - MRFLD_FAMILY(11, 158, 179), - MRFLD_FAMILY_PROTECTED(12, 180, 194), - MRFLD_FAMILY(13, 195, 214), - MRFLD_FAMILY(14, 215, 227), - MRFLD_FAMILY(15, 228, 232), +static const struct tng_family mrfld_families[] = { + TNG_FAMILY(1, 0, 12), + TNG_FAMILY(2, 13, 36), + TNG_FAMILY(3, 37, 56), + TNG_FAMILY(4, 57, 64), + TNG_FAMILY(5, 65, 78), + TNG_FAMILY(6, 79, 100), + TNG_FAMILY_PROTECTED(7, 101, 114), + TNG_FAMILY(8, 115, 126), + TNG_FAMILY(9, 127, 145), + TNG_FAMILY(10, 146, 157), + TNG_FAMILY(11, 158, 179), + TNG_FAMILY_PROTECTED(12, 180, 194), + TNG_FAMILY(13, 195, 214), + TNG_FAMILY(14, 215, 227), + TNG_FAMILY(15, 228, 232), }; -/** - * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure - * @dev: Pointer to the device structure - * @lock: Lock to serialize register access - * @pctldesc: Pin controller description - * @pctldev: Pointer to the pin controller device - * @families: Array of families this pinctrl handles - * @nfamilies: Number of families in the array - * @functions: Array of functions - * @nfunctions: Number of functions in the array - * @groups: Array of pin groups - * @ngroups: Number of groups in the array - * @pins: Array of pins this pinctrl controls - * @npins: Number of pins in the array - */ -struct mrfld_pinctrl { - struct device *dev; - raw_spinlock_t lock; - struct pinctrl_desc pctldesc; - struct pinctrl_dev *pctldev; - - /* Pin controller configuration */ - const struct mrfld_family *families; - size_t nfamilies; - const struct intel_function *functions; - size_t nfunctions; - const struct intel_pingroup *groups; - size_t ngroups; - const struct pinctrl_pin_desc *pins; - size_t npins; -}; - -#define pin_to_bufno(f, p) ((p) - (f)->pin_base) - -static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp, - unsigned int pin) -{ - const struct mrfld_family *family; - unsigned int i; - - for (i = 0; i < mp->nfamilies; i++) { - family = &mp->families[i]; - if (pin >= family->pin_base && - pin < family->pin_base + family->npins) - return family; - } - - dev_warn(mp->dev, "failed to find family for pin %u\n", pin); - return NULL; -} - -static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin) -{ - const struct mrfld_family *family; - - family = mrfld_get_family(mp, pin); - if (!family) - return false; - - return !family->protected; -} - -static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin) -{ - const struct mrfld_family *family; - unsigned int bufno; - - family = mrfld_get_family(mp, pin); - if (!family) - return NULL; - - bufno = pin_to_bufno(family, pin); - return family->regs + BUFCFG_OFFSET + bufno * 4; -} - -static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value) -{ - void __iomem *bufcfg; - - if (!mrfld_buf_available(mp, pin)) - return -EBUSY; - - bufcfg = mrfld_get_bufcfg(mp, pin); - *value = readl(bufcfg); - - return 0; -} - -static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, - u32 bits, u32 mask) -{ - void __iomem *bufcfg; - u32 value; - - bufcfg = mrfld_get_bufcfg(mp, pin); - value = readl(bufcfg); - - value &= ~mask; - value |= bits & mask; - - writel(value, bufcfg); -} - -static int mrfld_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->ngroups; -} - -static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->groups[group].grp.name; -} - -static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, - const unsigned int **pins, unsigned int *npins) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - *pins = mp->groups[group].grp.pins; - *npins = mp->groups[group].grp.npins; - return 0; -} - -static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned int pin) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - u32 value, mode; - int ret; - - ret = mrfld_read_bufcfg(mp, pin, &value); - if (ret) { - seq_puts(s, "not available"); - return; - } - - mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; - if (mode == BUFCFG_PINMODE_GPIO) - seq_puts(s, "GPIO "); - else - seq_printf(s, "mode %d ", mode); - - seq_printf(s, "0x%08x", value); -} - -static const struct pinctrl_ops mrfld_pinctrl_ops = { - .get_groups_count = mrfld_get_groups_count, - .get_group_name = mrfld_get_group_name, - .get_group_pins = mrfld_get_group_pins, - .pin_dbg_show = mrfld_pin_dbg_show, +static const struct tng_pinctrl mrfld_soc_data = { + .pins = mrfld_pins, + .npins = ARRAY_SIZE(mrfld_pins), + .groups = mrfld_groups, + .ngroups = ARRAY_SIZE(mrfld_groups), + .families = mrfld_families, + .nfamilies = ARRAY_SIZE(mrfld_families), + .functions = mrfld_functions, + .nfunctions = ARRAY_SIZE(mrfld_functions), }; -static int mrfld_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->nfunctions; -} - -static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->functions[function].func.name; -} - -static int mrfld_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const ngroups) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - *groups = mp->functions[function].func.groups; - *ngroups = mp->functions[function].func.ngroups; - return 0; -} - -static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev, - unsigned int function, - unsigned int group) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - const struct intel_pingroup *grp = &mp->groups[group]; - u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; - u32 mask = BUFCFG_PINMODE_MASK; - unsigned long flags; - unsigned int i; - - /* - * All pins in the groups needs to be accessible and writable - * before we can enable the mux for this group. - */ - for (i = 0; i < grp->grp.npins; i++) { - if (!mrfld_buf_available(mp, grp->grp.pins[i])) - return -EBUSY; - } - - /* Now enable the mux setting for each pin in the group */ - raw_spin_lock_irqsave(&mp->lock, flags); - for (i = 0; i < grp->grp.npins; i++) - mrfld_update_bufcfg(mp, grp->grp.pins[i], bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; - u32 mask = BUFCFG_PINMODE_MASK; - unsigned long flags; - - if (!mrfld_buf_available(mp, pin)) - return -EBUSY; - - raw_spin_lock_irqsave(&mp->lock, flags); - mrfld_update_bufcfg(mp, pin, bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static const struct pinmux_ops mrfld_pinmux_ops = { - .get_functions_count = mrfld_get_functions_count, - .get_function_name = mrfld_get_function_name, - .get_function_groups = mrfld_get_function_groups, - .set_mux = mrfld_pinmux_set_mux, - .gpio_request_enable = mrfld_gpio_request_enable, -}; - -static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *config) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - u32 value, term; - u16 arg = 0; - int ret; - - ret = mrfld_read_bufcfg(mp, pin, &value); - if (ret) - return -ENOTSUPP; - - term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - if (value & BUFCFG_Px_EN_MASK) - return -EINVAL; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) - return -EINVAL; - - switch (term) { - case BUFCFG_PUPD_VAL_910: - arg = 910; - break; - case BUFCFG_PUPD_VAL_2K: - arg = 2000; - break; - case BUFCFG_PUPD_VAL_20K: - arg = 20000; - break; - case BUFCFG_PUPD_VAL_50K: - arg = 50000; - break; - } - - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) - return -EINVAL; - - switch (term) { - case BUFCFG_PUPD_VAL_910: - arg = 910; - break; - case BUFCFG_PUPD_VAL_2K: - arg = 2000; - break; - case BUFCFG_PUPD_VAL_20K: - arg = 20000; - break; - case BUFCFG_PUPD_VAL_50K: - arg = 50000; - break; - } - - break; - - case PIN_CONFIG_DRIVE_PUSH_PULL: - if (value & BUFCFG_OD_EN) - return -EINVAL; - break; - - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (!(value & BUFCFG_OD_EN)) - return -EINVAL; - break; - - case PIN_CONFIG_SLEW_RATE: - if (!(value & BUFCFG_SLEWSEL)) - arg = 0; - else - arg = 1; - break; - - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - return 0; -} - -static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin, - unsigned long config) -{ - unsigned int param = pinconf_to_config_param(config); - unsigned int arg = pinconf_to_config_argument(config); - u32 bits = 0, mask = 0; - unsigned long flags; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - bits |= BUFCFG_PU_EN; - - /* Set default strength value in case none is given */ - if (arg == 1) - arg = 20000; - - switch (arg) { - case 50000: - bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 20000: - bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 2000: - bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; - break; - default: - return -EINVAL; - } - - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - bits |= BUFCFG_PD_EN; - - /* Set default strength value in case none is given */ - if (arg == 1) - arg = 20000; - - switch (arg) { - case 50000: - bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 20000: - bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 2000: - bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; - break; - default: - return -EINVAL; - } - - break; - - case PIN_CONFIG_DRIVE_PUSH_PULL: - mask |= BUFCFG_OD_EN; - bits &= ~BUFCFG_OD_EN; - break; - - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - mask |= BUFCFG_OD_EN; - bits |= BUFCFG_OD_EN; - break; - - case PIN_CONFIG_SLEW_RATE: - mask |= BUFCFG_SLEWSEL; - if (arg) - bits |= BUFCFG_SLEWSEL; - break; - } - - raw_spin_lock_irqsave(&mp->lock, flags); - mrfld_update_bufcfg(mp, pin, bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned int nconfigs) -{ - struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - unsigned int i; - int ret; - - if (!mrfld_buf_available(mp, pin)) - return -ENOTSUPP; - - for (i = 0; i < nconfigs; i++) { - switch (pinconf_to_config_param(configs[i])) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_DRIVE_PUSH_PULL: - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - case PIN_CONFIG_SLEW_RATE: - ret = mrfld_config_set_pin(mp, pin, configs[i]); - if (ret) - return ret; - break; - - default: - return -ENOTSUPP; - } - } - - return 0; -} - -static int mrfld_config_group_get(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long *config) -{ - const unsigned int *pins; - unsigned int npins; - int ret; - - ret = mrfld_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - - ret = mrfld_config_get(pctldev, pins[0], config); - if (ret) - return ret; - - return 0; -} - -static int mrfld_config_group_set(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long *configs, - unsigned int num_configs) -{ - const unsigned int *pins; - unsigned int npins; - int i, ret; - - ret = mrfld_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - - for (i = 0; i < npins; i++) { - ret = mrfld_config_set(pctldev, pins[i], configs, num_configs); - if (ret) - return ret; - } - - return 0; -} - -static const struct pinconf_ops mrfld_pinconf_ops = { - .is_generic = true, - .pin_config_get = mrfld_config_get, - .pin_config_set = mrfld_config_set, - .pin_config_group_get = mrfld_config_group_get, - .pin_config_group_set = mrfld_config_group_set, -}; - -static const struct pinctrl_desc mrfld_pinctrl_desc = { - .pctlops = &mrfld_pinctrl_ops, - .pmxops = &mrfld_pinmux_ops, - .confops = &mrfld_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int mrfld_pinctrl_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct mrfld_family *families; - struct mrfld_pinctrl *mp; - void __iomem *regs; - size_t nfamilies; - unsigned int i; - - mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); - if (!mp) - return -ENOMEM; - - mp->dev = dev; - raw_spin_lock_init(&mp->lock); - - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); - - /* - * Make a copy of the families which we can use to hold pointers - * to the registers. - */ - nfamilies = ARRAY_SIZE(mrfld_families), - families = devm_kmemdup(dev, mrfld_families, sizeof(mrfld_families), GFP_KERNEL); - if (!families) - return -ENOMEM; - - /* Splice memory resource by chunk per family */ - for (i = 0; i < nfamilies; i++) { - struct mrfld_family *family = &families[i]; - - family->regs = regs + family->barno * MRFLD_FAMILY_LEN; - } - - mp->families = families; - mp->nfamilies = nfamilies; - mp->functions = mrfld_functions; - mp->nfunctions = ARRAY_SIZE(mrfld_functions); - mp->groups = mrfld_groups; - mp->ngroups = ARRAY_SIZE(mrfld_groups); - mp->pctldesc = mrfld_pinctrl_desc; - mp->pctldesc.name = dev_name(dev); - mp->pctldesc.pins = mrfld_pins; - mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins); - - mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp); - if (IS_ERR(mp->pctldev)) { - dev_err(dev, "failed to register pinctrl driver\n"); - return PTR_ERR(mp->pctldev); - } - - platform_set_drvdata(pdev, mp); - return 0; -} - static const struct acpi_device_id mrfld_acpi_table[] = { - { "INTC1002" }, + { "INTC1002", (kernel_ulong_t)&mrfld_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table); static struct platform_driver mrfld_pinctrl_driver = { - .probe = mrfld_pinctrl_probe, + .probe = devm_tng_pinctrl_probe, .driver = { .name = "pinctrl-merrifield", .acpi_match_table = mrfld_acpi_table, @@ -992,3 +380,4 @@ MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:pinctrl-merrifield"); +MODULE_IMPORT_NS(PINCTRL_TANGIER); diff --git a/drivers/pinctrl/intel/pinctrl-meteorlake.c b/drivers/pinctrl/intel/pinctrl-meteorlake.c index 9a11f729bec8..7ced2b402dce 100644 --- a/drivers/pinctrl/intel/pinctrl-meteorlake.c +++ b/drivers/pinctrl/intel/pinctrl-meteorlake.c @@ -604,3 +604,4 @@ module_platform_driver(mtl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_DESCRIPTION("Intel Meteor Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-moorefield.c b/drivers/pinctrl/intel/pinctrl-moorefield.c index 2d38d953f360..807a694b818b 100644 --- a/drivers/pinctrl/intel/pinctrl-moorefield.c +++ b/drivers/pinctrl/intel/pinctrl-moorefield.c @@ -6,77 +6,16 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/bits.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/module.h> +#include <linux/init.h> +#include <linux/kernel.h> #include <linux/mod_devicetable.h> +#include <linux/module.h> #include <linux/platform_device.h> -#include <linux/seq_file.h> +#include <linux/types.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> - -#include "pinctrl-intel.h" - -#define MOFLD_FAMILY_NR 64 -#define MOFLD_FAMILY_LEN 0x400 - -#define SLEW_OFFSET 0x000 -#define BUFCFG_OFFSET 0x100 -#define MISC_OFFSET 0x300 -#define BUFCFG_PINMODE_SHIFT 0 -#define BUFCFG_PINMODE_MASK GENMASK(2, 0) -#define BUFCFG_PINMODE_GPIO 0 -#define BUFCFG_PUPD_VAL_SHIFT 4 -#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) -#define BUFCFG_PUPD_VAL_2K 0 -#define BUFCFG_PUPD_VAL_20K 1 -#define BUFCFG_PUPD_VAL_50K 2 -#define BUFCFG_PUPD_VAL_910 3 -#define BUFCFG_PU_EN BIT(8) -#define BUFCFG_PD_EN BIT(9) -#define BUFCFG_Px_EN_MASK GENMASK(9, 8) -#define BUFCFG_SLEWSEL BIT(10) -#define BUFCFG_OVINEN BIT(12) -#define BUFCFG_OVINEN_EN BIT(13) -#define BUFCFG_OVINEN_MASK GENMASK(13, 12) -#define BUFCFG_OVOUTEN BIT(14) -#define BUFCFG_OVOUTEN_EN BIT(15) -#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) -#define BUFCFG_INDATAOV_VAL BIT(16) -#define BUFCFG_INDATAOV_EN BIT(17) -#define BUFCFG_INDATAOV_MASK GENMASK(17, 16) -#define BUFCFG_OUTDATAOV_VAL BIT(18) -#define BUFCFG_OUTDATAOV_EN BIT(19) -#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) -#define BUFCFG_OD_EN BIT(21) - -/** - * struct mofld_family - Intel pin family description - * @barno: MMIO BAR number where registers for this family reside - * @pin_base: Starting pin of pins in this family - * @npins: Number of pins in this family - * @protected: True if family is protected by access - * @regs: family specific common registers - */ -struct mofld_family { - unsigned int barno; - unsigned int pin_base; - size_t npins; - bool protected; - void __iomem *regs; -}; - -#define MOFLD_FAMILY(b, s, e) \ - { \ - .barno = (b), \ - .pin_base = (s), \ - .npins = (e) - (s) + 1, \ - } +#include "pinctrl-tangier.h" static const struct pinctrl_pin_desc mofld_pins[] = { /* ULPI (13 pins) */ @@ -347,561 +286,39 @@ static const struct pinctrl_pin_desc mofld_pins[] = { PINCTRL_PIN(250, "JTAG_TRST"), }; -static const struct mofld_family mofld_families[] = { - MOFLD_FAMILY(0, 0, 12), - MOFLD_FAMILY(1, 13, 24), - MOFLD_FAMILY(2, 25, 44), - MOFLD_FAMILY(3, 45, 52), - MOFLD_FAMILY(4, 53, 66), - MOFLD_FAMILY(5, 67, 88), - MOFLD_FAMILY(6, 89, 108), - MOFLD_FAMILY(7, 109, 131), - MOFLD_FAMILY(8, 132, 151), - MOFLD_FAMILY(9, 152, 166), - MOFLD_FAMILY(10, 167, 180), - MOFLD_FAMILY(11, 181, 195), - MOFLD_FAMILY(12, 196, 215), - MOFLD_FAMILY(13, 216, 228), - MOFLD_FAMILY(14, 229, 250), -}; - -/** - * struct mofld_pinctrl - Intel Merrifield pinctrl private structure - * @dev: Pointer to the device structure - * @lock: Lock to serialize register access - * @pctldesc: Pin controller description - * @pctldev: Pointer to the pin controller device - * @families: Array of families this pinctrl handles - * @nfamilies: Number of families in the array - * @functions: Array of functions - * @nfunctions: Number of functions in the array - * @groups: Array of pin groups - * @ngroups: Number of groups in the array - * @pins: Array of pins this pinctrl controls - * @npins: Number of pins in the array - */ -struct mofld_pinctrl { - struct device *dev; - raw_spinlock_t lock; - struct pinctrl_desc pctldesc; - struct pinctrl_dev *pctldev; - - /* Pin controller configuration */ - const struct mofld_family *families; - size_t nfamilies; - const struct intel_function *functions; - size_t nfunctions; - const struct intel_pingroup *groups; - size_t ngroups; - const struct pinctrl_pin_desc *pins; - size_t npins; -}; - -#define pin_to_bufno(f, p) ((p) - (f)->pin_base) - -static const struct mofld_family *mofld_get_family(struct mofld_pinctrl *mp, unsigned int pin) -{ - const struct mofld_family *family; - unsigned int i; - - for (i = 0; i < mp->nfamilies; i++) { - family = &mp->families[i]; - if (pin >= family->pin_base && - pin < family->pin_base + family->npins) - return family; - } - - dev_warn(mp->dev, "failed to find family for pin %u\n", pin); - return NULL; -} - -static bool mofld_buf_available(struct mofld_pinctrl *mp, unsigned int pin) -{ - const struct mofld_family *family; - - family = mofld_get_family(mp, pin); - if (!family) - return false; - - return !family->protected; -} - -static void __iomem *mofld_get_bufcfg(struct mofld_pinctrl *mp, unsigned int pin) -{ - const struct mofld_family *family; - unsigned int bufno; - - family = mofld_get_family(mp, pin); - if (!family) - return NULL; - - bufno = pin_to_bufno(family, pin); - return family->regs + BUFCFG_OFFSET + bufno * 4; -} - -static int mofld_read_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 *value) -{ - void __iomem *bufcfg; - - if (!mofld_buf_available(mp, pin)) - return -EBUSY; - - bufcfg = mofld_get_bufcfg(mp, pin); - *value = readl(bufcfg); - - return 0; -} - -static void mofld_update_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 bits, u32 mask) -{ - void __iomem *bufcfg; - u32 value; - - bufcfg = mofld_get_bufcfg(mp, pin); - value = readl(bufcfg); - - value &= ~mask; - value |= bits & mask; - - writel(value, bufcfg); -} - -static int mofld_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->ngroups; -} - -static const char *mofld_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->groups[group].grp.name; -} - -static int mofld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, - const unsigned int **pins, unsigned int *npins) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - *pins = mp->groups[group].grp.pins; - *npins = mp->groups[group].grp.npins; - return 0; -} - -static void mofld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned int pin) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - u32 value, mode; - int ret; - - ret = mofld_read_bufcfg(mp, pin, &value); - if (ret) { - seq_puts(s, "not available"); - return; - } - - mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; - if (mode == BUFCFG_PINMODE_GPIO) - seq_puts(s, "GPIO "); - else - seq_printf(s, "mode %d ", mode); - - seq_printf(s, "0x%08x", value); -} - -static const struct pinctrl_ops mofld_pinctrl_ops = { - .get_groups_count = mofld_get_groups_count, - .get_group_name = mofld_get_group_name, - .get_group_pins = mofld_get_group_pins, - .pin_dbg_show = mofld_pin_dbg_show, -}; - -static int mofld_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->nfunctions; -} - -static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - return mp->functions[function].func.name; -} - -static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, - const char * const **groups, unsigned int * const ngroups) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - - *groups = mp->functions[function].func.groups; - *ngroups = mp->functions[function].func.ngroups; - return 0; -} - -static int mofld_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, - unsigned int group) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - const struct intel_pingroup *grp = &mp->groups[group]; - u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; - u32 mask = BUFCFG_PINMODE_MASK; - unsigned long flags; - unsigned int i; - - /* - * All pins in the groups needs to be accessible and writable - * before we can enable the mux for this group. - */ - for (i = 0; i < grp->grp.npins; i++) { - if (!mofld_buf_available(mp, grp->grp.pins[i])) - return -EBUSY; - } - - /* Now enable the mux setting for each pin in the group */ - raw_spin_lock_irqsave(&mp->lock, flags); - for (i = 0; i < grp->grp.npins; i++) - mofld_update_bufcfg(mp, grp->grp.pins[i], bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static int mofld_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; - u32 mask = BUFCFG_PINMODE_MASK; - unsigned long flags; - - if (!mofld_buf_available(mp, pin)) - return -EBUSY; - - raw_spin_lock_irqsave(&mp->lock, flags); - mofld_update_bufcfg(mp, pin, bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static const struct pinmux_ops mofld_pinmux_ops = { - .get_functions_count = mofld_get_functions_count, - .get_function_name = mofld_get_function_name, - .get_function_groups = mofld_get_function_groups, - .set_mux = mofld_pinmux_set_mux, - .gpio_request_enable = mofld_gpio_request_enable, -}; - -static int mofld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *config) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - u32 value, term; - u16 arg = 0; - int ret; - - ret = mofld_read_bufcfg(mp, pin, &value); - if (ret) - return -ENOTSUPP; - - term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - if (value & BUFCFG_Px_EN_MASK) - return -EINVAL; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) - return -EINVAL; - - switch (term) { - case BUFCFG_PUPD_VAL_910: - arg = 910; - break; - case BUFCFG_PUPD_VAL_2K: - arg = 2000; - break; - case BUFCFG_PUPD_VAL_20K: - arg = 20000; - break; - case BUFCFG_PUPD_VAL_50K: - arg = 50000; - break; - } - - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) - return -EINVAL; - - switch (term) { - case BUFCFG_PUPD_VAL_910: - arg = 910; - break; - case BUFCFG_PUPD_VAL_2K: - arg = 2000; - break; - case BUFCFG_PUPD_VAL_20K: - arg = 20000; - break; - case BUFCFG_PUPD_VAL_50K: - arg = 50000; - break; - } - - break; - - case PIN_CONFIG_DRIVE_PUSH_PULL: - if (value & BUFCFG_OD_EN) - return -EINVAL; - break; - - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (!(value & BUFCFG_OD_EN)) - return -EINVAL; - break; - - case PIN_CONFIG_SLEW_RATE: - if (!(value & BUFCFG_SLEWSEL)) - arg = 0; - else - arg = 1; - break; - - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - return 0; -} - -static int mofld_config_set_pin(struct mofld_pinctrl *mp, unsigned int pin, - unsigned long config) -{ - unsigned int param = pinconf_to_config_param(config); - unsigned int arg = pinconf_to_config_argument(config); - u32 bits = 0, mask = 0; - unsigned long flags; - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - break; - - case PIN_CONFIG_BIAS_PULL_UP: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - bits |= BUFCFG_PU_EN; - - switch (arg) { - case 50000: - bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 20000: - bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 2000: - bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; - break; - default: - return -EINVAL; - } - - break; - - case PIN_CONFIG_BIAS_PULL_DOWN: - mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; - bits |= BUFCFG_PD_EN; - - switch (arg) { - case 50000: - bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 20000: - bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; - break; - case 2000: - bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; - break; - default: - return -EINVAL; - } - - break; - - case PIN_CONFIG_DRIVE_PUSH_PULL: - mask |= BUFCFG_OD_EN; - bits &= ~BUFCFG_OD_EN; - break; - - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - mask |= BUFCFG_OD_EN; - bits |= BUFCFG_OD_EN; - break; - - case PIN_CONFIG_SLEW_RATE: - mask |= BUFCFG_SLEWSEL; - if (arg) - bits |= BUFCFG_SLEWSEL; - break; - } - - raw_spin_lock_irqsave(&mp->lock, flags); - mofld_update_bufcfg(mp, pin, bits, mask); - raw_spin_unlock_irqrestore(&mp->lock, flags); - - return 0; -} - -static int mofld_config_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned int nconfigs) -{ - struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - unsigned int i; - int ret; - - if (!mofld_buf_available(mp, pin)) - return -ENOTSUPP; - - for (i = 0; i < nconfigs; i++) { - switch (pinconf_to_config_param(configs[i])) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_DRIVE_PUSH_PULL: - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - case PIN_CONFIG_SLEW_RATE: - ret = mofld_config_set_pin(mp, pin, configs[i]); - if (ret) - return ret; - break; - - default: - return -ENOTSUPP; - } - } - - return 0; -} - -static int mofld_config_group_get(struct pinctrl_dev *pctldev, unsigned int group, - unsigned long *config) -{ - const unsigned int *pins; - unsigned int npins; - int ret; - - ret = mofld_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - - ret = mofld_config_get(pctldev, pins[0], config); - if (ret) - return ret; - - return 0; -} - -static int mofld_config_group_set(struct pinctrl_dev *pctldev, unsigned int group, - unsigned long *configs, unsigned int num_configs) -{ - const unsigned int *pins; - unsigned int npins; - int i, ret; - - ret = mofld_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - - for (i = 0; i < npins; i++) { - ret = mofld_config_set(pctldev, pins[i], configs, num_configs); - if (ret) - return ret; - } - - return 0; -} - -static const struct pinconf_ops mofld_pinconf_ops = { - .is_generic = true, - .pin_config_get = mofld_config_get, - .pin_config_set = mofld_config_set, - .pin_config_group_get = mofld_config_group_get, - .pin_config_group_set = mofld_config_group_set, +static const struct tng_family mofld_families[] = { + TNG_FAMILY(0, 0, 12), + TNG_FAMILY(1, 13, 24), + TNG_FAMILY(2, 25, 44), + TNG_FAMILY(3, 45, 52), + TNG_FAMILY(4, 53, 66), + TNG_FAMILY(5, 67, 88), + TNG_FAMILY(6, 89, 108), + TNG_FAMILY(7, 109, 131), + TNG_FAMILY(8, 132, 151), + TNG_FAMILY(9, 152, 166), + TNG_FAMILY(10, 167, 180), + TNG_FAMILY(11, 181, 195), + TNG_FAMILY(12, 196, 215), + TNG_FAMILY(13, 216, 228), + TNG_FAMILY(14, 229, 250), }; -static const struct pinctrl_desc mofld_pinctrl_desc = { - .pctlops = &mofld_pinctrl_ops, - .pmxops = &mofld_pinmux_ops, - .confops = &mofld_pinconf_ops, - .owner = THIS_MODULE, +static const struct tng_pinctrl mofld_soc_data = { + .pins = mofld_pins, + .npins = ARRAY_SIZE(mofld_pins), + .families = mofld_families, + .nfamilies = ARRAY_SIZE(mofld_families), }; -static int mofld_pinctrl_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct mofld_family *families; - struct mofld_pinctrl *mp; - void __iomem *regs; - size_t nfamilies; - unsigned int i; - - mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); - if (!mp) - return -ENOMEM; - - mp->dev = dev; - raw_spin_lock_init(&mp->lock); - - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); - - nfamilies = ARRAY_SIZE(mofld_families), - families = devm_kmemdup(dev, mofld_families, sizeof(mofld_families), GFP_KERNEL); - if (!families) - return -ENOMEM; - - /* Splice memory resource by chunk per family */ - for (i = 0; i < nfamilies; i++) { - struct mofld_family *family = &families[i]; - - family->regs = regs + family->barno * MOFLD_FAMILY_LEN; - } - - mp->families = families; - mp->nfamilies = nfamilies; - mp->pctldesc = mofld_pinctrl_desc; - mp->pctldesc.name = dev_name(dev); - mp->pctldesc.pins = mofld_pins; - mp->pctldesc.npins = ARRAY_SIZE(mofld_pins); - - mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp); - if (IS_ERR(mp->pctldev)) - return PTR_ERR(mp->pctldev); - - platform_set_drvdata(pdev, mp); - return 0; -} - static const struct acpi_device_id mofld_acpi_table[] = { - { "INTC1003" }, + { "INTC1003", (kernel_ulong_t)&mofld_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, mofld_acpi_table); static struct platform_driver mofld_pinctrl_driver = { - .probe = mofld_pinctrl_probe, + .probe = devm_tng_pinctrl_probe, .driver = { .name = "pinctrl-moorefield", .acpi_match_table = mofld_acpi_table, @@ -924,3 +341,4 @@ MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_DESCRIPTION("Intel Moorefield SoC pinctrl driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:pinctrl-moorefield"); +MODULE_IMPORT_NS(PINCTRL_TANGIER); diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index f91e27feb7c3..b7a40ab0bca8 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -606,3 +606,4 @@ MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/intel/pinctrl-tangier.c b/drivers/pinctrl/intel/pinctrl-tangier.c new file mode 100644 index 000000000000..40dd60c9e526 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-tangier.c @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Tangier pinctrl driver + * + * Copyright (C) 2016, 2023 Intel Corporation + * + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> + * Raag Jadav <raag.jadav@intel.com> + */ + +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/export.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/overflow.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "../core.h" +#include "pinctrl-intel.h" +#include "pinctrl-tangier.h" + +#define SLEW_OFFSET 0x000 +#define BUFCFG_OFFSET 0x100 +#define MISC_OFFSET 0x300 + +#define BUFCFG_PINMODE_SHIFT 0 +#define BUFCFG_PINMODE_MASK GENMASK(2, 0) +#define BUFCFG_PINMODE_GPIO 0 +#define BUFCFG_PUPD_VAL_SHIFT 4 +#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) +#define BUFCFG_PUPD_VAL_2K 0 +#define BUFCFG_PUPD_VAL_20K 1 +#define BUFCFG_PUPD_VAL_50K 2 +#define BUFCFG_PUPD_VAL_910 3 +#define BUFCFG_PU_EN BIT(8) +#define BUFCFG_PD_EN BIT(9) +#define BUFCFG_Px_EN_MASK GENMASK(9, 8) +#define BUFCFG_SLEWSEL BIT(10) +#define BUFCFG_OVINEN BIT(12) +#define BUFCFG_OVINEN_EN BIT(13) +#define BUFCFG_OVINEN_MASK GENMASK(13, 12) +#define BUFCFG_OVOUTEN BIT(14) +#define BUFCFG_OVOUTEN_EN BIT(15) +#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) +#define BUFCFG_INDATAOV_VAL BIT(16) +#define BUFCFG_INDATAOV_EN BIT(17) +#define BUFCFG_INDATAOV_MASK GENMASK(17, 16) +#define BUFCFG_OUTDATAOV_VAL BIT(18) +#define BUFCFG_OUTDATAOV_EN BIT(19) +#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) +#define BUFCFG_OD_EN BIT(21) + +#define pin_to_bufno(f, p) ((p) - (f)->pin_base) + +static const struct tng_family *tng_get_family(struct tng_pinctrl *tp, + unsigned int pin) +{ + const struct tng_family *family; + unsigned int i; + + for (i = 0; i < tp->nfamilies; i++) { + family = &tp->families[i]; + if (pin >= family->pin_base && + pin < family->pin_base + family->npins) + return family; + } + + dev_warn(tp->dev, "failed to find family for pin %u\n", pin); + return NULL; +} + +static bool tng_buf_available(struct tng_pinctrl *tp, unsigned int pin) +{ + const struct tng_family *family; + + family = tng_get_family(tp, pin); + if (!family) + return false; + + return !family->protected; +} + +static void __iomem *tng_get_bufcfg(struct tng_pinctrl *tp, unsigned int pin) +{ + const struct tng_family *family; + unsigned int bufno; + + family = tng_get_family(tp, pin); + if (!family) + return NULL; + + bufno = pin_to_bufno(family, pin); + return family->regs + BUFCFG_OFFSET + bufno * 4; +} + +static int tng_read_bufcfg(struct tng_pinctrl *tp, unsigned int pin, u32 *value) +{ + void __iomem *bufcfg; + + if (!tng_buf_available(tp, pin)) + return -EBUSY; + + bufcfg = tng_get_bufcfg(tp, pin); + *value = readl(bufcfg); + + return 0; +} + +static void tng_update_bufcfg(struct tng_pinctrl *tp, unsigned int pin, + u32 bits, u32 mask) +{ + void __iomem *bufcfg; + u32 value; + + bufcfg = tng_get_bufcfg(tp, pin); + + value = readl(bufcfg); + value = (value & ~mask) | (bits & mask); + writel(value, bufcfg); +} + +static int tng_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + return tp->ngroups; +} + +static const char *tng_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + return tp->groups[group].grp.name; +} + +static int tng_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + *pins = tp->groups[group].grp.pins; + *npins = tp->groups[group].grp.npins; + return 0; +} + +static void tng_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int pin) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + u32 value, mode; + int ret; + + ret = tng_read_bufcfg(tp, pin, &value); + if (ret) { + seq_puts(s, "not available"); + return; + } + + mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; + if (mode == BUFCFG_PINMODE_GPIO) + seq_puts(s, "GPIO "); + else + seq_printf(s, "mode %d ", mode); + + seq_printf(s, "0x%08x", value); +} + +static const struct pinctrl_ops tng_pinctrl_ops = { + .get_groups_count = tng_get_groups_count, + .get_group_name = tng_get_group_name, + .get_group_pins = tng_get_group_pins, + .pin_dbg_show = tng_pin_dbg_show, +}; + +static int tng_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + return tp->nfunctions; +} + +static const char *tng_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + return tp->functions[function].func.name; +} + +static int tng_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const ngroups) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + + *groups = tp->functions[function].func.groups; + *ngroups = tp->functions[function].func.ngroups; + return 0; +} + +static int tng_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + const struct intel_pingroup *grp = &tp->groups[group]; + u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; + u32 mask = BUFCFG_PINMODE_MASK; + unsigned long flags; + unsigned int i; + + /* + * All pins in the groups needs to be accessible and writable + * before we can enable the mux for this group. + */ + for (i = 0; i < grp->grp.npins; i++) { + if (!tng_buf_available(tp, grp->grp.pins[i])) + return -EBUSY; + } + + /* Now enable the mux setting for each pin in the group */ + raw_spin_lock_irqsave(&tp->lock, flags); + for (i = 0; i < grp->grp.npins; i++) + tng_update_bufcfg(tp, grp->grp.pins[i], bits, mask); + raw_spin_unlock_irqrestore(&tp->lock, flags); + + return 0; +} + +static int tng_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; + u32 mask = BUFCFG_PINMODE_MASK; + unsigned long flags; + + if (!tng_buf_available(tp, pin)) + return -EBUSY; + + raw_spin_lock_irqsave(&tp->lock, flags); + tng_update_bufcfg(tp, pin, bits, mask); + raw_spin_unlock_irqrestore(&tp->lock, flags); + + return 0; +} + +static const struct pinmux_ops tng_pinmux_ops = { + .get_functions_count = tng_get_functions_count, + .get_function_name = tng_get_function_name, + .get_function_groups = tng_get_function_groups, + .set_mux = tng_pinmux_set_mux, + .gpio_request_enable = tng_gpio_request_enable, +}; + +static int tng_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 value, term; + u16 arg = 0; + int ret; + + ret = tng_read_bufcfg(tp, pin, &value); + if (ret) + return -ENOTSUPP; + + term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (value & BUFCFG_Px_EN_MASK) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) + return -EINVAL; + + switch (term) { + case BUFCFG_PUPD_VAL_910: + arg = 910; + break; + case BUFCFG_PUPD_VAL_2K: + arg = 2000; + break; + case BUFCFG_PUPD_VAL_20K: + arg = 20000; + break; + case BUFCFG_PUPD_VAL_50K: + arg = 50000; + break; + } + + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) + return -EINVAL; + + switch (term) { + case BUFCFG_PUPD_VAL_910: + arg = 910; + break; + case BUFCFG_PUPD_VAL_2K: + arg = 2000; + break; + case BUFCFG_PUPD_VAL_20K: + arg = 20000; + break; + case BUFCFG_PUPD_VAL_50K: + arg = 50000; + break; + } + + break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (value & BUFCFG_OD_EN) + return -EINVAL; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!(value & BUFCFG_OD_EN)) + return -EINVAL; + break; + + case PIN_CONFIG_SLEW_RATE: + if (value & BUFCFG_SLEWSEL) + arg = 1; + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin, + unsigned long config) +{ + unsigned int param = pinconf_to_config_param(config); + unsigned int arg = pinconf_to_config_argument(config); + u32 mask, term, value = 0; + unsigned long flags; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + /* Set default strength value in case none is given */ + if (arg == 1) + arg = 20000; + + switch (arg) { + case 50000: + term = BUFCFG_PUPD_VAL_50K; + break; + case 20000: + term = BUFCFG_PUPD_VAL_20K; + break; + case 2000: + term = BUFCFG_PUPD_VAL_2K; + break; + default: + return -EINVAL; + } + + mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + value = BUFCFG_PU_EN | (term << BUFCFG_PUPD_VAL_SHIFT); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + /* Set default strength value in case none is given */ + if (arg == 1) + arg = 20000; + + switch (arg) { + case 50000: + term = BUFCFG_PUPD_VAL_50K; + break; + case 20000: + term = BUFCFG_PUPD_VAL_20K; + break; + case 2000: + term = BUFCFG_PUPD_VAL_2K; + break; + default: + return -EINVAL; + } + + mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + value = BUFCFG_PD_EN | (term << BUFCFG_PUPD_VAL_SHIFT); + break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + mask = BUFCFG_OD_EN; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + mask = BUFCFG_OD_EN; + value = BUFCFG_OD_EN; + break; + + case PIN_CONFIG_SLEW_RATE: + mask = BUFCFG_SLEWSEL; + if (arg) + value = BUFCFG_SLEWSEL; + break; + + default: + return -EINVAL; + } + + raw_spin_lock_irqsave(&tp->lock, flags); + tng_update_bufcfg(tp, pin, value, mask); + raw_spin_unlock_irqrestore(&tp->lock, flags); + + return 0; +} + +static int tng_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int nconfigs) +{ + struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev); + unsigned int i; + int ret; + + if (!tng_buf_available(tp, pin)) + return -ENOTSUPP; + + for (i = 0; i < nconfigs; i++) { + switch (pinconf_to_config_param(configs[i])) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_DRIVE_PUSH_PULL: + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_SLEW_RATE: + ret = tng_config_set_pin(tp, pin, configs[i]); + if (ret) + return ret; + break; + + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static int tng_config_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret = tng_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + return tng_config_get(pctldev, pins[0], config); +} + +static int tng_config_group_set(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int i, ret; + + ret = tng_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = tng_config_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops tng_pinconf_ops = { + .is_generic = true, + .pin_config_get = tng_config_get, + .pin_config_set = tng_config_set, + .pin_config_group_get = tng_config_group_get, + .pin_config_group_set = tng_config_group_set, +}; + +static const struct pinctrl_desc tng_pinctrl_desc = { + .pctlops = &tng_pinctrl_ops, + .pmxops = &tng_pinmux_ops, + .confops = &tng_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int tng_pinctrl_probe(struct platform_device *pdev, + const struct tng_pinctrl *data) +{ + struct device *dev = &pdev->dev; + struct tng_family *families; + struct tng_pinctrl *tp; + size_t families_len; + void __iomem *regs; + unsigned int i; + + tp = devm_kmemdup(dev, data, sizeof(*data), GFP_KERNEL); + if (!tp) + return -ENOMEM; + + tp->dev = dev; + raw_spin_lock_init(&tp->lock); + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + /* + * Make a copy of the families which we can use to hold pointers + * to the registers. + */ + families_len = size_mul(sizeof(*families), tp->nfamilies); + families = devm_kmemdup(dev, tp->families, families_len, GFP_KERNEL); + if (!families) + return -ENOMEM; + + /* Splice memory resource by chunk per family */ + for (i = 0; i < tp->nfamilies; i++) { + struct tng_family *family = &families[i]; + + family->regs = regs + family->barno * TNG_FAMILY_LEN; + } + + tp->families = families; + tp->pctldesc = tng_pinctrl_desc; + tp->pctldesc.name = dev_name(dev); + tp->pctldesc.pins = tp->pins; + tp->pctldesc.npins = tp->npins; + + tp->pctldev = devm_pinctrl_register(dev, &tp->pctldesc, tp); + if (IS_ERR(tp->pctldev)) + return dev_err_probe(dev, PTR_ERR(tp->pctldev), + "failed to register pinctrl driver\n"); + + return 0; +} + +int devm_tng_pinctrl_probe(struct platform_device *pdev) +{ + const struct tng_pinctrl *data; + + data = device_get_match_data(&pdev->dev); + if (!data) + return -ENODATA; + + return tng_pinctrl_probe(pdev, data); +} +EXPORT_SYMBOL_NS_GPL(devm_tng_pinctrl_probe, PINCTRL_TANGIER); + +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); +MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>"); +MODULE_DESCRIPTION("Intel Tangier pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/intel/pinctrl-tangier.h b/drivers/pinctrl/intel/pinctrl-tangier.h new file mode 100644 index 000000000000..955cc967c0bc --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-tangier.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel Tangier pinctrl functions + * + * Copyright (C) 2016, 2023 Intel Corporation + * + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> + * Raag Jadav <raag.jadav@intel.com> + */ + +#ifndef PINCTRL_TANGIER_H +#define PINCTRL_TANGIER_H + +#include <linux/spinlock_types.h> +#include <linux/types.h> + +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +struct device; +struct platform_device; + +#define TNG_FAMILY_NR 64 +#define TNG_FAMILY_LEN 0x400 + +/** + * struct tng_family - Tangier pin family description + * @barno: MMIO BAR number where registers for this family reside + * @pin_base: Starting pin of pins in this family + * @npins: Number of pins in this family + * @protected: True if family is protected by access + * @regs: Family specific common registers + */ +struct tng_family { + unsigned int barno; + unsigned int pin_base; + size_t npins; + bool protected; + void __iomem *regs; +}; + +#define TNG_FAMILY(b, s, e) \ + { \ + .barno = (b), \ + .pin_base = (s), \ + .npins = (e) - (s) + 1, \ + } + +#define TNG_FAMILY_PROTECTED(b, s, e) \ + { \ + .barno = (b), \ + .pin_base = (s), \ + .npins = (e) - (s) + 1, \ + .protected = true, \ + } + +/** + * struct tng_pinctrl - Tangier pinctrl private structure + * @dev: Pointer to the device structure + * @lock: Lock to serialize register access + * @pctldesc: Pin controller description + * @pctldev: Pointer to the pin controller device + * @families: Array of families this pinctrl handles + * @nfamilies: Number of families in the array + * @functions: Array of functions + * @nfunctions: Number of functions in the array + * @groups: Array of pin groups + * @ngroups: Number of groups in the array + * @pins: Array of pins this pinctrl controls + * @npins: Number of pins in the array + */ +struct tng_pinctrl { + struct device *dev; + raw_spinlock_t lock; + struct pinctrl_desc pctldesc; + struct pinctrl_dev *pctldev; + + /* Pin controller configuration */ + const struct tng_family *families; + size_t nfamilies; + const struct intel_function *functions; + size_t nfunctions; + const struct intel_pingroup *groups; + size_t ngroups; + const struct pinctrl_pin_desc *pins; + size_t npins; +}; + +int devm_tng_pinctrl_probe(struct platform_device *pdev); + +#endif /* PINCTRL_TANGIER_H */ diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 6e3a651d1241..4768a69a9258 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -753,10 +753,10 @@ static struct platform_driver tgl_pinctrl_driver = { .pm = &tgl_pinctrl_pm_ops, }, }; - module_platform_driver(tgl_pinctrl_driver); MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(PINCTRL_INTEL); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index b185538452a0..5fb377c1668b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -7,7 +7,6 @@ #include <dt-bindings/pinctrl/mt65xx.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index 730a496848dc..8a6daa0db54b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -8,7 +8,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> #include <linux/pinctrl/pinconf-generic.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index bc5c3dfcdc76..03d0f65d7bcc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -7,7 +7,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/mfd/mt6397/core.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 18abc5780011..0fd2c0c451f9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_type[] = { MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ - MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ - MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ - MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ - MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ - MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ - MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ - MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ - MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ - MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ - MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ - MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ - MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ - MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ - MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ - MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ - MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ - MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ - MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ - MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ - MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ - MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ - MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ - MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ - MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ - MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ - MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ - MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ - MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ - MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ - MTK_PULL_PU_PD_TYPE,/*100*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ + MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ + MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ + MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ + MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ + MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ + MTK_PULL_PU_PD_TYPE,/*56*/ }; static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { @@ -1014,6 +992,10 @@ static struct mtk_pin_soc mt7981_data = { .ies_present = false, .base_names = mt7981_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7981_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index aa0ccd67f4f4..acaac9b38aa8 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, @@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index e8772dcfe69e..f5030a9ea40b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -8,7 +8,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> #include <dt-bindings/pinctrl/mt65xx.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index cdb0252071fb..77c6ac464e86 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -7,7 +7,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> #include <dt-bindings/pinctrl/mt65xx.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index 866da2c4a890..ba7f30c3296f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -6,7 +6,6 @@ #include <dt-bindings/pinctrl/mt65xx.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/module.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index 37d8cec1c3ce..455eec018f93 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -7,7 +7,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> #include <linux/pinctrl/pinconf-generic.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 75a505035e96..1db04bbdb423 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -6,7 +6,6 @@ #include <dt-bindings/pinctrl/mt65xx.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/module.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index e929339dd2cb..950275c47122 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -6,7 +6,6 @@ #include <dt-bindings/pinctrl/mt65xx.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/module.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 665dec419e7c..74b15952b742 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -8,8 +8,6 @@ #include <linux/io.h> #include <linux/gpio/driver.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/of_irq.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index 64fb9e074ac6..71fa7431df67 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -67,4 +67,10 @@ config PINCTRL_MESON_S4 select PINCTRL_MESON_AXG_PMX default y +config PINCTRL_AMLOGIC_C3 + tristate "Amlogic C3 SoC pinctrl driver" + depends on ARM64 + select PINCTRL_MESON_AXG_PMX + default y + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 694f0596bfbc..7ecddf7f683e 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o +obj-$(CONFIG_PINCTRL_AMLOGIC_C3) += pinctrl-amlogic-c3.o diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-c3.c b/drivers/pinctrl/meson/pinctrl-amlogic-c3.c new file mode 100644 index 000000000000..04f1e87bae99 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-amlogic-c3.c @@ -0,0 +1,1108 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Pin controller and GPIO driver for Amlogic C3 SoC. + * + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Huqiang Qin <huqiang.qin@amlogic.com> + */ + +#include <dt-bindings/gpio/amlogic-c3-gpio.h> +#include "pinctrl-meson.h" +#include "pinctrl-meson-axg-pmx.h" + +static const struct pinctrl_pin_desc c3_periphs_pins[] = { + MESON_PIN(GPIOE_0), + MESON_PIN(GPIOE_1), + MESON_PIN(GPIOE_2), + MESON_PIN(GPIOE_3), + MESON_PIN(GPIOE_4), + MESON_PIN(GPIOB_0), + MESON_PIN(GPIOB_1), + MESON_PIN(GPIOB_2), + MESON_PIN(GPIOB_3), + MESON_PIN(GPIOB_4), + MESON_PIN(GPIOB_5), + MESON_PIN(GPIOB_6), + MESON_PIN(GPIOB_7), + MESON_PIN(GPIOB_8), + MESON_PIN(GPIOB_9), + MESON_PIN(GPIOB_10), + MESON_PIN(GPIOB_11), + MESON_PIN(GPIOB_12), + MESON_PIN(GPIOB_13), + MESON_PIN(GPIOB_14), + MESON_PIN(GPIOC_0), + MESON_PIN(GPIOC_1), + MESON_PIN(GPIOC_2), + MESON_PIN(GPIOC_3), + MESON_PIN(GPIOC_4), + MESON_PIN(GPIOC_5), + MESON_PIN(GPIOC_6), + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOD_0), + MESON_PIN(GPIOD_1), + MESON_PIN(GPIOD_2), + MESON_PIN(GPIOD_3), + MESON_PIN(GPIOD_4), + MESON_PIN(GPIOD_5), + MESON_PIN(GPIOD_6), + MESON_PIN(GPIOA_0), + MESON_PIN(GPIOA_1), + MESON_PIN(GPIOA_2), + MESON_PIN(GPIOA_3), + MESON_PIN(GPIOA_4), + MESON_PIN(GPIOA_5), + MESON_PIN(GPIO_TEST_N), +}; + +/* Bank E func1 */ +static const unsigned int pwm_a_pins[] = { GPIOE_0 }; +static const unsigned int pwm_b_pins[] = { GPIOE_1 }; +static const unsigned int i2c2_sda_pins[] = { GPIOE_2 }; +static const unsigned int i2c2_scl_pins[] = { GPIOE_3 }; +static const unsigned int gen_clk_e_pins[] = { GPIOE_4 }; + +/* Bank E func2 */ +static const unsigned int i2c0_sda_e_pins[] = { GPIOE_0 }; +static const unsigned int i2c0_scl_e_pins[] = { GPIOE_1 }; +static const unsigned int clk_32k_in_pins[] = { GPIOE_4 }; + +/* Bank E func3 */ +static const unsigned int i2c_slave_scl_pins[] = { GPIOE_0 }; +static const unsigned int i2c_slave_sda_pins[] = { GPIOE_1 }; +static const unsigned int clk12_24_e_pins[] = { GPIOE_4 }; + +/* Bank B func1 */ +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; +static const unsigned int emmc_rst_pins[] = { GPIOB_9 }; +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; + +/* Bank B func2 */ +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; +static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 }; +static const unsigned int nand_cle_pins[] = { GPIOB_11 }; +static const unsigned int nand_ce0_pins[] = { GPIOB_12 }; + +/* Bank B func3 */ +static const unsigned int pwm_g_b_pins[] = { GPIOB_0 }; +static const unsigned int pwm_h_b_pins[] = { GPIOB_1 }; +static const unsigned int pwm_i_b_pins[] = { GPIOB_2 }; +static const unsigned int spif_hold_pins[] = { GPIOB_3 }; +static const unsigned int spif_mo_pins[] = { GPIOB_4 }; +static const unsigned int spif_mi_pins[] = { GPIOB_5 }; +static const unsigned int spif_clk_pins[] = { GPIOB_6 }; +static const unsigned int spif_wp_pins[] = { GPIOB_7 }; +static const unsigned int pwm_j_b_pins[] = { GPIOB_8 }; +static const unsigned int pwm_k_b_pins[] = { GPIOB_9 }; +static const unsigned int pwm_l_b_pins[] = { GPIOB_10 }; +static const unsigned int pwm_m_b_pins[] = { GPIOB_11 }; +static const unsigned int pwm_n_b_pins[] = { GPIOB_12 }; +static const unsigned int spif_cs_pins[] = { GPIOB_13 }; +static const unsigned int spif_clk_loop_pins[] = { GPIOB_14 }; + +/* Bank B func4 */ +static const unsigned int lcd_d0_pins[] = { GPIOB_0 }; +static const unsigned int lcd_d1_pins[] = { GPIOB_1 }; +static const unsigned int lcd_d2_pins[] = { GPIOB_2 }; +static const unsigned int lcd_d3_pins[] = { GPIOB_8 }; +static const unsigned int lcd_d4_pins[] = { GPIOB_9 }; +static const unsigned int lcd_d5_pins[] = { GPIOB_10 }; +static const unsigned int lcd_d6_pins[] = { GPIOB_11 }; +static const unsigned int lcd_d7_pins[] = { GPIOB_12 }; + +/* Bank B func5 */ +static const unsigned int spi_a_mosi_b_pins[] = { GPIOB_0 }; +static const unsigned int spi_a_miso_b_pins[] = { GPIOB_1 }; +static const unsigned int spi_a_clk_b_pins[] = { GPIOB_2 }; +static const unsigned int spi_a_ss0_b_pins[] = { GPIOB_8 }; +static const unsigned int spi_a_ss1_b_pins[] = { GPIOB_9 }; +static const unsigned int spi_a_ss2_b_pins[] = { GPIOB_10 }; +static const unsigned int i2c1_sda_b_pins[] = { GPIOB_11 }; +static const unsigned int i2c1_scl_b_pins[] = { GPIOB_12 }; + +/* Bank B func6 */ +static const unsigned int uart_a_tx_b_pins[] = { GPIOB_0 }; +static const unsigned int uart_a_rx_b_pins[] = { GPIOB_1 }; +static const unsigned int uart_a_cts_b_pins[] = { GPIOB_2 }; +static const unsigned int uart_a_rts_b_pins[] = { GPIOB_8 }; +static const unsigned int uart_d_tx_b_pins[] = { GPIOB_9 }; +static const unsigned int uart_d_rx_b_pins[] = { GPIOB_10 }; +static const unsigned int pdm_dclk_b_pins[] = { GPIOB_11 }; +static const unsigned int pdm_din0_b_pins[] = { GPIOB_12 }; + +/* Bank C func1 */ +static const unsigned int sdcard_d0_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 }; +static const unsigned int sdcard_cd_pins[] = { GPIOC_6 }; + +/* Bank C func2 */ +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; +static const unsigned int gen_clk_c_pins[] = { GPIOC_6 }; + +/* Bank C func3 */ +static const unsigned int tdm_d3_pins[] = { GPIOC_0 }; +static const unsigned int tdm_d2_pins[] = { GPIOC_1 }; +static const unsigned int mclk_1_pins[] = { GPIOC_2 }; +static const unsigned int tdm_sclk1_pins[] = { GPIOC_3 }; +static const unsigned int tdm_fs1_pins[] = { GPIOC_4 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_5 }; +static const unsigned int pdm_din0_c_pins[] = { GPIOC_6 }; + +/* Bank C func4 */ +static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 }; +static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 }; +static const unsigned int spi_a_clk_c_pins[] = { GPIOC_2 }; +static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_3 }; +static const unsigned int spi_a_ss1_c_pins[] = { GPIOC_4 }; + +/* Bank C func5 */ +static const unsigned int pwm_g_c_pins[] = { GPIOC_0 }; +static const unsigned int pwm_h_c_pins[] = { GPIOC_1 }; +static const unsigned int pwm_i_c_pins[] = { GPIOC_2 }; +static const unsigned int pwm_j_c_pins[] = { GPIOC_3 }; +static const unsigned int pwm_k_c_pins[] = { GPIOC_4 }; +static const unsigned int pwm_l_c_pins[] = { GPIOC_5 }; +static const unsigned int pwm_m_c_pins[] = { GPIOC_6 }; + +/* Bank C func6 */ +static const unsigned int uart_a_rx_c_pins[] = { GPIOC_0 }; +static const unsigned int uart_a_tx_c_pins[] = { GPIOC_1 }; +static const unsigned int uart_c_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_c_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int i2c3_sda_c_pins[] = { GPIOC_4 }; +static const unsigned int i2c3_scl_c_pins[] = { GPIOC_5 }; +static const unsigned int clk12_24_c_pins[] = { GPIOC_6 }; + +/* Bank X func1 */ +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; +static const unsigned int clk12_24_x_pins[] = { GPIOX_6 }; +static const unsigned int uart_e_tx_x_pins[] = { GPIOX_7 }; +static const unsigned int uart_e_rx_x_pins[] = { GPIOX_8 }; +static const unsigned int uart_e_cts_pins[] = { GPIOX_9 }; +static const unsigned int uart_e_rts_pins[] = { GPIOX_10 }; +static const unsigned int pwm_e_pins[] = { GPIOX_11 }; +static const unsigned int pwm_j_x12_pins[] = { GPIOX_12 }; +static const unsigned int pwm_k_x13_pins[] = { GPIOX_13 }; + +/* Bank X func2 */ +static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_0 }; +static const unsigned int spi_a_miso_x_pins[] = { GPIOX_1 }; +static const unsigned int spi_a_clk_x_pins[] = { GPIOX_2 }; +static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_3 }; +static const unsigned int spi_a_ss1_x_pins[] = { GPIOX_4 }; +static const unsigned int spi_a_ss2_x_pins[] = { GPIOX_5 }; +static const unsigned int spi_b_ss2_x6_pins[] = { GPIOX_6 }; +static const unsigned int spi_b_miso_x_pins[] = { GPIOX_7 }; +static const unsigned int spi_b_clk_x_pins[] = { GPIOX_8 }; +static const unsigned int spi_b_mosi_x_pins[] = { GPIOX_9 }; +static const unsigned int spi_b_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi_b_ss1_x_pins[] = { GPIOX_11 }; +static const unsigned int spi_b_ss2_x12_pins[] = { GPIOX_12 }; +static const unsigned int gen_clk_x_pins[] = { GPIOX_13 }; + +/* Bank X func3 */ +static const unsigned int tdm_d1_x_pins[] = { GPIOX_0 }; +static const unsigned int tdm_d0_x_pins[] = { GPIOX_1 }; +static const unsigned int mclk_0_x_pins[] = { GPIOX_2 }; +static const unsigned int tdm_sclk0_x_pins[] = { GPIOX_3 }; +static const unsigned int tdm_fs0_x_pins[] = { GPIOX_4 }; +static const unsigned int pdm_dclk_x5_pins[] = { GPIOX_5 }; +static const unsigned int pdm_din0_x6_pins[] = { GPIOX_6 }; +static const unsigned int pdm_din0_x9_pins[] = { GPIOX_9 }; +static const unsigned int pdm_dclk_x10_pins[] = { GPIOX_10 }; +static const unsigned int clk12_24_x13_pins[] = { GPIOX_13 }; + +/* Bank X func4 */ +static const unsigned int lcd_d8_pins[] = { GPIOX_0 }; +static const unsigned int lcd_d9_pins[] = { GPIOX_1 }; +static const unsigned int lcd_d10_pins[] = { GPIOX_2 }; +static const unsigned int lcd_d11_pins[] = { GPIOX_3 }; +static const unsigned int lcd_d12_pins[] = { GPIOX_4 }; +static const unsigned int lcd_d13_pins[] = { GPIOX_5 }; +static const unsigned int lcd_d14_pins[] = { GPIOX_6 }; +static const unsigned int lcd_d15_pins[] = { GPIOX_7 }; +static const unsigned int lcd_vs_pins[] = { GPIOX_8 }; +static const unsigned int lcd_hs_pins[] = { GPIOX_9 }; +static const unsigned int lcd_den_pins[] = { GPIOX_10 }; +static const unsigned int lcd_d16_pins[] = { GPIOX_11 }; +static const unsigned int lcd_clk_x_pins[] = { GPIOX_12 }; +static const unsigned int lcd_d17_pins[] = { GPIOX_13 }; + +/* Bank X func5 */ +static const unsigned int pwm_g_x0_pins[] = { GPIOX_0 }; +static const unsigned int pwm_h_x1_pins[] = { GPIOX_1 }; +static const unsigned int pwm_i_x2_pins[] = { GPIOX_2 }; +static const unsigned int pwm_j_x3_pins[] = { GPIOX_3 }; +static const unsigned int pwm_k_x4_pins[] = { GPIOX_4 }; +static const unsigned int pwm_l_x_pins[] = { GPIOX_5 }; +static const unsigned int pwm_m_x_pins[] = { GPIOX_6 }; +static const unsigned int pwm_n_x_pins[] = { GPIOX_7 }; +static const unsigned int pwm_g_x8_pins[] = { GPIOX_8 }; +static const unsigned int pwm_h_x9_pins[] = { GPIOX_9 }; +static const unsigned int pwm_i_x10_pins[] = { GPIOX_10 }; +static const unsigned int clk12_24_x11_pins[] = { GPIOX_11 }; + +/* Bank X func6 */ +static const unsigned int uart_a_rx_x_pins[] = { GPIOX_0 }; +static const unsigned int uart_a_tx_x_pins[] = { GPIOX_1 }; +static const unsigned int uart_c_rx_x_pins[] = { GPIOX_2 }; +static const unsigned int uart_c_tx_x_pins[] = { GPIOX_3 }; +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_4 }; +static const unsigned int i2c3_scl_x_pins[] = { GPIOX_5 }; +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_7 }; +static const unsigned int i2c1_scl_x_pins[] = { GPIOX_8 }; +static const unsigned int uart_d_tx_x_pins[] = { GPIOX_9 }; +static const unsigned int uart_d_rx_x_pins[] = { GPIOX_10 }; + +/* Bank D func1 */ +static const unsigned int pwm_g_d_pins[] = { GPIOD_0 }; +static const unsigned int pwm_h_d_pins[] = { GPIOD_1 }; +static const unsigned int eth_led_act_pins[] = { GPIOD_2 }; +static const unsigned int eth_led_link_pins[] = { GPIOD_3 }; +static const unsigned int pwm_d_pins[] = { GPIOD_4 }; +static const unsigned int pwm_f_pins[] = { GPIOD_5 }; +static const unsigned int pwm_k_d_pins[] = { GPIOD_6 }; + +/* Bank D func2 */ +static const unsigned int uart_a_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_a_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int spi_b_miso_d_pins[] = { GPIOD_2 }; +static const unsigned int spi_b_clk_d_pins[] = { GPIOD_3 }; +static const unsigned int spi_b_mosi_d_pins[] = { GPIOD_4 }; +static const unsigned int spi_b_ss0_d_pins[] = { GPIOD_5 }; +static const unsigned int spi_b_ss1_d_pins[] = { GPIOD_6 }; + +/* Bank D func3 */ +static const unsigned int i2c0_sda_d_pins[] = { GPIOD_0 }; +static const unsigned int i2c0_scl_d_pins[] = { GPIOD_1 }; +static const unsigned int i2c1_sda_d_pins[] = { GPIOD_2 }; +static const unsigned int i2c1_scl_d_pins[] = { GPIOD_3 }; +static const unsigned int pdm_dclk_d_pins[] = { GPIOD_4 }; +static const unsigned int pdm_din0_d_pins[] = { GPIOD_5 }; +static const unsigned int ir_in_d6_pins[] = { GPIOD_6 }; + +/* Bank D func4 */ +static const unsigned int ir_in_d0_pins[] = { GPIOD_0 }; +static const unsigned int ir_out_pins[] = { GPIOD_1 }; +static const unsigned int pwm_i_d_pins[] = { GPIOD_2 }; +static const unsigned int pwm_j_d_pins[] = { GPIOD_3 }; +static const unsigned int i2c3_sda_d_pins[] = { GPIOD_4 }; +static const unsigned int i2c3_scl_d_pins[] = { GPIOD_5 }; + +/* Bank D func5 */ +static const unsigned int tdm_fs0_d_pins[] = { GPIOD_2 }; +static const unsigned int tdm_sclk0_d_pins[] = { GPIOD_3 }; +static const unsigned int mclk_0_d_pins[] = { GPIOD_4 }; +static const unsigned int tdm_d1_d_pins[] = { GPIOD_5 }; +static const unsigned int tdm_d0_d_pins[] = { GPIOD_6 }; + +/* Bank D func6 */ +static const unsigned int uart_d_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_d_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int uart_c_tx_d_pins[] = { GPIOD_2 }; +static const unsigned int uart_c_rx_d_pins[] = { GPIOD_3 }; + +/* Bank A func1 */ +static const unsigned int uart_b_tx_a_pins[] = { GPIOA_0 }; +static const unsigned int uart_b_rx_a_pins[] = { GPIOA_1 }; +static const unsigned int pwm_c_pins[] = { GPIOA_2 }; +static const unsigned int pwm_l_a_pins[] = { GPIOA_3 }; +static const unsigned int i2c1_sda_a_pins[] = { GPIOA_4 }; +static const unsigned int i2c1_scl_a_pins[] = { GPIOA_5 }; + +/* Bank A func2 */ +static const unsigned int pwm_c_hiz_pins[] = { GPIOA_2 }; +static const unsigned int gen_clk_a_pins[] = { GPIOA_3 }; +static const unsigned int pdm_dclk_z_pins[] = { GPIOA_4 }; +static const unsigned int pdm_din0_a_pins[] = { GPIOA_5 }; + +/* Bank A func3 */ +static const unsigned int jtag_a_clk_pins[] = { GPIOA_2 }; +static const unsigned int jtag_a_tms_pins[] = { GPIOA_3 }; +static const unsigned int jtag_a_tdi_pins[] = { GPIOA_4 }; +static const unsigned int jtag_a_tdo_pins[] = { GPIOA_5 }; + +/* Bank A func4 */ +static const unsigned int lcd_clk_a_pins[] = { GPIOA_3 }; +static const unsigned int uart_f_tx_a_pins[] = { GPIOA_4 }; +static const unsigned int uart_f_rx_a_pins[] = { GPIOA_5 }; + +/* Bank A func5 */ +static const unsigned int uart_e_tx_a_pins[] = { GPIOA_2 }; +static const unsigned int uart_e_rx_a_pins[] = { GPIOA_3 }; +static const unsigned int pwm_m_a_pins[] = { GPIOA_4 }; +static const unsigned int pwm_n_a_pins[] = { GPIOA_5 }; + +/* Bank A func6 */ +static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_3 }; +static const unsigned int gen_clk_a4_pins[] = { GPIOA_4 }; +static const unsigned int clk12_24_a_pins[] = { GPIOA_5 }; + +static struct meson_pmx_group c3_periphs_groups[] = { + GPIO_GROUP(GPIOE_0), + GPIO_GROUP(GPIOE_1), + GPIO_GROUP(GPIOE_2), + GPIO_GROUP(GPIOE_3), + GPIO_GROUP(GPIOE_4), + GPIO_GROUP(GPIOB_0), + GPIO_GROUP(GPIOB_1), + GPIO_GROUP(GPIOB_2), + GPIO_GROUP(GPIOB_3), + GPIO_GROUP(GPIOB_4), + GPIO_GROUP(GPIOB_5), + GPIO_GROUP(GPIOB_6), + GPIO_GROUP(GPIOB_7), + GPIO_GROUP(GPIOB_8), + GPIO_GROUP(GPIOB_9), + GPIO_GROUP(GPIOB_10), + GPIO_GROUP(GPIOB_11), + GPIO_GROUP(GPIOB_12), + GPIO_GROUP(GPIOB_13), + GPIO_GROUP(GPIOB_14), + GPIO_GROUP(GPIOC_0), + GPIO_GROUP(GPIOC_1), + GPIO_GROUP(GPIOC_2), + GPIO_GROUP(GPIOC_3), + GPIO_GROUP(GPIOC_4), + GPIO_GROUP(GPIOC_5), + GPIO_GROUP(GPIOC_6), + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOD_0), + GPIO_GROUP(GPIOD_1), + GPIO_GROUP(GPIOD_2), + GPIO_GROUP(GPIOD_3), + GPIO_GROUP(GPIOD_4), + GPIO_GROUP(GPIOD_5), + GPIO_GROUP(GPIOD_6), + GPIO_GROUP(GPIOA_0), + GPIO_GROUP(GPIOA_1), + GPIO_GROUP(GPIOA_2), + GPIO_GROUP(GPIOA_3), + GPIO_GROUP(GPIOA_4), + GPIO_GROUP(GPIOA_5), + GPIO_GROUP(GPIO_TEST_N), + + /* Bank E func1 */ + GROUP(pwm_a, 1), + GROUP(pwm_b, 1), + GROUP(i2c2_sda, 1), + GROUP(i2c2_scl, 1), + GROUP(gen_clk_e, 1), + + /* Bank E func2 */ + GROUP(i2c0_sda_e, 2), + GROUP(i2c0_scl_e, 2), + GROUP(clk_32k_in, 2), + + /* Bank E func3 */ + GROUP(i2c_slave_scl, 3), + GROUP(i2c_slave_sda, 3), + GROUP(clk12_24_e, 3), + + /* Bank B func1 */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_rst, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_ds, 1), + + /* Bank B func2 */ + GROUP(nand_wen_clk, 2), + GROUP(nand_ale, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_cle, 2), + GROUP(nand_ce0, 2), + + /* Bank B func3 */ + GROUP(pwm_g_b, 3), + GROUP(pwm_h_b, 3), + GROUP(pwm_i_b, 3), + GROUP(spif_hold, 3), + GROUP(spif_mo, 3), + GROUP(spif_mi, 3), + GROUP(spif_clk, 3), + GROUP(spif_wp, 3), + GROUP(pwm_j_b, 3), + GROUP(pwm_k_b, 3), + GROUP(pwm_l_b, 3), + GROUP(pwm_m_b, 3), + GROUP(pwm_n_b, 3), + GROUP(spif_cs, 3), + GROUP(spif_clk_loop, 3), + + /* Bank B func4 */ + GROUP(lcd_d0, 4), + GROUP(lcd_d1, 4), + GROUP(lcd_d2, 4), + GROUP(lcd_d3, 4), + GROUP(lcd_d4, 4), + GROUP(lcd_d5, 4), + GROUP(lcd_d6, 4), + GROUP(lcd_d7, 4), + + /* Bank B func5 */ + GROUP(spi_a_mosi_b, 5), + GROUP(spi_a_miso_b, 5), + GROUP(spi_a_clk_b, 5), + GROUP(spi_a_ss0_b, 5), + GROUP(spi_a_ss1_b, 5), + GROUP(spi_a_ss2_b, 5), + GROUP(i2c1_sda_b, 5), + GROUP(i2c1_scl_b, 5), + + /* Bank B func6 */ + GROUP(uart_a_tx_b, 6), + GROUP(uart_a_rx_b, 6), + GROUP(uart_a_cts_b, 6), + GROUP(uart_a_rts_b, 6), + GROUP(uart_d_tx_b, 6), + GROUP(uart_d_rx_b, 6), + GROUP(pdm_dclk_b, 6), + GROUP(pdm_din0_b, 6), + + /* Bank C func1 */ + GROUP(sdcard_d0, 1), + GROUP(sdcard_d1, 1), + GROUP(sdcard_d2, 1), + GROUP(sdcard_d3, 1), + GROUP(sdcard_clk, 1), + GROUP(sdcard_cmd, 1), + GROUP(sdcard_cd, 1), + + /* Bank C func2 */ + GROUP(jtag_b_tdo, 2), + GROUP(jtag_b_tdi, 2), + GROUP(uart_b_rx_c, 2), + GROUP(uart_b_tx_c, 2), + GROUP(jtag_b_clk, 2), + GROUP(jtag_b_tms, 2), + GROUP(gen_clk_c, 2), + + /* Bank C func3 */ + GROUP(tdm_d3, 3), + GROUP(tdm_d2, 3), + GROUP(mclk_1, 3), + GROUP(tdm_sclk1, 3), + GROUP(tdm_fs1, 3), + GROUP(pdm_dclk_c, 3), + GROUP(pdm_din0_c, 3), + + /* Bank C func4 */ + GROUP(spi_a_mosi_c, 4), + GROUP(spi_a_miso_c, 4), + GROUP(spi_a_clk_c, 4), + GROUP(spi_a_ss0_c, 4), + GROUP(spi_a_ss1_c, 4), + + /* Bank C func5 */ + GROUP(pwm_g_c, 5), + GROUP(pwm_h_c, 5), + GROUP(pwm_i_c, 5), + GROUP(pwm_j_c, 5), + GROUP(pwm_k_c, 5), + GROUP(pwm_l_c, 5), + GROUP(pwm_m_c, 5), + + /* Bank C func6 */ + GROUP(uart_a_rx_c, 6), + GROUP(uart_a_tx_c, 6), + GROUP(uart_c_rx_c, 6), + GROUP(uart_c_tx_c, 6), + GROUP(i2c3_sda_c, 6), + GROUP(i2c3_scl_c, 6), + GROUP(clk12_24_c, 6), + + /* Bank X func1 */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(clk12_24_x, 1), + GROUP(uart_e_tx_x, 1), + GROUP(uart_e_rx_x, 1), + GROUP(uart_e_cts, 1), + GROUP(uart_e_rts, 1), + GROUP(pwm_e, 1), + GROUP(pwm_j_x12, 1), + GROUP(pwm_k_x13, 1), + + /* Bank X func2 */ + GROUP(spi_a_mosi_x, 2), + GROUP(spi_a_miso_x, 2), + GROUP(spi_a_clk_x, 2), + GROUP(spi_a_ss0_x, 2), + GROUP(spi_a_ss1_x, 2), + GROUP(spi_a_ss2_x, 2), + GROUP(spi_b_ss2_x6, 2), + GROUP(spi_b_miso_x, 2), + GROUP(spi_b_clk_x, 2), + GROUP(spi_b_mosi_x, 2), + GROUP(spi_b_ss0_x, 2), + GROUP(spi_b_ss1_x, 2), + GROUP(spi_b_ss2_x12, 2), + GROUP(gen_clk_x, 2), + + /* Bank X func3 */ + GROUP(tdm_d1_x, 3), + GROUP(tdm_d0_x, 3), + GROUP(mclk_0_x, 3), + GROUP(tdm_sclk0_x, 3), + GROUP(tdm_fs0_x, 3), + GROUP(pdm_dclk_x5, 3), + GROUP(pdm_din0_x6, 3), + GROUP(pdm_din0_x9, 3), + GROUP(pdm_dclk_x10, 3), + GROUP(clk12_24_x13, 3), + + /* Bank X func4 */ + GROUP(lcd_d8, 4), + GROUP(lcd_d9, 4), + GROUP(lcd_d10, 4), + GROUP(lcd_d11, 4), + GROUP(lcd_d12, 4), + GROUP(lcd_d13, 4), + GROUP(lcd_d14, 4), + GROUP(lcd_d15, 4), + GROUP(lcd_vs, 4), + GROUP(lcd_hs, 4), + GROUP(lcd_den, 4), + GROUP(lcd_d16, 4), + GROUP(lcd_clk_x, 4), + GROUP(lcd_d17, 4), + + /* Bank X func5 */ + GROUP(pwm_g_x0, 5), + GROUP(pwm_h_x1, 5), + GROUP(pwm_i_x2, 5), + GROUP(pwm_j_x3, 5), + GROUP(pwm_k_x4, 5), + GROUP(pwm_l_x, 5), + GROUP(pwm_m_x, 5), + GROUP(pwm_n_x, 5), + GROUP(pwm_g_x8, 5), + GROUP(pwm_h_x9, 5), + GROUP(pwm_i_x10, 5), + GROUP(clk12_24_x11, 5), + + /* Bank X func6 */ + GROUP(uart_a_rx_x, 6), + GROUP(uart_a_tx_x, 6), + GROUP(uart_c_rx_x, 6), + GROUP(uart_c_tx_x, 6), + GROUP(i2c3_sda_x, 6), + GROUP(i2c3_scl_x, 6), + GROUP(i2c1_sda_x, 6), + GROUP(i2c1_scl_x, 6), + GROUP(uart_d_tx_x, 6), + GROUP(uart_d_rx_x, 6), + + /* Bank D func1 */ + GROUP(pwm_g_d, 1), + GROUP(pwm_h_d, 1), + GROUP(eth_led_act, 1), + GROUP(eth_led_link, 1), + GROUP(pwm_d, 1), + GROUP(pwm_f, 1), + GROUP(pwm_k_d, 1), + + /* Bank D func2 */ + GROUP(uart_a_tx_d, 2), + GROUP(uart_a_rx_d, 2), + GROUP(spi_b_miso_d, 2), + GROUP(spi_b_clk_d, 2), + GROUP(spi_b_mosi_d, 2), + GROUP(spi_b_ss0_d, 2), + GROUP(spi_b_ss1_d, 2), + + /* Bank D func3 */ + GROUP(i2c0_sda_d, 3), + GROUP(i2c0_scl_d, 3), + GROUP(i2c1_sda_d, 3), + GROUP(i2c1_scl_d, 3), + GROUP(pdm_dclk_d, 3), + GROUP(pdm_din0_d, 3), + GROUP(ir_in_d6, 3), + + /* Bank D func4 */ + GROUP(ir_in_d0, 4), + GROUP(ir_out, 4), + GROUP(pwm_i_d, 4), + GROUP(pwm_j_d, 4), + GROUP(i2c3_sda_d, 4), + GROUP(i2c3_scl_d, 4), + + /* Bank D func5 */ + GROUP(tdm_fs0_d, 5), + GROUP(tdm_sclk0_d, 5), + GROUP(mclk_0_d, 5), + GROUP(tdm_d1_d, 5), + GROUP(tdm_d0_d, 5), + + /* Bank D func6 */ + GROUP(uart_d_tx_d, 6), + GROUP(uart_d_rx_d, 6), + GROUP(uart_c_tx_d, 6), + GROUP(uart_c_rx_d, 6), + + /* Bank A func1 */ + GROUP(uart_b_tx_a, 1), + GROUP(uart_b_rx_a, 1), + GROUP(pwm_c, 1), + GROUP(pwm_l_a, 1), + GROUP(i2c1_sda_a, 1), + GROUP(i2c1_scl_a, 1), + + /* Bank A func2 */ + GROUP(pwm_c_hiz, 2), + GROUP(gen_clk_a, 2), + GROUP(pdm_dclk_z, 2), + GROUP(pdm_din0_a, 2), + + /* Bank A func3 */ + GROUP(jtag_a_clk, 3), + GROUP(jtag_a_tms, 3), + GROUP(jtag_a_tdi, 3), + GROUP(jtag_a_tdo, 3), + + /* Bank A func4 */ + GROUP(lcd_clk_a, 4), + GROUP(uart_f_tx_a, 4), + GROUP(uart_f_rx_a, 4), + + /* Bank A func5 */ + GROUP(uart_e_tx_a, 5), + GROUP(uart_e_rx_a, 5), + GROUP(pwm_m_a, 5), + GROUP(pwm_n_a, 5), + + /* Bank A func6 */ + GROUP(spi_a_mosi_a, 6), + GROUP(gen_clk_a4, 6), + GROUP(clk12_24_a, 6), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIO_TEST_N", + + "GPIOE_0", "GPIOE_1", "GPIOE_2", "GPIOE_3", "GPIOE_4", + + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", + "GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", + "GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13", + "GPIOB_14", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", + "GPIOC_5", "GPIOC_6", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", + + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", + "GPIOD_5", "GPIOD_6", + + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", + "GPIOA_5", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx_b", "uart_a_rx_b", "uart_a_cts_b", "uart_a_rts_b", + "uart_a_rx_c", "uart_a_tx_c", "uart_a_rx_x", "uart_a_tx_x", + "uart_a_tx_d", "uart_a_rx_d", +}; + +static const char * const uart_b_groups[] = { + "uart_b_rx_c", "uart_b_tx_c", "uart_b_tx_a", "uart_b_rx_a", +}; + +static const char * const uart_c_groups[] = { + "uart_c_rx_c", "uart_c_tx_c", + "uart_c_rx_x", "uart_c_tx_x", + "uart_c_tx_d", "uart_c_rx_d", +}; + +static const char * const uart_d_groups[] = { + "uart_d_tx_b", "uart_d_rx_b", "uart_d_tx_d", "uart_d_rx_d", + "uart_d_rx_x", "uart_d_tx_x", +}; + +static const char * const uart_e_groups[] = { + "uart_e_cts", "uart_e_tx_x", "uart_e_rx_x", "uart_e_rts", + "uart_e_tx_a", "uart_e_rx_a", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sda_e", "i2c0_scl_e", + "i2c0_sda_d", "i2c0_scl_d", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sda_x", "i2c1_scl_x", + "i2c1_sda_d", "i2c1_scl_d", + "i2c1_sda_a", "i2c1_scl_a", + "i2c1_sda_b", "i2c1_scl_b", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sda", "i2c2_scl", +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_c", "i2c3_scl_c", + "i2c3_sda_x", "i2c3_scl_x", + "i2c3_sda_d", "i2c3_scl_d", +}; + +static const char * const i2c_slave_groups[] = { + "i2c_slave_scl", "i2c_slave_sda", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f", +}; + +static const char * const pwm_g_groups[] = { + "pwm_g_b", "pwm_g_c", "pwm_g_d", "pwm_g_x0", "pwm_g_x8", +}; + +static const char * const pwm_h_groups[] = { + "pwm_h_b", "pwm_h_c", "pwm_h_d", "pwm_h_x1", "pwm_h_x9", +}; + +static const char * const pwm_i_groups[] = { + "pwm_i_b", "pwm_i_c", "pwm_i_d", "pwm_i_x2", "pwm_i_x10", +}; + +static const char * const pwm_j_groups[] = { + "pwm_j_c", "pwm_j_d", "pwm_j_b", "pwm_j_x3", "pwm_j_x12", +}; + +static const char * const pwm_k_groups[] = { + "pwm_k_c", "pwm_k_d", "pwm_k_b", "pwm_k_x4", "pwm_k_x13", +}; + +static const char * const pwm_l_groups[] = { + "pwm_l_c", "pwm_l_x", "pwm_l_b", "pwm_l_a", +}; + +static const char * const pwm_m_groups[] = { + "pwm_m_c", "pwm_m_x", "pwm_m_a", "pwm_m_b", +}; + +static const char * const pwm_n_groups[] = { + "pwm_n_x", "pwm_n_a", "pwm_n_b", +}; + +static const char * const pwm_c_hiz_groups[] = { + "pwm_c_hiz", +}; + +static const char * const ir_out_groups[] = { + "ir_out", +}; + +static const char * const ir_in_groups[] = { + "ir_in_d0", "ir_in_d6", +}; + +static const char * const jtag_a_groups[] = { + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo", +}; + +static const char * const jtag_b_groups[] = { + "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms", +}; + +static const char * const gen_clk_groups[] = { + "gen_clk_e", "gen_clk_c", "gen_clk_a", "gen_clk_x", + "gen_clk_a4", +}; + +static const char * const clk12_24_groups[] = { + "clk12_24_e", "clk12_24_c", "clk12_24_x", "clk12_24_a", + "clk12_24_x13", "clk12_24_x11", +}; + +static const char * const clk_32k_in_groups[] = { + "clk_32k_in", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", + "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", + "nand_ce0", +}; + +static const char * const spif_groups[] = { + "spif_mo", "spif_mi", "spif_wp", "spif_cs", + "spif_clk", "spif_hold", "spif_clk_loop", +}; + +static const char * const spi_a_groups[] = { + "spi_a_clk_b", "spi_a_ss0_b", "spi_a_ss1_b", "spi_a_ss2_b", + "spi_a_mosi_b", "spi_a_miso_b", + + "spi_a_clk_c", "spi_a_ss0_c", "spi_a_ss1_c", + "spi_a_mosi_c", "spi_a_miso_c", + + "spi_a_clk_x", "spi_a_ss0_x", "spi_a_ss1_x", "spi_a_ss2_x", + "spi_a_mosi_x", "spi_a_miso_x", + "spi_a_mosi_a", +}; + +static const char * const spi_b_groups[] = { + "spi_b_clk_x", "spi_b_ss0_x", "spi_b_ss1_x", "spi_b_ss2_x6", + "spi_b_miso_x", "spi_b_mosi_x", "spi_b_ss2_x12", + + "spi_b_clk_d", "spi_b_ss0_d", "spi_b_ss1_d", "spi_b_miso_d", + "spi_b_mosi_d", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", + "sdcard_cd", "sdcard_clk", "sdcard_cmd", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_clk", "sdio_cmd", +}; + +static const char * const pdm_groups[] = { + "pdm_dclk_c", "pdm_din0_c", "pdm_dclk_d", "pdm_din0_d", + "pdm_dclk_z", "pdm_din0_a", "pdm_dclk_b", "pdm_din0_b", + "pdm_dclk_x5", "pdm_din0_x6", "pdm_din0_x9", "pdm_dclk_x10", +}; + +static const char * const eth_groups[] = { + "eth_led_act", "eth_led_link", +}; + +static const char * const mclk_0_groups[] = { + "mclk_0_x", "mclk_0_d", +}; + +static const char * const mclk_1_groups[] = { + "mclk_1", +}; + +static const char * const tdm_groups[] = { + "tdm_d3", "tdm_d2", "tdm_fs1", "tdm_d1_x", "tdm_d0_x", + "tdm_d1_d", "tdm_d0_d", "tdm_sclk1", "tdm_fs0_x", "tdm_fs0_d", + "tdm_sclk0_x", "tdm_sclk0_d", +}; + +static const char * const lcd_groups[] = { + "lcd_d0", "lcd_d1", "lcd_d2", "lcd_d3", "lcd_d4", + "lcd_d5", "lcd_d6", "lcd_d7", "lcd_d8", "lcd_d9", + "lcd_d10", "lcd_d11", "lcd_d12", "lcd_d13", "lcd_d14", + "lcd_d15", "lcd_d16", "lcd_d17", "lcd_den", + "lcd_clk_a", "lcd_clk_x", "lcd_hs", "lcd_vs", +}; + +static struct meson_pmx_func c3_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_d), + FUNCTION(uart_e), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(i2c_slave), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(pwm_g), + FUNCTION(pwm_h), + FUNCTION(pwm_i), + FUNCTION(pwm_j), + FUNCTION(pwm_k), + FUNCTION(pwm_l), + FUNCTION(pwm_m), + FUNCTION(pwm_n), + FUNCTION(pwm_c_hiz), + FUNCTION(ir_out), + FUNCTION(ir_in), + FUNCTION(jtag_a), + FUNCTION(jtag_b), + FUNCTION(gen_clk), + FUNCTION(clk12_24), + FUNCTION(clk_32k_in), + FUNCTION(emmc), + FUNCTION(nand), + FUNCTION(spif), + FUNCTION(spi_a), + FUNCTION(spi_b), + FUNCTION(sdcard), + FUNCTION(sdio), + FUNCTION(pdm), + FUNCTION(eth), + FUNCTION(mclk_0), + FUNCTION(mclk_1), + FUNCTION(tdm), + FUNCTION(lcd), +}; + +static struct meson_bank c3_periphs_banks[] = { + /* name first last irq pullen pull dir out in ds */ + BANK_DS("X", GPIOX_0, GPIOX_13, 40, 53, + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), + BANK_DS("D", GPIOD_0, GPIOD_6, 33, 39, + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), + BANK_DS("E", GPIOE_0, GPIOE_4, 22, 26, + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), + BANK_DS("C", GPIOC_0, GPIOC_6, 15, 21, + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), + BANK_DS("B", GPIOB_0, GPIOB_14, 0, 14, + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), + BANK_DS("A", GPIOA_0, GPIOA_5, 27, 32, + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 54, 54, + 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0), +}; + +static struct meson_pmx_bank c3_periphs_pmx_banks[] = { + /* name first last reg offset */ + BANK_PMX("B", GPIOB_0, GPIOB_14, 0x00, 0), + BANK_PMX("X", GPIOX_0, GPIOX_13, 0x03, 0), + BANK_PMX("C", GPIOC_0, GPIOC_6, 0x09, 0), + BANK_PMX("A", GPIOA_0, GPIOA_5, 0x0b, 0), + BANK_PMX("D", GPIOD_0, GPIOD_6, 0x10, 0), + BANK_PMX("E", GPIOE_0, GPIOE_4, 0x12, 0), + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x02, 0), +}; + +static struct meson_axg_pmx_data c3_periphs_pmx_banks_data = { + .pmx_banks = c3_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(c3_periphs_pmx_banks), +}; + +static struct meson_pinctrl_data c3_periphs_pinctrl_data = { + .name = "periphs-banks", + .pins = c3_periphs_pins, + .groups = c3_periphs_groups, + .funcs = c3_periphs_functions, + .banks = c3_periphs_banks, + .num_pins = ARRAY_SIZE(c3_periphs_pins), + .num_groups = ARRAY_SIZE(c3_periphs_groups), + .num_funcs = ARRAY_SIZE(c3_periphs_functions), + .num_banks = ARRAY_SIZE(c3_periphs_banks), + .pmx_ops = &meson_axg_pmx_ops, + .pmx_data = &c3_periphs_pmx_banks_data, + .parse_dt = &meson_a1_parse_dt_extra, +}; + +static const struct of_device_id c3_pinctrl_dt_match[] = { + { + .compatible = "amlogic,c3-periphs-pinctrl", + .data = &c3_periphs_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, c3_pinctrl_dt_match); + +static struct platform_driver c3_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "amlogic-c3-pinctrl", + .of_match_table = c3_pinctrl_dt_match, + }, +}; +module_platform_driver(c3_pinctrl_driver); + +MODULE_AUTHOR("Huqiang Qin <huqiang.qin@amlogic.com>"); +MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic C3 SoC"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c index 80c43683c789..ae3f8d0da05f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Second generation of pinmux driver for Amlogic Meson-AXG SoC. * @@ -6,8 +7,6 @@ * * Copyright (c) 2017 Amlogic, Inc. All rights reserved. * Author: Xingyu Chen <xingyu.chen@amlogic.com> - * - * SPDX-License-Identifier: (GPL-2.0+ or MIT) */ /* diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h index aa79d7ecee00..67147ebaef1b 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2017 Baylibre SAS. * Author: Jerome Brunet <jbrunet@baylibre.com> diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index d249a035c2b9..6667c9d0238f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -1,10 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Pin controller and GPIO driver for Amlogic Meson AXG SoC. * * Copyright (c) 2017 Amlogic, Inc. All rights reserved. * Author: Xingyu Chen <xingyu.chen@amlogic.com> - * - * SPDX-License-Identifier: (GPL-2.0+ or MIT) */ #include <dt-bindings/gpio/meson-axg-gpio.h> diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index d182a575981e..2c17891ba6a9 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Pin controller and GPIO driver for Amlogic Meson G12A SoC. * @@ -8,6 +8,7 @@ */ #include <dt-bindings/gpio/meson-g12a-gpio.h> +#include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h> #include "pinctrl-meson.h" #include "pinctrl-meson-axg-pmx.h" @@ -1318,31 +1319,31 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = { static struct meson_bank meson_g12a_periphs_banks[] = { /* name first last irq pullen pull dir out in ds */ - BANK_DS("Z", GPIOZ_0, GPIOZ_15, 12, 27, - 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0), - BANK_DS("H", GPIOH_0, GPIOH_8, 28, 36, - 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0), - BANK_DS("BOOT", BOOT_0, BOOT_15, 37, 52, - 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0), - BANK_DS("C", GPIOC_0, GPIOC_7, 53, 60, - 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0), - BANK_DS("A", GPIOA_0, GPIOA_15, 61, 76, - 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0), - BANK_DS("X", GPIOX_0, GPIOX_19, 77, 96, - 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0), + BANK_DS("Z", GPIOZ_0, GPIOZ_15, IRQID_GPIOZ_0, IRQID_GPIOZ_15, + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0), + BANK_DS("H", GPIOH_0, GPIOH_8, IRQID_GPIOH_0, IRQID_GPIOH_8, + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0), + BANK_DS("BOOT", BOOT_0, BOOT_15, IRQID_BOOT_0, IRQID_BOOT_15, + 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0), + BANK_DS("C", GPIOC_0, GPIOC_7, IRQID_GPIOC_0, IRQID_GPIOC_7, + 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0), + BANK_DS("A", GPIOA_0, GPIOA_15, IRQID_GPIOA_0, IRQID_GPIOA_15, + 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0), + BANK_DS("X", GPIOX_0, GPIOX_19, IRQID_GPIOX_0, IRQID_GPIOX_19, + 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0), }; static struct meson_bank meson_g12a_aobus_banks[] = { /* name first last irq pullen pull dir out in ds */ - BANK_DS("AO", GPIOAO_0, GPIOAO_11, 0, 11, 3, 0, 2, 0, 0, 0, 4, 0, 1, 0, - 0, 0), + BANK_DS("AO", GPIOAO_0, GPIOAO_11, IRQID_GPIOAO_0, IRQID_GPIOAO_11, + 3, 0, 2, 0, 0, 0, 4, 0, 1, 0, 0, 0), /* GPIOE actually located in the AO bank */ - BANK_DS("E", GPIOE_0, GPIOE_2, 97, 99, 3, 16, 2, 16, 0, 16, 4, 16, 1, - 16, 1, 0), + BANK_DS("E", GPIOE_0, GPIOE_2, IRQID_GPIOE_0, IRQID_GPIOE_2, + 3, 16, 2, 16, 0, 16, 4, 16, 1, 16, 1, 0), }; static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { - /* name first lask reg offset */ + /* name first last reg offset */ BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0), diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 530f3f934e19..524424ee6c4e 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -43,7 +43,6 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/mvebu/pinctrl-ac5.c b/drivers/pinctrl/mvebu/pinctrl-ac5.c index 292633e61129..09ddfc434c6b 100644 --- a/drivers/pinctrl/mvebu/pinctrl-ac5.c +++ b/drivers/pinctrl/mvebu/pinctrl-ac5.c @@ -12,7 +12,6 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-mvebu.h" diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index d3195557a901..a50c2183e49a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -13,7 +13,6 @@ #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-mvebu.h" diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index e6aaa3708e58..64e2096a05e4 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -13,7 +13,6 @@ #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-mvebu.h" diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 67c6751a6f06..c34719b7506d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -13,8 +13,6 @@ #include <linux/gpio/driver.h> #include <linux/mfd/syscon.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/of_irq.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> @@ -1013,7 +1011,6 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, return 0; } -#if defined(CONFIG_PM) static int armada_3700_pinctrl_suspend(struct device *dev) { struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); @@ -1107,15 +1104,8 @@ static int armada_3700_pinctrl_resume(struct device *dev) * Since pinctrl is an infrastructure module, its resume should be issued prior * to other IO drivers. */ -static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = { - .suspend_noirq = armada_3700_pinctrl_suspend, - .resume_noirq = armada_3700_pinctrl_resume, -}; - -#define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops) -#else -#define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL -#endif /* CONFIG_PM */ +static DEFINE_NOIRQ_DEV_PM_OPS(armada_3700_pinctrl_pm_ops, + armada_3700_pinctrl_suspend, armada_3700_pinctrl_resume); static const struct of_device_id armada_37xx_pinctrl_of_match[] = { { @@ -1182,7 +1172,7 @@ static struct platform_driver armada_37xx_pinctrl_driver = { .driver = { .name = "armada-37xx-pinctrl", .of_match_table = armada_37xx_pinctrl_of_match, - .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS, + .pm = pm_sleep_ptr(&armada_3700_pinctrl_pm_ops), }, }; diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index 545486d98532..bd74daa9ed66 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c @@ -784,8 +784,7 @@ static int dove_pinctrl_probe(struct platform_device *pdev) } clk_prepare_enable(clk); - mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, mpp_res); + base = devm_platform_get_and_ioremap_resource(pdev, 0, &mpp_res); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 8e6aac4164df..84a119718f86 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -11,8 +11,6 @@ #include <linux/io.h> #include <linux/mfd/syscon.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/seq_file.h> diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 3ae043b27463..7daff9f186cd 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -14,7 +14,7 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c index 224a12ce70ed..440ff1879424 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -12,7 +12,7 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-s32.h" diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 4dff656af3ad..74241b2ff21e 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -748,7 +748,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, break; default: - dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", + dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; } @@ -798,7 +798,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, break; default: - dev_err(&gpio_dev->pdev->dev, + dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); ret = -ENOTSUPP; } diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 5d360ba3abc2..383309e533c3 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -939,10 +939,9 @@ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, if (!atmel_pioctrl->pins[pin_id]->device) return; - if (atmel_pioctrl->pins[pin_id]) - seq_printf(s, " (%s, ioset %u) ", - atmel_pioctrl->pins[pin_id]->device, - atmel_pioctrl->pins[pin_id]->ioset); + seq_printf(s, " (%s, ioset %u) ", + atmel_pioctrl->pins[pin_id]->device, + atmel_pioctrl->pins[pin_id]->ioset); conf = atmel_pin_config_read(pctldev, pin_id); if (conf & ATMEL_PIO_PUEN_MASK) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 39956d821ad7..608f55c5ba5f 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1657,7 +1657,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) return 0; } -static int __maybe_unused at91_gpio_suspend(struct device *dev) +static int at91_gpio_suspend(struct device *dev) { struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev); void __iomem *pio = at91_chip->regbase; @@ -1675,7 +1675,7 @@ static int __maybe_unused at91_gpio_suspend(struct device *dev) return 0; } -static int __maybe_unused at91_gpio_resume(struct device *dev) +static int at91_gpio_resume(struct device *dev) { struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev); void __iomem *pio = at91_chip->regbase; @@ -1903,15 +1903,13 @@ static int at91_gpio_probe(struct platform_device *pdev) return 0; } -static const struct dev_pm_ops at91_gpio_pm_ops = { - NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume) -}; +static DEFINE_NOIRQ_DEV_PM_OPS(at91_gpio_pm_ops, at91_gpio_suspend, at91_gpio_resume); static struct platform_driver at91_gpio_driver = { .driver = { .name = "gpio-at91", .of_match_table = at91_gpio_of_match, - .pm = pm_ptr(&at91_gpio_pm_ops), + .pm = pm_sleep_ptr(&at91_gpio_pm_ops), }, .probe = at91_gpio_probe, }; diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index b3ba25435c34..9f5b3ab8e184 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -15,7 +15,6 @@ #include <linux/mfd/axp20x.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 2ecc96691c55..58ca6fac7849 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -164,6 +164,7 @@ struct cy8c95x0_pinctrl { struct pinctrl_desc pinctrl_desc; char name[32]; unsigned int tpin; + struct gpio_desc *gpio_reset; }; static const struct pinctrl_pin_desc cy8c9560_pins[] = { @@ -1383,6 +1384,20 @@ static int cy8c95x0_probe(struct i2c_client *client) chip->regulator = reg; } + /* bring the chip out of reset if reset pin is provided */ + chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(chip->gpio_reset)) { + ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset), + "Failed to get GPIO 'reset'\n"); + goto err_exit; + } else if (chip->gpio_reset) { + usleep_range(1000, 2000); + gpiod_set_value_cansleep(chip->gpio_reset, 0); + usleep_range(250000, 300000); + + gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); + } + chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap); if (IS_ERR(chip->regmap)) { ret = PTR_ERR(chip->regmap); diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index 97920fb517bc..b6d1ed9ec9a3 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -7,7 +7,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/mfd/syscon.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/seq_file.h> diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index 13c041dd2ce0..0f5a7bed2f81 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -12,8 +12,8 @@ #include <linux/clk.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> diff --git a/drivers/pinctrl/pinctrl-mcp23s08_spi.c b/drivers/pinctrl/pinctrl-mcp23s08_spi.c index 9ae10318f6f3..ea059b9c5542 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08_spi.c +++ b/drivers/pinctrl/pinctrl-mcp23s08_spi.c @@ -91,18 +91,28 @@ static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, mcp->reg_shift = 0; mcp->chip.ngpio = 8; mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", addr); + if (!mcp->chip.label) + return -ENOMEM; config = &mcp23x08_regmap; name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + if (!name) + return -ENOMEM; + break; case MCP_TYPE_S17: mcp->reg_shift = 1; mcp->chip.ngpio = 16; mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", addr); + if (!mcp->chip.label) + return -ENOMEM; config = &mcp23x17_regmap; name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + if (!name) + return -ENOMEM; + break; case MCP_TYPE_S18: diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c index d9944e6a0af9..7d1713824a89 100644 --- a/drivers/pinctrl/pinctrl-mlxbf3.c +++ b/drivers/pinctrl/pinctrl-mlxbf3.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause +// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause /* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */ #include <linux/bitfield.h> @@ -223,26 +223,12 @@ static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static void mlxbf3_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); - - /* disable GPIO functionality by giving control back to hardware */ - if (offset < MLXBF3_NGPIOS_GPIO0) - writel(BIT(offset), priv->fw_ctrl_clr0); - else - writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1); -} - static const struct pinmux_ops mlxbf3_pmx_ops = { .get_functions_count = mlxbf3_pmx_get_funcs_count, .get_function_name = mlxbf3_pmx_get_func_name, .get_function_groups = mlxbf3_pmx_get_groups, .set_mux = mlxbf3_pmx_set, .gpio_request_enable = mlxbf3_gpio_request_enable, - .gpio_disable_free = mlxbf3_gpio_disable_free, }; static struct pinctrl_desc mlxbf3_pin_desc = { diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 1dcbd0937ef5..f8ae2e974221 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -11,9 +11,7 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/mfd/ocelot.h> -#include <linux/of_device.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset.h> diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c deleted file mode 100644 index fb10a8473ebe..000000000000 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ /dev/null @@ -1,1292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Oxford Semiconductor OXNAS SoC Family pinctrl driver - * - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> - * - * Based on pinctrl-pic32.c - * Joshua Henderson, <joshua.henderson@microchip.com> - * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. - */ -#include <linux/gpio/driver.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/regmap.h> -#include <linux/mfd/syscon.h> - -#include "pinctrl-utils.h" - -#define PINS_PER_BANK 32 - -#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) - -/* OX810 Regmap Offsets */ -#define PINMUX_810_PRIMARY_SEL0 0x0c -#define PINMUX_810_SECONDARY_SEL0 0x14 -#define PINMUX_810_TERTIARY_SEL0 0x8c -#define PINMUX_810_PRIMARY_SEL1 0x10 -#define PINMUX_810_SECONDARY_SEL1 0x18 -#define PINMUX_810_TERTIARY_SEL1 0x90 -#define PINMUX_810_PULLUP_CTRL0 0xac -#define PINMUX_810_PULLUP_CTRL1 0xb0 - -/* OX820 Regmap Offsets */ -#define PINMUX_820_BANK_OFFSET 0x100000 -#define PINMUX_820_SECONDARY_SEL 0x14 -#define PINMUX_820_TERTIARY_SEL 0x8c -#define PINMUX_820_QUATERNARY_SEL 0x94 -#define PINMUX_820_DEBUG_SEL 0x9c -#define PINMUX_820_ALTERNATIVE_SEL 0xa4 -#define PINMUX_820_PULLUP_CTRL 0xac - -/* GPIO Registers */ -#define INPUT_VALUE 0x00 -#define OUTPUT_EN 0x04 -#define IRQ_PENDING 0x0c -#define OUTPUT_SET 0x14 -#define OUTPUT_CLEAR 0x18 -#define OUTPUT_EN_SET 0x1c -#define OUTPUT_EN_CLEAR 0x20 -#define RE_IRQ_ENABLE 0x28 -#define FE_IRQ_ENABLE 0x2c - -struct oxnas_function { - const char *name; - const char * const *groups; - unsigned int ngroups; -}; - -struct oxnas_pin_group { - const char *name; - unsigned int pin; - unsigned int bank; - struct oxnas_desc_function *functions; -}; - -struct oxnas_desc_function { - const char *name; - unsigned int fct; -}; - -struct oxnas_gpio_bank { - void __iomem *reg_base; - struct gpio_chip gpio_chip; - struct irq_chip irq_chip; - unsigned int id; -}; - -struct oxnas_pinctrl { - struct regmap *regmap; - struct device *dev; - struct pinctrl_dev *pctldev; - const struct oxnas_function *functions; - unsigned int nfunctions; - const struct oxnas_pin_group *groups; - unsigned int ngroups; - struct oxnas_gpio_bank *gpio_banks; - unsigned int nbanks; -}; - -struct oxnas_pinctrl_data { - struct pinctrl_desc *desc; - struct oxnas_pinctrl *pctl; -}; - -static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = { - PINCTRL_PIN(0, "gpio0"), - PINCTRL_PIN(1, "gpio1"), - PINCTRL_PIN(2, "gpio2"), - PINCTRL_PIN(3, "gpio3"), - PINCTRL_PIN(4, "gpio4"), - PINCTRL_PIN(5, "gpio5"), - PINCTRL_PIN(6, "gpio6"), - PINCTRL_PIN(7, "gpio7"), - PINCTRL_PIN(8, "gpio8"), - PINCTRL_PIN(9, "gpio9"), - PINCTRL_PIN(10, "gpio10"), - PINCTRL_PIN(11, "gpio11"), - PINCTRL_PIN(12, "gpio12"), - PINCTRL_PIN(13, "gpio13"), - PINCTRL_PIN(14, "gpio14"), - PINCTRL_PIN(15, "gpio15"), - PINCTRL_PIN(16, "gpio16"), - PINCTRL_PIN(17, "gpio17"), - PINCTRL_PIN(18, "gpio18"), - PINCTRL_PIN(19, "gpio19"), - PINCTRL_PIN(20, "gpio20"), - PINCTRL_PIN(21, "gpio21"), - PINCTRL_PIN(22, "gpio22"), - PINCTRL_PIN(23, "gpio23"), - PINCTRL_PIN(24, "gpio24"), - PINCTRL_PIN(25, "gpio25"), - PINCTRL_PIN(26, "gpio26"), - PINCTRL_PIN(27, "gpio27"), - PINCTRL_PIN(28, "gpio28"), - PINCTRL_PIN(29, "gpio29"), - PINCTRL_PIN(30, "gpio30"), - PINCTRL_PIN(31, "gpio31"), - PINCTRL_PIN(32, "gpio32"), - PINCTRL_PIN(33, "gpio33"), - PINCTRL_PIN(34, "gpio34"), -}; - -static const struct pinctrl_pin_desc oxnas_ox820_pins[] = { - PINCTRL_PIN(0, "gpio0"), - PINCTRL_PIN(1, "gpio1"), - PINCTRL_PIN(2, "gpio2"), - PINCTRL_PIN(3, "gpio3"), - PINCTRL_PIN(4, "gpio4"), - PINCTRL_PIN(5, "gpio5"), - PINCTRL_PIN(6, "gpio6"), - PINCTRL_PIN(7, "gpio7"), - PINCTRL_PIN(8, "gpio8"), - PINCTRL_PIN(9, "gpio9"), - PINCTRL_PIN(10, "gpio10"), - PINCTRL_PIN(11, "gpio11"), - PINCTRL_PIN(12, "gpio12"), - PINCTRL_PIN(13, "gpio13"), - PINCTRL_PIN(14, "gpio14"), - PINCTRL_PIN(15, "gpio15"), - PINCTRL_PIN(16, "gpio16"), - PINCTRL_PIN(17, "gpio17"), - PINCTRL_PIN(18, "gpio18"), - PINCTRL_PIN(19, "gpio19"), - PINCTRL_PIN(20, "gpio20"), - PINCTRL_PIN(21, "gpio21"), - PINCTRL_PIN(22, "gpio22"), - PINCTRL_PIN(23, "gpio23"), - PINCTRL_PIN(24, "gpio24"), - PINCTRL_PIN(25, "gpio25"), - PINCTRL_PIN(26, "gpio26"), - PINCTRL_PIN(27, "gpio27"), - PINCTRL_PIN(28, "gpio28"), - PINCTRL_PIN(29, "gpio29"), - PINCTRL_PIN(30, "gpio30"), - PINCTRL_PIN(31, "gpio31"), - PINCTRL_PIN(32, "gpio32"), - PINCTRL_PIN(33, "gpio33"), - PINCTRL_PIN(34, "gpio34"), - PINCTRL_PIN(35, "gpio35"), - PINCTRL_PIN(36, "gpio36"), - PINCTRL_PIN(37, "gpio37"), - PINCTRL_PIN(38, "gpio38"), - PINCTRL_PIN(39, "gpio39"), - PINCTRL_PIN(40, "gpio40"), - PINCTRL_PIN(41, "gpio41"), - PINCTRL_PIN(42, "gpio42"), - PINCTRL_PIN(43, "gpio43"), - PINCTRL_PIN(44, "gpio44"), - PINCTRL_PIN(45, "gpio45"), - PINCTRL_PIN(46, "gpio46"), - PINCTRL_PIN(47, "gpio47"), - PINCTRL_PIN(48, "gpio48"), - PINCTRL_PIN(49, "gpio49"), -}; - -static const char * const oxnas_ox810se_fct0_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio28", "gpio29", "gpio30", "gpio31", - "gpio32", "gpio33", "gpio34" -}; - -static const char * const oxnas_ox810se_fct3_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio20", - "gpio22", "gpio23", "gpio24", "gpio25", - "gpio26", "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32", "gpio33", - "gpio34" -}; - -static const char * const oxnas_ox820_fct0_group[] = { - "gpio0", "gpio1", "gpio2", "gpio3", - "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio28", "gpio29", "gpio30", "gpio31", - "gpio32", "gpio33", "gpio34", "gpio35", - "gpio36", "gpio37", "gpio38", "gpio39", - "gpio40", "gpio41", "gpio42", "gpio43", - "gpio44", "gpio45", "gpio46", "gpio47", - "gpio48", "gpio49" -}; - -static const char * const oxnas_ox820_fct1_group[] = { - "gpio3", "gpio4", - "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24" -}; - -static const char * const oxnas_ox820_fct4_group[] = { - "gpio5", "gpio6", "gpio7", "gpio8", - "gpio24", "gpio25", "gpio26", "gpio27", - "gpio40", "gpio41", "gpio42", "gpio43" -}; - -static const char * const oxnas_ox820_fct5_group[] = { - "gpio28", "gpio29", "gpio30", "gpio31" -}; - -#define FUNCTION(_name, _gr) \ - { \ - .name = #_name, \ - .groups = oxnas_##_gr##_group, \ - .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \ - } - -static const struct oxnas_function oxnas_ox810se_functions[] = { - FUNCTION(gpio, ox810se_fct0), - FUNCTION(fct3, ox810se_fct3), -}; - -static const struct oxnas_function oxnas_ox820_functions[] = { - FUNCTION(gpio, ox820_fct0), - FUNCTION(fct1, ox820_fct1), - FUNCTION(fct4, ox820_fct4), - FUNCTION(fct5, ox820_fct5), -}; - -#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \ - { \ - .name = #_name, \ - .pin = _pin, \ - .bank = _pin / PINS_PER_BANK, \ - .functions = (struct oxnas_desc_function[]){ \ - __VA_ARGS__, { } }, \ - } - -#define OXNAS_PINCTRL_FUNCTION(_name, _fct) \ - { \ - .name = #_name, \ - .fct = _fct, \ - } - -static const struct oxnas_pin_group oxnas_ox810se_groups[] = { - OXNAS_PINCTRL_GROUP(0, gpio0, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(1, gpio1, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(2, gpio2, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(3, gpio3, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(4, gpio4, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(5, gpio5, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(6, gpio6, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(7, gpio7, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(8, gpio8, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(9, gpio9, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(10, gpio10, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(11, gpio11, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(12, gpio12, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(13, gpio13, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(14, gpio14, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(15, gpio15, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(16, gpio16, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(17, gpio17, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(18, gpio18, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(19, gpio19, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(20, gpio20, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(21, gpio21, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(22, gpio22, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(23, gpio23, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(24, gpio24, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(25, gpio25, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(26, gpio26, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(27, gpio27, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(28, gpio28, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(29, gpio29, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(30, gpio30, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(31, gpio31, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(32, gpio32, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(33, gpio33, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), - OXNAS_PINCTRL_GROUP(34, gpio34, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct3, 3)), -}; - -static const struct oxnas_pin_group oxnas_ox820_groups[] = { - OXNAS_PINCTRL_GROUP(0, gpio0, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(1, gpio1, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(2, gpio2, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(3, gpio3, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(4, gpio4, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(5, gpio5, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(6, gpio6, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(7, gpio7, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(8, gpio8, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(9, gpio9, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(10, gpio10, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(11, gpio11, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(12, gpio12, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(13, gpio13, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(14, gpio14, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(15, gpio15, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(16, gpio16, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(17, gpio17, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(18, gpio18, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(19, gpio19, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(20, gpio20, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(21, gpio21, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(22, gpio22, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(23, gpio23, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1)), - OXNAS_PINCTRL_GROUP(24, gpio24, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct1, 1), - OXNAS_PINCTRL_FUNCTION(fct4, 5)), - OXNAS_PINCTRL_GROUP(25, gpio25, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(26, gpio26, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(27, gpio27, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(28, gpio28, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(29, gpio29, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(30, gpio30, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(31, gpio31, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct5, 5)), - OXNAS_PINCTRL_GROUP(32, gpio32, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(33, gpio33, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(34, gpio34, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(35, gpio35, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(36, gpio36, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(37, gpio37, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(38, gpio38, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(39, gpio39, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(40, gpio40, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(41, gpio41, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(42, gpio42, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(43, gpio43, - OXNAS_PINCTRL_FUNCTION(gpio, 0), - OXNAS_PINCTRL_FUNCTION(fct4, 4)), - OXNAS_PINCTRL_GROUP(44, gpio44, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(45, gpio45, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(46, gpio46, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(47, gpio47, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(48, gpio48, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), - OXNAS_PINCTRL_GROUP(49, gpio49, - OXNAS_PINCTRL_FUNCTION(gpio, 0)), -}; - -static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl, - unsigned int pin) -{ - return &pctl->gpio_banks[pin / PINS_PER_BANK]; -} - -static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->ngroups; -} - -static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->groups[group].name; -} - -static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *pins = &pctl->groups[group].pin; - *num_pins = 1; - - return 0; -} - -static const struct pinctrl_ops oxnas_pinctrl_ops = { - .get_groups_count = oxnas_pinctrl_get_groups_count, - .get_group_name = oxnas_pinctrl_get_group_name, - .get_group_pins = oxnas_pinctrl_get_group_pins, - .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, - .dt_free_map = pinctrl_utils_free_map, -}; - -static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->nfunctions; -} - -static const char * -oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - return pctl->functions[func].name; -} - -static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev, - unsigned int func, - const char * const **groups, - unsigned int * const num_groups) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctl->functions[func].groups; - *num_groups = pctl->functions[func].ngroups; - - return 0; -} - -static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned int func, unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pin_group *pg = &pctl->groups[group]; - const struct oxnas_function *pf = &pctl->functions[func]; - const char *fname = pf->name; - struct oxnas_desc_function *functions = pg->functions; - u32 mask = BIT(pg->pin); - - while (functions->name) { - if (!strcmp(functions->name, fname)) { - dev_dbg(pctl->dev, - "setting function %s bank %d pin %d fct %d mask %x\n", - fname, pg->bank, pg->pin, - functions->fct, mask); - - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_PRIMARY_SEL1 : - PINMUX_810_PRIMARY_SEL0), - mask, - (functions->fct == 1 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_SECONDARY_SEL1 : - PINMUX_810_SECONDARY_SEL0), - mask, - (functions->fct == 2 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - (pg->bank ? - PINMUX_810_TERTIARY_SEL1 : - PINMUX_810_TERTIARY_SEL0), - mask, - (functions->fct == 3 ? - mask : 0)); - - return 0; - } - - functions++; - } - - dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); - - return -EINVAL; -} - -static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned int func, unsigned int group) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pin_group *pg = &pctl->groups[group]; - const struct oxnas_function *pf = &pctl->functions[func]; - const char *fname = pf->name; - struct oxnas_desc_function *functions = pg->functions; - unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(pg->pin); - - while (functions->name) { - if (!strcmp(functions->name, fname)) { - dev_dbg(pctl->dev, - "setting function %s bank %d pin %d fct %d mask %x\n", - fname, pg->bank, pg->pin, - functions->fct, mask); - - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_SECONDARY_SEL, - mask, - (functions->fct == 1 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_TERTIARY_SEL, - mask, - (functions->fct == 2 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_QUATERNARY_SEL, - mask, - (functions->fct == 3 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_DEBUG_SEL, - mask, - (functions->fct == 4 ? - mask : 0)); - regmap_write_bits(pctl->regmap, - offset + PINMUX_820_ALTERNATIVE_SEL, - mask, - (functions->fct == 5 ? - mask : 0)); - - return 0; - } - - functions++; - } - - dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); - - return -EINVAL; -} - -static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); - u32 mask = BIT(offset - bank->gpio_chip.base); - - dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n", - offset, bank->gpio_chip.base, bank->id, mask); - - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_PRIMARY_SEL1 : - PINMUX_810_PRIMARY_SEL0), - mask, 0); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_SECONDARY_SEL1 : - PINMUX_810_SECONDARY_SEL0), - mask, 0); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_TERTIARY_SEL1 : - PINMUX_810_TERTIARY_SEL0), - mask, 0); - - return 0; -} - -static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(offset - bank->gpio_chip.base); - - dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n", - offset, bank->gpio_chip.base, bank->id, mask); - - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_SECONDARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_TERTIARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_QUATERNARY_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_DEBUG_SEL, - mask, 0); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_ALTERNATIVE_SEL, - mask, 0); - - return 0; -} - -static int oxnas_gpio_get_direction(struct gpio_chip *chip, - unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int oxnas_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR); - - return 0; -} - -static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0; -} - -static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - if (value) - writel_relaxed(mask, bank->reg_base + OUTPUT_SET); - else - writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR); -} - -static int oxnas_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(offset); - - oxnas_gpio_set(chip, offset, value); - writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET); - - return 0; -} - -static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset, bool input) -{ - struct gpio_chip *chip = range->gc; - - if (input) - oxnas_gpio_direction_input(chip, offset); - else - oxnas_gpio_direction_output(chip, offset, 0); - - return 0; -} - -static const struct pinmux_ops oxnas_ox810se_pinmux_ops = { - .get_functions_count = oxnas_pinmux_get_functions_count, - .get_function_name = oxnas_pinmux_get_function_name, - .get_function_groups = oxnas_pinmux_get_function_groups, - .set_mux = oxnas_ox810se_pinmux_enable, - .gpio_request_enable = oxnas_ox810se_gpio_request_enable, - .gpio_set_direction = oxnas_gpio_set_direction, -}; - -static const struct pinmux_ops oxnas_ox820_pinmux_ops = { - .get_functions_count = oxnas_pinmux_get_functions_count, - .get_function_name = oxnas_pinmux_get_function_name, - .get_function_groups = oxnas_pinmux_get_function_groups, - .set_mux = oxnas_ox820_pinmux_enable, - .gpio_request_enable = oxnas_ox820_gpio_request_enable, - .gpio_set_direction = oxnas_gpio_set_direction, -}; - -static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param = pinconf_to_config_param(*config); - u32 mask = BIT(pin - bank->gpio_chip.base); - int ret; - u32 arg; - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - ret = regmap_read(pctl->regmap, - (bank->id ? - PINMUX_810_PULLUP_CTRL1 : - PINMUX_810_PULLUP_CTRL0), - &arg); - if (ret) - return ret; - - arg = !!(arg & mask); - break; - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param = pinconf_to_config_param(*config); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - u32 mask = BIT(pin - bank->gpio_chip.base); - int ret; - u32 arg; - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - ret = regmap_read(pctl->regmap, - bank_offset + PINMUX_820_PULLUP_CTRL, - &arg); - if (ret) - return ret; - - arg = !!(arg & mask); - break; - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned int num_configs) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int param; - unsigned int i; - u32 offset = pin - bank->gpio_chip.base; - u32 mask = BIT(offset); - - dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", - pin, bank->gpio_chip.base, mask); - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - dev_dbg(pctl->dev, " pullup\n"); - regmap_write_bits(pctl->regmap, - (bank->id ? - PINMUX_810_PULLUP_CTRL1 : - PINMUX_810_PULLUP_CTRL0), - mask, mask); - break; - default: - dev_err(pctl->dev, "Property %u not supported\n", - param); - return -ENOTSUPP; - } - } - - return 0; -} - -static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned int num_configs) -{ - struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); - unsigned int param; - unsigned int i; - u32 offset = pin - bank->gpio_chip.base; - u32 mask = BIT(offset); - - dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", - pin, bank->gpio_chip.base, mask); - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - dev_dbg(pctl->dev, " pullup\n"); - regmap_write_bits(pctl->regmap, - bank_offset + PINMUX_820_PULLUP_CTRL, - mask, mask); - break; - default: - dev_err(pctl->dev, "Property %u not supported\n", - param); - return -ENOTSUPP; - } - } - - return 0; -} - -static const struct pinconf_ops oxnas_ox810se_pinconf_ops = { - .pin_config_get = oxnas_ox810se_pinconf_get, - .pin_config_set = oxnas_ox810se_pinconf_set, - .is_generic = true, -}; - -static const struct pinconf_ops oxnas_ox820_pinconf_ops = { - .pin_config_get = oxnas_ox820_pinconf_get, - .pin_config_set = oxnas_ox820_pinconf_set, - .is_generic = true, -}; - -static void oxnas_gpio_irq_ack(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - u32 mask = BIT(data->hwirq); - - writel(mask, bank->reg_base + IRQ_PENDING); -} - -static void oxnas_gpio_irq_mask(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - unsigned int type = irqd_get_trigger_type(data); - u32 mask = BIT(data->hwirq); - - if (type & IRQ_TYPE_EDGE_RISING) - writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask, - bank->reg_base + RE_IRQ_ENABLE); - - if (type & IRQ_TYPE_EDGE_FALLING) - writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask, - bank->reg_base + FE_IRQ_ENABLE); -} - -static void oxnas_gpio_irq_unmask(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); - unsigned int type = irqd_get_trigger_type(data); - u32 mask = BIT(data->hwirq); - - if (type & IRQ_TYPE_EDGE_RISING) - writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask, - bank->reg_base + RE_IRQ_ENABLE); - - if (type & IRQ_TYPE_EDGE_FALLING) - writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask, - bank->reg_base + FE_IRQ_ENABLE); -} - -static unsigned int oxnas_gpio_irq_startup(struct irq_data *data) -{ - struct gpio_chip *chip = irq_data_get_irq_chip_data(data); - - oxnas_gpio_direction_input(chip, data->hwirq); - oxnas_gpio_irq_unmask(data); - - return 0; -} - -static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type) -{ - if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0) - return -EINVAL; - - irq_set_handler_locked(data, handle_edge_irq); - - return 0; -} - -static void oxnas_gpio_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct oxnas_gpio_bank *bank = gpiochip_get_data(gc); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned long stat; - unsigned int pin; - - chained_irq_enter(chip, desc); - - stat = readl(bank->reg_base + IRQ_PENDING); - - for_each_set_bit(pin, &stat, BITS_PER_LONG) - generic_handle_domain_irq(gc->irq.domain, pin); - - chained_irq_exit(chip, desc); -} - -#define GPIO_BANK(_bank) \ - { \ - .gpio_chip = { \ - .label = "GPIO" #_bank, \ - .request = gpiochip_generic_request, \ - .free = gpiochip_generic_free, \ - .get_direction = oxnas_gpio_get_direction, \ - .direction_input = oxnas_gpio_direction_input, \ - .direction_output = oxnas_gpio_direction_output, \ - .get = oxnas_gpio_get, \ - .set = oxnas_gpio_set, \ - .ngpio = PINS_PER_BANK, \ - .base = GPIO_BANK_START(_bank), \ - .owner = THIS_MODULE, \ - .can_sleep = 0, \ - }, \ - .irq_chip = { \ - .name = "GPIO" #_bank, \ - .irq_startup = oxnas_gpio_irq_startup, \ - .irq_ack = oxnas_gpio_irq_ack, \ - .irq_mask = oxnas_gpio_irq_mask, \ - .irq_unmask = oxnas_gpio_irq_unmask, \ - .irq_set_type = oxnas_gpio_irq_set_type, \ - }, \ - } - -static struct oxnas_gpio_bank oxnas_gpio_banks[] = { - GPIO_BANK(0), - GPIO_BANK(1), -}; - -static struct oxnas_pinctrl ox810se_pinctrl = { - .functions = oxnas_ox810se_functions, - .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions), - .groups = oxnas_ox810se_groups, - .ngroups = ARRAY_SIZE(oxnas_ox810se_groups), - .gpio_banks = oxnas_gpio_banks, - .nbanks = ARRAY_SIZE(oxnas_gpio_banks), -}; - -static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = { - .name = "oxnas-pinctrl", - .pins = oxnas_ox810se_pins, - .npins = ARRAY_SIZE(oxnas_ox810se_pins), - .pctlops = &oxnas_pinctrl_ops, - .pmxops = &oxnas_ox810se_pinmux_ops, - .confops = &oxnas_ox810se_pinconf_ops, - .owner = THIS_MODULE, -}; - -static struct oxnas_pinctrl ox820_pinctrl = { - .functions = oxnas_ox820_functions, - .nfunctions = ARRAY_SIZE(oxnas_ox820_functions), - .groups = oxnas_ox820_groups, - .ngroups = ARRAY_SIZE(oxnas_ox820_groups), - .gpio_banks = oxnas_gpio_banks, - .nbanks = ARRAY_SIZE(oxnas_gpio_banks), -}; - -static struct pinctrl_desc oxnas_ox820_pinctrl_desc = { - .name = "oxnas-pinctrl", - .pins = oxnas_ox820_pins, - .npins = ARRAY_SIZE(oxnas_ox820_pins), - .pctlops = &oxnas_pinctrl_ops, - .pmxops = &oxnas_ox820_pinmux_ops, - .confops = &oxnas_ox820_pinconf_ops, - .owner = THIS_MODULE, -}; - -static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = { - .desc = &oxnas_ox810se_pinctrl_desc, - .pctl = &ox810se_pinctrl, -}; - -static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = { - .desc = &oxnas_ox820_pinctrl_desc, - .pctl = &ox820_pinctrl, -}; - -static const struct of_device_id oxnas_pinctrl_of_match[] = { - { .compatible = "oxsemi,ox810se-pinctrl", - .data = &oxnas_ox810se_pinctrl_data - }, - { .compatible = "oxsemi,ox820-pinctrl", - .data = &oxnas_ox820_pinctrl_data, - }, - { }, -}; - -static int oxnas_pinctrl_probe(struct platform_device *pdev) -{ - const struct of_device_id *id; - const struct oxnas_pinctrl_data *data; - struct oxnas_pinctrl *pctl; - - id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node); - if (!id) - return -ENODEV; - - data = id->data; - if (!data || !data->pctl || !data->desc) - return -EINVAL; - - pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); - if (!pctl) - return -ENOMEM; - pctl->dev = &pdev->dev; - dev_set_drvdata(&pdev->dev, pctl); - - pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "oxsemi,sys-ctrl"); - if (IS_ERR(pctl->regmap)) { - dev_err(&pdev->dev, "failed to get sys ctrl regmap\n"); - return -ENODEV; - } - - pctl->functions = data->pctl->functions; - pctl->nfunctions = data->pctl->nfunctions; - pctl->groups = data->pctl->groups; - pctl->ngroups = data->pctl->ngroups; - pctl->gpio_banks = data->pctl->gpio_banks; - pctl->nbanks = data->pctl->nbanks; - - pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl); - if (IS_ERR(pctl->pctldev)) { - dev_err(&pdev->dev, "Failed to register pinctrl device\n"); - return PTR_ERR(pctl->pctldev); - } - - return 0; -} - -static int oxnas_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct of_phandle_args pinspec; - struct oxnas_gpio_bank *bank; - unsigned int id, ngpios; - int irq, ret; - struct gpio_irq_chip *girq; - - if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", - 3, 0, &pinspec)) { - dev_err(&pdev->dev, "gpio-ranges property not found\n"); - return -EINVAL; - } - - id = pinspec.args[1] / PINS_PER_BANK; - ngpios = pinspec.args[2]; - - if (id >= ARRAY_SIZE(oxnas_gpio_banks)) { - dev_err(&pdev->dev, "invalid gpio-ranges base arg\n"); - return -EINVAL; - } - - if (ngpios > PINS_PER_BANK) { - dev_err(&pdev->dev, "invalid gpio-ranges count arg\n"); - return -EINVAL; - } - - bank = &oxnas_gpio_banks[id]; - - bank->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(bank->reg_base)) - return PTR_ERR(bank->reg_base); - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - bank->id = id; - bank->gpio_chip.parent = &pdev->dev; - bank->gpio_chip.ngpio = ngpios; - girq = &bank->gpio_chip.irq; - girq->chip = &bank->irq_chip; - girq->parent_handler = oxnas_gpio_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = irq; - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_level_irq; - - ret = gpiochip_add_data(&bank->gpio_chip, bank); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", - id, ret); - return ret; - } - - return 0; -} - -static struct platform_driver oxnas_pinctrl_driver = { - .driver = { - .name = "oxnas-pinctrl", - .of_match_table = oxnas_pinctrl_of_match, - .suppress_bind_attrs = true, - }, - .probe = oxnas_pinctrl_probe, -}; - -static const struct of_device_id oxnas_gpio_of_match[] = { - { .compatible = "oxsemi,ox810se-gpio", }, - { .compatible = "oxsemi,ox820-gpio", }, - { }, -}; - -static struct platform_driver oxnas_gpio_driver = { - .driver = { - .name = "oxnas-gpio", - .of_match_table = oxnas_gpio_of_match, - .suppress_bind_attrs = true, - }, - .probe = oxnas_gpio_probe, -}; - -static int __init oxnas_gpio_register(void) -{ - return platform_driver_register(&oxnas_gpio_driver); -} -arch_initcall(oxnas_gpio_register); - -static int __init oxnas_pinctrl_register(void) -{ - return platform_driver_register(&oxnas_pinctrl_driver); -} -arch_initcall(oxnas_pinctrl_register); diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c index fecc25d35d02..9e272f9deb4f 100644 --- a/drivers/pinctrl/pinctrl-palmas.c +++ b/drivers/pinctrl/pinctrl-palmas.c @@ -11,7 +11,6 @@ #include <linux/module.h> #include <linux/mfd/palmas.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index dad05294fa72..bf827ab081a1 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -11,7 +11,6 @@ #include <linux/io.h> #include <linux/irq.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> @@ -2162,7 +2161,6 @@ static const struct irq_chip pic32_gpio_irq_chip = { static int pic32_pinctrl_probe(struct platform_device *pdev) { struct pic32_pinctrl *pctl; - struct resource *res; int ret; pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); @@ -2171,8 +2169,7 @@ static int pic32_pinctrl_probe(struct platform_device *pdev) pctl->dev = &pdev->dev; dev_set_drvdata(&pdev->dev, pctl); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pctl->reg_base = devm_ioremap_resource(&pdev->dev, res); + pctl->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctl->reg_base)) return PTR_ERR(pctl->reg_base); diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 0276b52f3716..45e416f68e74 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -21,9 +21,8 @@ #include <linux/io.h> #include <linux/bitops.h> #include <linux/gpio/driver.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_irq.h> +#include <linux/of.h> +#include <linux/of_platform.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 0dabbcf68b9f..461a7c02d4a3 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -12,14 +12,13 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/io.h> +#include <linux/platform_device.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/list.h> #include <linux/interrupt.h> #include <linux/irqchip/chained_irq.h> #include <linux/of.h> -#include <linux/of_device.h> -#include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/seq_file.h> @@ -1955,6 +1954,12 @@ static const struct pcs_soc_data pinctrl_single_am437x = { .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ }; +static const struct pcs_soc_data pinctrl_single_am654 = { + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, + .irq_enable_mask = (1 << 29), /* WKUP_EN */ + .irq_status_mask = (1 << 30), /* WKUP_EVT */ +}; + static const struct pcs_soc_data pinctrl_single = { }; @@ -1963,11 +1968,12 @@ static const struct pcs_soc_data pinconf_single = { }; static const struct of_device_id pcs_of_match[] = { + { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, + { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 }, + { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, - { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, - { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, { .compatible = "pinctrl-single", .data = &pinctrl_single }, { .compatible = "pinconf-single", .data = &pinconf_single }, { }, diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index ab23d7ac3107..0974bbf57b54 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -659,8 +659,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -ENXIO; + if (irq < 0) + return irq; mutex_init(&pctl->lock); diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 35faea8dfb0b..fef1ee7b7945 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -19,7 +19,6 @@ #include <linux/mutex.h> #include <linux/slab.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/gpio/driver.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 8d2cb0999f2f..f2be341f73e1 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -415,6 +415,10 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_ENABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; case PIN_CONFIG_MODE_LOW_POWER: /* * These cases are mentioned in dts but configurable @@ -423,6 +427,11 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, */ ret = 0; break; + case PIN_CONFIG_OUTPUT_ENABLE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_DISABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; default: dev_warn(pctldev->dev, "unsupported configuration parameter '%u'\n", diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 82c750a31952..2a180a5d64a4 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -872,7 +872,7 @@ int pinmux_generic_add_function(struct pinctrl_dev *pctldev, void *data) { struct function_desc *function; - int selector; + int selector, error; if (!name) return -EINVAL; @@ -892,7 +892,9 @@ int pinmux_generic_add_function(struct pinctrl_dev *pctldev, function->num_group_names = num_groups; function->data = data; - radix_tree_insert(&pctldev->pin_function_tree, selector, function); + error = radix_tree_insert(&pctldev->pin_function_tree, selector, function); + if (error) + return error; pctldev->num_functions++; diff --git a/drivers/pinctrl/pxa/pinctrl-pxa25x.c b/drivers/pinctrl/pxa/pinctrl-pxa25x.c index 95640698422f..2a4842557bb2 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa25x.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa25x.c @@ -7,7 +7,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-pxa2xx.h" diff --git a/drivers/pinctrl/pxa/pinctrl-pxa27x.c b/drivers/pinctrl/pxa/pinctrl-pxa27x.c index ff9302e4803a..b3acbaf8c85f 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa27x.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa27x.c @@ -7,7 +7,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-pxa2xx.h" diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 634c75336983..f84c0d3b7951 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. +config PINCTRL_SM6115_LPASS_LPI + tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform. + config PINCTRL_SM8250_LPASS_LPI tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST @@ -77,6 +86,16 @@ config PINCTRL_SM8250_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform. +config PINCTRL_SM8350_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8350 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8350 + platform. + config PINCTRL_SM8450_LPASS_LPI tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 426ddbf35f32..5910e08c84ce 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o @@ -52,6 +53,7 @@ obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o +obj-$(CONFIG_PINCTRL_SM8350_LPASS_LPI) += pinctrl-sm8350-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8550) += pinctrl-sm8550.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c index ed58f750f1eb..e2951f81c3ee 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -241,16 +241,6 @@ static const char * const atest_char_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio37", }; -static const char * const _groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", - "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", - "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", - "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", "gpio46", -}; - static const char * const wci_txd_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio42", "gpio43", "gpio44", "gpio45", diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index fdb6585a9234..e5a418026ba3 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -8,7 +8,8 @@ #include <linux/clk.h> #include <linux/gpio/driver.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/seq_file.h> #include <linux/pinctrl/pinconf-generic.h> @@ -438,11 +439,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), "Slew resource not provided\n"); - if (of_property_read_bool(dev->of_node, "qcom,adsp-bypass-mode")) - ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); - else - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); - + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) return ret; diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c index 2ade7866dbc5..3cfe8c7f04df 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx75.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c @@ -5,7 +5,6 @@ #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include "pinctrl-msm.h" diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c new file mode 100644 index 000000000000..2b09bf171a2c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, 2023 Linaro Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic01_clk, + LPI_MUX_dmic01_data, + LPI_MUX_dmic23_clk, + LPI_MUX_dmic23_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_mclk, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; + +static const struct pinctrl_pin_desc sm6115_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), +}; + +static const char * const dmic01_clk_groups[] = { "gpio6" }; +static const char * const dmic01_data_groups[] = { "gpio7" }; +static const char * const dmic23_clk_groups[] = { "gpio8" }; +static const char * const dmic23_data_groups[] = { "gpio9" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s3_clk_groups[] = { "gpio14" }; +static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" }; +static const char * const i2s3_ws_groups[] = { "gpio15" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" }; +static const char * const wsa_mclk_groups[] = { "gpio18" }; + +static const struct lpi_pingroup sm6115_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, i2s2_clk, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, i2s2_ws, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(18, 14, wsa_mclk, _, _, _), +}; + +static const struct lpi_function sm6115_functions[] = { + LPI_FUNCTION(dmic01_clk), + LPI_FUNCTION(dmic01_data), + LPI_FUNCTION(dmic23_clk), + LPI_FUNCTION(dmic23_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_mclk), +}; + +static const struct lpi_pinctrl_variant_data sm6115_lpi_data = { + .pins = sm6115_lpi_pins, + .npins = ARRAY_SIZE(sm6115_lpi_pins), + .groups = sm6115_groups, + .ngroups = ARRAY_SIZE(sm6115_groups), + .functions = sm6115_functions, + .nfunctions = ARRAY_SIZE(sm6115_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm6115-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c new file mode 100644 index 000000000000..f889c779bccd --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023 Linaro Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; + +static const struct pinctrl_pin_desc sm8350_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; + +static const struct lpi_pingroup sm8350_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sm8350_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm8350_lpi_data = { + .pins = sm8350_lpi_pins, + .npins = ARRAY_SIZE(sm8350_lpi_pins), + .groups = sm8350_groups, + .ngroups = ARRAY_SIZE(sm8350_groups), + .functions = sm8350_functions, + .nfunctions = ARRAY_SIZE(sm8350_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8350-lpass-lpi-pinctrl", + .data = &sm8350_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm8350-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; +module_platform_driver(lpi_pinctrl_driver); + +MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>"); +MODULE_DESCRIPTION("QTI SM8350 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index b4cd66886f29..deded9c6fd7d 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1205,6 +1205,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 }, { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8}, { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, @@ -1252,6 +1253,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 }, + { .compatible = "qcom,pmx75-gpio", .data = (void *) 16 }, { }, }; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index dec1ffc49ffd..e0d43d076c01 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -7,7 +7,7 @@ #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/regmap.h> diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index b5aed540f07e..985d1a0ee8f8 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -7,7 +7,7 @@ #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/regmap.h> diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 0c8d081da6a8..93e51abbf519 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -19,7 +19,6 @@ #include <linux/kernel.h> #include <linux/math.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/machine.h> #include <linux/platform_device.h> #include <linux/psci.h> @@ -649,7 +648,7 @@ static const struct of_device_id sh_pfc_of_table[] = { }; #endif -#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) +#if defined(CONFIG_ARM_PSCI_FW) static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) { } @@ -732,15 +731,13 @@ static int sh_pfc_resume_noirq(struct device *dev) sh_pfc_walk_regs(pfc, sh_pfc_restore_reg); return 0; } - -static const struct dev_pm_ops sh_pfc_pm = { - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq) -}; -#define DEV_PM_OPS &sh_pfc_pm #else static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } -#define DEV_PM_OPS NULL -#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ +static int sh_pfc_suspend_noirq(struct device *dev) { return 0; } +static int sh_pfc_resume_noirq(struct device *dev) { return 0; } +#endif /* CONFIG_ARM_PSCI_FW */ + +static DEFINE_NOIRQ_DEV_PM_OPS(sh_pfc_pm, sh_pfc_suspend_noirq, sh_pfc_resume_noirq); #ifdef DEBUG #define SH_PFC_MAX_REGS 300 @@ -1418,7 +1415,7 @@ static struct platform_driver sh_pfc_driver = { .driver = { .name = DRV_NAME, .of_match_table = of_match_ptr(sh_pfc_of_table), - .pm = DEV_PM_OPS, + .pm = pm_sleep_ptr(&sh_pfc_pm), }, }; diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index 68c7af5d86bc..f43f1196fea8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -19,11 +19,10 @@ #include <linux/ioport.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> #include <linux/property.h> #include <linux/slab.h> diff --git a/drivers/pinctrl/renesas/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c index 5591ddf16fdf..990b96d45967 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza2.c +++ b/drivers/pinctrl/renesas/pinctrl-rza2.c @@ -15,8 +15,9 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/mutex.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> #include "../core.h" #include "../pinmux.h" diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 6e8a76556e23..37cdfe4b04f9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -12,8 +12,9 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/mutex.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/of_irq.h> +#include <linux/platform_device.h> #include <linux/seq_file.h> #include <linux/spinlock.h> @@ -145,7 +146,6 @@ struct rzg2l_pinctrl { const struct rzg2l_pinctrl_data *data; void __iomem *base; struct device *dev; - struct clk *clk; struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; @@ -1478,14 +1478,10 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) return 0; } -static void rzg2l_pinctrl_clk_disable(void *data) -{ - clk_disable_unprepare(data); -} - static int rzg2l_pinctrl_probe(struct platform_device *pdev) { struct rzg2l_pinctrl *pctrl; + struct clk *clk; int ret; BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > @@ -1508,12 +1504,10 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctrl->base)) return PTR_ERR(pctrl->base); - pctrl->clk = devm_clk_get(pctrl->dev, NULL); - if (IS_ERR(pctrl->clk)) { - ret = PTR_ERR(pctrl->clk); - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); - return ret; - } + clk = devm_clk_get_enabled(pctrl->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(pctrl->dev, PTR_ERR(clk), + "failed to enable GPIO clk\n"); spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); @@ -1521,21 +1515,6 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pctrl); - ret = clk_prepare_enable(pctrl->clk); - if (ret) { - dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); - return ret; - } - - ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, - pctrl->clk); - if (ret) { - dev_err(pctrl->dev, - "failed to register GPIO clk disable action, %i\n", - ret); - return ret; - } - ret = rzg2l_pinctrl_register(pctrl); if (ret) return ret; diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index 9146101ea9e2..52aeafaba4b6 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -15,7 +15,8 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/mutex.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/spinlock.h> #include <linux/pinctrl/consumer.h> @@ -119,7 +120,6 @@ struct rzv2m_pinctrl { const struct rzv2m_pinctrl_data *data; void __iomem *base; struct device *dev; - struct clk *clk; struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; @@ -1047,14 +1047,10 @@ static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl) return 0; } -static void rzv2m_pinctrl_clk_disable(void *data) -{ - clk_disable_unprepare(data); -} - static int rzv2m_pinctrl_probe(struct platform_device *pdev) { struct rzv2m_pinctrl *pctrl; + struct clk *clk; int ret; pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); @@ -1071,33 +1067,16 @@ static int rzv2m_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctrl->base)) return PTR_ERR(pctrl->base); - pctrl->clk = devm_clk_get(pctrl->dev, NULL); - if (IS_ERR(pctrl->clk)) { - ret = PTR_ERR(pctrl->clk); - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); - return ret; - } + clk = devm_clk_get_enabled(pctrl->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(pctrl->dev, PTR_ERR(clk), + "failed to enable GPIO clk\n"); spin_lock_init(&pctrl->lock); mutex_init(&pctrl->mutex); platform_set_drvdata(pdev, pctrl); - ret = clk_prepare_enable(pctrl->clk); - if (ret) { - dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); - return ret; - } - - ret = devm_add_action_or_reset(&pdev->dev, rzv2m_pinctrl_clk_disable, - pctrl->clk); - if (ret) { - dev_err(pctrl->dev, - "failed to register GPIO clk disable action, %i\n", - ret); - return ret; - } - ret = rzv2m_pinctrl_register(pctrl); if (ret) return ret; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 833e170e3d99..e54847040b4a 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -20,7 +20,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/irqdomain.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/seq_file.h> diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c index 0180eb544f02..fb624a051e26 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1310.c +++ b/drivers/pinctrl/spear/pinctrl-spear1310.c @@ -11,7 +11,7 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c index 0ca961219b3b..48f068cf5e24 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1340.c +++ b/drivers/pinctrl/spear/pinctrl-spear1340.c @@ -11,7 +11,7 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c index d53a04597cbe..7530252ef7bc 100644 --- a/drivers/pinctrl/spear/pinctrl-spear300.c +++ b/drivers/pinctrl/spear/pinctrl-spear300.c @@ -11,7 +11,7 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c index 9d9facc4a6e4..c476e5478646 100644 --- a/drivers/pinctrl/spear/pinctrl-spear310.c +++ b/drivers/pinctrl/spear/pinctrl-spear310.c @@ -11,7 +11,7 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c index e629e3035543..401477cfbf57 100644 --- a/drivers/pinctrl/spear/pinctrl-spear320.c +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -11,7 +11,7 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index ca9659f4e4b1..ccdcc91c7fa5 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -11,7 +11,6 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/seq_file.h> #include <linux/slab.h> diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c index 8cf28aaed254..4bfe3aa57f8a 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c @@ -10,11 +10,8 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c index bc279a39613f..20c85db1cd3a 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c @@ -13,8 +13,6 @@ #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/mutex.h> -#include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/reset.h> #include <linux/spinlock.h> diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c index 5fe729b4a03d..b9081805c8f6 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c @@ -14,7 +14,6 @@ #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/reset.h> #include <linux/seq_file.h> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 4b97bd00191b..a73385a431de 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -13,9 +13,8 @@ #include <linux/irq.h> #include <linux/mfd/syscon.h> #include <linux/module.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/property.h> @@ -1275,6 +1274,28 @@ static const struct pinconf_ops stm32_pconf_ops = { .pin_config_dbg_show = stm32_pconf_dbg_show, }; +static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl, + struct stm32_gpio_bank *bank, + unsigned int offset) +{ + unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; + struct stm32_desc_pin *pin_desc; + int i; + + /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */ + pin_desc = pctl->pins + stm32_pin_nb; + if (pin_desc->pin.number == stm32_pin_nb) + return pin_desc; + + /* Otherwise, loop all array to find the pin with the right number */ + for (i = 0; i < pctl->npins; i++) { + pin_desc = pctl->pins + i; + if (pin_desc->pin.number == stm32_pin_nb) + return pin_desc; + } + return NULL; +} + static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) { struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; @@ -1285,6 +1306,8 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode struct resource res; int npins = STM32_GPIO_PINS_PER_BANK; int bank_nr, err, i = 0; + struct stm32_desc_pin *stm32_pin; + char **names; if (!IS_ERR(bank->rstc)) reset_control_deassert(bank->rstc); @@ -1354,6 +1377,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode } } + names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL); + for (i = 0; i < npins; i++) { + stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); + if (stm32_pin && stm32_pin->pin.name) + names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name); + else + names[i] = NULL; + } + + bank->gpio_chip.names = (const char * const *)names; + err = gpiochip_add_data(&bank->gpio_chip, bank); if (err) { dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); diff --git a/drivers/pinctrl/sunplus/sppctl.c b/drivers/pinctrl/sunplus/sppctl.c index 150996949ede..bb5ef391dbe4 100644 --- a/drivers/pinctrl/sunplus/sppctl.c +++ b/drivers/pinctrl/sunplus/sppctl.c @@ -11,7 +11,6 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/overflow.h> #include <linux/platform_device.h> #include <linux/seq_file.h> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c index 9cc94be1046d..8e2aab542fcf 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c @@ -9,7 +9,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index 0c7c361ebac5..fa47fe36ee5b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -13,7 +13,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c index b82ad135bf2a..6d121bec4445 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c @@ -8,7 +8,6 @@ #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c index f682e0e4244d..df90c75fb3c5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -8,7 +8,6 @@ #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c index ef261eccda56..8693cd4877e1 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c @@ -21,7 +21,6 @@ */ #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c index 7b83d3755a0e..1c23ce9df52f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c @@ -15,7 +15,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c index 96a350e70668..669793c6578e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -18,7 +18,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c index 3aba0aec3d78..394476a35cad 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c @@ -14,7 +14,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c index 3cc1121589c9..517118341316 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -8,7 +8,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c index c39ea46046c2..d1f7cfa824c5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c @@ -10,7 +10,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c index d6ca720ee8d8..73f012823a98 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c @@ -10,7 +10,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i.c b/drivers/pinctrl/sunxi/pinctrl-sun5i.c index 27ec99e81c4c..06ecb121c827 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c index 2486cdf345e1..c983243cd6fb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 82ffaf466892..82ac064931df 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -13,7 +13,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c index 4fae12c905b7..de00d3ef5e82 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -18,7 +18,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c index 402fd7d21e7b..f6b01a8a8977 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c @@ -17,7 +17,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c index f043afa1aac5..f48f3e8cbe87 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c index 0cb6c1a970c9..c6a3ab3461ac 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c @@ -24,7 +24,6 @@ */ #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c index b5c1a8f363f3..fd1c65c0180c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c index b795a199e240..45e1531697fb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c @@ -11,7 +11,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c index d1719a738c20..1c0823d50250 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c @@ -15,7 +15,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index ca85438e379a..49c9a0b6a0eb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -18,7 +18,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c index f11cb5bba0f7..919b6a20af83 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index 0633a03d5e13..61137c7f09b6 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -13,7 +13,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c index b8fc88a23cf4..bfc39cc3b3e3 100644 --- a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c +++ b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c @@ -25,7 +25,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 1dc1882cbdd7..73bcf806af0e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -18,10 +18,7 @@ #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/of.h> -#include <linux/of_address.h> #include <linux/of_clk.h> -#include <linux/of_device.h> -#include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <linux/slab.h> @@ -848,6 +845,9 @@ static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) char supply[16]; int ret; + if (WARN_ON_ONCE(bank_offset >= ARRAY_SIZE(pctl->regulators))) + return -EINVAL; + if (reg) { refcount_inc(&s_reg->refcount); return 0; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 4547cf66d03b..cfeda5b3e048 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -96,6 +96,7 @@ static const struct cfg_param { {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, + {"nvidia,function", TEGRA_PINCONF_PARAM_FUNCTION}, }; static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, @@ -470,6 +471,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *bit = g->drvtype_bit; *width = 2; break; + case TEGRA_PINCONF_PARAM_FUNCTION: + *bank = g->mux_bank; + *reg = g->mux_reg; + *bit = g->mux_bit; + *width = 2; + break; default: dev_err(pmx->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; @@ -633,8 +640,16 @@ static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, val >>= bit; val &= (1 << width) - 1; - seq_printf(s, "\n\t%s=%u", - strip_prefix(cfg_params[i].property), val); + if (cfg_params[i].param == TEGRA_PINCONF_PARAM_FUNCTION) { + u8 idx = pmx->soc->groups[group].funcs[val]; + + seq_printf(s, "\n\t%s=%s", + strip_prefix(cfg_params[i].property), + pmx->functions[idx].name); + } else { + seq_printf(s, "\n\t%s=%u", + strip_prefix(cfg_params[i].property), val); + } } } @@ -747,10 +762,7 @@ static int tegra_pinctrl_resume(struct device *dev) return 0; } -const struct dev_pm_ops tegra_pinctrl_pm = { - .suspend_noirq = &tegra_pinctrl_suspend, - .resume_noirq = &tegra_pinctrl_resume -}; +DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume); static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx) { diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index b3289bdf727d..e728efeaa4de 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -54,6 +54,8 @@ enum tegra_pinconf_param { TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, /* argument: Integer, range is HW-dependant */ TEGRA_PINCONF_PARAM_DRIVE_TYPE, + /* argument: pinmux settings */ + TEGRA_PINCONF_PARAM_FUNCTION, }; enum tegra_pinconf_pull { diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c index 69f58df62897..6d77954d286b 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c @@ -16,7 +16,6 @@ #include <linux/init.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c index 9bb29146dfff..bc668b9c2ae0 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c @@ -1570,7 +1570,7 @@ static struct platform_driver tegra210_pinctrl_driver = { .driver = { .name = "tegra210-pinctrl", .of_match_table = tegra210_pinctrl_of_match, - .pm = &tegra_pinctrl_pm, + .pm = pm_sleep_ptr(&tegra_pinctrl_pm), }, .probe = tegra210_pinctrl_probe, }; diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 53abddaebce1..c1477f657839 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -849,19 +849,12 @@ static int ti_iodelay_probe(struct platform_device *pdev) iod->reg_data = match->data; /* So far We can assume there is only 1 bank of registers */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "Missing MEM resource\n"); - ret = -ENODEV; - goto exit_out; - } - - iod->phys_base = res->start; - iod->reg_base = devm_ioremap_resource(dev, res); + iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(iod->reg_base)) { ret = PTR_ERR(iod->reg_base); goto exit_out; } + iod->phys_base = res->start; iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base, iod->reg_data->regmap_config); diff --git a/include/dt-bindings/gpio/amlogic-c3-gpio.h b/include/dt-bindings/gpio/amlogic-c3-gpio.h new file mode 100644 index 000000000000..75c8da6f505f --- /dev/null +++ b/include/dt-bindings/gpio/amlogic-c3-gpio.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Huqiang Qin <huqiang.qin@amlogic.com> + */ + +#ifndef _DT_BINDINGS_AMLOGIC_C3_GPIO_H +#define _DT_BINDINGS_AMLOGIC_C3_GPIO_H + +#define GPIOE_0 0 +#define GPIOE_1 1 +#define GPIOE_2 2 +#define GPIOE_3 3 +#define GPIOE_4 4 + +#define GPIOB_0 5 +#define GPIOB_1 6 +#define GPIOB_2 7 +#define GPIOB_3 8 +#define GPIOB_4 9 +#define GPIOB_5 10 +#define GPIOB_6 11 +#define GPIOB_7 12 +#define GPIOB_8 13 +#define GPIOB_9 14 +#define GPIOB_10 15 +#define GPIOB_11 16 +#define GPIOB_12 17 +#define GPIOB_13 18 +#define GPIOB_14 19 + +#define GPIOC_0 20 +#define GPIOC_1 21 +#define GPIOC_2 22 +#define GPIOC_3 23 +#define GPIOC_4 24 +#define GPIOC_5 25 +#define GPIOC_6 26 + +#define GPIOX_0 27 +#define GPIOX_1 28 +#define GPIOX_2 29 +#define GPIOX_3 30 +#define GPIOX_4 31 +#define GPIOX_5 32 +#define GPIOX_6 33 +#define GPIOX_7 34 +#define GPIOX_8 35 +#define GPIOX_9 36 +#define GPIOX_10 37 +#define GPIOX_11 38 +#define GPIOX_12 39 +#define GPIOX_13 40 + +#define GPIOD_0 41 +#define GPIOD_1 42 +#define GPIOD_2 43 +#define GPIOD_3 44 +#define GPIOD_4 45 +#define GPIOD_5 46 +#define GPIOD_6 47 + +#define GPIOA_0 48 +#define GPIOA_1 49 +#define GPIOA_2 50 +#define GPIOA_3 51 +#define GPIOA_4 52 +#define GPIOA_5 53 + +#define GPIO_TEST_N 54 + +#endif /* _DT_BINDINGS_AMLOGIC_C3_GPIO_H */ diff --git a/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h b/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h new file mode 100644 index 000000000000..bd415cb7b669 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Huqiang Qin <huqiang.qin@amlogic.com> + */ + +#ifndef _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H +#define _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H + +/* IRQID[11:0] - GPIOAO[11:0] */ +#define IRQID_GPIOAO_0 0 +#define IRQID_GPIOAO_1 1 +#define IRQID_GPIOAO_2 2 +#define IRQID_GPIOAO_3 3 +#define IRQID_GPIOAO_4 4 +#define IRQID_GPIOAO_5 5 +#define IRQID_GPIOAO_6 6 +#define IRQID_GPIOAO_7 7 +#define IRQID_GPIOAO_8 8 +#define IRQID_GPIOAO_9 9 +#define IRQID_GPIOAO_10 10 +#define IRQID_GPIOAO_11 11 + +/* IRQID[27:12] - GPIOZ[15:0] */ +#define IRQID_GPIOZ_0 12 +#define IRQID_GPIOZ_1 13 +#define IRQID_GPIOZ_2 14 +#define IRQID_GPIOZ_3 15 +#define IRQID_GPIOZ_4 16 +#define IRQID_GPIOZ_5 17 +#define IRQID_GPIOZ_6 18 +#define IRQID_GPIOZ_7 19 +#define IRQID_GPIOZ_8 20 +#define IRQID_GPIOZ_9 21 +#define IRQID_GPIOZ_10 22 +#define IRQID_GPIOZ_11 23 +#define IRQID_GPIOZ_12 24 +#define IRQID_GPIOZ_13 25 +#define IRQID_GPIOZ_14 26 +#define IRQID_GPIOZ_15 27 + +/* IRQID[36:28] - GPIOH[8:0] */ +#define IRQID_GPIOH_0 28 +#define IRQID_GPIOH_1 29 +#define IRQID_GPIOH_2 30 +#define IRQID_GPIOH_3 31 +#define IRQID_GPIOH_4 32 +#define IRQID_GPIOH_5 33 +#define IRQID_GPIOH_6 34 +#define IRQID_GPIOH_7 35 +#define IRQID_GPIOH_8 36 + +/* IRQID[52:37] - BOOT[15:0] */ +#define IRQID_BOOT_0 37 +#define IRQID_BOOT_1 38 +#define IRQID_BOOT_2 39 +#define IRQID_BOOT_3 40 +#define IRQID_BOOT_4 41 +#define IRQID_BOOT_5 42 +#define IRQID_BOOT_6 43 +#define IRQID_BOOT_7 44 +#define IRQID_BOOT_8 45 +#define IRQID_BOOT_9 46 +#define IRQID_BOOT_10 47 +#define IRQID_BOOT_11 48 +#define IRQID_BOOT_12 49 +#define IRQID_BOOT_13 50 +#define IRQID_BOOT_14 51 +#define IRQID_BOOT_15 52 + +/* IRQID[60:53] - GPIOC[7:0] */ +#define IRQID_GPIOC_0 53 +#define IRQID_GPIOC_1 54 +#define IRQID_GPIOC_2 55 +#define IRQID_GPIOC_3 56 +#define IRQID_GPIOC_4 57 +#define IRQID_GPIOC_5 58 +#define IRQID_GPIOC_6 59 +#define IRQID_GPIOC_7 60 + +/* IRQID[76:61] - GPIOA[15:0] */ +#define IRQID_GPIOA_0 61 +#define IRQID_GPIOA_1 62 +#define IRQID_GPIOA_2 63 +#define IRQID_GPIOA_3 64 +#define IRQID_GPIOA_4 65 +#define IRQID_GPIOA_5 66 +#define IRQID_GPIOA_6 67 +#define IRQID_GPIOA_7 68 +#define IRQID_GPIOA_8 69 +#define IRQID_GPIOA_9 70 +#define IRQID_GPIOA_10 71 +#define IRQID_GPIOA_11 72 +#define IRQID_GPIOA_12 73 +#define IRQID_GPIOA_13 74 +#define IRQID_GPIOA_14 75 +#define IRQID_GPIOA_15 76 + +/* IRQID[96:77] - GPIOX[19:0] */ +#define IRQID_GPIOX_0 77 +#define IRQID_GPIOX_1 78 +#define IRQID_GPIOX_2 79 +#define IRQID_GPIOX_3 80 +#define IRQID_GPIOX_4 81 +#define IRQID_GPIOX_5 82 +#define IRQID_GPIOX_6 83 +#define IRQID_GPIOX_7 84 +#define IRQID_GPIOX_8 85 +#define IRQID_GPIOX_9 86 +#define IRQID_GPIOX_10 87 +#define IRQID_GPIOX_11 88 +#define IRQID_GPIOX_12 89 +#define IRQID_GPIOX_13 90 +#define IRQID_GPIOX_14 91 +#define IRQID_GPIOX_15 92 +#define IRQID_GPIOX_16 93 +#define IRQID_GPIOX_17 94 +#define IRQID_GPIOX_18 95 +#define IRQID_GPIOX_19 96 + +/* IRQID[99:97] - GPIOE[2:0] */ +#define IRQID_GPIOE_0 97 +#define IRQID_GPIOE_1 98 +#define IRQID_GPIOE_2 99 + +#endif /* _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H */ diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 9dda7d9898ff..e8b12ec8b060 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -34,6 +34,19 @@ /* PM API versions */ #define PM_API_VERSION_2 2 +#define PM_PINCTRL_PARAM_SET_VERSION 2 + +#define ZYNQMP_FAMILY_CODE 0x23 +#define VERSAL_FAMILY_CODE 0x26 + +/* When all subfamily of platform need to support */ +#define ALL_SUB_FAMILY_CODE 0x00 +#define VERSAL_SUB_FAMILY_CODE 0x01 +#define VERSALNET_SUB_FAMILY_CODE 0x03 + +#define FAMILY_CODE_MASK GENMASK(27, 21) +#define SUB_FAMILY_CODE_MASK GENMASK(20, 19) + /* ATF only commands */ #define TF_A_PM_REGISTER_SGI 0xa04 #define PM_GET_TRUSTZONE_VERSION 0xa03 diff --git a/include/linux/pm.h b/include/linux/pm.h index badad7d11f4f..1400c37b29c7 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -448,6 +448,15 @@ const struct dev_pm_ops __maybe_unused name = { \ SET_RUNTIME_PM_OPS(suspend_fn, resume_fn, idle_fn) \ } +/* + * Use this if you want to have the suspend and resume callbacks be called + * with IRQs disabled. + */ +#define DEFINE_NOIRQ_DEV_PM_OPS(name, suspend_fn, resume_fn) \ +const struct dev_pm_ops name = { \ + NOIRQ_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) \ +} + #define pm_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM), (_ptr)) #define pm_sleep_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM_SLEEP), (_ptr)) |