diff options
| -rw-r--r-- | drivers/perf/fsl_imx8_ddr_perf.c | 80 |
1 files changed, 54 insertions, 26 deletions
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 397540a4b799..4f063fb1c6b4 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -361,25 +361,6 @@ static int ddr_perf_event_init(struct perf_event *event) return 0; } - -static void ddr_perf_event_update(struct perf_event *event) -{ - struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - u64 delta, prev_raw_count, new_raw_count; - int counter = hwc->idx; - - do { - prev_raw_count = local64_read(&hwc->prev_count); - new_raw_count = ddr_perf_read_counter(pmu, counter); - } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - new_raw_count) != prev_raw_count); - - delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; - - local64_add(delta, &event->count); -} - static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, int counter, bool enable) { @@ -404,6 +385,56 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, } } +static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter) +{ + int val; + + val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL); + + return val & CNTL_OVER; +} + +static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter) +{ + u8 reg = counter * 4 + COUNTER_CNTL; + int val; + + val = readl_relaxed(pmu->base + reg); + val &= ~CNTL_CLEAR; + writel(val, pmu->base + reg); + + val |= CNTL_CLEAR; + writel(val, pmu->base + reg); +} + +static void ddr_perf_event_update(struct perf_event *event) +{ + struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 new_raw_count; + int counter = hwc->idx; + int ret; + + new_raw_count = ddr_perf_read_counter(pmu, counter); + local64_add(new_raw_count, &event->count); + + /* + * For legacy SoCs: event counter continue counting when overflow, + * no need to clear the counter. + * For new SoCs: event counter stop counting when overflow, need + * clear counter to let it count again. + */ + if (counter != EVENT_CYCLES_COUNTER) { + ret = ddr_perf_counter_overflow(pmu, counter); + if (ret) + dev_warn_ratelimited(pmu->dev, "events lost due to counter overflow (config 0x%llx)\n", + event->attr.config); + } + + /* clear counter every time for both cycle counter and event counter */ + ddr_perf_counter_clear(pmu, counter); +} + static void ddr_perf_event_start(struct perf_event *event, int flags) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -537,7 +568,7 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) { int i; struct ddr_pmu *pmu = (struct ddr_pmu *) p; - struct perf_event *event, *cycle_event = NULL; + struct perf_event *event; /* all counter will stop if cycle counter disabled */ ddr_perf_counter_enable(pmu, @@ -547,7 +578,9 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) /* * When the cycle counter overflows, all counters are stopped, * and an IRQ is raised. If any other counter overflows, it - * continues counting, and no IRQ is raised. + * continues counting, and no IRQ is raised. But for new SoCs, + * such as i.MX8MP, event counter would stop when overflow, so + * we need use cycle counter to stop overflow of event counter. * * Cycles occur at least 4 times as often as other events, so we * can update all events on a cycle counter overflow and not @@ -562,17 +595,12 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) event = pmu->events[i]; ddr_perf_event_update(event); - - if (event->hw.idx == EVENT_CYCLES_COUNTER) - cycle_event = event; } ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, EVENT_CYCLES_COUNTER, true); - if (cycle_event) - ddr_perf_event_update(cycle_event); return IRQ_HANDLED; } |