diff options
83 files changed, 2265 insertions, 1413 deletions
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 378e825754d5..0ca1550fd9dc 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -267,19 +267,22 @@ i915 driver. Intel GPU Basics ---------------- -An Intel GPU has multiple engines. There are several engine types. - -- RCS engine is for rendering 3D and performing compute, this is named - `I915_EXEC_RENDER` in user space. -- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user - space. -- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` - in user space -- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user - space. -- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; - instead it is to be used by user space to specify a default rendering - engine (for 3D) that may or may not be the same as RCS. +An Intel GPU has multiple engines. There are several engine types: + +- Render Command Streamer (RCS). An engine for rendering 3D and + performing compute. +- Blitting Command Streamer (BCS). An engine for performing blitting and/or + copying operations. +- Video Command Streamer. An engine used for video encoding and decoding. Also + sometimes called 'BSD' in hardware documentation. +- Video Enhancement Command Streamer (VECS). An engine for video enhancement. + Also sometimes called 'VEBOX' in hardware documentation. +- Compute Command Streamer (CCS). An engine that has access to the media and + GPGPU pipelines, but not the 3D pipeline. +- Graphics Security Controller (GSCCS). A dedicated engine for internal + communication with GSC controller on security related tasks like + High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), + and HuC firmware authentication. The Intel GPU family is a family of integrated GPU's using Unified Memory Access. For having the GPU "do work", user space will feed the diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index de4967c141f0..88b2bb005014 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -3,24 +3,34 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -# Add a set of useful warning flags and enable -Werror for CI to prevent -# trivial mistakes from creeping in. We have to do this piecemeal as we reject -# any patch that isn't warning clean, so turning on -Wall -Wextra (or W=1) we -# need to filter out dubious warnings. Still it is our interest -# to keep running locally with W=1 C=1 until we are completely clean. -# -# Note the danger in using -Wall -Wextra is that when CI updates gcc we -# will most likely get a sudden build breakage... Hopefully we will fix -# new warnings before CI updates! -subdir-ccflags-y := -Wall -Wextra -subdir-ccflags-y += -Wno-format-security -subdir-ccflags-y += -Wno-unused-parameter -subdir-ccflags-y += -Wno-type-limits +# Unconditionally enable W=1 warnings locally +# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn +subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter +subdir-ccflags-y += -Wmissing-declarations +subdir-ccflags-y += $(call cc-option, -Wrestrict) +subdir-ccflags-y += -Wmissing-format-attribute +subdir-ccflags-y += -Wmissing-prototypes +subdir-ccflags-y += -Wold-style-definition +subdir-ccflags-y += -Wmissing-include-dirs +subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable) +subdir-ccflags-y += $(call cc-option, -Wunused-const-variable) +subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned) +subdir-ccflags-y += $(call cc-option, -Wformat-overflow) +subdir-ccflags-y += $(call cc-option, -Wformat-truncation) +subdir-ccflags-y += $(call cc-option, -Wstringop-overflow) +subdir-ccflags-y += $(call cc-option, -Wstringop-truncation) +# The following turn off the warnings enabled by -Wextra +ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),) subdir-ccflags-y += -Wno-missing-field-initializers -subdir-ccflags-y += -Wno-sign-compare +subdir-ccflags-y += -Wno-type-limits subdir-ccflags-y += -Wno-shift-negative-value -subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable) -subdir-ccflags-y += $(call cc-disable-warning, frame-address) +endif +ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),) +subdir-ccflags-y += -Wno-sign-compare +endif +# --- end copy-paste + +# Enable -Werror in CI and development subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror # Fine grained warnings disable @@ -28,6 +38,10 @@ CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init) CFLAGS_display/intel_display_device.o = $(call cc-disable-warning, override-init) CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init) +# Support compiling the display code separately for both i915 and xe +# drivers. Define I915 when building i915. +subdir-ccflags-y += -DI915 + subdir-ccflags-y += -I$(srctree)/$(src) # Please keep these build lists sorted! @@ -265,6 +279,7 @@ i915-y += \ display/intel_global_state.o \ display/intel_hdcp.o \ display/intel_hdcp_gsc.o \ + display/intel_hdcp_gsc_message.o \ display/intel_hotplug.o \ display/intel_hotplug_irq.o \ display/intel_hti.o \ diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h b/drivers/gpu/drm/i915/display/g4x_dp.h index a38b3e1e01d3..a10638ab749c 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.h +++ b/drivers/gpu/drm/i915/display/g4x_dp.h @@ -17,6 +17,7 @@ struct intel_crtc_state; struct intel_dp; struct intel_encoder; +#ifdef I915 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915); enum pipe vlv_active_pipe(struct intel_dp *intel_dp); void g4x_dp_set_clock(struct intel_encoder *encoder, @@ -26,5 +27,30 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, enum pipe *pipe); bool g4x_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, enum port port); +#else +static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) +{ + return NULL; +} +static inline int vlv_active_pipe(struct intel_dp *intel_dp) +{ + return 0; +} +static inline void g4x_dp_set_clock(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ +} +static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, + i915_reg_t dp_reg, int port, + enum pipe *pipe) +{ + return false; +} +static inline bool g4x_dp_init(struct drm_i915_private *dev_priv, + i915_reg_t output_reg, int port) +{ + return false; +} +#endif #endif diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h index 1e3ea7f3c846..817f55c7a3a1 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h @@ -15,9 +15,21 @@ struct drm_atomic_state; struct drm_connector; struct drm_i915_private; +#ifdef I915 void g4x_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, enum port port); int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state); +#else +static inline void g4x_hdmi_init(struct drm_i915_private *dev_priv, + i915_reg_t hdmi_reg, int port) +{ +} +static inline int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + return 0; +} +#endif #endif diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h index 4eb83b350791..35364228e1c1 100644 --- a/drivers/gpu/drm/i915/display/hsw_ips.h +++ b/drivers/gpu/drm/i915/display/hsw_ips.h @@ -12,6 +12,7 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +#ifdef I915 bool hsw_ips_disable(const struct intel_crtc_state *crtc_state); bool hsw_ips_pre_update(struct intel_atomic_state *state, struct intel_crtc *crtc); @@ -23,5 +24,39 @@ int hsw_ips_compute_config(struct intel_atomic_state *state, struct intel_crtc *crtc); void hsw_ips_get_config(struct intel_crtc_state *crtc_state); void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc); +#else +static inline bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) +{ + return false; +} +static inline bool hsw_ips_pre_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + return false; +} +static inline void hsw_ips_post_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline bool hsw_crtc_supports_ips(struct intel_crtc *crtc) +{ + return false; +} +static inline bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) +{ + return false; +} +static inline int hsw_ips_compute_config(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + return 0; +} +static inline void hsw_ips_get_config(struct intel_crtc_state *crtc_state) +{ +} +static inline void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc) +{ +} +#endif #endif /* __HSW_IPS_H__ */ diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h index 027b66053984..b3d724a144cb 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane.h @@ -15,6 +15,7 @@ struct intel_initial_plane_config; struct intel_plane; struct intel_plane_state; +#ifdef I915 unsigned int i965_plane_max_stride(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation); @@ -25,4 +26,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe); void i9xx_get_initial_plane_config(struct intel_crtc *crtc, struct intel_initial_plane_config *plane_config); +#else +static inline unsigned int i965_plane_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + return 0; +} +static inline int i9xx_check_plane_surface(struct intel_plane_state *plane_state) +{ + return 0; +} +static inline struct intel_plane * +intel_primary_plane_create(struct drm_i915_private *dev_priv, int pipe) +{ + return NULL; +} +static inline void i9xx_get_initial_plane_config(struct intel_crtc *crtc, + struct intel_initial_plane_config *plane_config) +{ +} +#endif + #endif diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.h b/drivers/gpu/drm/i915/display/i9xx_wm.h index b87ae369685a..de0920730ab2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.h +++ b/drivers/gpu/drm/i915/display/i9xx_wm.h @@ -12,9 +12,26 @@ struct drm_i915_private; struct intel_crtc_state; struct intel_plane_state; +#ifdef I915 bool ilk_disable_lp_wm(struct drm_i915_private *i915); void ilk_wm_sanitize(struct drm_i915_private *i915); bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable); void i9xx_wm_init(struct drm_i915_private *i915); +#else +static inline bool ilk_disable_lp_wm(struct drm_i915_private *i915) +{ + return false; +} +static inline void ilk_wm_sanitize(struct drm_i915_private *i915) +{ +} +static inline bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable) +{ + return false; +} +static inline void i9xx_wm_init(struct drm_i915_private *i915) +{ +} +#endif #endif /* __I9XX_WM_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4f92fc31059f..2a2a163ea652 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3702,6 +3702,7 @@ static const struct intel_color_funcs vlv_color_funcs = { .read_luts = i965_read_luts, .lut_equal = i965_lut_equal, .read_csc = vlv_read_csc, + .get_config = i9xx_get_config, }; static const struct intel_color_funcs i965_color_funcs = { diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index d4bad0ddff41..913e5d230a4d 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -838,7 +838,7 @@ intel_crt_detect(struct drm_connector *connector, connector->base.id, connector->name, force); - if (!INTEL_DISPLAY_ENABLED(dev_priv)) + if (!intel_display_device_enabled(dev_priv)) return connector_status_disconnected; if (dev_priv->params.load_detect_test) { diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h index c6071efd93ce..fe7690c2b948 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.h +++ b/drivers/gpu/drm/i915/display/intel_crt.h @@ -12,9 +12,23 @@ enum pipe; struct drm_encoder; struct drm_i915_private; +#ifdef I915 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, i915_reg_t adpa_reg, enum pipe *pipe); void intel_crt_init(struct drm_i915_private *dev_priv); void intel_crt_reset(struct drm_encoder *encoder); +#else +static inline bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, + i915_reg_t adpa_reg, enum pipe *pipe) +{ + return false; +} +static inline void intel_crt_init(struct drm_i915_private *dev_priv) +{ +} +static inline void intel_crt_reset(struct drm_encoder *encoder) +{ +} +#endif #endif /* __INTEL_CRT_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index abd607b564f1..6e6a1818071e 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2596,8 +2596,7 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n", phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US); - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), - XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1), + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, lane_pipe_reset); if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port), @@ -3005,12 +3004,13 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder, } void intel_c10pll_state_verify(struct intel_atomic_state *state, - struct intel_crtc_state *new_crtc_state) + struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); struct intel_c10pll_state mpllb_hw_state = { 0 }; - struct intel_c10pll_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10; - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); + const struct intel_c10pll_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10; struct intel_encoder *encoder; enum phy phy; int i; diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index 912e0eeb0be3..0e0a38dac8cd 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -16,6 +16,7 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_c10pll_state; struct intel_c20pll_state; +struct intel_crtc; struct intel_crtc_state; struct intel_encoder; struct intel_hdmi; @@ -34,7 +35,7 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv, int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, const struct intel_c10pll_state *pll_state); void intel_c10pll_state_verify(struct intel_atomic_state *state, - struct intel_crtc_state *new_crtc_state); + struct intel_crtc *crtc); void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c20pll_state *pll_state); void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4668de45d6fe..9151d5add960 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4333,7 +4333,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, u8 config; int ret; - if (!connector || connector->base.status != connector_status_connected) + if (connector->base.status != connector_status_connected) return 0; ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b3ae81a6ab16..28d85e1e858e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -956,6 +956,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; + intel_psr_post_plane_update(state, crtc); + intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) @@ -3997,7 +3999,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder) } if (!intel_crtc_get_pipe_config(crtc_state)) { - kfree(crtc_state); + intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); kfree(mode); return NULL; } @@ -4006,7 +4008,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder) intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); - kfree(crtc_state); + intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); return mode; } @@ -4986,9 +4988,6 @@ pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, static bool fastboot_enabled(struct drm_i915_private *dev_priv) { - if (dev_priv->params.fastboot != -1) - return dev_priv->params.fastboot; - /* Enable fastboot by default on Skylake and newer */ if (DISPLAY_VER(dev_priv) >= 9) return true; @@ -7216,7 +7215,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_set_cdclk_pre_plane_update(state); - intel_modeset_verify_disabled(dev_priv, state); + intel_modeset_verify_disabled(state); } intel_sagv_pre_plane_update(state); @@ -7296,14 +7295,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } intel_dbuf_post_plane_update(state); - intel_psr_post_plane_update(state); for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { intel_post_plane_update(state, crtc); intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); - intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); + intel_modeset_verify_crtc(state, crtc); /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ hsw_ips_post_update(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 8f19701ed9c1..fbe75d47a165 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -644,6 +644,7 @@ static int i915_display_info(struct seq_file *m, void *unused) static int i915_shared_dplls_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_shared_dpll *pll; int i; drm_modeset_lock_all(&dev_priv->drm); @@ -652,11 +653,9 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) dev_priv->display.dpll.ref_clks.nssc, dev_priv->display.dpll.ref_clks.ssc); - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - - seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, - pll->info->id); + for_each_shared_dpll(dev_priv, pll, i) { + seq_printf(m, "DPLL%i: %s, id: %i\n", pll->index, + pll->info->name, pll->info->id); seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", pll->state.pipe_mask, pll->active_mask, str_yes_no(pll->on)); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index a6a18eae7ae8..2b1ec23ba9c3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -926,7 +926,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) else info = probe_display(i915); - i915->display.info.__device_info = info; + DISPLAY_INFO(i915) = info; memcpy(DISPLAY_RUNTIME_INFO(i915), &DISPLAY_INFO(i915)->__runtime_defaults, @@ -939,7 +939,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) } } -void intel_display_device_info_runtime_init(struct drm_i915_private *i915) +static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915) { struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); enum pipe pipe; @@ -948,6 +948,13 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915) BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); + /* This covers both ULT and ULX */ + if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915)) + display_runtime->port_mask &= ~BIT(PORT_D); + + if (IS_ICL_WITH_PORT_F(i915)) + display_runtime->port_mask |= BIT(PORT_F); + /* Wa_14011765242: adl-s A0,A1 */ if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) for_each_pipe(i915, pipe) @@ -1065,12 +1072,44 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915) display_runtime->has_dsc = 0; } + if (DISPLAY_VER(i915) >= 20) { + u32 cap = intel_de_read(i915, XE2LPD_DE_CAP); + + if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) == + XE2LPD_DE_CAP_DSC_REMOVED) + display_runtime->has_dsc = 0; + + if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) == + XE2LPD_DE_CAP_SCALER_SINGLE) { + for_each_pipe(i915, pipe) + if (display_runtime->num_scalers[pipe]) + display_runtime->num_scalers[pipe] = 1; + } + } + return; display_fused_off: memset(display_runtime, 0, sizeof(*display_runtime)); } +void intel_display_device_info_runtime_init(struct drm_i915_private *i915) +{ + if (HAS_DISPLAY(i915)) + __intel_display_device_info_runtime_init(i915); + + /* Display may have been disabled by runtime init */ + if (!HAS_DISPLAY(i915)) { + i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); + i915->display.info.__device_info = &no_display; + } + + /* Disable nuclear pageflip by default on pre-g4x */ + if (!i915->params.nuclear_pageflip && + DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) + i915->drm.driver_features &= ~DRIVER_ATOMIC; +} + void intel_display_device_info_print(const struct intel_display_device_info *info, const struct intel_display_runtime_info *runtime, struct drm_printer *p) @@ -1091,3 +1130,20 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); } + +/* + * Assuming the device has display hardware, should it be enabled? + * + * It's an error to call this function if the device does not have display + * hardware. + * + * Disabling display means taking over the display hardware, putting it to + * sleep, and preventing connectors from being connected via any means. + */ +bool intel_display_device_enabled(struct drm_i915_private *i915) +{ + /* Only valid when HAS_DISPLAY() is true */ + drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915)); + + return !i915->params.disable_display && !intel_opregion_headless_sku(i915); +} diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 44733c9d5812..5b5c0e53307f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -98,6 +98,15 @@ struct drm_printer; (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \ IS_DISPLAY_STEP((__i915), (from), (until))) +#define DISPLAY_INFO(i915) ((i915)->display.info.__device_info) +#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info) + +#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) +#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \ + DISPLAY_RUNTIME_INFO(i915)->ip.rel) +#define IS_DISPLAY_VER(i915, from, until) \ + (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) + struct intel_display_runtime_info { struct { u16 ver; @@ -150,6 +159,7 @@ struct intel_display_device_info { } color; }; +bool intel_display_device_enabled(struct drm_i915_private *i915); void intel_display_device_probe(struct drm_i915_private *i915); void intel_display_device_info_runtime_init(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 1623c0c5e8a1..63e080e07023 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -309,7 +309,7 @@ static const struct stepping_info * intel_get_stepping_info(struct drm_i915_private *i915, struct stepping_info *si) { - const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); + const char *step_name = intel_display_step_name(i915); si->stepping = step_name[0]; si->substepping = step_name[1]; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9c174ff93398..4f6835a7578e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5354,7 +5354,7 @@ intel_dp_detect(struct drm_connector *connector, drm_WARN_ON(&dev_priv->drm, !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); - if (!INTEL_DISPLAY_ENABLED(dev_priv)) + if (!intel_display_device_enabled(dev_priv)) return connector_status_disconnected; /* Can't disconnect eDP */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 648cf37e02a8..73e397736463 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -94,12 +94,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, crtc_state->lane_count = limits->max_lane_count; crtc_state->port_clock = limits->max_rate; - // TODO: Handle pbn_div changes by adding a new MST helper - if (!mst_state->pbn_div) { - mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr, - crtc_state->port_clock, - crtc_state->lane_count); - } + mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr, + crtc_state->port_clock, + crtc_state->lane_count); for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -1062,7 +1059,7 @@ intel_dp_mst_detect(struct drm_connector *connector, struct intel_connector *intel_connector = to_intel_connector(connector); struct intel_dp *intel_dp = intel_connector->mst_port; - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; if (drm_connector_is_unregistered(connector)) diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h index 9c7725dacb47..4d43dbbdf81c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h @@ -26,6 +26,7 @@ enum dpio_phy { DPIO_PHY2, }; +#ifdef I915 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, enum dpio_phy *phy, enum dpio_channel *ch); void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, @@ -70,5 +71,100 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void vlv_phy_reset_lanes(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state); +#else +static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, + enum dpio_phy *phy, enum dpio_channel *ch) +{ +} +static inline void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) +{ +} +static inline void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) +{ +} +static inline bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, + enum dpio_phy phy) +{ + return false; +} +static inline bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, + enum dpio_phy phy) +{ + return true; +} +static inline u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) +{ + return 0; +} +static inline void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, + u8 lane_lat_optim_mask) +{ +} +static inline u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) +{ + return 0; +} +static inline enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port) +{ + return DPIO_CH0; +} +static inline enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port) +{ + return DPIO_PHY0; +} +static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe) +{ + return DPIO_CH0; +} +static inline void chv_set_phy_signal_level(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + u32 deemph_reg_value, u32 margin_reg_value, + bool uniq_trans_scale) +{ +} +static inline void chv_data_lane_soft_reset(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + bool reset) +{ +} +static inline void chv_phy_pre_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void chv_phy_release_cl2_override(struct intel_encoder *encoder) +{ +} +static inline void chv_phy_post_pll_disable(struct intel_encoder *encoder, + const struct intel_crtc_state *old_crtc_state) +{ +} + +static inline void vlv_set_phy_signal_level(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + u32 demph_reg_value, u32 preemph_reg_value, + u32 uniqtranscale_reg_value, u32 tx3_demph) +{ +} +static inline void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ +} +static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder, + const struct intel_crtc_state *old_crtc_state) +{ +} +#endif #endif /* __INTEL_DPIO_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 2255ad651486..d41c1dc9f66c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -7,6 +7,7 @@ #include <linux/string_helpers.h> #include "i915_reg.h" +#include "intel_atomic.h" #include "intel_crtc.h" #include "intel_cx0_phy.h" #include "intel_de.h" @@ -2006,7 +2007,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, vlv_enable_pll(crtc_state); } - kfree(crtc_state); + intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 6d68b36292d3..399653a20f98 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -107,22 +107,20 @@ struct intel_dpll_mgr { struct intel_crtc *crtc, struct intel_encoder *encoder); void (*update_ref_clks)(struct drm_i915_private *i915); - void (*dump_hw_state)(struct drm_i915_private *dev_priv, + void (*dump_hw_state)(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state); }; static void -intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, +intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll_state *shared_dpll) { - enum intel_dpll_id i; + struct intel_shared_dpll *pll; + int i; /* Copy shared dpll state */ - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; - - shared_dpll[i] = pll->state; - } + for_each_shared_dpll(i915, pll, i) + shared_dpll[pll->index] = pll->state; } static struct intel_shared_dpll_state * @@ -144,33 +142,42 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) /** * intel_get_shared_dpll_by_id - get a DPLL given its id - * @dev_priv: i915 device instance + * @i915: i915 device instance * @id: pll id * * Returns: * A pointer to the DPLL with @id */ struct intel_shared_dpll * -intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, +intel_get_shared_dpll_by_id(struct drm_i915_private *i915, enum intel_dpll_id id) { - return &dev_priv->display.dpll.shared_dplls[id]; + struct intel_shared_dpll *pll; + int i; + + for_each_shared_dpll(i915, pll, i) { + if (pll->info->id == id) + return pll; + } + + MISSING_CASE(id); + return NULL; } /* For ILK+ */ -void assert_shared_dpll(struct drm_i915_private *dev_priv, +void assert_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll, bool state) { bool cur_state; struct intel_dpll_hw_state hw_state; - if (drm_WARN(&dev_priv->drm, !pll, + if (drm_WARN(&i915->drm, !pll, "asserting DPLL %s with no DPLL\n", str_on_off(state))) return; - cur_state = intel_dpll_get_hw_state(dev_priv, pll, &hw_state); - I915_STATE_WARN(dev_priv, cur_state != state, + cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state); + I915_STATE_WARN(i915, cur_state != state, "%s assertion failure (expected %s, current %s)\n", pll->info->name, str_on_off(state), str_on_off(cur_state)); @@ -221,41 +228,41 @@ intel_tc_pll_enable_reg(struct drm_i915_private *i915, void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; unsigned int pipe_mask = BIT(crtc->pipe); unsigned int old_mask; - if (drm_WARN_ON(&dev_priv->drm, pll == NULL)) + if (drm_WARN_ON(&i915->drm, pll == NULL)) return; - mutex_lock(&dev_priv->display.dpll.lock); + mutex_lock(&i915->display.dpll.lock); old_mask = pll->active_mask; - if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) || - drm_WARN_ON(&dev_priv->drm, pll->active_mask & pipe_mask)) + if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) || + drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask)) goto out; pll->active_mask |= pipe_mask; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n", pll->info->name, pll->active_mask, pll->on, crtc->base.base.id, crtc->base.name); if (old_mask) { - drm_WARN_ON(&dev_priv->drm, !pll->on); - assert_shared_dpll_enabled(dev_priv, pll); + drm_WARN_ON(&i915->drm, !pll->on); + assert_shared_dpll_enabled(i915, pll); goto out; } - drm_WARN_ON(&dev_priv->drm, pll->on); + drm_WARN_ON(&i915->drm, pll->on); - drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name); - pll->info->funcs->enable(dev_priv, pll); + drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name); + pll->info->funcs->enable(i915, pll); pll->on = true; out: - mutex_unlock(&dev_priv->display.dpll.lock); + mutex_unlock(&i915->display.dpll.lock); } /** @@ -267,41 +274,57 @@ out: void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; unsigned int pipe_mask = BIT(crtc->pipe); /* PCH only available on ILK+ */ - if (DISPLAY_VER(dev_priv) < 5) + if (DISPLAY_VER(i915) < 5) return; if (pll == NULL) return; - mutex_lock(&dev_priv->display.dpll.lock); - if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask), + mutex_lock(&i915->display.dpll.lock); + if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask), "%s not used by [CRTC:%d:%s]\n", pll->info->name, crtc->base.base.id, crtc->base.name)) goto out; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n", pll->info->name, pll->active_mask, pll->on, crtc->base.base.id, crtc->base.name); - assert_shared_dpll_enabled(dev_priv, pll); - drm_WARN_ON(&dev_priv->drm, !pll->on); + assert_shared_dpll_enabled(i915, pll); + drm_WARN_ON(&i915->drm, !pll->on); pll->active_mask &= ~pipe_mask; if (pll->active_mask) goto out; - drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name); - pll->info->funcs->disable(dev_priv, pll); + drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name); + pll->info->funcs->disable(i915, pll); pll->on = false; out: - mutex_unlock(&dev_priv->display.dpll.lock); + mutex_unlock(&i915->display.dpll.lock); +} + +static unsigned long +intel_dpll_mask_all(struct drm_i915_private *i915) +{ + struct intel_shared_dpll *pll; + unsigned long dpll_mask = 0; + int i; + + for_each_shared_dpll(i915, pll, i) { + drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); + + dpll_mask |= BIT(pll->info->id); + } + + return dpll_mask; } static struct intel_shared_dpll * @@ -310,33 +333,38 @@ intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_dpll_hw_state *pll_state, unsigned long dpll_mask) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_shared_dpll *pll, *unused_pll = NULL; + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + unsigned long dpll_mask_all = intel_dpll_mask_all(i915); struct intel_shared_dpll_state *shared_dpll; - enum intel_dpll_id i; + struct intel_shared_dpll *unused_pll = NULL; + enum intel_dpll_id id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all); + + for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) { + struct intel_shared_dpll *pll; - for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { - pll = &dev_priv->display.dpll.shared_dplls[i]; + pll = intel_get_shared_dpll_by_id(i915, id); + if (!pll) + continue; /* Only want to check enabled timings first */ - if (shared_dpll[i].pipe_mask == 0) { + if (shared_dpll[pll->index].pipe_mask == 0) { if (!unused_pll) unused_pll = pll; continue; } if (memcmp(pll_state, - &shared_dpll[i].hw_state, + &shared_dpll[pll->index].hw_state, sizeof(*pll_state)) == 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n", crtc->base.base.id, crtc->base.name, pll->info->name, - shared_dpll[i].pipe_mask, + shared_dpll[pll->index].pipe_mask, pll->active_mask); return pll; } @@ -344,7 +372,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, /* Ok no matching timings, maybe there's a free one? */ if (unused_pll) { - drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n", + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n", crtc->base.base.id, crtc->base.name, unused_pll->info->name); return unused_pll; @@ -383,14 +411,13 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_dpll_hw_state *pll_state) { struct intel_shared_dpll_state *shared_dpll; - const enum intel_dpll_id id = pll->info->id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - if (shared_dpll[id].pipe_mask == 0) - shared_dpll[id].hw_state = *pll_state; + if (shared_dpll[pll->index].pipe_mask == 0) + shared_dpll[pll->index].hw_state = *pll_state; - intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]); + intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); } /** @@ -421,11 +448,10 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state, const struct intel_shared_dpll *pll) { struct intel_shared_dpll_state *shared_dpll; - const enum intel_dpll_id id = pll->info->id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]); + intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); } static void intel_put_dpll(struct intel_atomic_state *state, @@ -457,22 +483,19 @@ static void intel_put_dpll(struct intel_atomic_state *state, */ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; - enum intel_dpll_id i; + struct intel_shared_dpll *pll; + int i; if (!state->dpll_set) return; - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - struct intel_shared_dpll *pll = - &dev_priv->display.dpll.shared_dplls[i]; - - swap(pll->state, shared_dpll[i]); - } + for_each_shared_dpll(i915, pll, i) + swap(pll->state, shared_dpll[pll->index]); } -static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, +static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -480,48 +503,48 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, PCH_DPLL(id)); + val = intel_de_read(i915, PCH_DPLL(id)); hw_state->dpll = val; - hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); - hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); + hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); + hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & DPLL_VCO_ENABLE; } -static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) +static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) { u32 val; bool enabled; - val = intel_de_read(dev_priv, PCH_DREF_CONTROL); + val = intel_de_read(i915, PCH_DREF_CONTROL); enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | DREF_SUPERSPREAD_SOURCE_MASK)); - I915_STATE_WARN(dev_priv, !enabled, + I915_STATE_WARN(i915, !enabled, "PCH refclk assertion failure, should be active but is disabled\n"); } -static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, +static void ibx_pch_dpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; /* PCH refclock must be enabled first */ - ibx_assert_pch_refclk_enabled(dev_priv); + ibx_assert_pch_refclk_enabled(i915); - intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); - intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); + intel_de_write(i915, PCH_FP0(id), pll->state.hw_state.fp0); + intel_de_write(i915, PCH_FP1(id), pll->state.hw_state.fp1); - intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); + intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll); /* Wait for the clocks to stabilize. */ - intel_de_posting_read(dev_priv, PCH_DPLL(id)); + intel_de_posting_read(i915, PCH_DPLL(id)); udelay(150); /* The pixel multiplier can only be updated once the @@ -529,18 +552,18 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, * * So write it again. */ - intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); - intel_de_posting_read(dev_priv, PCH_DPLL(id)); + intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll); + intel_de_posting_read(i915, PCH_DPLL(id)); udelay(200); } -static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, +static void ibx_pch_dpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_write(dev_priv, PCH_DPLL(id), 0); - intel_de_posting_read(dev_priv, PCH_DPLL(id)); + intel_de_write(i915, PCH_DPLL(id), 0); + intel_de_posting_read(i915, PCH_DPLL(id)); udelay(200); } @@ -557,16 +580,16 @@ static int ibx_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; - enum intel_dpll_id i; + enum intel_dpll_id id; - if (HAS_PCH_IBX(dev_priv)) { + if (HAS_PCH_IBX(i915)) { /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ - i = (enum intel_dpll_id) crtc->pipe; - pll = &dev_priv->display.dpll.shared_dplls[i]; + id = (enum intel_dpll_id) crtc->pipe; + pll = intel_get_shared_dpll_by_id(i915, id); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); @@ -589,10 +612,10 @@ static int ibx_get_dpll(struct intel_atomic_state *state, return 0; } -static void ibx_dump_hw_state(struct drm_i915_private *dev_priv, +static void ibx_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, @@ -621,57 +644,57 @@ static const struct intel_dpll_mgr pch_pll_mgr = { .dump_hw_state = ibx_dump_hw_state, }; -static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, +static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); - intel_de_posting_read(dev_priv, WRPLL_CTL(id)); + intel_de_write(i915, WRPLL_CTL(id), pll->state.hw_state.wrpll); + intel_de_posting_read(i915, WRPLL_CTL(id)); udelay(20); } -static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, +static void hsw_ddi_spll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); - intel_de_posting_read(dev_priv, SPLL_CTL); + intel_de_write(i915, SPLL_CTL, pll->state.hw_state.spll); + intel_de_posting_read(i915, SPLL_CTL); udelay(20); } -static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, +static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_rmw(dev_priv, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, WRPLL_CTL(id)); + intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); + intel_de_posting_read(i915, WRPLL_CTL(id)); /* * Try to set up the PCH reference clock once all DPLLs * that depend on it have been shut down. */ - if (dev_priv->display.dpll.pch_ssc_use & BIT(id)) - intel_init_pch_refclk(dev_priv); + if (i915->display.dpll.pch_ssc_use & BIT(id)) + intel_init_pch_refclk(i915); } -static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, +static void hsw_ddi_spll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { enum intel_dpll_id id = pll->info->id; - intel_de_rmw(dev_priv, SPLL_CTL, SPLL_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, SPLL_CTL); + intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0); + intel_de_posting_read(i915, SPLL_CTL); /* * Try to set up the PCH reference clock once all DPLLs * that depend on it have been shut down. */ - if (dev_priv->display.dpll.pch_ssc_use & BIT(id)) - intel_init_pch_refclk(dev_priv); + if (i915->display.dpll.pch_ssc_use & BIT(id)) + intel_init_pch_refclk(i915); } -static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, +static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -679,35 +702,35 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, WRPLL_CTL(id)); + val = intel_de_read(i915, WRPLL_CTL(id)); hw_state->wrpll = val; - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & WRPLL_PLL_ENABLE; } -static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, +static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, SPLL_CTL); + val = intel_de_read(i915, SPLL_CTL); hw_state->spll = val; - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & SPLL_PLL_ENABLE; } @@ -918,7 +941,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, *r2_out = best.r2; } -static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, +static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) { @@ -929,8 +952,8 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, switch (wrpll & WRPLL_REF_MASK) { case WRPLL_REF_SPECIAL_HSW: /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */ - if (IS_HASWELL(dev_priv) && !IS_HASWELL_ULT(dev_priv)) { - refclk = dev_priv->display.dpll.ref_clks.nssc; + if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) { + refclk = i915->display.dpll.ref_clks.nssc; break; } fallthrough; @@ -940,7 +963,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, * code only cares about 5% accuracy, and spread is a max of * 0.5% downspread. */ - refclk = dev_priv->display.dpll.ref_clks.ssc; + refclk = i915->display.dpll.ref_clks.ssc; break; case WRPLL_REF_LCPLL: refclk = 2700000; @@ -996,7 +1019,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, static int hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); int clock = crtc_state->port_clock; switch (clock / 2) { @@ -1005,7 +1028,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) case 270000: return 0; default: - drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n", + drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n", clock); return -EINVAL; } @@ -1014,7 +1037,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) static struct intel_shared_dpll * hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_shared_dpll *pll; enum intel_dpll_id pll_id; int clock = crtc_state->port_clock; @@ -1034,7 +1057,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) return NULL; } - pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); + pll = intel_get_shared_dpll_by_id(i915, pll_id); if (!pll) return NULL; @@ -1170,10 +1193,10 @@ static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915) i915->display.dpll.ref_clks.nssc = 135000; } -static void hsw_dump_hw_state(struct drm_i915_private *dev_priv, +static void hsw_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", + drm_dbg_kms(&i915->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", hw_state->wrpll, hw_state->spll); } @@ -1191,17 +1214,17 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { .get_freq = hsw_ddi_spll_get_freq, }; -static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv, +static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { } -static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv, +static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { } -static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv, +static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -1265,60 +1288,60 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = { }, }; -static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv, +static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_rmw(dev_priv, DPLL_CTRL1, + intel_de_rmw(i915, DPLL_CTRL1, DPLL_CTRL1_HDMI_MODE(id) | DPLL_CTRL1_SSC(id) | DPLL_CTRL1_LINK_RATE_MASK(id), pll->state.hw_state.ctrl1 << (id * 6)); - intel_de_posting_read(dev_priv, DPLL_CTRL1); + intel_de_posting_read(i915, DPLL_CTRL1); } -static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, +static void skl_ddi_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; - skl_ddi_pll_write_ctrl1(dev_priv, pll); + skl_ddi_pll_write_ctrl1(i915, pll); - intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); - intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); - intel_de_posting_read(dev_priv, regs[id].cfgcr1); - intel_de_posting_read(dev_priv, regs[id].cfgcr2); + intel_de_write(i915, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); + intel_de_write(i915, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); + intel_de_posting_read(i915, regs[id].cfgcr1); + intel_de_posting_read(i915, regs[id].cfgcr2); /* the enable bit is always bit 31 */ - intel_de_rmw(dev_priv, regs[id].ctl, 0, LCPLL_PLL_ENABLE); + intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE); - if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5)) - drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); + if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5)) + drm_err(&i915->drm, "DPLL %d not locked\n", id); } -static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, +static void skl_ddi_dpll0_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - skl_ddi_pll_write_ctrl1(dev_priv, pll); + skl_ddi_pll_write_ctrl1(i915, pll); } -static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, +static void skl_ddi_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; /* the enable bit is always bit 31 */ - intel_de_rmw(dev_priv, regs[id].ctl, LCPLL_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, regs[id].ctl); + intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0); + intel_de_posting_read(i915, regs[id].ctl); } -static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv, +static void skl_ddi_dpll0_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { } -static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -1328,34 +1351,34 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; ret = false; - val = intel_de_read(dev_priv, regs[id].ctl); + val = intel_de_read(i915, regs[id].ctl); if (!(val & LCPLL_PLL_ENABLE)) goto out; - val = intel_de_read(dev_priv, DPLL_CTRL1); + val = intel_de_read(i915, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; /* avoid reading back stale values if HDMI mode is not enabled */ if (val & DPLL_CTRL1_HDMI_MODE(id)) { - hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); - hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2); + hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1); + hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2); } ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, +static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -1365,7 +1388,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, u32 val; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -1373,17 +1396,17 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, ret = false; /* DPLL0 is always enabled since it drives CDCLK */ - val = intel_de_read(dev_priv, regs[id].ctl); - if (drm_WARN_ON(&dev_priv->drm, !(val & LCPLL_PLL_ENABLE))) + val = intel_de_read(i915, regs[id].ctl); + if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE))) goto out; - val = intel_de_read(dev_priv, DPLL_CTRL1); + val = intel_de_read(i915, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -1873,10 +1896,10 @@ static void skl_update_dpll_ref_clks(struct drm_i915_private *i915) i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; } -static void skl_dump_hw_state(struct drm_i915_private *dev_priv, +static void skl_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: " + drm_dbg_kms(&i915->drm, "dpll_hw_state: " "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1, hw_state->cfgcr1, @@ -1914,129 +1937,129 @@ static const struct intel_dpll_mgr skl_pll_mgr = { .dump_hw_state = skl_dump_hw_state, }; -static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, - struct intel_shared_dpll *pll) +static void bxt_ddi_pll_enable(struct drm_i915_private *i915, + struct intel_shared_dpll *pll) { u32 temp; enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ enum dpio_phy phy; enum dpio_channel ch; - bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); + bxt_port_to_phy_channel(i915, port, &phy, &ch); /* Non-SSC reference */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); - if (IS_GEMINILAKE(dev_priv)) { - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), + if (IS_GEMINILAKE(i915)) { + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_POWER_ENABLE); - if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & + if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - drm_err(&dev_priv->drm, + drm_err(&i915->drm, "Power state not set for PLL:%d\n", port); } /* Disable 10 bit clock */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), + intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch), PORT_PLL_10BIT_CLK_ENABLE, 0); /* Write P1 & P2 */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch), + intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch), PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, pll->state.hw_state.ebb0); /* Write M2 integer */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 0), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0), PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0); /* Write N */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 1), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1), PORT_PLL_N_MASK, pll->state.hw_state.pll1); /* Write M2 fraction */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 2), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2), PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2); /* Write M2 fraction enable */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 3), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3), PORT_PLL_M2_FRAC_ENABLE, pll->state.hw_state.pll3); /* Write coeff */ - temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); + temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); temp &= ~PORT_PLL_PROP_COEFF_MASK; temp &= ~PORT_PLL_INT_COEFF_MASK; temp &= ~PORT_PLL_GAIN_CTL_MASK; temp |= pll->state.hw_state.pll6; - intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 6), temp); + intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp); /* Write calibration val */ - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 8), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8), PORT_PLL_TARGET_CNT_MASK, pll->state.hw_state.pll8); - intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 9), + intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9), PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9); - temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); + temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; temp &= ~PORT_PLL_DCO_AMP_MASK; temp |= pll->state.hw_state.pll10; - intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 10), temp); + intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp); /* Recalibrate with new settings */ - temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); + temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); temp |= PORT_PLL_RECALIBRATE; - intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); temp &= ~PORT_PLL_10BIT_CLK_ENABLE; temp |= pll->state.hw_state.ebb4; - intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); /* Enable PLL */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); - intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); + intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); - if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), + if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), 200)) - drm_err(&dev_priv->drm, "PLL %d not locked\n", port); + drm_err(&i915->drm, "PLL %d not locked\n", port); - if (IS_GEMINILAKE(dev_priv)) { - temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch)); + if (IS_GEMINILAKE(i915)) { + temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN0(phy, ch)); temp |= DCC_DELAY_RANGE_2; - intel_de_write(dev_priv, BXT_PORT_TX_DW5_GRP(phy, ch), temp); + intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp); } /* * While we write to the group register to program all lanes at once we * can read only lane registers and we pick lanes 0/1 for that. */ - temp = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch)); + temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch)); temp &= ~LANE_STAGGER_MASK; temp &= ~LANESTAGGER_STRAP_OVRD; temp |= pll->state.hw_state.pcsdw12; - intel_de_write(dev_priv, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); + intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); } -static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, - struct intel_shared_dpll *pll) +static void bxt_ddi_pll_disable(struct drm_i915_private *i915, + struct intel_shared_dpll *pll) { enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); + intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); - if (IS_GEMINILAKE(dev_priv)) { - intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), + if (IS_GEMINILAKE(i915)) { + intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_POWER_ENABLE, 0); - if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & + if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - drm_err(&dev_priv->drm, + drm_err(&i915->drm, "Power state not reset for PLL:%d\n", port); } } -static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, - struct intel_shared_dpll *pll, - struct intel_dpll_hw_state *hw_state) +static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, + struct intel_shared_dpll *pll, + struct intel_dpll_hw_state *hw_state) { enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ intel_wakeref_t wakeref; @@ -2045,49 +2068,49 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, u32 val; bool ret; - bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); + bxt_port_to_phy_channel(i915, port, &phy, &ch); - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; ret = false; - val = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); + val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)); if (!(val & PORT_PLL_ENABLE)) goto out; - hw_state->ebb0 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)); + hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch)); hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; - hw_state->ebb4 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); + hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; - hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); + hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); hw_state->pll0 &= PORT_PLL_M2_INT_MASK; - hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); + hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1)); hw_state->pll1 &= PORT_PLL_N_MASK; - hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); + hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2)); hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; - hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); + hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; - hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); + hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | PORT_PLL_INT_COEFF_MASK | PORT_PLL_GAIN_CTL_MASK; - hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); + hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8)); hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; - hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); + hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9)); hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; - hw_state->pll10 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); + hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | PORT_PLL_DCO_AMP_MASK; @@ -2096,20 +2119,20 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, * can read only lane registers. We configure all lanes the same way, so * here just read out lanes 0/1 and output a note if lanes 2/3 differ. */ - hw_state->pcsdw12 = intel_de_read(dev_priv, + hw_state->pcsdw12 = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch)); - if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) - drm_dbg(&dev_priv->drm, + if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) + drm_dbg(&i915->drm, "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", hw_state->pcsdw12, - intel_de_read(dev_priv, + intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch))); hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -2300,15 +2323,15 @@ static int bxt_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; enum intel_dpll_id id; /* 1:1 mapping between ports and PLLs */ id = (enum intel_dpll_id) encoder->port; - pll = intel_get_shared_dpll_by_id(dev_priv, id); + pll = intel_get_shared_dpll_by_id(i915, id); - drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n", + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); intel_reference_shared_dpll(state, crtc, @@ -2326,10 +2349,10 @@ static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915) /* DSI non-SSC ref 19.2MHz */ } -static void bxt_dump_hw_state(struct drm_i915_private *dev_priv, +static void bxt_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," + drm_dbg_kms(&i915->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", hw_state->ebb0, @@ -2557,9 +2580,9 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = { static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); const struct icl_combo_pll_params *params = - dev_priv->display.dpll.ref_clks.nssc == 24000 ? + i915->display.dpll.ref_clks.nssc == 24000 ? icl_dp_combo_pll_24MHz_values : icl_dp_combo_pll_19_2MHz_values; int clock = crtc_state->port_clock; @@ -2579,12 +2602,12 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - if (DISPLAY_VER(dev_priv) >= 12) { - switch (dev_priv->display.dpll.ref_clks.nssc) { + if (DISPLAY_VER(i915) >= 12) { + switch (i915->display.dpll.ref_clks.nssc) { default: - MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); + MISSING_CASE(i915->display.dpll.ref_clks.nssc); fallthrough; case 19200: case 38400: @@ -2595,9 +2618,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, break; } } else { - switch (dev_priv->display.dpll.ref_clks.nssc) { + switch (i915->display.dpll.ref_clks.nssc) { default: - MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); + MISSING_CASE(i915->display.dpll.ref_clks.nssc); fallthrough; case 19200: case 38400: @@ -2853,8 +2876,8 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, struct intel_dpll_hw_state *pll_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - int refclk_khz = dev_priv->display.dpll.ref_clks.nssc; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + int refclk_khz = i915->display.dpll.ref_clks.nssc; int clock = crtc_state->port_clock; u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac; u32 iref_ndiv, iref_trim, iref_pulse_w; @@ -2864,7 +2887,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, u64 tmp; bool use_ssc = false; bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); - bool is_dkl = DISPLAY_VER(dev_priv) >= 12; + bool is_dkl = DISPLAY_VER(i915) >= 12; int ret; ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz, @@ -2962,8 +2985,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, DKL_PLL_DIV0_PROP_COEFF(prop_coeff) | DKL_PLL_DIV0_FBPREDIV(m1div) | DKL_PLL_DIV0_FBDIV_INT(m2div_int); - if (dev_priv->display.vbt.override_afc_startup) { - u8 val = dev_priv->display.vbt.override_afc_startup_val; + if (i915->display.vbt.override_afc_startup) { + u8 val = i915->display.vbt.override_afc_startup_val; pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val); } @@ -3053,16 +3076,16 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, return 0; } -static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv, +static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) { u32 m1, m2_int, m2_frac, div1, div2, ref_clock; u64 tmp; - ref_clock = dev_priv->display.dpll.ref_clks.nssc; + ref_clock = i915->display.dpll.ref_clks.nssc; - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(i915) >= 12) { m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; @@ -3167,7 +3190,7 @@ static void icl_update_active_dpll(struct intel_atomic_state *state, static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3184,12 +3207,12 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, if (ret) return ret; - icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); + icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); /* this is mainly for the fastset check */ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); - crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL, + crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL, &port_dpll->hw_state); return 0; @@ -3199,7 +3222,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3207,13 +3230,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, enum port port = encoder->port; unsigned long dpll_mask; - if (IS_ALDERLAKE_S(dev_priv)) { + if (IS_ALDERLAKE_S(i915)) { dpll_mask = BIT(DPLL_ID_DG1_DPLL3) | BIT(DPLL_ID_DG1_DPLL2) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - } else if (IS_DG1(dev_priv)) { + } else if (IS_DG1(i915)) { if (port == PORT_D || port == PORT_E) { dpll_mask = BIT(DPLL_ID_DG1_DPLL2) | @@ -3223,13 +3246,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, BIT(DPLL_ID_DG1_DPLL0) | BIT(DPLL_ID_DG1_DPLL1); } - } else if (IS_ROCKETLAKE(dev_priv)) { + } else if (IS_ROCKETLAKE(i915)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - } else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && - port != PORT_A) { + } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && + port != PORT_A) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | @@ -3239,7 +3262,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, } /* Eliminate DPLLs from consideration if reserved by HTI */ - dpll_mask &= ~intel_hti_dpll_mask(dev_priv); + dpll_mask &= ~intel_hti_dpll_mask(i915); port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -3258,7 +3281,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3271,7 +3294,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, if (ret) return ret; - icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); + icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state); @@ -3281,7 +3304,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, /* this is mainly for the fastset check */ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); - crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL, + crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, &port_dpll->hw_state); return 0; @@ -3291,7 +3314,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3310,7 +3333,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; - dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, + dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(i915, encoder->port)); port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -3337,12 +3360,12 @@ static int icl_compute_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct drm_i915_private *i915 = to_i915(state->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_phy_is_combo(i915, phy)) return icl_compute_combo_phy_dpll(state, crtc); - else if (intel_phy_is_tc(dev_priv, phy)) + else if (intel_phy_is_tc(i915, phy)) return icl_compute_tc_phy_dplls(state, crtc); MISSING_CASE(phy); @@ -3354,12 +3377,12 @@ static int icl_get_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct drm_i915_private *i915 = to_i915(state->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_phy_is_combo(i915, phy)) return icl_get_combo_phy_dpll(state, crtc, encoder); - else if (intel_phy_is_tc(dev_priv, phy)) + else if (intel_phy_is_tc(i915, phy)) return icl_get_tc_phy_dplls(state, crtc, encoder); MISSING_CASE(phy); @@ -3393,7 +3416,7 @@ static void icl_put_dplls(struct intel_atomic_state *state, } } -static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool mg_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -3403,46 +3426,46 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, bool ret = false; u32 val; - i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, enable_reg); + val = intel_de_read(i915, enable_reg); if (!(val & PLL_ENABLE)) goto out; - hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, + hw_state->mg_refclkin_ctl = intel_de_read(i915, MG_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); + intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; hw_state->mg_clktop2_hsclkctl = - intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); + intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; - hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)); - hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); - hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port)); - hw_state->mg_pll_frac_lock = intel_de_read(dev_priv, + hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port)); + hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port)); + hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port)); + hw_state->mg_pll_frac_lock = intel_de_read(i915, MG_PLL_FRAC_LOCK(tc_port)); - hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port)); - hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias = - intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); - if (dev_priv->display.dpll.ref_clks.nssc == 38400) { + if (i915->display.dpll.ref_clks.nssc == 38400) { hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; hw_state->mg_pll_bias_mask = 0; } else { @@ -3455,11 +3478,11 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { @@ -3469,12 +3492,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, bool ret = false; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, intel_tc_pll_enable_reg(dev_priv, pll)); + val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll)); if (!(val & PLL_ENABLE)) goto out; @@ -3482,12 +3505,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, * All registers read here have the same HIP_INDEX_REG even though * they are on different building blocks */ - hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv, + hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); + intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3495,42 +3518,42 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port)); + hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); val = DKL_PLL_DIV0_MASK; - if (dev_priv->display.vbt.override_afc_startup) + if (i915->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; hw_state->mg_pll_div0 &= val; - hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); + hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool icl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state, i915_reg_t enable_reg) @@ -3540,94 +3563,94 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, bool ret = false; u32 val; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(dev_priv, enable_reg); + val = intel_de_read(i915, enable_reg); if (!(val & PLL_ENABLE)) goto out; - if (IS_ALDERLAKE_S(dev_priv)) { - hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id)); - } else if (IS_DG1(dev_priv)) { - hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); - } else if (IS_ROCKETLAKE(dev_priv)) { - hw_state->cfgcr0 = intel_de_read(dev_priv, + if (IS_ALDERLAKE_S(i915)) { + hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id)); + } else if (IS_DG1(i915)) { + hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id)); + } else if (IS_ROCKETLAKE(i915)) { + hw_state->cfgcr0 = intel_de_read(i915, RKL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, + hw_state->cfgcr1 = intel_de_read(i915, RKL_DPLL_CFGCR1(id)); - } else if (DISPLAY_VER(dev_priv) >= 12) { - hw_state->cfgcr0 = intel_de_read(dev_priv, + } else if (DISPLAY_VER(i915) >= 12) { + hw_state->cfgcr0 = intel_de_read(i915, TGL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, + hw_state->cfgcr1 = intel_de_read(i915, TGL_DPLL_CFGCR1(id)); - if (dev_priv->display.vbt.override_afc_startup) { - hw_state->div0 = intel_de_read(dev_priv, TGL_DPLL0_DIV0(id)); + if (i915->display.vbt.override_afc_startup) { + hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK; } } else { - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && id == DPLL_ID_EHL_DPLL4) { - hw_state->cfgcr0 = intel_de_read(dev_priv, + hw_state->cfgcr0 = intel_de_read(i915, ICL_DPLL_CFGCR0(4)); - hw_state->cfgcr1 = intel_de_read(dev_priv, + hw_state->cfgcr1 = intel_de_read(i915, ICL_DPLL_CFGCR1(4)); } else { - hw_state->cfgcr0 = intel_de_read(dev_priv, + hw_state->cfgcr0 = intel_de_read(i915, ICL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(dev_priv, + hw_state->cfgcr1 = intel_de_read(i915, ICL_DPLL_CFGCR1(id)); } } ret = true; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool combo_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); - return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); + return icl_pll_get_hw_state(i915, pll, hw_state, enable_reg); } -static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv, +static bool tbt_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { - return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE); + return icl_pll_get_hw_state(i915, pll, hw_state, TBT_PLL_ENABLE); } -static void icl_dpll_write(struct drm_i915_private *dev_priv, +static void icl_dpll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; const enum intel_dpll_id id = pll->info->id; i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG; - if (IS_ALDERLAKE_S(dev_priv)) { + if (IS_ALDERLAKE_S(i915)) { cfgcr0_reg = ADLS_DPLL_CFGCR0(id); cfgcr1_reg = ADLS_DPLL_CFGCR1(id); - } else if (IS_DG1(dev_priv)) { + } else if (IS_DG1(i915)) { cfgcr0_reg = DG1_DPLL_CFGCR0(id); cfgcr1_reg = DG1_DPLL_CFGCR1(id); - } else if (IS_ROCKETLAKE(dev_priv)) { + } else if (IS_ROCKETLAKE(i915)) { cfgcr0_reg = RKL_DPLL_CFGCR0(id); cfgcr1_reg = RKL_DPLL_CFGCR1(id); - } else if (DISPLAY_VER(dev_priv) >= 12) { + } else if (DISPLAY_VER(i915) >= 12) { cfgcr0_reg = TGL_DPLL_CFGCR0(id); cfgcr1_reg = TGL_DPLL_CFGCR1(id); div0_reg = TGL_DPLL0_DIV0(id); } else { - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && id == DPLL_ID_EHL_DPLL4) { cfgcr0_reg = ICL_DPLL_CFGCR0(4); cfgcr1_reg = ICL_DPLL_CFGCR1(4); @@ -3637,18 +3660,18 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, } } - intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); - intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1); - drm_WARN_ON_ONCE(&dev_priv->drm, dev_priv->display.vbt.override_afc_startup && + intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0); + intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1); + drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup && !i915_mmio_reg_valid(div0_reg)); - if (dev_priv->display.vbt.override_afc_startup && + if (i915->display.vbt.override_afc_startup && i915_mmio_reg_valid(div0_reg)) - intel_de_rmw(dev_priv, div0_reg, + intel_de_rmw(i915, div0_reg, TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); - intel_de_posting_read(dev_priv, cfgcr1_reg); + intel_de_posting_read(i915, cfgcr1_reg); } -static void icl_mg_pll_write(struct drm_i915_private *dev_priv, +static void icl_mg_pll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; @@ -3660,38 +3683,38 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv, * during the calc/readout phase if the mask depends on some other HW * state like refclk, see icl_calc_mg_pll_state(). */ - intel_de_rmw(dev_priv, MG_REFCLKIN_CTL(tc_port), + intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port), MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl); - intel_de_rmw(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port), + intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port), MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK, hw_state->mg_clktop2_coreclkctl1); - intel_de_rmw(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port), + intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port), MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK, hw_state->mg_clktop2_hsclkctl); - intel_de_write(dev_priv, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); - intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); - intel_de_write(dev_priv, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); - intel_de_write(dev_priv, MG_PLL_FRAC_LOCK(tc_port), + intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); + intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); + intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); + intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock); - intel_de_write(dev_priv, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); + intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); - intel_de_rmw(dev_priv, MG_PLL_BIAS(tc_port), + intel_de_rmw(i915, MG_PLL_BIAS(tc_port), hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias); - intel_de_rmw(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port), + intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port), hw_state->mg_pll_tdc_coldst_bias_mask, hw_state->mg_pll_tdc_coldst_bias); - intel_de_posting_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); } -static void dkl_pll_write(struct drm_i915_private *dev_priv, +static void dkl_pll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; @@ -3703,83 +3726,83 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv, * though on different building block */ /* All the registers are RMW */ - val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)); + val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val); + intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val); + intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val); val = DKL_PLL_DIV0_MASK; - if (dev_priv->display.vbt.override_afc_startup) + if (i915->display.vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; - intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val, + intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val, hw_state->mg_pll_div0); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); + val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), val); + intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); + val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), val); + intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); + val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), val); + intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val); - val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); - intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); } -static void icl_pll_power_enable(struct drm_i915_private *dev_priv, +static void icl_pll_power_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { - intel_de_rmw(dev_priv, enable_reg, 0, PLL_POWER_ENABLE); + intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE); /* * The spec says we need to "wait" but it also says it should be * immediate. */ - if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", + if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1)) + drm_err(&i915->drm, "PLL %d Power not enabled\n", pll->info->id); } -static void icl_pll_enable(struct drm_i915_private *dev_priv, +static void icl_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { - intel_de_rmw(dev_priv, enable_reg, 0, PLL_ENABLE); + intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE); /* Timeout is actually 600us. */ - if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id); + if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1)) + drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id); } static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) @@ -3806,12 +3829,12 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); } -static void combo_pll_enable(struct drm_i915_private *dev_priv, +static void combo_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && pll->info->id == DPLL_ID_EHL_DPLL4) { /* @@ -3819,13 +3842,13 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, * This can be done by taking a reference on DPLL4 power * domain. */ - pll->wakeref = intel_display_power_get(dev_priv, + pll->wakeref = intel_display_power_get(i915, POWER_DOMAIN_DC_OFF); } - icl_pll_power_enable(dev_priv, pll, enable_reg); + icl_pll_power_enable(i915, pll, enable_reg); - icl_dpll_write(dev_priv, pll); + icl_dpll_write(i915, pll); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3833,19 +3856,19 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, * nothing here. */ - icl_pll_enable(dev_priv, pll, enable_reg); + icl_pll_enable(i915, pll, enable_reg); - adlp_cmtg_clock_gating_wa(dev_priv, pll); + adlp_cmtg_clock_gating_wa(i915, pll); /* DVFS post sequence would be here. See the comment above. */ } -static void tbt_pll_enable(struct drm_i915_private *dev_priv, +static void tbt_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE); + icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE); - icl_dpll_write(dev_priv, pll); + icl_dpll_write(i915, pll); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3853,22 +3876,22 @@ static void tbt_pll_enable(struct drm_i915_private *dev_priv, * nothing here. */ - icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE); + icl_pll_enable(i915, pll, TBT_PLL_ENABLE); /* DVFS post sequence would be here. See the comment above. */ } -static void mg_pll_enable(struct drm_i915_private *dev_priv, +static void mg_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); - icl_pll_power_enable(dev_priv, pll, enable_reg); + icl_pll_power_enable(i915, pll, enable_reg); - if (DISPLAY_VER(dev_priv) >= 12) - dkl_pll_write(dev_priv, pll); + if (DISPLAY_VER(i915) >= 12) + dkl_pll_write(i915, pll); else - icl_mg_pll_write(dev_priv, pll); + icl_mg_pll_write(i915, pll); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3876,12 +3899,12 @@ static void mg_pll_enable(struct drm_i915_private *dev_priv, * nothing here. */ - icl_pll_enable(dev_priv, pll, enable_reg); + icl_pll_enable(i915, pll, enable_reg); /* DVFS post sequence would be here. See the comment above. */ } -static void icl_pll_disable(struct drm_i915_private *dev_priv, +static void icl_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { @@ -3893,50 +3916,50 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, * nothing here. */ - intel_de_rmw(dev_priv, enable_reg, PLL_ENABLE, 0); + intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0); /* Timeout is actually 1us. */ - if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id); + if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1)) + drm_err(&i915->drm, "PLL %d locked\n", pll->info->id); /* DVFS post sequence would be here. See the comment above. */ - intel_de_rmw(dev_priv, enable_reg, PLL_POWER_ENABLE, 0); + intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0); /* * The spec says we need to "wait" but it also says it should be * immediate. */ - if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", + if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1)) + drm_err(&i915->drm, "PLL %d Power not disabled\n", pll->info->id); } -static void combo_pll_disable(struct drm_i915_private *dev_priv, +static void combo_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); - icl_pll_disable(dev_priv, pll, enable_reg); + icl_pll_disable(i915, pll, enable_reg); - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && pll->info->id == DPLL_ID_EHL_DPLL4) - intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, + intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, pll->wakeref); } -static void tbt_pll_disable(struct drm_i915_private *dev_priv, +static void tbt_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE); + icl_pll_disable(i915, pll, TBT_PLL_ENABLE); } -static void mg_pll_disable(struct drm_i915_private *dev_priv, +static void mg_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); - icl_pll_disable(dev_priv, pll, enable_reg); + icl_pll_disable(i915, pll, enable_reg); } static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) @@ -3945,10 +3968,10 @@ static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; } -static void icl_dump_hw_state(struct drm_i915_private *dev_priv, +static void icl_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, div0: 0x%x, " "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, " @@ -4130,62 +4153,64 @@ static const struct intel_dpll_mgr adlp_pll_mgr = { /** * intel_shared_dpll_init - Initialize shared DPLLs - * @dev_priv: i915 device + * @i915: i915 device * - * Initialize shared DPLLs for @dev_priv. + * Initialize shared DPLLs for @i915. */ -void intel_shared_dpll_init(struct drm_i915_private *dev_priv) +void intel_shared_dpll_init(struct drm_i915_private *i915) { const struct intel_dpll_mgr *dpll_mgr = NULL; const struct dpll_info *dpll_info; int i; - mutex_init(&dev_priv->display.dpll.lock); + mutex_init(&i915->display.dpll.lock); - if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) + if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915)) /* No shared DPLLs on DG2; port PLLs are part of the PHY */ dpll_mgr = NULL; - else if (IS_ALDERLAKE_P(dev_priv)) + else if (IS_ALDERLAKE_P(i915)) dpll_mgr = &adlp_pll_mgr; - else if (IS_ALDERLAKE_S(dev_priv)) + else if (IS_ALDERLAKE_S(i915)) dpll_mgr = &adls_pll_mgr; - else if (IS_DG1(dev_priv)) + else if (IS_DG1(i915)) dpll_mgr = &dg1_pll_mgr; - else if (IS_ROCKETLAKE(dev_priv)) + else if (IS_ROCKETLAKE(i915)) dpll_mgr = &rkl_pll_mgr; - else if (DISPLAY_VER(dev_priv) >= 12) + else if (DISPLAY_VER(i915) >= 12) dpll_mgr = &tgl_pll_mgr; - else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) + else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) dpll_mgr = &ehl_pll_mgr; - else if (DISPLAY_VER(dev_priv) >= 11) + else if (DISPLAY_VER(i915) >= 11) dpll_mgr = &icl_pll_mgr; - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) dpll_mgr = &bxt_pll_mgr; - else if (DISPLAY_VER(dev_priv) == 9) + else if (DISPLAY_VER(i915) == 9) dpll_mgr = &skl_pll_mgr; - else if (HAS_DDI(dev_priv)) + else if (HAS_DDI(i915)) dpll_mgr = &hsw_pll_mgr; - else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) + else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915)) dpll_mgr = &pch_pll_mgr; - if (!dpll_mgr) { - dev_priv->display.dpll.num_shared_dpll = 0; + if (!dpll_mgr) return; - } dpll_info = dpll_mgr->dpll_info; for (i = 0; dpll_info[i].name; i++) { - if (drm_WARN_ON(&dev_priv->drm, - i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls))) + if (drm_WARN_ON(&i915->drm, + i >= ARRAY_SIZE(i915->display.dpll.shared_dplls))) + break; + + /* must fit into unsigned long bitmask on 32bit */ + if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32)) break; - drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id); - dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i]; + i915->display.dpll.shared_dplls[i].info = &dpll_info[i]; + i915->display.dpll.shared_dplls[i].index = i; } - dev_priv->display.dpll.mgr = dpll_mgr; - dev_priv->display.dpll.num_shared_dpll = i; + i915->display.dpll.mgr = dpll_mgr; + i915->display.dpll.num_shared_dpll = i; } /** @@ -4206,10 +4231,10 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; - if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) + if (drm_WARN_ON(&i915->drm, !dpll_mgr)) return -EINVAL; return dpll_mgr->compute_dplls(state, crtc, encoder); @@ -4239,10 +4264,10 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; - if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) + if (drm_WARN_ON(&i915->drm, !dpll_mgr)) return -EINVAL; return dpll_mgr->get_dplls(state, crtc, encoder); @@ -4262,8 +4287,8 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, void intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; /* * FIXME: this function is called for every platform having a @@ -4291,10 +4316,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; - if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) + if (drm_WARN_ON(&i915->drm, !dpll_mgr)) return; dpll_mgr->update_active_dpll(state, crtc, encoder); @@ -4370,10 +4395,11 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915) void intel_dpll_readout_hw_state(struct drm_i915_private *i915) { + struct intel_shared_dpll *pll; int i; - for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) - readout_dpll_hw_state(i915, &i915->display.dpll.shared_dplls[i]); + for_each_shared_dpll(i915, pll, i) + readout_dpll_hw_state(i915, pll); } static void sanitize_dpll_state(struct drm_i915_private *i915, @@ -4397,29 +4423,30 @@ static void sanitize_dpll_state(struct drm_i915_private *i915, void intel_dpll_sanitize_state(struct drm_i915_private *i915) { + struct intel_shared_dpll *pll; int i; - for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) - sanitize_dpll_state(i915, &i915->display.dpll.shared_dplls[i]); + for_each_shared_dpll(i915, pll, i) + sanitize_dpll_state(i915, pll); } /** * intel_dpll_dump_hw_state - write hw_state to dmesg - * @dev_priv: i915 drm device + * @i915: i915 drm device * @hw_state: hw state to be written to the log * * Write the relevant values in @hw_state to dmesg using drm_dbg_kms. */ -void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, +void intel_dpll_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state) { - if (dev_priv->display.dpll.mgr) { - dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state); + if (i915->display.dpll.mgr) { + i915->display.dpll.mgr->dump_hw_state(i915, hw_state); } else { /* fallback for platforms that don't use the shared dpll * infrastructure */ - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " "fp0: 0x%x, fp1: 0x%x\n", hw_state->dpll, @@ -4430,10 +4457,10 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, } static void -verify_single_dpll_state(struct drm_i915_private *dev_priv, +verify_single_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_crtc *crtc, - struct intel_crtc_state *new_crtc_state) + const struct intel_crtc_state *new_crtc_state) { struct intel_dpll_hw_state dpll_hw_state; u8 pipe_mask; @@ -4441,22 +4468,22 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); - drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); + drm_dbg_kms(&i915->drm, "%s\n", pll->info->name); - active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state); + active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { - I915_STATE_WARN(dev_priv, !pll->on && pll->active_mask, + I915_STATE_WARN(i915, !pll->on && pll->active_mask, "pll in active use but not on in sw tracking\n"); - I915_STATE_WARN(dev_priv, pll->on && !pll->active_mask, + I915_STATE_WARN(i915, pll->on && !pll->active_mask, "pll is on but not used by any active pipe\n"); - I915_STATE_WARN(dev_priv, pll->on != active, + I915_STATE_WARN(i915, pll->on != active, "pll on state mismatch (expected %i, found %i)\n", pll->on, active); } if (!crtc) { - I915_STATE_WARN(dev_priv, + I915_STATE_WARN(i915, pll->active_mask & ~pll->state.pipe_mask, "more active pll users than references: 0x%x vs 0x%x\n", pll->active_mask, pll->state.pipe_mask); @@ -4467,32 +4494,35 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, pipe_mask = BIT(crtc->pipe); if (new_crtc_state->hw.active) - I915_STATE_WARN(dev_priv, !(pll->active_mask & pipe_mask), + I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask), "pll active mismatch (expected pipe %c in active mask 0x%x)\n", pipe_name(crtc->pipe), pll->active_mask); else - I915_STATE_WARN(dev_priv, pll->active_mask & pipe_mask, + I915_STATE_WARN(i915, pll->active_mask & pipe_mask, "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", pipe_name(crtc->pipe), pll->active_mask); - I915_STATE_WARN(dev_priv, !(pll->state.pipe_mask & pipe_mask), + I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask), "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", pipe_mask, pll->state.pipe_mask); - I915_STATE_WARN(dev_priv, + I915_STATE_WARN(i915, pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, sizeof(dpll_hw_state)), "pll hw state mismatch\n"); } -void intel_shared_dpll_state_verify(struct intel_crtc *crtc, - struct intel_crtc_state *old_crtc_state, - struct intel_crtc_state *new_crtc_state) +void intel_shared_dpll_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); if (new_crtc_state->shared_dpll) - verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, + verify_single_dpll_state(i915, new_crtc_state->shared_dpll, crtc, new_crtc_state); if (old_crtc_state->shared_dpll && @@ -4500,20 +4530,21 @@ void intel_shared_dpll_state_verify(struct intel_crtc *crtc, u8 pipe_mask = BIT(crtc->pipe); struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; - I915_STATE_WARN(dev_priv, pll->active_mask & pipe_mask, + I915_STATE_WARN(i915, pll->active_mask & pipe_mask, "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", pipe_name(crtc->pipe), pll->active_mask); - I915_STATE_WARN(dev_priv, pll->state.pipe_mask & pipe_mask, + I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask, "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", pipe_name(crtc->pipe), pll->state.pipe_mask); } } -void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915) +void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state) { + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_shared_dpll *pll; int i; - for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) - verify_single_dpll_state(i915, &i915->display.dpll.shared_dplls[i], - NULL, NULL); + for_each_shared_dpll(i915, pll, i) + verify_single_dpll_state(i915, pll, NULL, NULL); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 04e6810954b2..dd4796a61751 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -29,6 +29,10 @@ #include "intel_wakeref.h" +#define for_each_shared_dpll(__i915, __pll, __i) \ + for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \ + ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++) + enum tc_port; struct drm_i915_private; struct intel_atomic_state; @@ -262,8 +266,7 @@ struct dpll_info { const struct intel_shared_dpll_funcs *funcs; /** - * @id: unique indentifier for this DPLL; should match the index in the - * dev_priv->shared_dplls array + * @id: unique indentifier for this DPLL */ enum intel_dpll_id id; @@ -291,6 +294,11 @@ struct intel_shared_dpll { struct intel_shared_dpll_state state; /** + * @index: index for atomic state + */ + u8 index; + + /** * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL */ u8 active_mask; @@ -319,9 +327,9 @@ struct intel_shared_dpll { /* shared dpll functions */ struct intel_shared_dpll * -intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, +intel_get_shared_dpll_by_id(struct drm_i915_private *i915, enum intel_dpll_id id); -void assert_shared_dpll(struct drm_i915_private *dev_priv, +void assert_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll, bool state); #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) @@ -351,19 +359,18 @@ bool intel_dpll_get_hw_state(struct drm_i915_private *i915, void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void intel_shared_dpll_init(struct drm_i915_private *dev_priv); -void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv); -void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); -void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); +void intel_shared_dpll_init(struct drm_i915_private *i915); +void intel_dpll_update_ref_clks(struct drm_i915_private *i915); +void intel_dpll_readout_hw_state(struct drm_i915_private *i915); +void intel_dpll_sanitize_state(struct drm_i915_private *i915); -void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, +void intel_dpll_dump_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *hw_state); enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); bool intel_dpll_is_combophy(enum intel_dpll_id id); -void intel_shared_dpll_state_verify(struct intel_crtc *crtc, - struct intel_crtc_state *old_crtc_state, - struct intel_crtc_state *new_crtc_state); -void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915); +void intel_shared_dpll_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state); #endif /* _INTEL_DPLL_MGR_H_ */ diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index e56ec3f2d84a..24b2cbcfc1ef 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -565,6 +565,9 @@ static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) u8 payload_size = *(data + 6); u8 *payload_data; + drm_dbg_kms(&i915->drm, "bus %d client-addr 0x%02x reg 0x%02x data %*ph\n", + vbt_i2c_bus_num, slave_addr, reg_offset, payload_size, data + 7); + if (intel_dsi->i2c_bus_num < 0) { intel_dsi->i2c_bus_num = vbt_i2c_bus_num; i2c_acpi_find_adapter(intel_dsi, slave_addr); diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index d9f427856fb8..55d6743374bd 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -319,7 +319,7 @@ intel_dvo_detect(struct drm_connector *_connector, bool force) drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id, connector->base.name); - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); diff --git a/drivers/gpu/drm/i915/display/intel_dvo.h b/drivers/gpu/drm/i915/display/intel_dvo.h index 3ed0fdf8efff..bf7a356422ab 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.h +++ b/drivers/gpu/drm/i915/display/intel_dvo.h @@ -8,6 +8,12 @@ struct drm_i915_private; +#ifdef I915 void intel_dvo_init(struct drm_i915_private *dev_priv); +#else +static inline void intel_dvo_init(struct drm_i915_private *dev_priv) +{ +} +#endif #endif /* __INTEL_DVO_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1cb9eec29640..4820d21cc942 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -593,6 +593,9 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) if (IS_IVYBRIDGE(i915)) dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); + if (DISPLAY_VER(i915) >= 20) + dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id); + if (fbc_state->fence_id >= 0) dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; @@ -850,39 +853,64 @@ void intel_fbc_cleanup(struct drm_i915_private *i915) } } -static bool stride_is_valid(const struct intel_plane_state *plane_state) +static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int stride = intel_fbc_plane_stride(plane_state) * fb->format->cpp[0]; - /* This should have been caught earlier. */ - if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0)) - return false; + return stride == 4096 || stride == 8192; +} - /* Below are the additional FBC restrictions. */ - if (stride < 512) - return false; +static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state) +{ + const struct drm_framebuffer *fb = plane_state->hw.fb; + unsigned int stride = intel_fbc_plane_stride(plane_state) * + fb->format->cpp[0]; - if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3) - return stride == 4096 || stride == 8192; + return stride >= 2048 && stride <= 16384; +} - if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048) - return false; +static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state) +{ + return true; +} + +static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state) +{ + const struct drm_framebuffer *fb = plane_state->hw.fb; + unsigned int stride = intel_fbc_plane_stride(plane_state) * + fb->format->cpp[0]; /* Display WA #1105: skl,bxt,kbl,cfl,glk */ - if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) && - fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) + if (fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) return false; - if (stride > 16384) - return false; + return true; +} +static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state) +{ return true; } -static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) +static bool stride_is_valid(const struct intel_plane_state *plane_state) +{ + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + + if (DISPLAY_VER(i915) >= 11) + return icl_fbc_stride_is_valid(plane_state); + else if (DISPLAY_VER(i915) >= 9) + return skl_fbc_stride_is_valid(plane_state); + else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) + return g4x_fbc_stride_is_valid(plane_state); + else if (DISPLAY_VER(i915) == 4) + return i965_fbc_stride_is_valid(plane_state); + else + return i8xx_fbc_stride_is_valid(plane_state); +} + +static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) { struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); const struct drm_framebuffer *fb = plane_state->hw.fb; @@ -896,6 +924,22 @@ static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) /* 16bpp not supported on gen2 */ if (DISPLAY_VER(i915) == 2) return false; + return true; + default: + return false; + } +} + +static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) +{ + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + const struct drm_framebuffer *fb = plane_state->hw.fb; + + switch (fb->format->format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + return true; + case DRM_FORMAT_RGB565: /* WaFbcOnly1to1Ratio:ctg */ if (IS_G4X(i915)) return false; @@ -905,22 +949,68 @@ static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) } } -static bool rotation_is_valid(const struct intel_plane_state *plane_state) +static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) +{ + const struct drm_framebuffer *fb = plane_state->hw.fb; + + switch (fb->format->format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_RGB565: + return true; + default: + return false; + } +} + +static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) { struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + + if (DISPLAY_VER(i915) >= 20) + return lnl_fbc_pixel_format_is_valid(plane_state); + else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) + return g4x_fbc_pixel_format_is_valid(plane_state); + else + return i8xx_fbc_pixel_format_is_valid(plane_state); +} + +static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) +{ + return plane_state->hw.rotation == DRM_MODE_ROTATE_0; +} + +static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) +{ + return true; +} + +static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) +{ const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; - if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 && + if (fb->format->format == DRM_FORMAT_RGB565 && drm_rotation_90_or_270(rotation)) return false; - else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) && - rotation != DRM_MODE_ROTATE_0) - return false; return true; } +static bool rotation_is_valid(const struct intel_plane_state *plane_state) +{ + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + + if (DISPLAY_VER(i915) >= 9) + return skl_fbc_rotation_is_valid(plane_state); + else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) + return g4x_fbc_rotation_is_valid(plane_state); + else + return i8xx_fbc_rotation_is_valid(plane_state); +} + /* * For some reason, the hardware tracking starts looking at whatever we * programmed as the display plane base address register. It does not look at @@ -954,16 +1044,21 @@ static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state * return effective_w <= max_w && effective_h <= max_h; } -static bool tiling_is_valid(const struct intel_plane_state *plane_state) +static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state) +{ + const struct drm_framebuffer *fb = plane_state->hw.fb; + + return fb->modifier == I915_FORMAT_MOD_X_TILED; +} + +static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); const struct drm_framebuffer *fb = plane_state->hw.fb; switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: - return DISPLAY_VER(i915) >= 9; case I915_FORMAT_MOD_4_TILED: case I915_FORMAT_MOD_X_TILED: return true; @@ -972,6 +1067,16 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state) } } +static bool tiling_is_valid(const struct intel_plane_state *plane_state) +{ + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + + if (DISPLAY_VER(i915) >= 9) + return skl_fbc_tiling_valid(plane_state); + else + return i8xx_fbc_tiling_valid(plane_state); +} + static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) @@ -1129,7 +1234,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && + if (DISPLAY_VER(i915) < 20 && + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && fb->format->has_alpha) { plane_state->no_fbc_reason = "per-pixel alpha not supported"; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 412a19a888a2..ec46716b2f49 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -56,6 +56,7 @@ */ #include "gem/i915_gem_object_frontbuffer.h" +#include "i915_active.h" #include "i915_drv.h" #include "intel_display_trace.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 8cca4793cf92..c89da3568ebd 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -173,14 +173,8 @@ bool intel_hdcp2_capable(struct intel_connector *connector) /* If MTL+ make sure gsc is loaded and proxy is setup */ if (intel_hdcp_gsc_cs_required(i915)) { - struct intel_gt *gt = i915->media_gt; - struct intel_gsc_uc *gsc = gt ? >->uc.gsc : NULL; - - if (!gsc || !intel_uc_fw_is_running(&gsc->fw)) { - drm_dbg_kms(&i915->drm, - "GSC components required for HDCP2.2 are not ready\n"); + if (!intel_hdcp_gsc_check_status(i915)) return false; - } } /* MEI/GSC interface is solid depending on which is used */ diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c index d753db3eef15..18117b789b16 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c @@ -11,610 +11,27 @@ #include "i915_drv.h" #include "i915_utils.h" #include "intel_hdcp_gsc.h" +#include "intel_hdcp_gsc_message.h" bool intel_hdcp_gsc_cs_required(struct drm_i915_private *i915) { return DISPLAY_VER(i915) >= 14; } -static int -gsc_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data, - struct hdcp2_ake_init *ake_data) +bool intel_hdcp_gsc_check_status(struct drm_i915_private *i915) { - struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } }; - struct wired_cmd_initiate_hdcp2_session_out - session_init_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data || !ake_data) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - session_init_in.header.api_version = HDCP_API_VERSION; - session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION; - session_init_in.header.status = FW_HDCP_STATUS_SUCCESS; - session_init_in.header.buffer_len = - WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN; - - session_init_in.port.integrated_port_type = data->port_type; - session_init_in.port.physical_port = (u8)data->hdcp_ddi; - session_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - session_init_in.protocol = data->protocol; - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&session_init_in, - sizeof(session_init_in), - (u8 *)&session_init_out, - sizeof(session_init_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (session_init_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", - WIRED_INITIATE_HDCP2_SESSION, - session_init_out.header.status); - return -EIO; - } - - ake_data->msg_id = HDCP_2_2_AKE_INIT; - ake_data->tx_caps = session_init_out.tx_caps; - memcpy(ake_data->r_tx, session_init_out.r_tx, HDCP_2_2_RTX_LEN); - - return 0; -} - -static int -gsc_hdcp_verify_receiver_cert_prepare_km(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ake_send_cert *rx_cert, - bool *km_stored, - struct hdcp2_ake_no_stored_km - *ek_pub_km, - size_t *msg_sz) -{ - struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = { { 0 } }; - struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data || !rx_cert || !km_stored || !ek_pub_km || !msg_sz) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - verify_rxcert_in.header.api_version = HDCP_API_VERSION; - verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT; - verify_rxcert_in.header.status = FW_HDCP_STATUS_SUCCESS; - verify_rxcert_in.header.buffer_len = - WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN; - - verify_rxcert_in.port.integrated_port_type = data->port_type; - verify_rxcert_in.port.physical_port = (u8)data->hdcp_ddi; - verify_rxcert_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - - verify_rxcert_in.cert_rx = rx_cert->cert_rx; - memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN); - memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN); - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_rxcert_in, - sizeof(verify_rxcert_in), - (u8 *)&verify_rxcert_out, - sizeof(verify_rxcert_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed: %zd\n", byte); - return byte; - } - - if (verify_rxcert_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", - WIRED_VERIFY_RECEIVER_CERT, - verify_rxcert_out.header.status); - return -EIO; - } - - *km_stored = !!verify_rxcert_out.km_stored; - if (verify_rxcert_out.km_stored) { - ek_pub_km->msg_id = HDCP_2_2_AKE_STORED_KM; - *msg_sz = sizeof(struct hdcp2_ake_stored_km); - } else { - ek_pub_km->msg_id = HDCP_2_2_AKE_NO_STORED_KM; - *msg_sz = sizeof(struct hdcp2_ake_no_stored_km); - } - - memcpy(ek_pub_km->e_kpub_km, &verify_rxcert_out.ekm_buff, - sizeof(verify_rxcert_out.ekm_buff)); - - return 0; -} - -static int -gsc_hdcp_verify_hprime(struct device *dev, struct hdcp_port_data *data, - struct hdcp2_ake_send_hprime *rx_hprime) -{ - struct wired_cmd_ake_send_hprime_in send_hprime_in = { { 0 } }; - struct wired_cmd_ake_send_hprime_out send_hprime_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data || !rx_hprime) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - send_hprime_in.header.api_version = HDCP_API_VERSION; - send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME; - send_hprime_in.header.status = FW_HDCP_STATUS_SUCCESS; - send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN; - - send_hprime_in.port.integrated_port_type = data->port_type; - send_hprime_in.port.physical_port = (u8)data->hdcp_ddi; - send_hprime_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - - memcpy(send_hprime_in.h_prime, rx_hprime->h_prime, - HDCP_2_2_H_PRIME_LEN); - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&send_hprime_in, - sizeof(send_hprime_in), - (u8 *)&send_hprime_out, - sizeof(send_hprime_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (send_hprime_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", - WIRED_AKE_SEND_HPRIME, send_hprime_out.header.status); - return -EIO; - } - - return 0; -} - -static int -gsc_hdcp_store_pairing_info(struct device *dev, struct hdcp_port_data *data, - struct hdcp2_ake_send_pairing_info *pairing_info) -{ - struct wired_cmd_ake_send_pairing_info_in pairing_info_in = { { 0 } }; - struct wired_cmd_ake_send_pairing_info_out pairing_info_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data || !pairing_info) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - pairing_info_in.header.api_version = HDCP_API_VERSION; - pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO; - pairing_info_in.header.status = FW_HDCP_STATUS_SUCCESS; - pairing_info_in.header.buffer_len = - WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN; - - pairing_info_in.port.integrated_port_type = data->port_type; - pairing_info_in.port.physical_port = (u8)data->hdcp_ddi; - pairing_info_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - - memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km, - HDCP_2_2_E_KH_KM_LEN); - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&pairing_info_in, - sizeof(pairing_info_in), - (u8 *)&pairing_info_out, - sizeof(pairing_info_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (pairing_info_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. Status: 0x%X\n", - WIRED_AKE_SEND_PAIRING_INFO, - pairing_info_out.header.status); - return -EIO; - } - - return 0; -} - -static int -gsc_hdcp_initiate_locality_check(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_lc_init *lc_init_data) -{ - struct wired_cmd_init_locality_check_in lc_init_in = { { 0 } }; - struct wired_cmd_init_locality_check_out lc_init_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data || !lc_init_data) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - lc_init_in.header.api_version = HDCP_API_VERSION; - lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK; - lc_init_in.header.status = FW_HDCP_STATUS_SUCCESS; - lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN; - - lc_init_in.port.integrated_port_type = data->port_type; - lc_init_in.port.physical_port = (u8)data->hdcp_ddi; - lc_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&lc_init_in, sizeof(lc_init_in), - (u8 *)&lc_init_out, sizeof(lc_init_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (lc_init_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X Failed. status: 0x%X\n", - WIRED_INIT_LOCALITY_CHECK, lc_init_out.header.status); - return -EIO; - } - - lc_init_data->msg_id = HDCP_2_2_LC_INIT; - memcpy(lc_init_data->r_n, lc_init_out.r_n, HDCP_2_2_RN_LEN); - - return 0; -} - -static int -gsc_hdcp_verify_lprime(struct device *dev, struct hdcp_port_data *data, - struct hdcp2_lc_send_lprime *rx_lprime) -{ - struct wired_cmd_validate_locality_in verify_lprime_in = { { 0 } }; - struct wired_cmd_validate_locality_out verify_lprime_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data || !rx_lprime) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - verify_lprime_in.header.api_version = HDCP_API_VERSION; - verify_lprime_in.header.command_id = WIRED_VALIDATE_LOCALITY; - verify_lprime_in.header.status = FW_HDCP_STATUS_SUCCESS; - verify_lprime_in.header.buffer_len = - WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN; - - verify_lprime_in.port.integrated_port_type = data->port_type; - verify_lprime_in.port.physical_port = (u8)data->hdcp_ddi; - verify_lprime_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - - memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime, - HDCP_2_2_L_PRIME_LEN); - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_lprime_in, - sizeof(verify_lprime_in), - (u8 *)&verify_lprime_out, - sizeof(verify_lprime_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (verify_lprime_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", - WIRED_VALIDATE_LOCALITY, - verify_lprime_out.header.status); - return -EIO; - } - - return 0; -} - -static int gsc_hdcp_get_session_key(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ske_send_eks *ske_data) -{ - struct wired_cmd_get_session_key_in get_skey_in = { { 0 } }; - struct wired_cmd_get_session_key_out get_skey_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data || !ske_data) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - get_skey_in.header.api_version = HDCP_API_VERSION; - get_skey_in.header.command_id = WIRED_GET_SESSION_KEY; - get_skey_in.header.status = FW_HDCP_STATUS_SUCCESS; - get_skey_in.header.buffer_len = WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN; - - get_skey_in.port.integrated_port_type = data->port_type; - get_skey_in.port.physical_port = (u8)data->hdcp_ddi; - get_skey_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&get_skey_in, sizeof(get_skey_in), - (u8 *)&get_skey_out, sizeof(get_skey_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (get_skey_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", - WIRED_GET_SESSION_KEY, get_skey_out.header.status); - return -EIO; - } - - ske_data->msg_id = HDCP_2_2_SKE_SEND_EKS; - memcpy(ske_data->e_dkey_ks, get_skey_out.e_dkey_ks, - HDCP_2_2_E_DKEY_KS_LEN); - memcpy(ske_data->riv, get_skey_out.r_iv, HDCP_2_2_RIV_LEN); - - return 0; -} - -static int -gsc_hdcp_repeater_check_flow_prepare_ack(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_rep_send_receiverid_list - *rep_topology, - struct hdcp2_rep_send_ack - *rep_send_ack) -{ - struct wired_cmd_verify_repeater_in verify_repeater_in = { { 0 } }; - struct wired_cmd_verify_repeater_out verify_repeater_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !rep_topology || !rep_send_ack || !data) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - verify_repeater_in.header.api_version = HDCP_API_VERSION; - verify_repeater_in.header.command_id = WIRED_VERIFY_REPEATER; - verify_repeater_in.header.status = FW_HDCP_STATUS_SUCCESS; - verify_repeater_in.header.buffer_len = - WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN; - - verify_repeater_in.port.integrated_port_type = data->port_type; - verify_repeater_in.port.physical_port = (u8)data->hdcp_ddi; - verify_repeater_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - - memcpy(verify_repeater_in.rx_info, rep_topology->rx_info, - HDCP_2_2_RXINFO_LEN); - memcpy(verify_repeater_in.seq_num_v, rep_topology->seq_num_v, - HDCP_2_2_SEQ_NUM_LEN); - memcpy(verify_repeater_in.v_prime, rep_topology->v_prime, - HDCP_2_2_V_PRIME_HALF_LEN); - memcpy(verify_repeater_in.receiver_ids, rep_topology->receiver_ids, - HDCP_2_2_RECEIVER_IDS_MAX_LEN); - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_repeater_in, - sizeof(verify_repeater_in), - (u8 *)&verify_repeater_out, - sizeof(verify_repeater_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (verify_repeater_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", - WIRED_VERIFY_REPEATER, - verify_repeater_out.header.status); - return -EIO; - } - - memcpy(rep_send_ack->v, verify_repeater_out.v, - HDCP_2_2_V_PRIME_HALF_LEN); - rep_send_ack->msg_id = HDCP_2_2_REP_SEND_ACK; - - return 0; -} - -static int gsc_hdcp_verify_mprime(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_rep_stream_ready *stream_ready) -{ - struct wired_cmd_repeater_auth_stream_req_in *verify_mprime_in; - struct wired_cmd_repeater_auth_stream_req_out - verify_mprime_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - size_t cmd_size; - - if (!dev || !stream_ready || !data) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - cmd_size = struct_size(verify_mprime_in, streams, data->k); - if (cmd_size == SIZE_MAX) - return -EINVAL; - - verify_mprime_in = kzalloc(cmd_size, GFP_KERNEL); - if (!verify_mprime_in) - return -ENOMEM; - - verify_mprime_in->header.api_version = HDCP_API_VERSION; - verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ; - verify_mprime_in->header.status = FW_HDCP_STATUS_SUCCESS; - verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header); - - verify_mprime_in->port.integrated_port_type = data->port_type; - verify_mprime_in->port.physical_port = (u8)data->hdcp_ddi; - verify_mprime_in->port.attached_transcoder = (u8)data->hdcp_transcoder; - - memcpy(verify_mprime_in->m_prime, stream_ready->m_prime, HDCP_2_2_MPRIME_LEN); - drm_hdcp_cpu_to_be24(verify_mprime_in->seq_num_m, data->seq_num_m); - - memcpy(verify_mprime_in->streams, data->streams, - array_size(data->k, sizeof(*data->streams))); - - verify_mprime_in->k = cpu_to_be16(data->k); - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)verify_mprime_in, cmd_size, - (u8 *)&verify_mprime_out, - sizeof(verify_mprime_out)); - kfree(verify_mprime_in); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (verify_mprime_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", - WIRED_REPEATER_AUTH_STREAM_REQ, - verify_mprime_out.header.status); - return -EIO; - } - - return 0; -} - -static int gsc_hdcp_enable_authentication(struct device *dev, - struct hdcp_port_data *data) -{ - struct wired_cmd_enable_auth_in enable_auth_in = { { 0 } }; - struct wired_cmd_enable_auth_out enable_auth_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - enable_auth_in.header.api_version = HDCP_API_VERSION; - enable_auth_in.header.command_id = WIRED_ENABLE_AUTH; - enable_auth_in.header.status = FW_HDCP_STATUS_SUCCESS; - enable_auth_in.header.buffer_len = WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN; - - enable_auth_in.port.integrated_port_type = data->port_type; - enable_auth_in.port.physical_port = (u8)data->hdcp_ddi; - enable_auth_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - enable_auth_in.stream_type = data->streams[0].stream_type; - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&enable_auth_in, - sizeof(enable_auth_in), - (u8 *)&enable_auth_out, - sizeof(enable_auth_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } - - if (enable_auth_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", - WIRED_ENABLE_AUTH, enable_auth_out.header.status); - return -EIO; - } - - return 0; -} - -static int -gsc_hdcp_close_session(struct device *dev, struct hdcp_port_data *data) -{ - struct wired_cmd_close_session_in session_close_in = { { 0 } }; - struct wired_cmd_close_session_out session_close_out = { { 0 } }; - struct drm_i915_private *i915; - ssize_t byte; - - if (!dev || !data) - return -EINVAL; - - i915 = kdev_to_i915(dev); - if (!i915) { - dev_err(dev, "DRM not initialized, aborting HDCP.\n"); - return -ENODEV; - } - - session_close_in.header.api_version = HDCP_API_VERSION; - session_close_in.header.command_id = WIRED_CLOSE_SESSION; - session_close_in.header.status = FW_HDCP_STATUS_SUCCESS; - session_close_in.header.buffer_len = - WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN; - - session_close_in.port.integrated_port_type = data->port_type; - session_close_in.port.physical_port = (u8)data->hdcp_ddi; - session_close_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&session_close_in, - sizeof(session_close_in), - (u8 *)&session_close_out, - sizeof(session_close_out)); - if (byte < 0) { - drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); - return byte; - } + struct intel_gt *gt = i915->media_gt; + struct intel_gsc_uc *gsc = gt ? >->uc.gsc : NULL; - if (session_close_out.header.status != FW_HDCP_STATUS_SUCCESS) { - drm_dbg_kms(&i915->drm, "Session Close Failed. status: 0x%X\n", - session_close_out.header.status); - return -EIO; + if (!gsc || !intel_uc_fw_is_running(&gsc->fw)) { + drm_dbg_kms(&i915->drm, + "GSC components required for HDCP2.2 are not ready\n"); + return false; } - return 0; + return true; } -static const struct i915_hdcp_ops gsc_hdcp_ops = { - .initiate_hdcp2_session = gsc_hdcp_initiate_session, - .verify_receiver_cert_prepare_km = - gsc_hdcp_verify_receiver_cert_prepare_km, - .verify_hprime = gsc_hdcp_verify_hprime, - .store_pairing_info = gsc_hdcp_store_pairing_info, - .initiate_locality_check = gsc_hdcp_initiate_locality_check, - .verify_lprime = gsc_hdcp_verify_lprime, - .get_session_key = gsc_hdcp_get_session_key, - .repeater_check_flow_prepare_ack = - gsc_hdcp_repeater_check_flow_prepare_ack, - .verify_mprime = gsc_hdcp_verify_mprime, - .enable_hdcp_authentication = gsc_hdcp_enable_authentication, - .close_hdcp_session = gsc_hdcp_close_session, -}; - /*This function helps allocate memory for the command that we will send to gsc cs */ static int intel_hdcp_gsc_initialize_message(struct drm_i915_private *i915, struct intel_hdcp_gsc_message *hdcp_message) @@ -667,6 +84,22 @@ out_unpin: return err; } +static const struct i915_hdcp_ops gsc_hdcp_ops = { + .initiate_hdcp2_session = intel_hdcp_gsc_initiate_session, + .verify_receiver_cert_prepare_km = + intel_hdcp_gsc_verify_receiver_cert_prepare_km, + .verify_hprime = intel_hdcp_gsc_verify_hprime, + .store_pairing_info = intel_hdcp_gsc_store_pairing_info, + .initiate_locality_check = intel_hdcp_gsc_initiate_locality_check, + .verify_lprime = intel_hdcp_gsc_verify_lprime, + .get_session_key = intel_hdcp_gsc_get_session_key, + .repeater_check_flow_prepare_ack = + intel_hdcp_gsc_repeater_check_flow_prepare_ack, + .verify_mprime = intel_hdcp_gsc_verify_mprime, + .enable_hdcp_authentication = intel_hdcp_gsc_enable_authentication, + .close_hdcp_session = intel_hdcp_gsc_close_session, +}; + static int intel_hdcp_gsc_hdcp2_init(struct drm_i915_private *i915) { struct intel_hdcp_gsc_message *hdcp_message; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h index cbf96551e534..eba2057c5a9e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h @@ -23,5 +23,6 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in, size_t msg_out_len); int intel_hdcp_gsc_init(struct drm_i915_private *i915); void intel_hdcp_gsc_fini(struct drm_i915_private *i915); +bool intel_hdcp_gsc_check_status(struct drm_i915_private *i915); #endif /* __INTEL_HDCP_GCS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c new file mode 100644 index 000000000000..caa9f0b25729 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c @@ -0,0 +1,592 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2023, Intel Corporation. + */ + +#include <linux/err.h> +#include <drm/i915_hdcp_interface.h> + +#include "i915_drv.h" +#include "intel_hdcp_gsc_message.h" + +int +intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, + struct hdcp2_ake_init *ake_data) +{ + struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } }; + struct wired_cmd_initiate_hdcp2_session_out + session_init_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data || !ake_data) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + session_init_in.header.api_version = HDCP_API_VERSION; + session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION; + session_init_in.header.status = FW_HDCP_STATUS_SUCCESS; + session_init_in.header.buffer_len = + WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN; + + session_init_in.port.integrated_port_type = data->port_type; + session_init_in.port.physical_port = (u8)data->hdcp_ddi; + session_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + session_init_in.protocol = data->protocol; + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&session_init_in, + sizeof(session_init_in), + (u8 *)&session_init_out, + sizeof(session_init_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (session_init_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", + WIRED_INITIATE_HDCP2_SESSION, + session_init_out.header.status); + return -EIO; + } + + ake_data->msg_id = HDCP_2_2_AKE_INIT; + ake_data->tx_caps = session_init_out.tx_caps; + memcpy(ake_data->r_tx, session_init_out.r_tx, HDCP_2_2_RTX_LEN); + + return 0; +} + +int +intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ake_send_cert *rx_cert, + bool *km_stored, + struct hdcp2_ake_no_stored_km + *ek_pub_km, + size_t *msg_sz) +{ + struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = { { 0 } }; + struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data || !rx_cert || !km_stored || !ek_pub_km || !msg_sz) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + verify_rxcert_in.header.api_version = HDCP_API_VERSION; + verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT; + verify_rxcert_in.header.status = FW_HDCP_STATUS_SUCCESS; + verify_rxcert_in.header.buffer_len = + WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN; + + verify_rxcert_in.port.integrated_port_type = data->port_type; + verify_rxcert_in.port.physical_port = (u8)data->hdcp_ddi; + verify_rxcert_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + + verify_rxcert_in.cert_rx = rx_cert->cert_rx; + memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN); + memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN); + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_rxcert_in, + sizeof(verify_rxcert_in), + (u8 *)&verify_rxcert_out, + sizeof(verify_rxcert_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed: %zd\n", byte); + return byte; + } + + if (verify_rxcert_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", + WIRED_VERIFY_RECEIVER_CERT, + verify_rxcert_out.header.status); + return -EIO; + } + + *km_stored = !!verify_rxcert_out.km_stored; + if (verify_rxcert_out.km_stored) { + ek_pub_km->msg_id = HDCP_2_2_AKE_STORED_KM; + *msg_sz = sizeof(struct hdcp2_ake_stored_km); + } else { + ek_pub_km->msg_id = HDCP_2_2_AKE_NO_STORED_KM; + *msg_sz = sizeof(struct hdcp2_ake_no_stored_km); + } + + memcpy(ek_pub_km->e_kpub_km, &verify_rxcert_out.ekm_buff, + sizeof(verify_rxcert_out.ekm_buff)); + + return 0; +} + +int +intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, + struct hdcp2_ake_send_hprime *rx_hprime) +{ + struct wired_cmd_ake_send_hprime_in send_hprime_in = { { 0 } }; + struct wired_cmd_ake_send_hprime_out send_hprime_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data || !rx_hprime) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + send_hprime_in.header.api_version = HDCP_API_VERSION; + send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME; + send_hprime_in.header.status = FW_HDCP_STATUS_SUCCESS; + send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN; + + send_hprime_in.port.integrated_port_type = data->port_type; + send_hprime_in.port.physical_port = (u8)data->hdcp_ddi; + send_hprime_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + + memcpy(send_hprime_in.h_prime, rx_hprime->h_prime, + HDCP_2_2_H_PRIME_LEN); + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&send_hprime_in, + sizeof(send_hprime_in), + (u8 *)&send_hprime_out, + sizeof(send_hprime_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (send_hprime_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X Failed. Status: 0x%X\n", + WIRED_AKE_SEND_HPRIME, send_hprime_out.header.status); + return -EIO; + } + + return 0; +} + +int +intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *data, + struct hdcp2_ake_send_pairing_info *pairing_info) +{ + struct wired_cmd_ake_send_pairing_info_in pairing_info_in = { { 0 } }; + struct wired_cmd_ake_send_pairing_info_out pairing_info_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data || !pairing_info) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + pairing_info_in.header.api_version = HDCP_API_VERSION; + pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO; + pairing_info_in.header.status = FW_HDCP_STATUS_SUCCESS; + pairing_info_in.header.buffer_len = + WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN; + + pairing_info_in.port.integrated_port_type = data->port_type; + pairing_info_in.port.physical_port = (u8)data->hdcp_ddi; + pairing_info_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + + memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km, + HDCP_2_2_E_KH_KM_LEN); + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&pairing_info_in, + sizeof(pairing_info_in), + (u8 *)&pairing_info_out, + sizeof(pairing_info_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (pairing_info_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. Status: 0x%X\n", + WIRED_AKE_SEND_PAIRING_INFO, + pairing_info_out.header.status); + return -EIO; + } + + return 0; +} + +int +intel_hdcp_gsc_initiate_locality_check(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_lc_init *lc_init_data) +{ + struct wired_cmd_init_locality_check_in lc_init_in = { { 0 } }; + struct wired_cmd_init_locality_check_out lc_init_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data || !lc_init_data) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + lc_init_in.header.api_version = HDCP_API_VERSION; + lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK; + lc_init_in.header.status = FW_HDCP_STATUS_SUCCESS; + lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN; + + lc_init_in.port.integrated_port_type = data->port_type; + lc_init_in.port.physical_port = (u8)data->hdcp_ddi; + lc_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&lc_init_in, sizeof(lc_init_in), + (u8 *)&lc_init_out, sizeof(lc_init_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (lc_init_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X Failed. status: 0x%X\n", + WIRED_INIT_LOCALITY_CHECK, lc_init_out.header.status); + return -EIO; + } + + lc_init_data->msg_id = HDCP_2_2_LC_INIT; + memcpy(lc_init_data->r_n, lc_init_out.r_n, HDCP_2_2_RN_LEN); + + return 0; +} + +int +intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, + struct hdcp2_lc_send_lprime *rx_lprime) +{ + struct wired_cmd_validate_locality_in verify_lprime_in = { { 0 } }; + struct wired_cmd_validate_locality_out verify_lprime_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data || !rx_lprime) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + verify_lprime_in.header.api_version = HDCP_API_VERSION; + verify_lprime_in.header.command_id = WIRED_VALIDATE_LOCALITY; + verify_lprime_in.header.status = FW_HDCP_STATUS_SUCCESS; + verify_lprime_in.header.buffer_len = + WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN; + + verify_lprime_in.port.integrated_port_type = data->port_type; + verify_lprime_in.port.physical_port = (u8)data->hdcp_ddi; + verify_lprime_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + + memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime, + HDCP_2_2_L_PRIME_LEN); + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_lprime_in, + sizeof(verify_lprime_in), + (u8 *)&verify_lprime_out, + sizeof(verify_lprime_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (verify_lprime_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", + WIRED_VALIDATE_LOCALITY, + verify_lprime_out.header.status); + return -EIO; + } + + return 0; +} + +int intel_hdcp_gsc_get_session_key(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ske_send_eks *ske_data) +{ + struct wired_cmd_get_session_key_in get_skey_in = { { 0 } }; + struct wired_cmd_get_session_key_out get_skey_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data || !ske_data) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + get_skey_in.header.api_version = HDCP_API_VERSION; + get_skey_in.header.command_id = WIRED_GET_SESSION_KEY; + get_skey_in.header.status = FW_HDCP_STATUS_SUCCESS; + get_skey_in.header.buffer_len = WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN; + + get_skey_in.port.integrated_port_type = data->port_type; + get_skey_in.port.physical_port = (u8)data->hdcp_ddi; + get_skey_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&get_skey_in, sizeof(get_skey_in), + (u8 *)&get_skey_out, sizeof(get_skey_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (get_skey_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", + WIRED_GET_SESSION_KEY, get_skey_out.header.status); + return -EIO; + } + + ske_data->msg_id = HDCP_2_2_SKE_SEND_EKS; + memcpy(ske_data->e_dkey_ks, get_skey_out.e_dkey_ks, + HDCP_2_2_E_DKEY_KS_LEN); + memcpy(ske_data->riv, get_skey_out.r_iv, HDCP_2_2_RIV_LEN); + + return 0; +} + +int +intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_rep_send_receiverid_list + *rep_topology, + struct hdcp2_rep_send_ack + *rep_send_ack) +{ + struct wired_cmd_verify_repeater_in verify_repeater_in = { { 0 } }; + struct wired_cmd_verify_repeater_out verify_repeater_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !rep_topology || !rep_send_ack || !data) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + verify_repeater_in.header.api_version = HDCP_API_VERSION; + verify_repeater_in.header.command_id = WIRED_VERIFY_REPEATER; + verify_repeater_in.header.status = FW_HDCP_STATUS_SUCCESS; + verify_repeater_in.header.buffer_len = + WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN; + + verify_repeater_in.port.integrated_port_type = data->port_type; + verify_repeater_in.port.physical_port = (u8)data->hdcp_ddi; + verify_repeater_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + + memcpy(verify_repeater_in.rx_info, rep_topology->rx_info, + HDCP_2_2_RXINFO_LEN); + memcpy(verify_repeater_in.seq_num_v, rep_topology->seq_num_v, + HDCP_2_2_SEQ_NUM_LEN); + memcpy(verify_repeater_in.v_prime, rep_topology->v_prime, + HDCP_2_2_V_PRIME_HALF_LEN); + memcpy(verify_repeater_in.receiver_ids, rep_topology->receiver_ids, + HDCP_2_2_RECEIVER_IDS_MAX_LEN); + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_repeater_in, + sizeof(verify_repeater_in), + (u8 *)&verify_repeater_out, + sizeof(verify_repeater_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (verify_repeater_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", + WIRED_VERIFY_REPEATER, + verify_repeater_out.header.status); + return -EIO; + } + + memcpy(rep_send_ack->v, verify_repeater_out.v, + HDCP_2_2_V_PRIME_HALF_LEN); + rep_send_ack->msg_id = HDCP_2_2_REP_SEND_ACK; + + return 0; +} + +int intel_hdcp_gsc_verify_mprime(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_rep_stream_ready *stream_ready) +{ + struct wired_cmd_repeater_auth_stream_req_in *verify_mprime_in; + struct wired_cmd_repeater_auth_stream_req_out + verify_mprime_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + size_t cmd_size; + + if (!dev || !stream_ready || !data) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + cmd_size = struct_size(verify_mprime_in, streams, data->k); + if (cmd_size == SIZE_MAX) + return -EINVAL; + + verify_mprime_in = kzalloc(cmd_size, GFP_KERNEL); + if (!verify_mprime_in) + return -ENOMEM; + + verify_mprime_in->header.api_version = HDCP_API_VERSION; + verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ; + verify_mprime_in->header.status = FW_HDCP_STATUS_SUCCESS; + verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header); + + verify_mprime_in->port.integrated_port_type = data->port_type; + verify_mprime_in->port.physical_port = (u8)data->hdcp_ddi; + verify_mprime_in->port.attached_transcoder = (u8)data->hdcp_transcoder; + + memcpy(verify_mprime_in->m_prime, stream_ready->m_prime, HDCP_2_2_MPRIME_LEN); + drm_hdcp_cpu_to_be24(verify_mprime_in->seq_num_m, data->seq_num_m); + + memcpy(verify_mprime_in->streams, data->streams, + array_size(data->k, sizeof(*data->streams))); + + verify_mprime_in->k = cpu_to_be16(data->k); + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)verify_mprime_in, cmd_size, + (u8 *)&verify_mprime_out, + sizeof(verify_mprime_out)); + kfree(verify_mprime_in); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (verify_mprime_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", + WIRED_REPEATER_AUTH_STREAM_REQ, + verify_mprime_out.header.status); + return -EIO; + } + + return 0; +} + +int intel_hdcp_gsc_enable_authentication(struct device *dev, + struct hdcp_port_data *data) +{ + struct wired_cmd_enable_auth_in enable_auth_in = { { 0 } }; + struct wired_cmd_enable_auth_out enable_auth_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + enable_auth_in.header.api_version = HDCP_API_VERSION; + enable_auth_in.header.command_id = WIRED_ENABLE_AUTH; + enable_auth_in.header.status = FW_HDCP_STATUS_SUCCESS; + enable_auth_in.header.buffer_len = WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN; + + enable_auth_in.port.integrated_port_type = data->port_type; + enable_auth_in.port.physical_port = (u8)data->hdcp_ddi; + enable_auth_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + enable_auth_in.stream_type = data->streams[0].stream_type; + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&enable_auth_in, + sizeof(enable_auth_in), + (u8 *)&enable_auth_out, + sizeof(enable_auth_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (enable_auth_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "FW cmd 0x%08X failed. status: 0x%X\n", + WIRED_ENABLE_AUTH, enable_auth_out.header.status); + return -EIO; + } + + return 0; +} + +int +intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data) +{ + struct wired_cmd_close_session_in session_close_in = { { 0 } }; + struct wired_cmd_close_session_out session_close_out = { { 0 } }; + struct drm_i915_private *i915; + ssize_t byte; + + if (!dev || !data) + return -EINVAL; + + i915 = kdev_to_i915(dev); + if (!i915) { + dev_err(dev, "DRM not initialized, aborting HDCP.\n"); + return -ENODEV; + } + + session_close_in.header.api_version = HDCP_API_VERSION; + session_close_in.header.command_id = WIRED_CLOSE_SESSION; + session_close_in.header.status = FW_HDCP_STATUS_SUCCESS; + session_close_in.header.buffer_len = + WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN; + + session_close_in.port.integrated_port_type = data->port_type; + session_close_in.port.physical_port = (u8)data->hdcp_ddi; + session_close_in.port.attached_transcoder = (u8)data->hdcp_transcoder; + + byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&session_close_in, + sizeof(session_close_in), + (u8 *)&session_close_out, + sizeof(session_close_out)); + if (byte < 0) { + drm_dbg_kms(&i915->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); + return byte; + } + + if (session_close_out.header.status != FW_HDCP_STATUS_SUCCESS) { + drm_dbg_kms(&i915->drm, "Session Close Failed. status: 0x%X\n", + session_close_out.header.status); + return -EIO; + } + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h new file mode 100644 index 000000000000..ce199d6f6232 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __INTEL_HDCP_GSC_MESSAGE_H__ +#define __INTEL_HDCP_GSC_MESSAGE_H__ + +#include <linux/types.h> + +struct device; +struct drm_i915_private; +struct hdcp_port_data; +struct hdcp2_ake_init; +struct hdcp2_ake_send_cert; +struct hdcp2_ake_no_stored_km; +struct hdcp2_ake_send_hprime; +struct hdcp2_ake_send_pairing_info; +struct hdcp2_lc_init; +struct hdcp2_lc_send_lprime; +struct hdcp2_ske_send_eks; +struct hdcp2_rep_send_receiverid_list; +struct hdcp2_rep_send_ack; +struct hdcp2_rep_stream_ready; + +ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in, + size_t msg_in_len, u8 *msg_out, + size_t msg_out_len); +bool intel_hdcp_gsc_check_status(struct drm_i915_private *i915); +int +intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, + struct hdcp2_ake_init *ake_data); +int +intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ake_send_cert *rx_cert, + bool *km_stored, + struct hdcp2_ake_no_stored_km + *ek_pub_km, + size_t *msg_sz); +int +intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, + struct hdcp2_ake_send_hprime *rx_hprime); +int +intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *data, + struct hdcp2_ake_send_pairing_info *pairing_info); +int +intel_hdcp_gsc_initiate_locality_check(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_lc_init *lc_init_data); +int +intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, + struct hdcp2_lc_send_lprime *rx_lprime); +int intel_hdcp_gsc_get_session_key(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ske_send_eks *ske_data); +int +intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_rep_send_receiverid_list + *rep_topology, + struct hdcp2_rep_send_ack + *rep_send_ack); +int intel_hdcp_gsc_verify_mprime(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_rep_stream_ready *stream_ready); +int intel_hdcp_gsc_enable_authentication(struct device *dev, + struct hdcp_port_data *data); +int +intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data); + +#endif /* __INTEL_HDCP_GSC_MESSAGE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index af4102e91769..ac315f8e7820 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2496,7 +2496,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); - if (!INTEL_DISPLAY_ENABLED(dev_priv)) + if (!intel_display_device_enabled(dev_priv)) return connector_status_disconnected; wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index e8562f6f8bb4..0c0700c6ec66 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -763,7 +763,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) { if (!HAS_DISPLAY(dev_priv) || - !INTEL_DISPLAY_ENABLED(dev_priv)) + !intel_display_device_enabled(dev_priv)) return; WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true); diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.h b/drivers/gpu/drm/i915/display/intel_lpe_audio.h index 0beecac267ae..2c5fcb6e1fd0 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.h +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.h @@ -12,11 +12,29 @@ enum port; enum transcoder; struct drm_i915_private; +#ifdef I915 int intel_lpe_audio_init(struct drm_i915_private *dev_priv); void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder, enum port port, const void *eld, int ls_clock, bool dp_output); +#else +static inline int intel_lpe_audio_init(struct drm_i915_private *dev_priv) +{ + return -ENODEV; +} +static inline void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) +{ +} +static inline void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv) +{ +} +static inline void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder, enum port port, + const void *eld, int ls_clock, bool dp_output) +{ +} +#endif #endif /* __INTEL_LPE_AUDIO_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 152a22a8ffd2..1d048fa98561 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -153,6 +153,18 @@ static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) return current_mode; } +static int lspcon_get_mode_settle_timeout(struct intel_lspcon *lspcon) +{ + /* + * On some CometLake-based device designs the Parade PS175 takes more + * than 400ms to settle in PCON mode. 100 reboot trials on one device + * resulted in a median settle time of 440ms and a maximum of 444ms. + * Even after increasing the timeout to 500ms, 2% of devices still had + * this error. So this sets the timeout to 800ms. + */ + return lspcon->vendor == LSPCON_VENDOR_PARADE ? 800 : 400; +} + static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon, enum drm_lspcon_mode mode) { @@ -167,7 +179,8 @@ static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon, drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n", lspcon_mode_name(mode)); - wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); + wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, + lspcon_get_mode_settle_timeout(lspcon)); if (current_mode != mode) drm_err(&i915->drm, "LSPCON mode hasn't settled\n"); diff --git a/drivers/gpu/drm/i915/display/intel_lvds.h b/drivers/gpu/drm/i915/display/intel_lvds.h index 9d3372dc503f..7ad5fa9c0434 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.h +++ b/drivers/gpu/drm/i915/display/intel_lvds.h @@ -13,10 +13,29 @@ enum pipe; struct drm_i915_private; +#ifdef I915 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, i915_reg_t lvds_reg, enum pipe *pipe); void intel_lvds_init(struct drm_i915_private *dev_priv); struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv); bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv); +#else +static inline bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, + i915_reg_t lvds_reg, enum pipe *pipe) +{ + return false; +} +static inline void intel_lvds_init(struct drm_i915_private *dev_priv) +{ +} +static inline struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) +{ + return NULL; +} +static inline bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) +{ + return false; +} +#endif #endif /* __INTEL_LVDS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index 138144a65a45..5e1c2c780412 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -23,8 +23,8 @@ * Cross check the actual hw state with our own modeset state tracking (and its * internal consistency). */ -static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +static void intel_connector_verify_state(const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { struct intel_connector *connector = to_intel_connector(conn_state->connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); @@ -66,12 +66,12 @@ verify_connector_state(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_connector *connector; - struct drm_connector_state *new_conn_state; + const struct drm_connector_state *new_conn_state; int i; for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { struct drm_encoder *encoder = connector->encoder; - struct intel_crtc_state *crtc_state = NULL; + const struct intel_crtc_state *crtc_state = NULL; if (new_conn_state->crtc != &crtc->base) continue; @@ -86,38 +86,40 @@ verify_connector_state(struct intel_atomic_state *state, } } -static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, - const struct intel_crtc_state *pipe_config) +static void intel_pipe_config_sanity_check(const struct intel_crtc_state *crtc_state) { - if (pipe_config->has_pch_encoder) { - int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), - &pipe_config->fdi_m_n); - int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (crtc_state->has_pch_encoder) { + int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(i915, crtc_state), + &crtc_state->fdi_m_n); + int dotclock = crtc_state->hw.adjusted_mode.crtc_clock; /* * FDI already provided one idea for the dotclock. * Yell if the encoder disagrees. Allow for slight * rounding differences. */ - drm_WARN(&dev_priv->drm, abs(fdi_dotclock - dotclock) > 1, + drm_WARN(&i915->drm, abs(fdi_dotclock - dotclock) > 1, "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", fdi_dotclock, dotclock); } } static void -verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state) +verify_encoder_state(struct intel_atomic_state *state) { + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_encoder *encoder; struct drm_connector *connector; - struct drm_connector_state *old_conn_state, *new_conn_state; + const struct drm_connector_state *old_conn_state, *new_conn_state; int i; - for_each_intel_encoder(&dev_priv->drm, encoder) { + for_each_intel_encoder(&i915->drm, encoder) { bool enabled = false, found = false; enum pipe pipe; - drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s]\n", encoder->base.base.id, encoder->base.name); @@ -132,7 +134,7 @@ verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_stat found = true; enabled = true; - I915_STATE_WARN(dev_priv, + I915_STATE_WARN(i915, new_conn_state->crtc != encoder->base.crtc, "connector's crtc doesn't match encoder crtc\n"); } @@ -140,7 +142,7 @@ verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_stat if (!found) continue; - I915_STATE_WARN(dev_priv, !!encoder->base.crtc != enabled, + I915_STATE_WARN(i915, !!encoder->base.crtc != enabled, "encoder's enabled state mismatch (expected %i, found %i)\n", !!encoder->base.crtc, enabled); @@ -148,7 +150,7 @@ verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_stat bool active; active = encoder->get_hw_state(encoder, &pipe); - I915_STATE_WARN(dev_priv, active, + I915_STATE_WARN(i915, active, "encoder detached but still enabled on pipe %c.\n", pipe_name(pipe)); } @@ -156,96 +158,98 @@ verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_stat } static void -verify_crtc_state(struct intel_crtc *crtc, - struct intel_crtc_state *old_crtc_state, - struct intel_crtc_state *new_crtc_state) +verify_crtc_state(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_encoder *encoder; - struct intel_crtc_state *pipe_config = old_crtc_state; - struct drm_atomic_state *state = old_crtc_state->uapi.state; + struct drm_i915_private *i915 = to_i915(dev); + const struct intel_crtc_state *sw_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct intel_crtc_state *hw_crtc_state; struct intel_crtc *master_crtc; + struct intel_encoder *encoder; - __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); - intel_crtc_free_hw_state(old_crtc_state); - intel_crtc_state_reset(old_crtc_state, crtc); - old_crtc_state->uapi.state = state; + hw_crtc_state = intel_crtc_state_alloc(crtc); + if (!hw_crtc_state) + return; - drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, + drm_dbg_kms(&i915->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name); - pipe_config->hw.enable = new_crtc_state->hw.enable; + hw_crtc_state->hw.enable = sw_crtc_state->hw.enable; - intel_crtc_get_pipe_config(pipe_config); + intel_crtc_get_pipe_config(hw_crtc_state); /* we keep both pipes enabled on 830 */ - if (IS_I830(dev_priv) && pipe_config->hw.active) - pipe_config->hw.active = new_crtc_state->hw.active; + if (IS_I830(i915) && hw_crtc_state->hw.active) + hw_crtc_state->hw.active = sw_crtc_state->hw.active; - I915_STATE_WARN(dev_priv, - new_crtc_state->hw.active != pipe_config->hw.active, + I915_STATE_WARN(i915, + sw_crtc_state->hw.active != hw_crtc_state->hw.active, "crtc active state doesn't match with hw state (expected %i, found %i)\n", - new_crtc_state->hw.active, pipe_config->hw.active); + sw_crtc_state->hw.active, hw_crtc_state->hw.active); - I915_STATE_WARN(dev_priv, crtc->active != new_crtc_state->hw.active, + I915_STATE_WARN(i915, crtc->active != sw_crtc_state->hw.active, "transitional active state does not match atomic hw state (expected %i, found %i)\n", - new_crtc_state->hw.active, crtc->active); + sw_crtc_state->hw.active, crtc->active); - master_crtc = intel_master_crtc(new_crtc_state); + master_crtc = intel_master_crtc(sw_crtc_state); for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { enum pipe pipe; bool active; active = encoder->get_hw_state(encoder, &pipe); - I915_STATE_WARN(dev_priv, active != new_crtc_state->hw.active, + I915_STATE_WARN(i915, active != sw_crtc_state->hw.active, "[ENCODER:%i] active %i with crtc active %i\n", encoder->base.base.id, active, - new_crtc_state->hw.active); + sw_crtc_state->hw.active); - I915_STATE_WARN(dev_priv, active && master_crtc->pipe != pipe, + I915_STATE_WARN(i915, active && master_crtc->pipe != pipe, "Encoder connected to wrong pipe %c\n", pipe_name(pipe)); if (active) - intel_encoder_get_config(encoder, pipe_config); + intel_encoder_get_config(encoder, hw_crtc_state); } - if (!new_crtc_state->hw.active) - return; + if (!sw_crtc_state->hw.active) + goto destroy_state; - intel_pipe_config_sanity_check(dev_priv, pipe_config); + intel_pipe_config_sanity_check(hw_crtc_state); - if (!intel_pipe_config_compare(new_crtc_state, - pipe_config, false)) { - I915_STATE_WARN(dev_priv, 1, "pipe state doesn't match!\n"); - intel_crtc_state_dump(pipe_config, NULL, "hw state"); - intel_crtc_state_dump(new_crtc_state, NULL, "sw state"); + if (!intel_pipe_config_compare(sw_crtc_state, + hw_crtc_state, false)) { + I915_STATE_WARN(i915, 1, "pipe state doesn't match!\n"); + intel_crtc_state_dump(hw_crtc_state, NULL, "hw state"); + intel_crtc_state_dump(sw_crtc_state, NULL, "sw state"); } + +destroy_state: + intel_crtc_destroy_state(&crtc->base, &hw_crtc_state->uapi); } -void intel_modeset_verify_crtc(struct intel_crtc *crtc, - struct intel_atomic_state *state, - struct intel_crtc_state *old_crtc_state, - struct intel_crtc_state *new_crtc_state) +void intel_modeset_verify_crtc(struct intel_atomic_state *state, + struct intel_crtc *crtc) { + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + if (!intel_crtc_needs_modeset(new_crtc_state) && !intel_crtc_needs_fastset(new_crtc_state)) return; - intel_wm_state_verify(crtc, new_crtc_state); + intel_wm_state_verify(state, crtc); verify_connector_state(state, crtc); - verify_crtc_state(crtc, old_crtc_state, new_crtc_state); - intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state); - intel_mpllb_state_verify(state, new_crtc_state); - intel_c10pll_state_verify(state, new_crtc_state); + verify_crtc_state(state, crtc); + intel_shared_dpll_state_verify(state, crtc); + intel_mpllb_state_verify(state, crtc); + intel_c10pll_state_verify(state, crtc); } -void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, - struct intel_atomic_state *state) +void intel_modeset_verify_disabled(struct intel_atomic_state *state) { - verify_encoder_state(dev_priv, state); + verify_encoder_state(state); verify_connector_state(state, NULL); - intel_shared_dpll_verify_disabled(dev_priv); + intel_shared_dpll_verify_disabled(state); } diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.h b/drivers/gpu/drm/i915/display/intel_modeset_verify.h index 2d6fbe4f7846..3bef8735cb4b 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.h +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.h @@ -6,16 +6,11 @@ #ifndef __INTEL_MODESET_VERIFY_H__ #define __INTEL_MODESET_VERIFY_H__ -struct drm_i915_private; struct intel_atomic_state; struct intel_crtc; -struct intel_crtc_state; -void intel_modeset_verify_crtc(struct intel_crtc *crtc, - struct intel_atomic_state *state, - struct intel_crtc_state *old_crtc_state, - struct intel_crtc_state *new_crtc_state); -void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, - struct intel_atomic_state *state); +void intel_modeset_verify_crtc(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_modeset_verify_disabled(struct intel_atomic_state *state); #endif /* __INTEL_MODESET_VERIFY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_overlay.h b/drivers/gpu/drm/i915/display/intel_overlay.h index a167c28acd27..c3f68fce6f08 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.h +++ b/drivers/gpu/drm/i915/display/intel_overlay.h @@ -13,6 +13,7 @@ struct drm_i915_private; struct intel_overlay; struct intel_overlay_error_state; +#ifdef I915 void intel_overlay_setup(struct drm_i915_private *dev_priv); void intel_overlay_cleanup(struct drm_i915_private *dev_priv); int intel_overlay_switch_off(struct intel_overlay *overlay); @@ -25,5 +26,39 @@ struct intel_overlay_error_state * intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, struct intel_overlay_error_state *error); +#else +static inline void intel_overlay_setup(struct drm_i915_private *dev_priv) +{ +} +static inline void intel_overlay_cleanup(struct drm_i915_private *dev_priv) +{ +} +static inline int intel_overlay_switch_off(struct intel_overlay *overlay) +{ + return 0; +} +static inline int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + return 0; +} +static inline int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + return 0; +} +static inline void intel_overlay_reset(struct drm_i915_private *dev_priv) +{ +} +static inline struct intel_overlay_error_state * +intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) +{ + return NULL; +} +static inline void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, + struct intel_overlay_error_state *error) +{ +} +#endif #endif /* __INTEL_OVERLAY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 086cb8dbe22c..483beedac5b8 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -680,7 +680,7 @@ intel_panel_detect(struct drm_connector *connector, bool force) { struct drm_i915_private *i915 = to_i915(connector->dev); - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; return connector_status_connected; diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h index 41a63413cb3d..35f8288af3d1 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.h +++ b/drivers/gpu/drm/i915/display/intel_pch_display.h @@ -15,6 +15,7 @@ struct intel_crtc; struct intel_crtc_state; struct intel_link_m_n; +#ifdef I915 bool intel_has_pch_trancoder(struct drm_i915_private *i915, enum pipe pch_transcoder); enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); @@ -41,5 +42,57 @@ void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n); void intel_pch_sanitize(struct drm_i915_private *i915); +#else +static inline bool intel_has_pch_trancoder(struct drm_i915_private *i915, + enum pipe pch_transcoder) +{ + return false; +} +static inline int intel_crtc_pch_transcoder(struct intel_crtc *crtc) +{ + return 0; +} +static inline void ilk_pch_pre_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void ilk_pch_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void ilk_pch_disable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void ilk_pch_post_disable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void ilk_pch_get_config(struct intel_crtc_state *crtc_state) +{ +} +static inline void lpt_pch_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void lpt_pch_disable(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ +} +static inline void lpt_pch_get_config(struct intel_crtc_state *crtc_state) +{ +} +static inline void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, + struct intel_link_m_n *m_n) +{ +} +static inline void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, + struct intel_link_m_n *m_n) +{ +} +static inline void intel_pch_sanitize(struct drm_i915_private *i915) +{ +} +#endif #endif diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index 9583e86b602a..713cfba71475 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -492,6 +492,7 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; + struct intel_shared_dpll *pll; int i; u32 val, final; bool has_lvds = false; @@ -527,8 +528,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } /* Check if any DPLLs are using the SSC source */ - for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { - u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)); + for_each_shared_dpll(dev_priv, pll, i) { + u32 temp; + + temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id)); if (!(temp & DPLL_VCO_ENABLE)) continue; diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.h b/drivers/gpu/drm/i915/display/intel_pch_refclk.h index 9bcf56629f24..ae3403c0ced8 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.h +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.h @@ -11,6 +11,7 @@ struct drm_i915_private; struct intel_crtc_state; +#ifdef I915 void lpt_program_iclkip(const struct intel_crtc_state *crtc_state); void lpt_disable_iclkip(struct drm_i915_private *dev_priv); int lpt_get_iclkip(struct drm_i915_private *dev_priv); @@ -18,5 +19,27 @@ int lpt_iclkip(const struct intel_crtc_state *crtc_state); void intel_init_pch_refclk(struct drm_i915_private *dev_priv); void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); +#else +static inline void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) +{ +} +static inline void lpt_disable_iclkip(struct drm_i915_private *dev_priv) +{ +} +static inline int lpt_get_iclkip(struct drm_i915_private *dev_priv) +{ + return 0; +} +static inline int lpt_iclkip(const struct intel_crtc_state *crtc_state) +{ + return 0; +} +static inline void intel_init_pch_refclk(struct drm_i915_private *dev_priv) +{ +} +static inline void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) +{ +} +#endif #endif diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 850b11f20285..bb65881e87cc 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2195,10 +2195,12 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, } } -static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, - const struct intel_crtc_state *crtc_state) +void intel_psr_post_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); struct intel_encoder *encoder; if (!crtc_state->has_psr) @@ -2241,20 +2243,6 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, } } -void intel_psr_post_plane_update(const struct intel_atomic_state *state) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_crtc_state *crtc_state; - struct intel_crtc *crtc; - int i; - - if (!HAS_PSR(dev_priv)) - return; - - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) - _intel_psr_post_plane_update(state, crtc_state); -} - static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 0b95e8aa615f..bf35f42df6bc 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -24,7 +24,8 @@ struct intel_plane_state; void intel_psr_init_dpcd(struct intel_dp *intel_dp); void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc); -void intel_psr_post_plane_update(const struct intel_atomic_state *state); +void intel_psr_post_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_psr_disable(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state); int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value); diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 950ba0431f5f..35137e978591 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -2121,7 +2121,7 @@ intel_sdvo_detect(struct drm_connector *connector, bool force) DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; if (!intel_sdvo_set_target_output(intel_sdvo, diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h index 2868852c85f2..d1815b4103d4 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.h +++ b/drivers/gpu/drm/i915/display/intel_sdvo.h @@ -14,9 +14,22 @@ struct drm_i915_private; enum pipe; enum port; +#ifdef I915 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, i915_reg_t sdvo_reg, enum pipe *pipe); bool intel_sdvo_init(struct drm_i915_private *dev_priv, i915_reg_t reg, enum port port); +#else +static inline bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, + i915_reg_t sdvo_reg, enum pipe *pipe) +{ + return false; +} +static inline bool intel_sdvo_init(struct drm_i915_private *dev_priv, + i915_reg_t reg, enum port port) +{ + return false; +} +#endif #endif /* __INTEL_SDVO_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 88ef56b6e0fd..c0285365efae 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -1993,12 +1993,13 @@ int intel_snps_phy_check_hdmi_link_rate(int clock) } void intel_mpllb_state_verify(struct intel_atomic_state *state, - struct intel_crtc_state *new_crtc_state) + struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); struct intel_mpllb_state mpllb_hw_state = { 0 }; - struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); + const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; struct intel_encoder *encoder; if (!IS_DG2(i915)) diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index 557ef820bc0b..515abf7c5902 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -10,6 +10,7 @@ struct drm_i915_private; struct intel_atomic_state; +struct intel_crtc; struct intel_crtc_state; struct intel_encoder; struct intel_mpllb_state; @@ -33,6 +34,6 @@ int intel_snps_phy_check_hdmi_link_rate(int clock); void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_mpllb_state_verify(struct intel_atomic_state *state, - struct intel_crtc_state *new_crtc_state); + struct intel_crtc *crtc); #endif /* __INTEL_SNPS_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h index 91c6dca342b2..044a032e41b9 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.h +++ b/drivers/gpu/drm/i915/display/intel_sprite.h @@ -16,6 +16,7 @@ struct intel_crtc_state; struct intel_plane_state; enum pipe; +#ifdef I915 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe, int plane); int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, @@ -29,5 +30,12 @@ int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); +#else +static inline struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, + int pipe, int plane) +{ + return NULL; +} +#endif #endif /* __INTEL_SPRITE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index 36b479b46b60..31a79fdfc812 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -1720,7 +1720,7 @@ intel_tv_detect(struct drm_connector *connector, drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n", connector->base.id, connector->name, force); - if (!INTEL_DISPLAY_ENABLED(i915)) + if (!intel_display_device_enabled(i915)) return connector_status_disconnected; if (force) { diff --git a/drivers/gpu/drm/i915/display/intel_tv.h b/drivers/gpu/drm/i915/display/intel_tv.h index 44518575ec5c..f08827b8bf2b 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.h +++ b/drivers/gpu/drm/i915/display/intel_tv.h @@ -8,6 +8,12 @@ struct drm_i915_private; +#ifdef I915 void intel_tv_init(struct drm_i915_private *dev_priv); +#else +static inline void intel_tv_init(struct drm_i915_private *dev_priv) +{ +} +#endif #endif /* __INTEL_TV_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 286a0bdd28c6..4b98833bfa8c 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -3,11 +3,9 @@ * Copyright © 2019 Intel Corporation */ -#include <linux/pci.h> #include <linux/vgaarb.h> #include <video/vga.h> - #include "soc/intel_gmch.h" #include "i915_drv.h" @@ -99,20 +97,6 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915) vga_put(pdev, VGA_RSRC_LEGACY_IO); } -static unsigned int -intel_vga_set_decode(struct pci_dev *pdev, bool enable_decode) -{ - struct drm_i915_private *i915 = pdev_to_i915(pdev); - - intel_gmch_vga_set_state(i915, enable_decode); - - if (enable_decode) - return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | - VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; - else - return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; -} - int intel_vga_register(struct drm_i915_private *i915) { @@ -127,7 +111,7 @@ int intel_vga_register(struct drm_i915_private *i915) * then we do not take part in VGA arbitration and the * vga_client_register() fails with -ENODEV. */ - ret = vga_client_register(pdev, intel_vga_set_decode); + ret = vga_client_register(pdev, intel_gmch_vga_set_decode); if (ret && ret != -ENODEV) return ret; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 2a30b8aa2994..245a64332cc7 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1943,13 +1943,16 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) return pipe - PIPE_A + INTEL_FBC_A; } -static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, +static bool skl_plane_has_fbc(struct drm_i915_private *i915, enum intel_fbc_id fbc_id, enum plane_id plane_id) { - if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0) + if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) return false; - return plane_id == PLANE_PRIMARY; + if (DISPLAY_VER(i915) >= 20) + return icl_is_hdr_plane(i915, plane_id); + else + return plane_id == PLANE_PRIMARY; } static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 846e9a3e94dc..99b8ccdc3dfa 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3134,10 +3134,12 @@ static void skl_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915) skl_wm_sanitize(i915); } -void intel_wm_state_verify(struct intel_crtc *crtc, - struct intel_crtc_state *new_crtc_state) +void intel_wm_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); struct skl_hw_state { struct skl_ddb_entry ddb[I915_MAX_PLANES]; struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index edb61e33df83..fb0da36fd3ec 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -38,8 +38,8 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, const struct skl_ddb_entry *entries, int num_entries, int ignore_idx); -void intel_wm_state_verify(struct intel_crtc *crtc, - struct intel_crtc_state *new_crtc_state); +void intel_wm_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc); void skl_watermark_ipc_init(struct drm_i915_private *i915); void skl_watermark_ipc_update(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index a96e7d028c5c..55da627a8b8d 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -23,6 +23,7 @@ * Author: Jani Nikula <jani.nikula@intel.com> */ +#include <linux/dmi.h> #include <linux/slab.h> #include <drm/drm_atomic_helper.h> @@ -1744,6 +1745,126 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) intel_dsi_log_params(intel_dsi); } +typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi); + +/* + * Vtotal is wrong on the Asus TF103C leading to the last line of the display + * being shown as the first line. The factory installed Android has a hardcoded + * modeline, causing it to not suffer from this BIOS bug. + * + * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa + * Fixed mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa + * + * https://gitlab.freedesktop.org/drm/intel/-/issues/9381 + */ +static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi) +{ + /* Cast away the const as we want to fixup the mode */ + struct drm_display_mode *fixed_mode = (struct drm_display_mode *) + intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); + + if (fixed_mode->vtotal == 820) + fixed_mode->vtotal -= 4; +} + +/* + * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems: + * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7 + * which under Linux become bus 0 - 6. And the MIPI sequence reference + * to bus 3 is indented for I2C3 which is bus 2 under Linux. + * + * Note mipi_exec_i2c() cannot just subtract 1 from the bus + * given in the I2C MIPI sequence element. Since on other + * devices the I2C bus-numbers used in the MIPI sequences do + * actually start at 0. + * + * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is + * especially a problem on the 8" 830 version which uses a 10:16 + * portrait screen where as the bogus size is 16:10. + * + * https://gitlab.freedesktop.org/drm/intel/-/issues/9379 + */ +static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi) +{ + const struct drm_display_mode *fixed_mode = + intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); + struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info; + + intel_dsi->i2c_bus_num = 2; + + /* + * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830 + * uses a 1200x1920 portrait screen. + */ + if (fixed_mode->hdisplay == 1920) { + info->width_mm = 216; + info->height_mm = 135; + } else { + info->width_mm = 107; + info->height_mm = 171; + } +} + +/* + * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems: + * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c() + * to not work. Fix this by setting i2c_bus_num. + * 2. There is no backlight off MIPI sequence, causing the backlight to stay on. + * Add a backlight off sequence mirroring the existing backlight on sequence. + * + * https://gitlab.freedesktop.org/drm/intel/-/issues/9380 + */ +static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi) +{ + static const u8 backlight_off_sequence[16] = { + /* Header Seq-id 7, length after header 11 bytes */ + 0x07, 0x0b, 0x00, 0x00, 0x00, + /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */ + 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00, + /* MIPI_SEQ_ELEM_END */ + 0x00 + }; + struct intel_connector *connector = intel_dsi->attached_connector; + + intel_dsi->i2c_bus_num = 0; + connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence; +} + +static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = { + { + /* Asus Transformer Pad TF103C */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), + DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"), + }, + .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup, + }, + { + /* + * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10" + * Lenovo Yoga Tablet 2 use the same mainboard) + */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."), + DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"), + DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"), + /* Partial match on beginning of BIOS version */ + DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"), + }, + .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup, + }, + { + /* Lenovo Yoga Tab 3 Pro YT3-X90F */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), + DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"), + DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"), + }, + .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup, + }, + { } +}; + void vlv_dsi_init(struct drm_i915_private *dev_priv) { struct intel_dsi *intel_dsi; @@ -1752,6 +1873,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) struct intel_connector *intel_connector; struct drm_connector *connector; struct drm_display_mode *current_mode; + const struct dmi_system_id *dmi_id; enum port port; enum pipe pipe; @@ -1883,6 +2005,14 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) goto err_cleanup_connector; } + dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table); + if (dmi_id) { + vlv_dsi_dmi_quirk_func quirk_func = + (vlv_dsi_dmi_quirk_func)dmi_id->driver_data; + + quirk_func(intel_dsi); + } + intel_panel_init(intel_connector, NULL); intel_backlight_setup(intel_connector, INVALID_PIPE); diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h b/drivers/gpu/drm/i915/display/vlv_dsi.h index 0c2b279df9d4..cf9d7b82f288 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.h +++ b/drivers/gpu/drm/i915/display/vlv_dsi.h @@ -12,8 +12,21 @@ enum port; struct drm_i915_private; struct intel_dsi; +#ifdef I915 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port); enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt); void vlv_dsi_init(struct drm_i915_private *dev_priv); +#else +static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) +{ +} +static inline enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) +{ + return 0; +} +static inline void vlv_dsi_init(struct drm_i915_private *dev_priv) +{ +} +#endif #endif /* __VLV_DSI_H__ */ diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h index ab9291ad1e79..fbe5113dbeb9 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h @@ -32,7 +32,16 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, struct intel_crtc_state *config); void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); +#ifdef I915 void assert_dsi_pll_enabled(struct drm_i915_private *i915); void assert_dsi_pll_disabled(struct drm_i915_private *i915); +#else +static inline void assert_dsi_pll_enabled(struct drm_i915_private *i915) +{ +} +static inline void assert_dsi_pll_disabled(struct drm_i915_private *i915) +{ +} +#endif #endif /* __VLV_DSI_PLL_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 93062c35e072..bb6c3f68f7d2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -62,7 +62,13 @@ void intel_gt_common_init_early(struct intel_gt *gt) /* Preliminary initialization of Tile 0 */ int intel_root_gt_init_early(struct drm_i915_private *i915) { - struct intel_gt *gt = to_gt(i915); + struct intel_gt *gt; + + gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL); + if (!gt) + return -ENOMEM; + + i915->gt[0] = gt; gt->i915 = i915; gt->uncore = &i915->uncore; @@ -911,8 +917,6 @@ int intel_gt_probe_all(struct drm_i915_private *i915) if (ret) return ret; - i915->gt[0] = gt; - if (!HAS_EXTRA_GT_LIST(i915)) return 0; diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 07269ff3be13..353f93baaca0 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -487,7 +487,7 @@ static bool has_mocs(const struct drm_i915_private *i915) return !IS_DGFX(i915); } -static unsigned int get_mocs_settings(const struct drm_i915_private *i915, +static unsigned int get_mocs_settings(struct drm_i915_private *i915, struct drm_i915_mocs_table *table) { unsigned int flags; @@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, memset(table, 0, sizeof(struct drm_i915_mocs_table)); table->unused_entries_index = I915_MOCS_PTE; - if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) { + if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) { table->size = ARRAY_SIZE(mtl_mocs_table); table->table = mtl_mocs_table; table->n_entries = MTL_NUM_MOCS_ENTRIES; diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 53a0a42a50db..c57aba09091f 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -39,7 +39,7 @@ #include <asm/kvm_page_track.h> -#include "i915_drv.h" +#include "gt/intel_gt.h" #include "intel_gvt.h" #include "debug.h" @@ -60,6 +60,8 @@ #define GVT_MAX_VGPU 8 +struct engine_mmio; + /* Describe per-platform limitations. */ struct intel_gvt_device_info { u32 max_support_vgpus; @@ -368,11 +370,6 @@ struct intel_gvt { struct dentry *debugfs_root; }; -static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) -{ - return i915->gvt; -} - enum { /* Scheduling trigger by timer */ INTEL_GVT_REQUEST_SCHED = 0, diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c index 68eca023bbc6..de3f5903d1a7 100644 --- a/drivers/gpu/drm/i915/gvt/interrupt.c +++ b/drivers/gpu/drm/i915/gvt/interrupt.c @@ -36,6 +36,23 @@ #include "gvt.h" #include "trace.h" +struct intel_gvt_irq_info { + char *name; + i915_reg_t reg_base; + enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; + unsigned long warned; + int group; + DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); + bool has_upstream_irq; +}; + +struct intel_gvt_irq_map { + int up_irq_group; + int up_irq_bit; + int down_irq_group; + u32 down_irq_bitmask; +}; + /* common offset among interrupt control registers */ #define regbase_to_isr(base) (base) #define regbase_to_imr(base) (base + 0x4) diff --git a/drivers/gpu/drm/i915/gvt/interrupt.h b/drivers/gpu/drm/i915/gvt/interrupt.h index b62f04ab47cb..e60ad476fe60 100644 --- a/drivers/gpu/drm/i915/gvt/interrupt.h +++ b/drivers/gpu/drm/i915/gvt/interrupt.h @@ -32,10 +32,13 @@ #ifndef _GVT_INTERRUPT_H_ #define _GVT_INTERRUPT_H_ -#include <linux/hrtimer.h> -#include <linux/kernel.h> +#include <linux/bitops.h> -#include "i915_reg_defs.h" +struct intel_gvt; +struct intel_gvt_irq; +struct intel_gvt_irq_info; +struct intel_gvt_irq_map; +struct intel_vgpu; enum intel_gvt_event_type { RCS_MI_USER_INTERRUPT = 0, @@ -138,10 +141,6 @@ enum intel_gvt_event_type { INTEL_GVT_EVENT_MAX, }; -struct intel_gvt_irq; -struct intel_gvt; -struct intel_vgpu; - typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq, enum intel_gvt_event_type event, struct intel_vgpu *vgpu); @@ -175,17 +174,6 @@ enum intel_gvt_irq_type { #define INTEL_GVT_IRQ_BITWIDTH 32 -/* device specific interrupt bit definitions */ -struct intel_gvt_irq_info { - char *name; - i915_reg_t reg_base; - enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; - unsigned long warned; - int group; - DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); - bool has_upstream_irq; -}; - /* per-event information */ struct intel_gvt_event_info { int bit; /* map to register bit */ @@ -194,13 +182,6 @@ struct intel_gvt_event_info { gvt_event_virt_handler_t v_handler; /* for v_event */ }; -struct intel_gvt_irq_map { - int up_irq_group; - int up_irq_bit; - int down_irq_group; - u32 down_irq_bitmask; -}; - /* structure containing device specific IRQ state */ struct intel_gvt_irq { const struct intel_gvt_irq_ops *ops; diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 490e8ae51228..273db14fd5fc 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -45,6 +45,14 @@ #define GEN9_MOCS_SIZE 64 +struct engine_mmio { + enum intel_engine_id id; + i915_reg_t reg; + u32 mask; + bool in_context; + u32 value; +}; + /* Raw offset is appened to each line for convenience. */ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */ diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.h b/drivers/gpu/drm/i915/gvt/mmio_context.h index 9540813b88e5..a821edf574dd 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.h +++ b/drivers/gpu/drm/i915/gvt/mmio_context.h @@ -39,8 +39,6 @@ #include <linux/types.h> #include "gt/intel_engine_regs.h" -#include "gt/intel_engine_types.h" -#include "gt/intel_lrc_reg.h" struct i915_request; struct intel_context; @@ -48,14 +46,6 @@ struct intel_engine_cs; struct intel_gvt; struct intel_vgpu; -struct engine_mmio { - enum intel_engine_id id; - i915_reg_t reg; - u32 mask; - bool in_context; - u32 value; -}; - void intel_gvt_switch_mmio(struct intel_vgpu *pre, struct intel_vgpu *next, const struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index d50347e5773a..f30a0861541c 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -338,6 +338,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) /* Try to make sure MCHBAR is enabled before poking at it */ intel_gmch_bar_setup(dev_priv); intel_device_info_runtime_init(dev_priv); + intel_display_device_info_runtime_init(dev_priv); for_each_gt(gt, dev_priv, i) { ret = intel_gt_init_mmio(gt); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 511eba3bbdba..20bbad165d76 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -317,12 +317,6 @@ struct drm_i915_private { struct i915_hwmon *hwmon; - /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ - struct intel_gt gt0; - - /* - * i915->gt[0] == &i915->gt0 - */ struct intel_gt *gt[I915_MAX_GT]; struct kobject *sysfs_gt; @@ -382,9 +376,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) return pci_get_drvdata(pdev); } -static inline struct intel_gt *to_gt(struct drm_i915_private *i915) +static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) { - return &i915->gt0; + return i915->gt[0]; } /* Simple iterator over all initialised engines */ @@ -416,8 +410,6 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define INTEL_INFO(i915) ((i915)->__info) #define RUNTIME_INFO(i915) (&(i915)->__runtime) -#define DISPLAY_INFO(i915) ((i915)->display.info.__device_info) -#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info) #define DRIVER_CAPS(i915) (&(i915)->caps) #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) @@ -436,12 +428,6 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define IS_MEDIA_VER(i915, from, until) \ (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) -#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) -#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \ - DISPLAY_RUNTIME_INFO(i915)->ip.rel) -#define IS_DISPLAY_VER(i915, from, until) \ - (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) - #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) @@ -790,12 +776,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \ 2 : HAS_L3_DPF(i915)) -/* Only valid when HAS_DISPLAY() is true */ -#define INTEL_DISPLAY_ENABLED(i915) \ - (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \ - !(i915)->params.disable_display && \ - !intel_opregion_headless_sku(i915)) - #define HAS_GUC_DEPRIVILEGE(i915) \ (INTEL_INFO(i915)->has_guc_deprivilege) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 0a171b57fd8f..036c4c3ed6ed 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -137,11 +137,6 @@ i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)"); i915_param_named_unsafe(enable_dpt, bool, 0400, "Enable display page table (DPT) (default: true)"); -i915_param_named(fastboot, int, 0400, - "Try to skip unnecessary mode sets at boot time " - "(0=disabled, 1=enabled) " - "Default: -1 (use per-chip default)"); - i915_param_named_unsafe(load_detect_test, bool, 0400, "Force-enable the VGA load detect code for testing (default:false). " "For developers only."); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 68abf0ad6c00..d5194b039aab 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -72,7 +72,6 @@ struct drm_printer; param(int, edp_vswing, 0, 0400) \ param(unsigned int, reset, 3, 0600) \ param(unsigned int, inject_probe_failure, 0, 0) \ - param(int, fastboot, -1, 0600) \ param(int, enable_dpcd_backlight, -1, 0600) \ param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \ param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \ diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index d35973b41186..108b675088ba 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -696,12 +696,11 @@ static void i915_pmu_event_read(struct perf_event *event) event->hw.state = PERF_HES_STOPPED; return; } -again: - prev = local64_read(&hwc->prev_count); - new = __i915_pmu_event_read(event); - if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev) - goto again; + prev = local64_read(&hwc->prev_count); + do { + new = __i915_pmu_event_read(event); + } while (!local64_try_cmpxchg(&hwc->prev_count, &prev, new)); local64_add(new - prev, &event->count); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e0ea2dc13556..135e8d8dbdf0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1327,6 +1327,8 @@ #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ +#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */ +#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ @@ -4678,6 +4680,13 @@ #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) +#define XE2LPD_DE_CAP _MMIO(0x41100) +#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) +#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) +#define XE2LPD_DE_CAP_DSC_REMOVED 1 +#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) +#define XE2LPD_DE_CAP_SCALER_SINGLE 1 + #define SKL_DSSM _MMIO(0x51004) #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index d2ed0f057cb2..59bea1398c91 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -27,7 +27,6 @@ #include <drm/drm_print.h> #include <drm/i915_pciids.h> -#include "display/intel_display_device.h" #include "gt/intel_gt_regs.h" #include "i915_drv.h" #include "i915_reg.h" @@ -232,19 +231,15 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915) if (find_devid(devid, subplatform_ult_ids, ARRAY_SIZE(subplatform_ult_ids))) { mask = BIT(INTEL_SUBPLATFORM_ULT); - if (IS_HASWELL(i915) || IS_BROADWELL(i915)) - DISPLAY_RUNTIME_INFO(i915)->port_mask &= ~BIT(PORT_D); } else if (find_devid(devid, subplatform_ulx_ids, ARRAY_SIZE(subplatform_ulx_ids))) { mask = BIT(INTEL_SUBPLATFORM_ULX); if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { /* ULX machines are also considered ULT. */ mask |= BIT(INTEL_SUBPLATFORM_ULT); - DISPLAY_RUNTIME_INFO(i915)->port_mask &= ~BIT(PORT_D); } } else if (find_devid(devid, subplatform_portf_ids, ARRAY_SIZE(subplatform_portf_ids))) { - DISPLAY_RUNTIME_INFO(i915)->port_mask |= BIT(PORT_F); mask = BIT(INTEL_SUBPLATFORM_PORTF); } else if (find_devid(devid, subplatform_uy_ids, ARRAY_SIZE(subplatform_uy_ids))) { @@ -350,8 +345,6 @@ void intel_device_info_runtime_init_early(struct drm_i915_private *i915) intel_device_info_subplatform_init(i915); } -static const struct intel_display_device_info no_display = {}; - /** * intel_device_info_runtime_init - initialize runtime info * @dev_priv: the i915 device @@ -372,21 +365,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) { struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); - if (HAS_DISPLAY(dev_priv)) - intel_display_device_info_runtime_init(dev_priv); - - /* Display may have been disabled by runtime init */ - if (!HAS_DISPLAY(dev_priv)) { - dev_priv->drm.driver_features &= ~(DRIVER_MODESET | - DRIVER_ATOMIC); - dev_priv->display.info.__device_info = &no_display; - } - - /* Disable nuclear pageflip by default on pre-g4x */ - if (!dev_priv->params.nuclear_pageflip && - DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) - dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; - BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index b3c036a54529..87ecc5104fd9 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -15,8 +15,9 @@ #include "display/intel_psr_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" +#include "gt/intel_engine_regs.h" #include "gt/intel_gt_regs.h" -#include "gvt/gvt.h" +#include "gvt/reg.h" #include "i915_drv.h" #include "i915_pvinfo.h" diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index ee4e5a2c0220..b4162f1be765 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -353,3 +353,8 @@ const char *intel_step_name(enum intel_step step) return "**"; } } + +const char *intel_display_step_name(struct drm_i915_private *i915) +{ + return intel_step_name(RUNTIME_INFO(i915)->step.display_step); +} diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h index 96dfca4cba73..b6f43b624774 100644 --- a/drivers/gpu/drm/i915/intel_step.h +++ b/drivers/gpu/drm/i915/intel_step.h @@ -78,5 +78,6 @@ enum intel_step { void intel_step_init(struct drm_i915_private *i915); const char *intel_step_name(enum intel_step step); +const char *intel_display_step_name(struct drm_i915_private *i915); #endif /* __INTEL_STEP_H__ */ diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 7de6477803f8..af349fd9abc2 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -114,7 +114,6 @@ static struct dev_pm_domain pm_domain = { static void mock_gt_probe(struct drm_i915_private *i915) { - i915->gt[0] = to_gt(i915); i915->gt[0]->name = "Mock GT"; } diff --git a/drivers/gpu/drm/i915/soc/intel_gmch.c b/drivers/gpu/drm/i915/soc/intel_gmch.c index 49c7fb16e934..f32e9f78770a 100644 --- a/drivers/gpu/drm/i915/soc/intel_gmch.c +++ b/drivers/gpu/drm/i915/soc/intel_gmch.c @@ -5,6 +5,7 @@ #include <linux/pci.h> #include <linux/pnp.h> +#include <linux/vgaarb.h> #include <drm/drm_managed.h> #include <drm/i915_drm.h> @@ -167,3 +168,16 @@ int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode) return 0; } + +unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode) +{ + struct drm_i915_private *i915 = pdev_to_i915(pdev); + + intel_gmch_vga_set_state(i915, enable_decode); + + if (enable_decode) + return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | + VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; + else + return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; +} diff --git a/drivers/gpu/drm/i915/soc/intel_gmch.h b/drivers/gpu/drm/i915/soc/intel_gmch.h index d0133eedc720..23be2d113afd 100644 --- a/drivers/gpu/drm/i915/soc/intel_gmch.h +++ b/drivers/gpu/drm/i915/soc/intel_gmch.h @@ -8,11 +8,13 @@ #include <linux/types.h> +struct pci_dev; struct drm_i915_private; int intel_gmch_bridge_setup(struct drm_i915_private *i915); void intel_gmch_bar_setup(struct drm_i915_private *i915); void intel_gmch_bar_teardown(struct drm_i915_private *i915); int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode); +unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode); #endif /* __INTEL_GMCH_H__ */ diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 7000e5910a1d..218edb0a96f8 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -38,13 +38,13 @@ extern "C" { */ /** - * DOC: uevents generated by i915 on it's device node + * DOC: uevents generated by i915 on its device node * * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch - * event from the gpu l3 cache. Additional information supplied is ROW, + * event from the GPU L3 cache. Additional information supplied is ROW, * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep - * track of these events and if a specific cache-line seems to have a - * persistent error remap it with the l3 remapping tool supplied in + * track of these events, and if a specific cache-line seems to have a + * persistent error, remap it with the L3 remapping tool supplied in * intel-gpu-tools. The value supplied with the event is always 1. * * I915_ERROR_UEVENT - Generated upon error detection, currently only via |