diff options
| -rw-r--r-- | drivers/clk/ti/clk-7xx.c | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/dra7.h | 10 |
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 43b2bb690c71..a89b465f299b 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -164,6 +164,11 @@ static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = { 0 }, }; +static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = { + { DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" }, + { 0 }, +}; + static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, @@ -787,6 +792,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { { 0x4a005550, dra7_ipu_clkctrl_regs }, { 0x4a005620, dra7_dsp2_clkctrl_regs }, { 0x4a005720, dra7_rtc_clkctrl_regs }, + { 0x4a005760, dra7_vpe_clkctrl_regs }, { 0x4a008620, dra7_coreaon_clkctrl_regs }, { 0x4a008720, dra7_l3main1_clkctrl_regs }, { 0x4a008920, dra7_ipu2_clkctrl_regs }, diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h index d5d112bc632d..ff33f621b225 100644 --- a/include/dt-bindings/clock/dra7.h +++ b/include/dt-bindings/clock/dra7.h @@ -34,6 +34,11 @@ #define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +/* vpe clocks */ +#define DRA7_VPE_CLKCTRL_OFFSET 0x60 +#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) +#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) + /* coreaon clocks */ #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) @@ -202,6 +207,11 @@ #define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +/* vpe clocks */ +#define DRA7_VPE_CLKCTRL_OFFSET 0x60 +#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) +#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) + /* coreaon clocks */ #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) |