diff options
| -rw-r--r-- | Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 31cc0631ef7c..f4ad30ef1628 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -56,6 +56,12 @@ Required properties: On (H)SCI(F) and some SCIFA, an additional clock may be specified: - "hsck" for the optional external clock input (on HSCIF), - "sck" for the optional external clock input (on other variants). + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) + (some SCIF and HSCIF), additional clocks may be specified: + - "brg_int" for the optional internal clock source for the frequency + divider (typically the (AXI or SHwy) bus clock), + - "scif_clk" for the optional external clock source for the frequency + divider (SCIF_CLK). Note: Each enabled SCIx UART should have an alias correctly numbered in the "aliases" node. |