diff options
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 29 | ||||
| -rw-r--r-- | arch/powerpc/mm/8xx_mmu.c | 56 | ||||
| -rw-r--r-- | arch/powerpc/mm/mmu_decl.h | 3 |
3 files changed, 86 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 378a1858687d..44f4edbd5dee 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -384,6 +384,27 @@ InstructionTLBMiss: EXCEPTION_EPILOG_0 rfi +/* + * Bottom part of DataStoreTLBMiss handler for IMMR area + * not enough space in the DataStoreTLBMiss area + */ +DTLBMissIMMR: + mtcr r3 + /* Set 512k byte guarded page and mark it valid */ + li r10, MD_PS512K | MD_GUARDED | MD_SVALID + MTSPR_CPU6(SPRN_MD_TWC, r10, r3) + mfspr r10, SPRN_IMMR /* Get current IMMR */ + rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */ + ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \ + _PAGE_PRESENT | _PAGE_NO_CACHE + MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ + + li r11, RPN_PATTERN + mfspr r3, SPRN_SPRG_SCRATCH2 + mtspr SPRN_DAR, r11 /* Tag DAR */ + EXCEPTION_EPILOG_0 + rfi + . = 0x1200 DataStoreTLBMiss: mtspr SPRN_SPRG_SCRATCH2, r3 @@ -397,6 +418,14 @@ DataStoreTLBMiss: IS_KERNEL(r11, r10) mfspr r11, SPRN_M_TW /* Get level 1 table */ BRANCH_UNLESS_KERNEL(3f) + + rlwinm r11, r10, 16, 0xfff8 +#ifndef CONFIG_PIN_TLB + cmpli cr0, r11, VIRT_IMMR_BASE@h +_ENTRY(DTLBMiss_jmp) + beq- DTLBMissIMMR +#endif + lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3: diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c index 949100577db5..220772579113 100644 --- a/arch/powerpc/mm/8xx_mmu.c +++ b/arch/powerpc/mm/8xx_mmu.c @@ -13,10 +13,43 @@ */ #include <linux/memblock.h> +#include <asm/fixmap.h> +#include <asm/code-patching.h> #include "mmu_decl.h" +#define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT) + extern int __map_without_ltlbs; + +/* + * Return PA for this VA if it is in IMMR area, or 0 + */ +phys_addr_t v_block_mapped(unsigned long va) +{ + unsigned long p = PHYS_IMMR_BASE; + + if (__map_without_ltlbs) + return 0; + if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE) + return p + va - VIRT_IMMR_BASE; + return 0; +} + +/* + * Return VA for a given PA or 0 if not mapped + */ +unsigned long p_block_mapped(phys_addr_t pa) +{ + unsigned long p = PHYS_IMMR_BASE; + + if (__map_without_ltlbs) + return 0; + if (pa >= p && pa < p + IMMR_SIZE) + return VIRT_IMMR_BASE + pa - p; + return 0; +} + /* * MMU_init_hw does the chip-specific initialization of the MMU hardware. */ @@ -29,6 +62,22 @@ void __init MMU_init_hw(void) #define LARGE_PAGE_SIZE_8M (1<<23) #define LARGE_PAGE_SIZE_64M (1<<26) +static void mmu_mapin_immr(void) +{ + unsigned long p = PHYS_IMMR_BASE; + unsigned long v = VIRT_IMMR_BASE; + unsigned long f = pgprot_val(PAGE_KERNEL_NCG); + int offset; + + for (offset = 0; offset < IMMR_SIZE; offset += PAGE_SIZE) + map_page(v + offset, p + offset, f); +} + +/* Address of instructions to patch */ +#ifndef CONFIG_PIN_TLB +extern unsigned int DTLBMiss_jmp; +#endif + unsigned long __init mmu_mapin_ram(unsigned long top) { unsigned long v, s, mapped; @@ -38,8 +87,13 @@ unsigned long __init mmu_mapin_ram(unsigned long top) p = 0; s = top; - if (__map_without_ltlbs) + if (__map_without_ltlbs) { + mmu_mapin_immr(); +#ifndef CONFIG_PIN_TLB + patch_instruction(&DTLBMiss_jmp, PPC_INST_NOP); +#endif return 0; + } #ifdef CONFIG_PPC_4K_PAGES while (s >= LARGE_PAGE_SIZE_8M) { diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h index 6af65327c993..f988db655e5b 100644 --- a/arch/powerpc/mm/mmu_decl.h +++ b/arch/powerpc/mm/mmu_decl.h @@ -154,9 +154,10 @@ struct tlbcam { }; #endif -#if defined(CONFIG_6xx) || defined(CONFIG_FSL_BOOKE) +#if defined(CONFIG_6xx) || defined(CONFIG_FSL_BOOKE) || defined(CONFIG_PPC_8xx) /* 6xx have BATS */ /* FSL_BOOKE have TLBCAM */ +/* 8xx have LTLB */ phys_addr_t v_block_mapped(unsigned long va); unsigned long p_block_mapped(phys_addr_t pa); #else |