diff options
| -rw-r--r-- | arch/arm64/boot/dts/marvell/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts | 44 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi | 34 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi | 96 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi | 108 |
5 files changed, 283 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 79ac09b58a89..99b8cb3c49e1 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts new file mode 100644 index 000000000000..2a0b07000089 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * Utilizing the CN913x COM Express CPU module board. + * This specific carrier board in this mode of operation (external) + * only maintains a PCIe link with the CPU module, + * which does not require any special DTS definitions. + * + * AC5X RD works here in external mode (switch selectable at the back of the + * board), and connect via an external cable a kit + * which would allow it to use an external CN9131 CPU COM Express module, + * mounted on top of an interposer kit. + * + * So in this case, once the switch is set to external mode as explained above, + * the AC5X RD becomes part of the carrier solution. + * + * When the board boots in the external CPU mode, the internal CPU is disabled, + * and only the switch portion of the SOC acts as a PCIe end-point, Hence there + * is no need to describe this internal (disabled CPU) in the device tree. + * + * There is no CPU booting in this mode on the carrier, only on the + * CN9131 COM Express CPU module. + * What runs the Linux is the CN9131 on the COM Express CPU module, + * And it accesses the switch end-point on the AC5X RD portion of the carrier + * via PCIe. + */ + +#include "cn9131-db-comexpress.dtsi" +#include "ac5x-rd-carrier.dtsi" + +/ { + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module"; + compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier", + "marvell,cn9131-cpu-module", "marvell,cn9131", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x2 0x00000000>; + }; + +}; diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi new file mode 100644 index 000000000000..f98629abb58b --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * This specific board in external mode (see below) only maintains + * a PCIe link with the COM Express CPU module, which does not + * require any special DTS definitions. + * + * AC5X RD can either work as you would expect, as a complete standalone + * box using the internal CPU, or you can move the switch on the back of + * the box to "external" mode, and connect via an external cable a kit + * which would allow it to use an external CPU COM Express module, + * mounted on top of an interposer kit. + * + * So in this case, once the switch is set to external mode as explained above, + * the AC5X RD becomes part of the carrier solution. + * This is a development/reference solution, not a full commercial solution, + * hence it was designed with the flexibility to be configured in different + * modes of operation. + * + * When the board boots in the external CPU mode, the internal CPU is disabled, + * and only the switch portion of the SOC acts as a PCIe end-point, Hence there + * is no need to describe this internal (disabled CPU) in the device tree. + * + * There is no CPU booting in this mode on the carrier, + * only on the COM Express CPU module. + */ + +/ { + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board"; + compatible = "marvell,rd-ac5x-carrier"; + +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi new file mode 100644 index 000000000000..028496ebc473 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the CN9130-DB Com Express CPU module board. + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board"; + compatible = "marvell,cn9130-cpu-module", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + +}; + +&ap0_reg_sd_vccq { + regulator-max-microvolt = <1800000>; + states = <1800000 0x1 1800000 0x0>; + /delete-property/ gpios; +}; + +&cp0_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_usb3_vbus1 { + /delete-property/ gpio; +}; + +&cp0_reg_sd_vcc { + status = "disabled"; +}; + +&cp0_reg_sd_vccq { + status = "disabled"; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_eth0 { + status = "disabled"; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_eth2 { + status = "disabled"; +}; + +&cp0_mdio { + status = "okay"; + pinctrl-0 = <&cp0_ge_mdio_pins>; + phy0: ethernet-phy@0 { + status = "okay"; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "ge"; + }; + }; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_spi1 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy0>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp0_usb3_1 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy1>; + phy-names = "usb"; + /delete-property/ phys; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi new file mode 100644 index 000000000000..6f3914bcfd01 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the CN9131-DB Com Express CPU module board. + */ + +#include "cn9131-db.dtsi" + +/ { + model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board"; + compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + +}; + +&ap0_reg_sd_vccq { + regulator-max-microvolt = <1800000>; + states = <1800000 0x1 1800000 0x0>; + /delete-property/ gpios; +}; + +&cp0_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_usb3_vbus1 { + /delete-property/ gpio; +}; + +&cp1_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_sd_vcc { + status = "disabled"; +}; + +&cp0_reg_sd_vccq { + status = "disabled"; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_eth0 { + status = "disabled"; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_eth2 { + status = "disabled"; +}; + +&cp0_mdio { + status = "okay"; + pinctrl-0 = <&cp0_ge_mdio_pins>; + phy0: ethernet-phy@0 { + status = "okay"; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible = "marvell,cp115-standalone-pinctrl"; + + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "ge"; + }; + }; +}; + +&cp0_sdhci0 { + status = "disabled"; +}; + +&cp0_spi1 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy0>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp0_usb3_1 { + status = "okay"; + usb-phy = <&cp0_usb3_0_phy1>; + phy-names = "usb"; + /delete-property/ phys; +}; + +&cp1_usb3_1 { + status = "okay"; + usb-phy = <&cp1_usb3_0_phy0>; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy3 1>; + phy-names = "usb"; +}; |