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-rw-r--r--Documentation/devicetree/bindings/riscv/thead.yaml4
-rw-r--r--arch/riscv/boot/dts/starfive/jh7110.dtsi38
-rw-r--r--arch/riscv/boot/dts/thead/Makefile2
-rw-r--r--arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts61
-rw-r--r--arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi2
-rw-r--r--arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts2
-rw-r--r--arch/riscv/boot/dts/thead/th1520.dtsi2
7 files changed, 88 insertions, 23 deletions
diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml
index e62f6821372e..301912dcd290 100644
--- a/Documentation/devicetree/bindings/riscv/thead.yaml
+++ b/Documentation/devicetree/bindings/riscv/thead.yaml
@@ -17,6 +17,10 @@ properties:
const: '/'
compatible:
oneOf:
+ - description: BeagleV Ahead single board computer
+ items:
+ - const: beagle,beaglev-ahead
+ - const: thead,th1520
- description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
items:
- enum:
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 9aa563898868..e85464c328d0 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -676,25 +676,6 @@
status = "disabled";
};
- qspi: spi@13010000 {
- compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
- reg = <0x0 0x13010000 0x0 0x10000>,
- <0x0 0x21000000 0x0 0x400000>;
- interrupts = <25>;
- clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
- <&syscrg JH7110_SYSCLK_QSPI_AHB>,
- <&syscrg JH7110_SYSCLK_QSPI_APB>;
- clock-names = "ref", "ahb", "apb";
- resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
- <&syscrg JH7110_SYSRST_QSPI_AHB>,
- <&syscrg JH7110_SYSRST_QSPI_REF>;
- reset-names = "qspi", "qspi-ocp", "rstc_ref";
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- status = "disabled";
- };
-
spi3: spi@12070000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x12070000 0x0 0x10000>;
@@ -767,6 +748,25 @@
#thermal-sensor-cells = <0>;
};
+ qspi: spi@13010000 {
+ compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x13010000 0x0 0x10000>,
+ <0x0 0x21000000 0x0 0x400000>;
+ interrupts = <25>;
+ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+ <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+ <&syscrg JH7110_SYSCLK_QSPI_APB>;
+ clock-names = "ref", "ahb", "apb";
+ resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+ <&syscrg JH7110_SYSRST_QSPI_AHB>,
+ <&syscrg JH7110_SYSRST_QSPI_REF>;
+ reset-names = "qspi", "qspi-ocp", "rstc_ref";
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ status = "disabled";
+ };
+
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile
index e311fc9a5939..b55a17127c2b 100644
--- a/arch/riscv/boot/dts/thead/Makefile
+++ b/arch/riscv/boot/dts/thead/Makefile
@@ -1,2 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
new file mode 100644
index 000000000000..70e8042c8304
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Drew Fustini <dfustini@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "th1520.dtsi"
+
+/ {
+ model = "BeagleV Ahead";
+ compatible = "beagle,beaglev-ahead", "thead,th1520";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x1 0x00000000>;
+
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&osc_32k {
+ clock-frequency = <32768>;
+};
+
+&apb_clk {
+ clock-frequency = <62500000>;
+};
+
+&uart_sclk {
+ clock-frequency = <100000000>;
+};
+
+&dmac0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 4b0249ac710f..a802ab110429 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
index a1248b2ee3a3..9a3884a73e13 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 56a73134b49e..ce708183b6f6 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 Alibaba Group Holding Limited.
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>