diff options
27 files changed, 2 insertions, 4960 deletions
diff --git a/Documentation/devicetree/bindings/arm/sirf.yaml b/Documentation/devicetree/bindings/arm/sirf.yaml deleted file mode 100644 index b25eb35d1b66..000000000000 --- a/Documentation/devicetree/bindings/arm/sirf.yaml +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/sirf.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: CSR SiRFprimaII and SiRFmarco device tree bindings. - -maintainers: - - Binghua Duan <binghua.duan@csr.com> - - Barry Song <Baohua.Song@csr.com> - -properties: - $nodename: - const: '/' - compatible: - oneOf: - - items: - - const: sirf,atlas6-cb - - const: sirf,atlas6 - - items: - - const: sirf,atlas7-cb - - const: sirf,atlas7 - - items: - - const: sirf,prima2-cb - - const: sirf,prima2 - -additionalProperties: true - -... diff --git a/Documentation/devicetree/bindings/reset/sirf,rstc.txt b/Documentation/devicetree/bindings/reset/sirf,rstc.txt deleted file mode 100644 index 0505de742d30..000000000000 --- a/Documentation/devicetree/bindings/reset/sirf,rstc.txt +++ /dev/null @@ -1,42 +0,0 @@ -CSR SiRFSoC Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -example: - -rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -The reset controller(rstc) manages various reset sources. This module provides -reset signals for most blocks in system. Those device nodes should specify the -reset line on the rstc in their resets property, containing a phandle to the -rstc device node and a RESET_INDEX specifying which module to reset, as described -in reset.txt. - -For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers. -For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose -rest_bit is in SW_RST1, its RESET_INDEX is 32~63. - -example: - -vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; -}; diff --git a/MAINTAINERS b/MAINTAINERS index 7c3eadb185f9..aeef69cbc7ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1779,19 +1779,6 @@ F: drivers/net/ethernet/cortina/ F: drivers/pinctrl/pinctrl-gemini.c F: drivers/rtc/rtc-ftrtc010.c -ARM/CSR SIRFPRIMA2 MACHINE SUPPORT -M: Barry Song <baohua@kernel.org> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -T: git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git -F: arch/arm/boot/dts/prima2* -F: arch/arm/mach-prima2/ -F: drivers/clk/sirf/ -F: drivers/clocksource/timer-atlas7.c -F: drivers/clocksource/timer-prima2.c -X: drivers/gnss -N: [^a-z]sirf - ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun <marek.behun@nic.cz> S: Maintained diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 96f153c5639b..9d9a7060d365 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -671,8 +671,6 @@ source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/mach-oxnas/Kconfig" -source "arch/arm/mach-prima2/Kconfig" - source "arch/arm/mach-pxa/Kconfig" source "arch/arm/plat-pxa/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 23264f7bff72..fe8b95069d31 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1142,32 +1142,6 @@ choice Say Y here if you want kernel low-level debugging support on Allwinner A31/A23 based platforms on the R_UART. - config DEBUG_SIRFPRIMA2_UART1 - bool "Kernel low-level debugging messages via SiRFprimaII UART1" - depends on ARCH_PRIMA2 - select DEBUG_SIRFSOC_UART - help - Say Y here if you want the debug print routines to direct - their output to the uart1 port on SiRFprimaII devices. - - config DEBUG_SIRFATLAS7_UART0 - bool "Kernel low-level debugging messages via SiRFatlas7 UART0" - depends on ARCH_ATLAS7 - select DEBUG_SIRFSOC_UART - help - Say Y here if you want the debug print routines to direct - their output to the uart0 port on SiRFATLAS7 devices.The uart0 - is used on SiRFATLAS7 as a extra debug port.sometimes an extra - debug port can be very useful. - - config DEBUG_SIRFATLAS7_UART1 - bool "Kernel low-level debugging messages via SiRFatlas7 UART1" - depends on ARCH_ATLAS7 - select DEBUG_SIRFSOC_UART - help - Say Y here if you want the debug print routines to direct - their output to the uart1 port on SiRFATLAS7 devices. - config DEBUG_SPEAR3XX bool "Kernel low-level debugging messages via ST SPEAr 3xx/6xx UART" depends on ARCH_SPEAR3XX || ARCH_SPEAR6XX @@ -1538,10 +1512,6 @@ config DEBUG_STM32_UART bool depends on ARCH_STM32 -config DEBUG_SIRFSOC_UART - bool - depends on ARCH_SIRF - config DEBUG_UART_FLOW_CONTROL bool "Enable flow control (CTS) for the debug UART" depends on DEBUG_LL @@ -1596,7 +1566,6 @@ config DEBUG_LL_INCLUDE default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4 default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART default "debug/s5pv210.S" if DEBUG_S5PV210_UART - default "debug/sirf.S" if DEBUG_SIRFSOC_UART default "debug/sti.S" if DEBUG_STI_UART default "debug/stm32.S" if DEBUG_STM32_UART default "debug/tegra.S" if DEBUG_TEGRA_UART @@ -1648,8 +1617,6 @@ config DEBUG_UART_PHYS default 0x1600d000 if DEBUG_SD5203_UART default 0x18000300 if DEBUG_BCM_5301X default 0x18000400 if DEBUG_BCM_HR2 - default 0x18010000 if DEBUG_SIRFATLAS7_UART0 - default 0x18020000 if DEBUG_SIRFATLAS7_UART1 default 0x18023000 if DEBUG_BCM_IPROC_UART3 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 default 0x20001000 if DEBUG_HIP01_UART @@ -1695,7 +1662,6 @@ config DEBUG_UART_PHYS default 0x80074000 if DEBUG_IMX28_UART default 0x808c0000 if DEBUG_EP93XX || ARCH_EP93XX default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART - default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1 default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX default 0xc0013000 if DEBUG_U300_UART default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN @@ -1754,7 +1720,7 @@ config DEBUG_UART_PHYS DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \ DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ - DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \ + DEBUG_DIGICOLOR_UA0 || \ DEBUG_AT91_UART || DEBUG_STM32_UART config DEBUG_UART_VIRT @@ -1836,10 +1802,7 @@ config DEBUG_UART_VIRT default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE - default 0xfec10000 if DEBUG_SIRFATLAS7_UART0 default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 - default 0xfec20000 if DEBUG_SIRFATLAS7_UART1 - default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1 default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART @@ -1863,7 +1826,7 @@ config DEBUG_UART_VIRT DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ - DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \ + DEBUG_DIGICOLOR_UA0 || \ DEBUG_AT91_UART || DEBUG_STM32_UART config DEBUG_UART_8250_SHIFT diff --git a/arch/arm/Makefile b/arch/arm/Makefile index dd51416cdcd9..7c4b50852a78 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -209,7 +209,6 @@ machine-$(CONFIG_PLAT_SAMSUNG) += s3c machine-$(CONFIG_ARCH_S5PV210) += s5pv210 machine-$(CONFIG_ARCH_SA1100) += sa1100 machine-$(CONFIG_ARCH_RENESAS) += shmobile -machine-$(CONFIG_ARCH_SIRF) += prima2 machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STI) += sti machine-$(CONFIG_ARCH_STM32) += stm32 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2c02cb4c71cb..da413b4d5c3f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -74,10 +74,6 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d4_xplained.dtb \ at91-sama5d4ek.dtb \ at91-vinco.dtb -dtb-$(CONFIG_ARCH_ATLAS6) += \ - atlas6-evb.dtb -dtb-$(CONFIG_ARCH_ATLAS7) += \ - atlas7-evb.dtb dtb-$(CONFIG_ARCH_AXXIA) += \ axm5516-amarillo.dtb dtb-$(CONFIG_ARCH_BCM2835) += \ @@ -886,8 +882,6 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \ owl-s500-labrador-base-m.dtb \ owl-s500-roseapplepi.dtb \ owl-s500-sparky.dtb -dtb-$(CONFIG_ARCH_PRIMA2) += \ - prima2-evb.dtb dtb-$(CONFIG_ARCH_PXA) += \ pxa300-raumfeld-connector.dtb \ pxa300-raumfeld-controller.dtb \ diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts deleted file mode 100644 index 89e430392f26..000000000000 --- a/arch/arm/boot/dts/atlas6-evb.dts +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFatlas6 Evaluation Board - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/dts-v1/; - -/include/ "atlas6.dtsi" - -/ { - model = "CSR SiRFatlas6 Evaluation Board"; - compatible = "sirf,atlas6-cb", "sirf,atlas6"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - axi { - peri-iobg { - uart@b0060000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - }; - spi@b00d0000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - spi@b0170000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - }; - i2c0: i2c@b00e0000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - lcd@40 { - compatible = "sirf,lcd"; - reg = <0x40>; - }; - }; - - }; - disp-iobg { - lcd@90010000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_24pins_a>; - }; - }; - }; - display: display@0 { - panels { - panel0: panel@0 { - panel-name = "Innolux TFT"; - hactive = <800>; - vactive = <480>; - left_margin = <20>; - right_margin = <234>; - upper_margin = <3>; - lower_margin = <41>; - hsync_len = <3>; - vsync_len = <2>; - pixclock = <33264000>; - sync = <3>; - timing = <0x88>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi deleted file mode 100644 index 8ac5d1524a43..000000000000 --- a/arch/arm/boot/dts/atlas6.dtsi +++ /dev/null @@ -1,800 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFatlas6 SoC - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/ { - compatible = "sirf,atlas6"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - clocks = <&clks 12>; - operating-points = < - /* kHz uV */ - 200000 1025000 - 400000 1025000 - 600000 1050000 - 800000 1100000 - >; - clock-latency = <150000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <29>; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clks: clock-controller@88000000 { - compatible = "sirf,atlas6-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - #clock-cells = <1>; - }; - - rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - - cphifbg@88030000 { - compatible = "sirf,prima2-cphifbg"; - reg = <0x88030000 0x1000>; - clocks = <&clks 42>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x2000>; - interrupts = <27>; - clocks = <&clks 5>; - }; - - memc-monitor { - compatible = "sirf,prima2-memcmon"; - reg = <0x90002000 0x200>; - interrupts = <4>; - clocks = <&clks 32>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - lcd@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - clocks = <&clks 34>; - display=<&display>; - /* later transfer to pwm */ - bl-gpio = <&gpio 7 0>; - default-panel = <&panel0>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx510"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - clocks = <&clks 32>; - }; - }; - - graphics2d-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - ble@a0000000 { - compatible = "sirf,atlas6-ble"; - reg = <0xa0000000 0x2000>; - interrupts = <5>; - clocks = <&clks 33>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - resets = <&rstc 1>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - clocks = <&clks 9>; - resets = <&rstc 2>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - clocks = <&clks 8>; - resets = <&rstc 0>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>, - <0x56000000 0x56000000 0x1b00000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - clocks = <&clks 11>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - clocks = <&clks 26>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - clocks = <&clks 27>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x1000>; - interrupts = <17>; - fifosize = <128>; - clocks = <&clks 13>; - dmas = <&dmac1 5>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x1000>; - interrupts = <18>; - fifosize = <32>; - clocks = <&clks 14>; - dma-names = "no-rx", "no-tx"; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x1000>; - interrupts = <19>; - fifosize = <128>; - clocks = <&clks 15>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - fifosize = <128>; - clocks = <&clks 28>; - dmas = <&dmac1 1>, <&dmac1 2>; - dma-names = "rx", "tx"; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - fifosize = <128>; - clocks = <&clks 29>; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "rx", "tx"; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - clocks = <&clks 24>; - #dma-cells = <1>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - clocks = <&clks 25>; - #dma-cells = <1>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - clocks = <&clks 31>; - interrupts = <14>; - sirf,vip-dma-rx-channel = <16>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 19>; - resets = <&rstc 26>; - status = "disabled"; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac0 12>, - <&dmac0 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 20>; - resets = <&rstc 27>; - status = "disabled"; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 17>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 18>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - clocks = <&clks 16>; - }; - - gpio: pinctrl@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas6-pinctrl"; - reg = <0xb0120000 0x10000>; - interrupts = <43 44 45 46 47>; - gpio-controller; - interrupt-controller; - - lcd_16pins_a: lcd0@0 { - lcd { - sirf,pins = "lcd_16bitsgrp"; - sirf,function = "lcd_16bits"; - }; - }; - lcd_18pins_a: lcd0@1 { - lcd { - sirf,pins = "lcd_18bitsgrp"; - sirf,function = "lcd_18bits"; - }; - }; - lcd_24pins_a: lcd0@2 { - lcd { - sirf,pins = "lcd_24bitsgrp"; - sirf,function = "lcd_24bits"; - }; - }; - lcdrom_pins_a: lcdrom0@0 { - lcd { - sirf,pins = "lcdromgrp"; - sirf,function = "lcdrom"; - }; - }; - uart0_pins_a: uart0@0 { - uart { - sirf,pins = "uart0grp"; - sirf,function = "uart0"; - }; - }; - uart0_noflow_pins_a: uart0@1 { - uart { - sirf,pins = "uart0_nostreamctrlgrp"; - sirf,function = "uart0_nostreamctrl"; - }; - }; - uart1_pins_a: uart1@0 { - uart { - sirf,pins = "uart1grp"; - sirf,function = "uart1"; - }; - }; - uart2_pins_a: uart2@0 { - uart { - sirf,pins = "uart2grp"; - sirf,function = "uart2"; - }; - }; - uart2_noflow_pins_a: uart2@1 { - uart { - sirf,pins = "uart2_nostreamctrlgrp"; - sirf,function = "uart2_nostreamctrl"; - }; - }; - spi0_pins_a: spi0@0 { - spi { - sirf,pins = "spi0grp"; - sirf,function = "spi0"; - }; - }; - spi1_pins_a: spi1@0 { - spi { - sirf,pins = "spi1grp"; - sirf,function = "spi1"; - }; - }; - i2c0_pins_a: i2c0@0 { - i2c { - sirf,pins = "i2c0grp"; - sirf,function = "i2c0"; - }; - }; - i2c1_pins_a: i2c1@0 { - i2c { - sirf,pins = "i2c1grp"; - sirf,function = "i2c1"; - }; - }; - pwm0_pins_a: pwm0@0 { - pwm { - sirf,pins = "pwm0grp"; - sirf,function = "pwm0"; - }; - }; - pwm1_pins_a: pwm1@0 { - pwm { - sirf,pins = "pwm1grp"; - sirf,function = "pwm1"; - }; - }; - pwm2_pins_a: pwm2@0 { - pwm { - sirf,pins = "pwm2grp"; - sirf,function = "pwm2"; - }; - }; - pwm3_pins_a: pwm3@0 { - pwm { - sirf,pins = "pwm3grp"; - sirf,function = "pwm3"; - }; - }; - pwm4_pins_a: pwm4@0 { - pwm { - sirf,pins = "pwm4grp"; - sirf,function = "pwm4"; - }; - }; - gps_pins_a: gps@0 { - gps { - sirf,pins = "gpsgrp"; - sirf,function = "gps"; - }; - }; - vip_pins_a: vip@0 { - vip { - sirf,pins = "vipgrp"; - sirf,function = "vip"; - }; - }; - sdmmc0_pins_a: sdmmc0@0 { - sdmmc0 { - sirf,pins = "sdmmc0grp"; - sirf,function = "sdmmc0"; - }; - }; - sdmmc1_pins_a: sdmmc1@0 { - sdmmc1 { - sirf,pins = "sdmmc1grp"; - sirf,function = "sdmmc1"; - }; - }; - sdmmc2_pins_a: sdmmc2@0 { - sdmmc2 { - sirf,pins = "sdmmc2grp"; - sirf,function = "sdmmc2"; - }; - }; - sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { - sdmmc2_nowp { - sirf,pins = "sdmmc2_nowpgrp"; - sirf,function = "sdmmc2_nowp"; - }; - }; - sdmmc3_pins_a: sdmmc3@0 { - sdmmc3 { - sirf,pins = "sdmmc3grp"; - sirf,function = "sdmmc3"; - }; - }; - sdmmc5_pins_a: sdmmc5@0 { - sdmmc5 { - sirf,pins = "sdmmc5grp"; - sirf,function = "sdmmc5"; - }; - }; - i2s_mclk_pins_a: i2s_mclk@0 { - i2s_mclk { - sirf,pins = "i2smclkgrp"; - sirf,function = "i2s_mclk"; - }; - }; - i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { - i2s_ext_clk_input { - sirf,pins = "i2s_ext_clk_inputgrp"; - sirf,function = "i2s_ext_clk_input"; - }; - }; - i2s_pins_a: i2s@0 { - i2s { - sirf,pins = "i2sgrp"; - sirf,function = "i2s"; - }; - }; - i2s_no_din_pins_a: i2s_no_din@0 { - i2s_no_din { - sirf,pins = "i2s_no_dingrp"; - sirf,function = "i2s_no_din"; - }; - }; - i2s_6chn_pins_a: i2s_6chn@0 { - i2s_6chn { - sirf,pins = "i2s_6chngrp"; - sirf,function = "i2s_6chn"; - }; - }; - ac97_pins_a: ac97@0 { - ac97 { - sirf,pins = "ac97grp"; - sirf,function = "ac97"; - }; - }; - nand_pins_a: nand@0 { - nand { - sirf,pins = "nandgrp"; - sirf,function = "nand"; - }; - }; - usp0_pins_a: usp0@0 { - usp0 { - sirf,pins = "usp0grp"; - sirf,function = "usp0"; - }; - }; - usp0_uart_nostreamctrl_pins_a: usp0@1 { - usp0 { - sirf,pins = "usp0_uart_nostreamctrl_grp"; - sirf,function = "usp0_uart_nostreamctrl"; - }; - }; - usp0_only_utfs_pins_a: usp0@2 { - usp0 { - sirf,pins = "usp0_only_utfs_grp"; - sirf,function = "usp0_only_utfs"; - }; - }; - usp0_only_urfs_pins_a: usp0@3 { - usp0 { - sirf,pins = "usp0_only_urfs_grp"; - sirf,function = "usp0_only_urfs"; - }; - }; - usp1_pins_a: usp1@0 { - usp1 { - sirf,pins = "usp1grp"; - sirf,function = "usp1"; - }; - }; - usp1_uart_nostreamctrl_pins_a: usp1@1 { - usp1 { - sirf,pins = "usp1_uart_nostreamctrl_grp"; - sirf,function = "usp1_uart_nostreamctrl"; - }; - }; - usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { - usb0_upli_drvbus { - sirf,pins = "usb0_upli_drvbusgrp"; - sirf,function = "usb0_upli_drvbus"; - }; - }; - usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { - usb1_utmi_drvbus { - sirf,pins = "usb1_utmi_drvbusgrp"; - sirf,function = "usb1_utmi_drvbus"; - }; - }; - usb1_dp_dn_pins_a: usb1_dp_dn@0 { - usb1_dp_dn { - sirf,pins = "usb1_dp_dngrp"; - sirf,function = "usb1_dp_dn"; - }; - }; - uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { - uart1_route_io_usb1 { - sirf,pins = "uart1_route_io_usb1grp"; - sirf,function = "uart1_route_io_usb1"; - }; - }; - warm_rst_pins_a: warm_rst@0 { - warm_rst { - sirf,pins = "warm_rstgrp"; - sirf,function = "warm_rst"; - }; - }; - pulse_count_pins_a: pulse_count@0 { - pulse_count { - sirf,pins = "pulse_countgrp"; - sirf,function = "pulse_count"; - }; - }; - cko0_pins_a: cko0@0 { - cko0 { - sirf,pins = "cko0grp"; - sirf,function = "cko0"; - }; - }; - cko1_pins_a: cko1@0 { - cko1 { - sirf,pins = "cko1grp"; - sirf,function = "cko1"; - }; - }; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - clocks = <&clks 21>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - clocks = <&clks 22>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - clocks = <&clks 23>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - bus-width = <8>; - clocks = <&clks 36>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 36>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 37>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 37>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 38>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - minigpsrtc@2000 { - compatible = "sirf,prima2-minigpsrtc"; - reg = <0x2000 0x1000>; - interrupts = <54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - clocks = <&clks 40>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - clocks = <&clks 41>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - clocks = <&clks 7>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/atlas7-evb.dts b/arch/arm/boot/dts/atlas7-evb.dts deleted file mode 100644 index e0515043d145..000000000000 --- a/arch/arm/boot/dts/atlas7-evb.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFatlas7 Evaluation Board - * - * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/dts-v1/; - -/include/ "atlas7.dtsi" - -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "CSR SiRFatlas7 Evaluation Board"; - compatible = "sirf,atlas7-cb", "sirf,atlas7"; - - chosen { - bootargs = "console=ttySiRF1,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vpp_reserved: vpp_mem@5e800000 { - compatible = "sirf,reserved-memory"; - reg = <0x5e800000 0x800000>; - }; - - nanddisk_reserved: nanddisk@46000000 { - reg = <0x46000000 0x200000>; - no-map; - }; - }; - - - noc { - mediam { - nand@17050000 { - memory-region = <&nanddisk_reserved>; - }; - }; - - gnssm { - spi1: spi@18200000 { - status = "okay"; - spiflash: macronix@0{ - status = "okay"; - compatible = "macronix,mx25l6405d"; - reg = <0>; - spi-max-frequency = <37500000>; - spi-cpha; - spi-cpol; - #address-cells = <1>; - #size-cells = <1>; - partitions@0 { - label = "myspiboot"; - reg = <0x0 0x800000>; - }; - }; - }; - }; - - btm { - uart6: uart@11000000 { - status = "okay"; - uart-has-rtscts; - }; - }; - - disp-iobg { - vpp@13110000 { - memory-region = <&vpp_reserved>; - }; - }; - - display0: display@0 { - compatible = "lvds-panel"; - source = "lvds.0"; - - bl-gpios = <&gpio_1 63 0>; - data-lines = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <220>; - hback-porch = <100>; - hsync-len = <1>; - vback-porch = <10>; - vfront-porch = <25>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - rearview_key { - label = "rearview key"; - linux,code = <KEY_CAMERA>; - gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; - - }; -}; diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi deleted file mode 100644 index 99c9d9d9267f..000000000000 --- a/arch/arm/boot/dts/atlas7.dtsi +++ /dev/null @@ -1,1955 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFatlas7 SoC - * - * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/ { - compatible = "sirf,atlas7"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial9 = &usp2; - spi1 = &spi1; - spi2 = &usp1; - spi3 = &usp2; - spi4 = &usp3; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - }; - }; - - clocks { - xinw { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xinw"; - }; - xin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "xin"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <0 29 4>, <0 82 4>; - }; - - noc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10000000 0x10000000 0xc0000000>; - - gic: interrupt-controller@10301000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x10301000 0x1000>, - <0x10302000 0x0100>; - }; - - pmu_regulator: pmu_regulator@10E30020 { - compatible = "sirf,atlas7-pmu-ldo"; - reg = <0x10E30020 0x4>; - ldo: ldo { - regulator-name = "ldo"; - }; - }; - - atlas7_codec: atlas7_codec@10E30000 { - #sound-dai-cells = <0>; - compatible = "sirf,atlas7-codec"; - reg = <0x10E30000 0x400>; - clocks = <&car 62>; - ldo-supply = <&ldo>; - }; - - atlas7_iacc: atlas7_iacc@10D01000 { - #sound-dai-cells = <0>; - compatible = "sirf,atlas7-iacc"; - reg = <0x10D01000 0x100>; - dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>, - <&dmac3 3>, <&dmac3 9>; - dma-names = "rx", "tx0", "tx1", "tx2", "tx3"; - clocks = <&car 62>; - }; - - ipc@13240000 { - compatible = "sirf,atlas7-ipc"; - ranges = <0x13240000 0x13240000 0x00010000>; - #address-cells = <1>; - #size-cells = <1>; - - hwspinlock { - compatible = "sirf,hwspinlock"; - reg = <0x13240000 0x00010000>; - - num-spinlocks = <30>; - }; - - ns_m3_rproc@0 { - compatible = "sirf,ns2m30-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 123 0>; - }; - - ns_m3_rproc@1 { - compatible = "sirf,ns2m31-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 126 0>; - }; - - ns_kal_rproc@0 { - compatible = "sirf,ns2kal0-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 124 0>; - }; - - ns_kal_rproc@1 { - compatible = "sirf,ns2kal1-rproc"; - reg = <0x13240000 0x00010000>; - interrupts = <0 127 0>; - }; - }; - - pinctrl: ioc@18880000 { - compatible = "sirf,atlas7-ioc"; - reg = <0x18880000 0x1000>, - <0x10E40000 0x1000>; - - audio_ac97_pmx: audio_ac97@0 { - audio_ac97 { - groups = "audio_ac97_grp"; - function = "audio_ac97"; - }; - }; - - audio_func_dbg_pmx: audio_func_dbg@0 { - audio_func_dbg { - groups = "audio_func_dbg_grp"; - function = "audio_func_dbg"; - }; - }; - - audio_i2s_pmx: audio_i2s@0 { - audio_i2s { - groups = "audio_i2s_grp"; - function = "audio_i2s"; - }; - }; - - audio_i2s_2ch_pmx: audio_i2s_2ch@0 { - audio_i2s_2ch { - groups = "audio_i2s_2ch_grp"; - function = "audio_i2s_2ch"; - }; - }; - - audio_i2s_extclk_pmx: audio_i2s_extclk@0 { - audio_i2s_extclk { - groups = "audio_i2s_extclk_grp"; - function = "audio_i2s_extclk"; - }; - }; - - audio_uart0_pmx: audio_uart0@0 { - audio_uart0 { - groups = "audio_uart0_grp"; - function = "audio_uart0"; - }; - }; - - audio_uart1_pmx: audio_uart1@0 { - audio_uart1 { - groups = "audio_uart1_grp"; - function = "audio_uart1"; - }; - }; - - audio_uart2_pmx0: audio_uart2@0 { - audio_uart2_0 { - groups = "audio_uart2_grp0"; - function = "audio_uart2_m0"; - }; - }; - - audio_uart2_pmx1: audio_uart2@1 { - audio_uart2_1 { - groups = "audio_uart2_grp1"; - function = "audio_uart2_m1"; - }; - }; - - c_can_trnsvr_pmx: c_can_trnsvr@0 { - c_can_trnsvr { - groups = "c_can_trnsvr_grp"; - function = "c_can_trnsvr"; - }; - }; - - c0_can_pmx0: c0_can@0 { - c0_can_0 { - groups = "c0_can_grp0"; - function = "c0_can_m0"; - }; - }; - - c0_can_pmx1: c0_can@1 { - c0_can_1 { - groups = "c0_can_grp1"; - function = "c0_can_m1"; - }; - }; - - c1_can_pmx0: c1_can@0 { - c1_can_0 { - groups = "c1_can_grp0"; - function = "c1_can_m0"; - }; - }; - - c1_can_pmx1: c1_can@1 { - c1_can_1 { - groups = "c1_can_grp1"; - function = "c1_can_m1"; - }; - }; - - c1_can_pmx2: c1_can@2 { - c1_can_2 { - groups = "c1_can_grp2"; - function = "c1_can_m2"; - }; - }; - - ca_audio_lpc_pmx: ca_audio_lpc@0 { - ca_audio_lpc { - groups = "ca_audio_lpc_grp"; - function = "ca_audio_lpc"; - }; - }; - - ca_bt_lpc_pmx: ca_bt_lpc@0 { - ca_bt_lpc { - groups = "ca_bt_lpc_grp"; - function = "ca_bt_lpc"; - }; - }; - - ca_coex_pmx: ca_coex@0 { - ca_coex { - groups = "ca_coex_grp"; - function = "ca_coex"; - }; - }; - - ca_curator_lpc_pmx: ca_curator_lpc@0 { - ca_curator_lpc { - groups = "ca_curator_lpc_grp"; - function = "ca_curator_lpc"; - }; - }; - - ca_pcm_debug_pmx: ca_pcm_debug@0 { - ca_pcm_debug { - groups = "ca_pcm_debug_grp"; - function = "ca_pcm_debug"; - }; - }; - - ca_pio_pmx: ca_pio@0 { - ca_pio { - groups = "ca_pio_grp"; - function = "ca_pio"; - }; - }; - - ca_sdio_debug_pmx: ca_sdio_debug@0 { - ca_sdio_debug { - groups = "ca_sdio_debug_grp"; - function = "ca_sdio_debug"; - }; - }; - - ca_spi_pmx: ca_spi@0 { - ca_spi { - groups = "ca_spi_grp"; - function = "ca_spi"; - }; - }; - - ca_trb_pmx: ca_trb@0 { - ca_trb { - groups = "ca_trb_grp"; - function = "ca_trb"; - }; - }; - - ca_uart_debug_pmx: ca_uart_debug@0 { - ca_uart_debug { - groups = "ca_uart_debug_grp"; - function = "ca_uart_debug"; - }; - }; - - clkc_pmx0: clkc@0 { - clkc_0 { - groups = "clkc_grp0"; - function = "clkc_m0"; - }; - }; - - clkc_pmx1: clkc@1 { - clkc_1 { - groups = "clkc_grp1"; - function = "clkc_m1"; - }; - }; - - gn_gnss_i2c_pmx: gn_gnss_i2c@0 { - gn_gnss_i2c { - groups = "gn_gnss_i2c_grp"; - function = "gn_gnss_i2c"; - }; - }; - - gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 { - gn_gnss_uart_nopause { - groups = "gn_gnss_uart_nopause_grp"; - function = "gn_gnss_uart_nopause"; - }; - }; - - gn_gnss_uart_pmx: gn_gnss_uart@0 { - gn_gnss_uart { - groups = "gn_gnss_uart_grp"; - function = "gn_gnss_uart"; - }; - }; - - gn_trg_spi_pmx0: gn_trg_spi@0 { - gn_trg_spi_0 { - groups = "gn_trg_spi_grp0"; - function = "gn_trg_spi_m0"; - }; - }; - - gn_trg_spi_pmx1: gn_trg_spi@1 { - gn_trg_spi_1 { - groups = "gn_trg_spi_grp1"; - function = "gn_trg_spi_m1"; - }; - }; - - cvbs_dbg_pmx: cvbs_dbg@0 { - cvbs_dbg { - groups = "cvbs_dbg_grp"; - function = "cvbs_dbg"; - }; - }; - - cvbs_dbg_test_pmx0: cvbs_dbg_test@0 { - cvbs_dbg_test_0 { - groups = "cvbs_dbg_test_grp0"; - function = "cvbs_dbg_test_m0"; - }; - }; - - cvbs_dbg_test_pmx1: cvbs_dbg_test@1 { - cvbs_dbg_test_1 { - groups = "cvbs_dbg_test_grp1"; - function = "cvbs_dbg_test_m1"; - }; - }; - - cvbs_dbg_test_pmx2: cvbs_dbg_test@2 { - cvbs_dbg_test_2 { - groups = "cvbs_dbg_test_grp2"; - function = "cvbs_dbg_test_m2"; - }; - }; - - cvbs_dbg_test_pmx3: cvbs_dbg_test@3 { - cvbs_dbg_test_3 { - groups = "cvbs_dbg_test_grp3"; - function = "cvbs_dbg_test_m3"; - }; - }; - - cvbs_dbg_test_pmx4: cvbs_dbg_test@4 { - cvbs_dbg_test_4 { - groups = "cvbs_dbg_test_grp4"; - function = "cvbs_dbg_test_m4"; - }; - }; - - cvbs_dbg_test_pmx5: cvbs_dbg_test@5 { - cvbs_dbg_test_5 { - groups = "cvbs_dbg_test_grp5"; - function = "cvbs_dbg_test_m5"; - }; - }; - - cvbs_dbg_test_pmx6: cvbs_dbg_test@6 { - cvbs_dbg_test_6 { - groups = "cvbs_dbg_test_grp6"; - function = "cvbs_dbg_test_m6"; - }; - }; - - cvbs_dbg_test_pmx7: cvbs_dbg_test@7 { - cvbs_dbg_test_7 { - groups = "cvbs_dbg_test_grp7"; - function = "cvbs_dbg_test_m7"; - }; - }; - - cvbs_dbg_test_pmx8: cvbs_dbg_test@8 { - cvbs_dbg_test_8 { - groups = "cvbs_dbg_test_grp8"; - function = "cvbs_dbg_test_m8"; - }; - }; - - cvbs_dbg_test_pmx9: cvbs_dbg_test@9 { - cvbs_dbg_test_9 { - groups = "cvbs_dbg_test_grp9"; - function = "cvbs_dbg_test_m9"; - }; - }; - - cvbs_dbg_test_pmx10: cvbs_dbg_test@10 { - cvbs_dbg_test_10 { - groups = "cvbs_dbg_test_grp10"; - function = "cvbs_dbg_test_m10"; - }; - }; - - cvbs_dbg_test_pmx11: cvbs_dbg_test@11 { - cvbs_dbg_test_11 { - groups = "cvbs_dbg_test_grp11"; - function = "cvbs_dbg_test_m11"; - }; - }; - - cvbs_dbg_test_pmx12: cvbs_dbg_test@12 { - cvbs_dbg_test_12 { - groups = "cvbs_dbg_test_grp12"; - function = "cvbs_dbg_test_m12"; - }; - }; - - cvbs_dbg_test_pmx13: cvbs_dbg_test@13 { - cvbs_dbg_test_13 { - groups = "cvbs_dbg_test_grp13"; - function = "cvbs_dbg_test_m13"; - }; - }; - - cvbs_dbg_test_pmx14: cvbs_dbg_test@14 { - cvbs_dbg_test_14 { - groups = "cvbs_dbg_test_grp14"; - function = "cvbs_dbg_test_m14"; - }; - }; - - cvbs_dbg_test_pmx15: cvbs_dbg_test@15 { - cvbs_dbg_test_15 { - groups = "cvbs_dbg_test_grp15"; - function = "cvbs_dbg_test_m15"; - }; - }; - - gn_gnss_power_pmx: gn_gnss_power@0 { - gn_gnss_power { - groups = "gn_gnss_power_grp"; - function = "gn_gnss_power"; - }; - }; - - gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 { - gn_gnss_sw_status { - groups = "gn_gnss_sw_status_grp"; - function = "gn_gnss_sw_status"; - }; - }; - - gn_gnss_eclk_pmx: gn_gnss_eclk@0 { - gn_gnss_eclk { - groups = "gn_gnss_eclk_grp"; - function = "gn_gnss_eclk"; - }; - }; - - gn_gnss_irq1_pmx0: gn_gnss_irq1@0 { - gn_gnss_irq1_0 { - groups = "gn_gnss_irq1_grp0"; - function = "gn_gnss_irq1_m0"; - }; - }; - - gn_gnss_irq2_pmx0: gn_gnss_irq2@0 { - gn_gnss_irq2_0 { - groups = "gn_gnss_irq2_grp0"; - function = "gn_gnss_irq2_m0"; - }; - }; - - gn_gnss_tm_pmx: gn_gnss_tm@0 { - gn_gnss_tm { - groups = "gn_gnss_tm_grp"; - function = "gn_gnss_tm"; - }; - }; - - gn_gnss_tsync_pmx: gn_gnss_tsync@0 { - gn_gnss_tsync { - groups = "gn_gnss_tsync_grp"; - function = "gn_gnss_tsync"; - }; - }; - - gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 { - gn_io_gnsssys_sw_cfg { - groups = "gn_io_gnsssys_sw_cfg_grp"; - function = "gn_io_gnsssys_sw_cfg"; - }; - }; - - gn_trg_pmx0: gn_trg@0 { - gn_trg_0 { - groups = "gn_trg_grp0"; - function = "gn_trg_m0"; - }; - }; - - gn_trg_pmx1: gn_trg@1 { - gn_trg_1 { - groups = "gn_trg_grp1"; - function = "gn_trg_m1"; - }; - }; - - gn_trg_shutdown_pmx0: gn_trg_shutdown@0 { - gn_trg_shutdown_0 { - groups = "gn_trg_shutdown_grp0"; - function = "gn_trg_shutdown_m0"; - }; - }; - - gn_trg_shutdown_pmx1: gn_trg_shutdown@1 { - gn_trg_shutdown_1 { - groups = "gn_trg_shutdown_grp1"; - function = "gn_trg_shutdown_m1"; - }; - }; - - gn_trg_shutdown_pmx2: gn_trg_shutdown@2 { - gn_trg_shutdown_2 { - groups = "gn_trg_shutdown_grp2"; - function = "gn_trg_shutdown_m2"; - }; - }; - - gn_trg_shutdown_pmx3: gn_trg_shutdown@3 { - gn_trg_shutdown_3 { - groups = "gn_trg_shutdown_grp3"; - function = "gn_trg_shutdown_m3"; - }; - }; - - i2c0_pmx: i2c0@0 { - i2c0 { - groups = "i2c0_grp"; - function = "i2c0"; - }; - }; - - i2c1_pmx: i2c1@0 { - i2c1 { - groups = "i2c1_grp"; - function = "i2c1"; - }; - }; - - jtag_pmx0: jtag@0 { - jtag_0 { - groups = "jtag_grp0"; - function = "jtag_m0"; - }; - }; - - ks_kas_spi_pmx0: ks_kas_spi@0 { - ks_kas_spi_0 { - groups = "ks_kas_spi_grp0"; - function = "ks_kas_spi_m0"; - }; - }; - - ld_ldd_pmx: ld_ldd@0 { - ld_ldd { - groups = "ld_ldd_grp"; - function = "ld_ldd"; - }; - }; - - ld_ldd_16bit_pmx: ld_ldd_16bit@0 { - ld_ldd_16bit { - groups = "ld_ldd_16bit_grp"; - function = "ld_ldd_16bit"; - }; - }; - - ld_ldd_fck_pmx: ld_ldd_fck@0 { - ld_ldd_fck { - groups = "ld_ldd_fck_grp"; - function = "ld_ldd_fck"; - }; - }; - - ld_ldd_lck_pmx: ld_ldd_lck@0 { - ld_ldd_lck { - groups = "ld_ldd_lck_grp"; - function = "ld_ldd_lck"; - }; - }; - - lr_lcdrom_pmx: lr_lcdrom@0 { - lr_lcdrom { - groups = "lr_lcdrom_grp"; - function = "lr_lcdrom"; - }; - }; - - lvds_analog_pmx: lvds_analog@0 { - lvds_analog { - groups = "lvds_analog_grp"; - function = "lvds_analog"; - }; - }; - - nd_df_pmx: nd_df@0 { - nd_df { - groups = "nd_df_grp"; - function = "nd_df"; - }; - }; - - nd_df_nowp_pmx: nd_df_nowp@0 { - nd_df_nowp { - groups = "nd_df_nowp_grp"; - function = "nd_df_nowp"; - }; - }; - - ps_pmx: ps@0 { - ps { - groups = "ps_grp"; - function = "ps"; - }; - }; - - pwc_core_on_pmx: pwc_core_on@0 { - pwc_core_on { - groups = "pwc_core_on_grp"; - function = "pwc_core_on"; - }; - }; - - pwc_ext_on_pmx: pwc_ext_on@0 { - pwc_ext_on { - groups = "pwc_ext_on_grp"; - function = "pwc_ext_on"; - }; - }; - - pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 { - pwc_gpio3_clk { - groups = "pwc_gpio3_clk_grp"; - function = "pwc_gpio3_clk"; - }; - }; - - pwc_io_on_pmx: pwc_io_on@0 { - pwc_io_on { - groups = "pwc_io_on_grp"; - function = "pwc_io_on"; - }; - }; - - pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 { - pwc_lowbatt_b_0 { - groups = "pwc_lowbatt_b_grp0"; - function = "pwc_lowbatt_b_m0"; - }; - }; - - pwc_mem_on_pmx: pwc_mem_on@0 { - pwc_mem_on { - groups = "pwc_mem_on_grp"; - function = "pwc_mem_on"; - }; - }; - - pwc_on_key_b_pmx0: pwc_on_key_b@0 { - pwc_on_key_b_0 { - groups = "pwc_on_key_b_grp0"; - function = "pwc_on_key_b_m0"; - }; - }; - - pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 { - pwc_wakeup_src0 { - groups = "pwc_wakeup_src0_grp"; - function = "pwc_wakeup_src0"; - }; - }; - - pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 { - pwc_wakeup_src1 { - groups = "pwc_wakeup_src1_grp"; - function = "pwc_wakeup_src1"; - }; - }; - - pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 { - pwc_wakeup_src2 { - groups = "pwc_wakeup_src2_grp"; - function = "pwc_wakeup_src2"; - }; - }; - - pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 { - pwc_wakeup_src3 { - groups = "pwc_wakeup_src3_grp"; - function = "pwc_wakeup_src3"; - }; - }; - - pw_cko0_pmx0: pw_cko0@0 { - pw_cko0_0 { - groups = "pw_cko0_grp0"; - function = "pw_cko0_m0"; - }; - }; - - pw_cko0_pmx1: pw_cko0@1 { - pw_cko0_1 { - groups = "pw_cko0_grp1"; - function = "pw_cko0_m1"; - }; - }; - - pw_cko0_pmx2: pw_cko0@2 { - pw_cko0_2 { - groups = "pw_cko0_grp2"; - function = "pw_cko0_m2"; - }; - }; - - pw_cko1_pmx0: pw_cko1@0 { - pw_cko1_0 { - groups = "pw_cko1_grp0"; - function = "pw_cko1_m0"; - }; - }; - - pw_cko1_pmx1: pw_cko1@1 { - pw_cko1_1 { - groups = "pw_cko1_grp1"; - function = "pw_cko1_m1"; - }; - }; - - pw_i2s01_clk_pmx0: pw_i2s01_clk@0 { - pw_i2s01_clk_0 { - groups = "pw_i2s01_clk_grp0"; - function = "pw_i2s01_clk_m0"; - }; - }; - - pw_i2s01_clk_pmx1: pw_i2s01_clk@1 { - pw_i2s01_clk_1 { - groups = "pw_i2s01_clk_grp1"; - function = "pw_i2s01_clk_m1"; - }; - }; - - pw_pwm0_pmx: pw_pwm0@0 { - pw_pwm0 { - groups = "pw_pwm0_grp"; - function = "pw_pwm0"; - }; - }; - - pw_pwm1_pmx: pw_pwm1@0 { - pw_pwm1 { - groups = "pw_pwm1_grp"; - function = "pw_pwm1"; - }; - }; - - pw_pwm2_pmx0: pw_pwm2@0 { - pw_pwm2_0 { - groups = "pw_pwm2_grp0"; - function = "pw_pwm2_m0"; - }; - }; - - pw_pwm2_pmx1: pw_pwm2@1 { - pw_pwm2_1 { - groups = "pw_pwm2_grp1"; - function = "pw_pwm2_m1"; - }; - }; - - pw_pwm3_pmx0: pw_pwm3@0 { - pw_pwm3_0 { - groups = "pw_pwm3_grp0"; - function = "pw_pwm3_m0"; - }; - }; - - pw_pwm3_pmx1: pw_pwm3@1 { - pw_pwm3_1 { - groups = "pw_pwm3_grp1"; - function = "pw_pwm3_m1"; - }; - }; - - pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 { - pw_pwm_cpu_vol_0 { - groups = "pw_pwm_cpu_vol_grp0"; - function = "pw_pwm_cpu_vol_m0"; - }; - }; - - pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 { - pw_pwm_cpu_vol_1 { - groups = "pw_pwm_cpu_vol_grp1"; - function = "pw_pwm_cpu_vol_m1"; - }; - }; - - pw_backlight_pmx0: pw_backlight@0 { - pw_backlight_0 { - groups = "pw_backlight_grp0"; - function = "pw_backlight_m0"; - }; - }; - - pw_backlight_pmx1: pw_backlight@1 { - pw_backlight_1 { - groups = "pw_backlight_grp1"; - function = "pw_backlight_m1"; - }; - }; - - rg_eth_mac_pmx: rg_eth_mac@0 { - rg_eth_mac { - groups = "rg_eth_mac_grp"; - function = "rg_eth_mac"; - }; - }; - - rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 { - rg_gmac_phy_intr_n { - groups = "rg_gmac_phy_intr_n_grp"; - function = "rg_gmac_phy_intr_n"; - }; - }; - - rg_rgmii_mac_pmx: rg_rgmii_mac@0 { - rg_rgmii_mac { - groups = "rg_rgmii_mac_grp"; - function = "rg_rgmii_mac"; - }; - }; - - rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 { - rg_rgmii_phy_ref_clk_0 { - groups = - "rg_rgmii_phy_ref_clk_grp0"; - function = - "rg_rgmii_phy_ref_clk_m0"; - }; - }; - - rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 { - rg_rgmii_phy_ref_clk_1 { - groups = - "rg_rgmii_phy_ref_clk_grp1"; - function = - "rg_rgmii_phy_ref_clk_m1"; - }; - }; - - sd0_pmx: sd0@0 { - sd0 { - groups = "sd0_grp"; - function = "sd0"; - }; - }; - - sd0_4bit_pmx: sd0_4bit@0 { - sd0_4bit { - groups = "sd0_4bit_grp"; - function = "sd0_4bit"; - }; - }; - - sd1_pmx: sd1@0 { - sd1 { - groups = "sd1_grp"; - function = "sd1"; - }; - }; - - sd1_4bit_pmx0: sd1_4bit@0 { - sd1_4bit_0 { - groups = "sd1_4bit_grp0"; - function = "sd1_4bit_m0"; - }; - }; - - sd1_4bit_pmx1: sd1_4bit@1 { - sd1_4bit_1 { - groups = "sd1_4bit_grp1"; - function = "sd1_4bit_m1"; - }; - }; - - sd2_pmx0: sd2@0 { - sd2_0 { - groups = "sd2_grp0"; - function = "sd2_m0"; - }; - }; - - sd2_no_cdb_pmx0: sd2_no_cdb@0 { - sd2_no_cdb_0 { - groups = "sd2_no_cdb_grp0"; - function = "sd2_no_cdb_m0"; - }; - }; - - sd3_pmx: sd3@0 { - sd3 { - groups = "sd3_grp"; - function = "sd3"; - }; - }; - - sd5_pmx: sd5@0 { - sd5 { - groups = "sd5_grp"; - function = "sd5"; - }; - }; - - sd6_pmx0: sd6@0 { - sd6_0 { - groups = "sd6_grp0"; - function = "sd6_m0"; - }; - }; - - sd6_pmx1: sd6@1 { - sd6_1 { - groups = "sd6_grp1"; - function = "sd6_m1"; - }; - }; - - sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 { - sp0_ext_ldo_on { - groups = "sp0_ext_ldo_on_grp"; - function = "sp0_ext_ldo_on"; - }; - }; - - sp0_qspi_pmx: sp0_qspi@0 { - sp0_qspi { - groups = "sp0_qspi_grp"; - function = "sp0_qspi"; - }; - }; - - sp1_spi_pmx: sp1_spi@0 { - sp1_spi { - groups = "sp1_spi_grp"; - function = "sp1_spi"; - }; - }; - - tpiu_trace_pmx: tpiu_trace@0 { - tpiu_trace { - groups = "tpiu_trace_grp"; - function = "tpiu_trace"; - }; - }; - - uart0_pmx: uart0@0 { - uart0 { - groups = "uart0_grp"; - function = "uart0"; - }; - }; - - uart0_nopause_pmx: uart0_nopause@0 { - uart0_nopause { - groups = "uart0_nopause_grp"; - function = "uart0_nopause"; - }; - }; - - uart1_pmx: uart1@0 { - uart1 { - groups = "uart1_grp"; - function = "uart1"; - }; - }; - - uart2_pmx: uart2@0 { - uart2 { - groups = "uart2_grp"; - function = "uart2"; - }; - }; - - uart3_pmx0: uart3@0 { - uart3_0 { - groups = "uart3_grp0"; - function = "uart3_m0"; - }; - }; - - uart3_pmx1: uart3@1 { - uart3_1 { - groups = "uart3_grp1"; - function = "uart3_m1"; - }; - }; - - uart3_pmx2: uart3@2 { - uart3_2 { - groups = "uart3_grp2"; - function = "uart3_m2"; - }; - }; - - uart3_pmx3: uart3@3 { - uart3_3 { - groups = "uart3_grp3"; - function = "uart3_m3"; - }; - }; - - uart3_nopause_pmx0: uart3_nopause@0 { - uart3_nopause_0 { - groups = "uart3_nopause_grp0"; - function = "uart3_nopause_m0"; - }; - }; - - uart3_nopause_pmx1: uart3_nopause@1 { - uart3_nopause_1 { - groups = "uart3_nopause_grp1"; - function = "uart3_nopause_m1"; - }; - }; - - uart4_pmx0: uart4@0 { - uart4_0 { - groups = "uart4_grp0"; - function = "uart4_m0"; - }; - }; - - uart4_pmx1: uart4@1 { - uart4_1 { - groups = "uart4_grp1"; - function = "uart4_m1"; - }; - }; - - uart4_pmx2: uart4@2 { - uart4_2 { - groups = "uart4_grp2"; - function = "uart4_m2"; - }; - }; - - uart4_nopause_pmx: uart4_nopause@0 { - uart4_nopause { - groups = "uart4_nopause_grp"; - function = "uart4_nopause"; - }; - }; - - usb0_drvvbus_pmx: usb0_drvvbus@0 { - usb0_drvvbus { - groups = "usb0_drvvbus_grp"; - function = "usb0_drvvbus"; - }; - }; - - usb1_drvvbus_pmx: usb1_drvvbus@0 { - usb1_drvvbus { - groups = "usb1_drvvbus_grp"; - function = "usb1_drvvbus"; - }; - }; - - visbus_dout_pmx: visbus_dout@0 { - visbus_dout { - groups = "visbus_dout_grp"; - function = "visbus_dout"; - }; - }; - - vi_vip1_pmx: vi_vip1@0 { - vi_vip1 { - groups = "vi_vip1_grp"; - function = "vi_vip1"; - }; - }; - - vi_vip1_ext_pmx: vi_vip1_ext@0 { - vi_vip1_ext { - groups = "vi_vip1_ext_grp"; - function = "vi_vip1_ext"; - }; - }; - - vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 { - vi_vip1_low8bit { - groups = "vi_vip1_low8bit_grp"; - function = "vi_vip1_low8bit"; - }; - }; - - vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 { - vi_vip1_high8bit { - groups = "vi_vip1_high8bit_grp"; - function = "vi_vip1_high8bit"; - }; - }; - }; - - pmipc { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13240000 0x13240000 0x00010000>; - pmipc@0x13240000 { - compatible = "sirf,atlas7-pmipc"; - reg = <0x13240000 0x00010000>; - }; - }; - - dramfw { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10830000 0x10830000 0x18000>; - dramfw@10820000 { - compatible = "sirf,nocfw-dramfw"; - reg = <0x10830000 0x18000>; - }; - }; - - spramfw { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10250000 0x10250000 0x3000>; - spramfw@10820000 { - compatible = "sirf,nocfw-spramfw"; - reg = <0x10250000 0x3000>; - }; - }; - - cpum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10200000 0x10200000 0x3000>; - cpum@10200000 { - compatible = "sirf,nocfw-cpum"; - reg = <0x10200000 0x3000>; - }; - }; - - cgum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18641000 0x18641000 0x3000>, - <0x18620000 0x18620000 0x1000>, - <0x18630000 0x18630000 0x10000>; - - cgum@18641000 { - compatible = "sirf,nocfw-cgum"; - reg = <0x18641000 0x3000>; - }; - - car: clock-controller@18620000 { - compatible = "sirf,atlas7-car"; - reg = <0x18620000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - pwm: pwm@18630000 { - compatible = "sirf,prima2-pwm"; - #pwm-cells = <2>; - reg = <0x18630000 0x10000>; - clocks = <&car 138>, <&car 139>, <&car 237>, - <&car 240>, <&car 140>, <&car 246>; - clock-names = "pwmc", "sigsrc0", "sigsrc1", - "sigsrc2", "sigsrc3", "sigsrc4"; - }; - }; - - gnssm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18000000 0x18000000 0x0000ffff>, - <0x18010000 0x18010000 0x1000>, - <0x18020000 0x18020000 0x1000>, - <0x18030000 0x18030000 0x1000>, - <0x18040000 0x18040000 0x1000>, - <0x18050000 0x18050000 0x1000>, - <0x18060000 0x18060000 0x1000>, - <0x180b0000 0x180b0000 0x4000>, - <0x18100000 0x18100000 0x3000>, - <0x18250000 0x18250000 0x10000>, - <0x18200000 0x18200000 0x1000>; - - dmac0: dma-controller@18000000 { - cell-index = <0>; - compatible = "sirf,atlas7-dmac"; - reg = <0x18000000 0x1000>; - interrupts = <0 12 0>; - clocks = <&car 89>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - gnssmfw@0x18100000 { - compatible = "sirf,nocfw-gnssm"; - reg = <0x18100000 0x3000>; - }; - - uart0: uart@18010000 { - cell-index = <0>; - compatible = "sirf,atlas7-uart"; - reg = <0x18010000 0x1000>; - interrupts = <0 17 0>; - clocks = <&car 90>; - fifosize = <128>; - dmas = <&dmac0 3>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@18020000 { - cell-index = <1>; - compatible = "sirf,atlas7-uart"; - reg = <0x18020000 0x1000>; - interrupts = <0 18 0>; - clocks = <&car 88>; - fifosize = <32>; - }; - - uart2: uart@18030000 { - cell-index = <2>; - compatible = "sirf,atlas7-uart"; - reg = <0x18030000 0x1000>; - interrupts = <0 19 0>; - clocks = <&car 91>; - fifosize = <128>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart3: uart@18040000 { - cell-index = <3>; - compatible = "sirf,atlas7-uart"; - reg = <0x18040000 0x1000>; - interrupts = <0 66 0>; - clocks = <&car 92>; - fifosize = <128>; - dmas = <&dmac0 4>, <&dmac0 5>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart4: uart@18050000 { - cell-index = <4>; - compatible = "sirf,atlas7-uart"; - reg = <0x18050000 0x1000>; - interrupts = <0 69 0>; - clocks = <&car 93>; - fifosize = <128>; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - uart5: uart@18060000 { - cell-index = <5>; - compatible = "sirf,atlas7-uart"; - reg = <0x18060000 0x1000>; - interrupts = <0 71 0>; - clocks = <&car 94>; - fifosize = <128>; - dmas = <&dmac0 8>, <&dmac0 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - gmac: eth@180b0000 { - compatible = "snps, dwc-eth-qos"; - reg = <0x180b0000 0x4000>; - interrupts = <0 59 0>, <0 70 0>; - interrupt-names = "macirq", "macpmt"; - clocks = <&car 39>, <&car 45>, - <&car 86>, <&car 87>; - clock-names = "gnssm_rgmii", "gnssm_gmac", - "rgmii", "gmac"; - local-mac-address = [00 00 00 00 00 00]; - phy-mode = "rgmii"; - }; - dspub@18250000 { - compatible = "dx,cc44p"; - reg = <0x18250000 0x10000>; - interrupts = <0 27 0>; - }; - - spi1: spi@18200000 { - compatible = "sirf,prima2-spi"; - reg = <0x18200000 0x1000>; - interrupts = <0 16 0>; - clocks = <&car 95>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - - gpum { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13000000 0x13000000 0x3000>, - <0x13010000 0x13010000 0x1400>, - <0x13010800 0x13010800 0x100>, - <0x13011000 0x13011000 0x100>; - gpum@0x13000000 { - compatible = "sirf,nocfw-gpum"; - reg = <0x13000000 0x3000>; - }; - dmacsdrr: dma-controller@13010800 { - cell-index = <5>; - compatible = "sirf,atlas7-dmac-v2"; - reg = <0x13010800 0x100>; - interrupts = <0 8 0>; - clocks = <&car 127>; - #dma-cells = <1>; - #dma-channels = <1>; - }; - dmacsdrw: dma-controller@13011000 { - cell-index = <6>; - compatible = "sirf,atlas7-dmac-v2"; - reg = <0x13011000 0x100>; - interrupts = <0 9 0>; - clocks = <&car 127>; - #dma-cells = <1>; - #dma-channels = <1>; - }; - sdr@0x13010000 { - compatible = "sirf,atlas7-sdr"; - reg = <0x13010000 0x1400>; - interrupts = <0 7 0>, - <0 8 0>, - <0 9 0>; - clocks = <&car 127>; - dmas = <&dmacsdrr 0>, <&dmacsdrw 0>; - dma-names = "tx", "rx"; - }; - }; - - mediam { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x15000000 0x15000000 0x00600000>, - <0x16000000 0x16000000 0x00200000>, - <0x17000000 0x17000000 0x10000>, - <0x17020000 0x17020000 0x1000>, - <0x17030000 0x17030000 0x1000>, - <0x17040000 0x17040000 0x1000>, - <0x17050000 0x17050000 0x10000>, - <0x17060000 0x17060000 0x200>, - <0x17060200 0x17060200 0x100>, - <0x17070000 0x17070000 0x200>, - <0x17070200 0x17070200 0x100>, - <0x170A0000 0x170A0000 0x3000>; - - multimedia@15000000 { - compatible = "sirf,atlas7-video-codec"; - reg = <0x15000000 0x10000>; - interrupts = <0 5 0>; - clocks = <&car 102>; - }; - - mediam@170A0000 { - compatible = "sirf,nocfw-mediam"; - reg = <0x170A0000 0x3000>; - }; - - gpio_0: gpio_mediam@17040000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x17040000 0x1000>; - interrupts = <0 13 0>, <0 14 0>; - clocks = <&car 107>; - clock-names = "gpio0_io"; - gpio-controller; - interrupt-controller; - - gpio-banks = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 32 0 0>; - gpio-ranges-group-names = "lvds_gpio_grp", - "uart_nand_gpio_grp"; - }; - - nand@17050000 { - compatible = "sirf,atlas7-nand"; - reg = <0x17050000 0x10000>; - pinctrl-names = "default"; - pinctrl-0 = <&nd_df_pmx>; - interrupts = <0 41 0>; - clocks = <&car 108>, <&car 112>; - clock-names = "nand_io", "nand_nand"; - }; - - sd0: sdhci@16000000 { - cell-index = <0>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x16000000 0x100000>; - interrupts = <0 38 0>; - clocks = <&car 109>, <&car 111>; - clock-names = "core", "iface"; - wp-inverted; - non-removable; - status = "disabled"; - bus-width = <8>; - }; - - sd1: sdhci@16100000 { - cell-index = <1>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x16100000 0x100000>; - interrupts = <0 38 0>; - clocks = <&car 109>, <&car 111>; - clock-names = "core", "iface"; - non-removable; - status = "disabled"; - bus-width = <8>; - }; - - jpeg@17000000 { - compatible = "sirf,atlas7-jpeg"; - reg = <0x17000000 0x10000>; - interrupts = <0 72 0>, - <0 73 0>; - clocks = <&car 103>; - }; - - usb0: usb@17060000 { - cell-index = <0>; - compatible = "sirf,atlas7-usb"; - reg = <0x17060000 0x200>; - interrupts = <0 10 0>; - clocks = <&car 113>; - sirf,usbphy = <&usbphy0>; - phy_type = "utmi"; - dr_mode = "otg"; - maximum-speed = "high-speed"; - status = "okay"; - }; - - usb1: usb@17070000 { - cell-index = <1>; - compatible = "sirf,atlas7-usb"; - reg = <0x17070000 0x200>; - interrupts = <0 11 0>; - clocks = <&car 114>; - sirf,usbphy = <&usbphy1>; - phy_type = "utmi"; - dr_mode = "host"; - maximum-speed = "high-speed"; - status = "okay"; - }; - - usbphy0: usbphy@0 { - compatible = "sirf,atlas7-usbphy"; - reg = <0x17060200 0x100>; - clocks = <&car 115>; - status = "okay"; - }; - - usbphy1: usbphy@1 { - compatible = "sirf,atlas7-usbphy"; - reg = <0x17070200 0x100>; - clocks = <&car 116>; - status = "okay"; - }; - - i2c0: i2c@17020000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0x17020000 0x1000>; - interrupts = <0 24 0>; - clocks = <&car 105>; - #address-cells = <1>; - #size-cells = <0>; - }; - - }; - - vdifm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13290000 0x13290000 0x3000>, - <0x13300000 0x13300000 0x1000>, - <0x14200000 0x14200000 0x600000>; - - vdifm@13290000 { - compatible = "sirf,nocfw-vdifm"; - reg = <0x13290000 0x3000>; - }; - - gpio_1: gpio_vdifm@13300000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x13300000 0x1000>; - interrupts = <0 43 0>, <0 44 0>, - <0 45 0>, <0 46 0>; - clocks = <&car 84>; - clock-names = "gpio1_io"; - gpio-controller; - interrupt-controller; - - gpio-banks = <4>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 32 0 0>, - <&pinctrl 64 0 0>, - <&pinctrl 96 0 0>; - gpio-ranges-group-names = "gnss_gpio_grp", - "lcd_vip_gpio_grp", - "sdio_i2s_gpio_grp", - "sp_rgmii_gpio_grp"; - }; - - sd2: sdhci@14200000 { - cell-index = <2>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14200000 0x100000>; - interrupts = <0 23 0>; - clocks = <&car 70>, <&car 75>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - sd-uhs-sdr50; - vqmmc-supply = <&vqmmc>; - vqmmc: vqmmc@2 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-name = "vqmmc-ldo"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-allow-bypass; - }; - }; - - sd3: sdhci@14300000 { - cell-index = <3>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14300000 0x100000>; - interrupts = <0 23 0>; - clocks = <&car 76>, <&car 81>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - - sd5: sdhci@14500000 { - cell-index = <5>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14500000 0x100000>; - interrupts = <0 39 0>; - clocks = <&car 71>, <&car 76>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - loop-dma; - }; - - sd6: sdhci@14600000 { - cell-index = <6>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14600000 0x100000>; - interrupts = <0 98 0>; - clocks = <&car 72>, <&car 77>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - - sd7: sdhci@14700000 { - cell-index = <7>; - compatible = "sirf,atlas7-sdhc"; - reg = <0x14700000 0x100000>; - interrupts = <0 98 0>; - clocks = <&car 72>, <&car 77>; - clock-names = "core", "iface"; - status = "disabled"; - bus-width = <4>; - }; - }; - - audiom { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10d50000 0x10d50000 0x0000ffff>, - <0x10d60000 0x10d60000 0x0000ffff>, - <0x10d80000 0x10d80000 0x0000ffff>, - <0x10d90000 0x10d90000 0x0000ffff>, - <0x10ED0000 0x10ED0000 0x3000>, - <0x10dc8000 0x10dc8000 0x1000>, - <0x10dc0000 0x10dc0000 0x1000>, - <0x10db0000 0x10db0000 0x4000>, - <0x10d40000 0x10d40000 0x1000>, - <0x10d30000 0x10d30000 0x1000>; - - timer@10dc0000 { - compatible = "sirf,atlas7-tick"; - reg = <0x10dc0000 0x1000>; - interrupts = <0 0 0>, - <0 1 0>, - <0 2 0>, - <0 49 0>, - <0 50 0>, - <0 51 0>; - clocks = <&car 47>; - }; - - timerb@10dc8000 { - compatible = "sirf,atlas7-tick"; - reg = <0x10dc8000 0x1000>; - interrupts = <0 74 0>, - <0 75 0>, - <0 76 0>, - <0 77 0>, - <0 78 0>, - <0 79 0>; - clocks = <&car 47>; - }; - - vip0@10db0000 { - compatible = "sirf,atlas7-vip0"; - reg = <0x10db0000 0x2000>; - interrupts = <0 85 0>; - sirf,vip_cma_size = <0xC00000>; - }; - - cvd@10db2000 { - compatible = "sirf,cvd"; - reg = <0x10db2000 0x2000>; - clocks = <&car 46>; - }; - - dmac2: dma-controller@10d50000 { - cell-index = <2>; - compatible = "sirf,atlas7-dmac"; - reg = <0x10d50000 0xffff>; - interrupts = <0 55 0>; - clocks = <&car 60>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - dmac3: dma-controller@10d60000 { - cell-index = <3>; - compatible = "sirf,atlas7-dmac"; - reg = <0x10d60000 0xffff>; - interrupts = <0 56 0>; - clocks = <&car 61>; - dma-channels = <16>; - #dma-cells = <1>; - }; - - adc: adc@10d80000 { - compatible = "sirf,atlas7-adc"; - reg = <0x10d80000 0xffff>; - interrupts = <0 34 0>; - clocks = <&car 49>; - #io-channel-cells = <1>; - }; - - pulsec@10d90000 { - compatible = "sirf,prima2-pulsec"; - reg = <0x10d90000 0xffff>; - interrupts = <0 42 0>; - clocks = <&car 54>; - }; - - audiom@10ED0000 { - compatible = "sirf,nocfw-audiom"; - reg = <0x10ED0000 0x3000>; - interrupts = <0 102 0>; - }; - - usp1: usp@10d30000 { - cell-index = <1>; - reg = <0x10d30000 0x1000>; - fifosize = <512>; - clocks = <&car 58>; - dmas = <&dmac2 6>, <&dmac2 7>; - dma-names = "rx", "tx"; - }; - - usp2: usp@10d40000 { - cell-index = <2>; - reg = <0x10d40000 0x1000>; - interrupts = <0 22 0>; - clocks = <&car 59>; - dmas = <&dmac2 12>, <&dmac2 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - ddrm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x10820000 0x10820000 0x3000>, - <0x10800000 0x10800000 0x2000>; - ddrm@10820000 { - compatible = "sirf,nocfw-ddrm"; - reg = <0x10820000 0x3000>; - interrupts = <0 105 0>; - }; - - memory-controller@0x10800000 { - compatible = "sirf,atlas7-memc"; - reg = <0x10800000 0x2000>; - }; - - }; - - btm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x11002000 0x11002000 0x0000ffff>, - <0x11010000 0x11010000 0x3000>, - <0x11000000 0x11000000 0x1000>, - <0x11001000 0x11001000 0x1000>; - - dmac4: dma-controller@11002000 { - cell-index = <4>; - compatible = "sirf,atlas7-dmac"; - reg = <0x11002000 0x1000>; - interrupts = <0 99 0>; - clocks = <&car 130>; - dma-channels = <16>; - #dma-cells = <1>; - }; - uart6: uart@11000000 { - cell-index = <6>; - compatible = "sirf,atlas7-bt-uart", - "sirf,atlas7-uart"; - reg = <0x11000000 0x1000>; - interrupts = <0 100 0>; - clocks = <&car 131>, <&car 133>, <&car 134>; - clock-names = "uart", "general", "noc"; - fifosize = <128>; - dmas = <&dmac4 12>, <&dmac4 13>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usp3: usp@11001000 { - compatible = "sirf,atlas7-bt-usp", - "sirf,prima2-usp-pcm"; - cell-index = <3>; - reg = <0x11001000 0x1000>; - fifosize = <512>; - clocks = <&car 132>, <&car 129>, <&car 133>, - <&car 134>, <&car 135>; - clock-names = "usp3_io", "a7ca_btss", "a7ca_io", - "noc_btm_io", "thbtm_io"; - dmas = <&dmac4 0>, <&dmac4 1>; - dma-names = "rx", "tx"; - }; - - btm@11010000 { - compatible = "sirf,nocfw-btm"; - reg = <0x11010000 0x3000>; - }; - }; - - rtcm { - compatible = "arteris, flexnoc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x18810000 0x18810000 0x3000>, - <0x18840000 0x18840000 0x1000>, - <0x18890000 0x18890000 0x1000>, - <0x188B0000 0x188B0000 0x10000>, - <0x188D0000 0x188D0000 0x1000>; - rtcm@18810000 { - compatible = "sirf,nocfw-rtcm"; - reg = <0x18810000 0x3000>; - interrupts = <0 109 0>; - }; - - gpio_2: gpio_rtcm@18890000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,atlas7-gpio"; - reg = <0x18890000 0x1000>; - interrupts = <0 47 0>; - gpio-controller; - interrupt-controller; - - gpio-banks = <1>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "rtc_gpio_grp"; - }; - - rtc-iobg@18840000 { - compatible = "sirf,prima2-rtciobg", - "sirf-prima2-rtciobg-bus", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18840000 0x1000>; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x100>; - interrupts = <0 52 0>; - }; - pwrc@3000 { - compatible = "sirf,atlas7-pwrc"; - reg = <0x3000 0x100>; - }; - }; - - qspi: flash@188B0000 { - cell-index = <0>; - compatible = "sirf,atlas7-qspi-nor"; - reg = <0x188B0000 0x10000>; - interrupts = <0 15 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - retain@0x188D0000 { - compatible = "sirf,atlas7-retain"; - reg = <0x188D0000 0x1000>; - }; - - }; - disp-iobg { - /* lcdc0 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x13100000 0x13100000 0x20000>, - <0x10e10000 0x10e10000 0x10000>, - <0x17010000 0x17010000 0x10000>; - - lcd@13100000 { - compatible = "sirf,atlas7-lcdc"; - reg = <0x13100000 0x10000>; - interrupts = <0 30 0>; - clocks = <&car 79>; - }; - vpp@13110000 { - compatible = "sirf,atlas7-vpp"; - reg = <0x13110000 0x10000>; - interrupts = <0 31 0>; - clocks = <&car 78>; - resets = <&car 29>; - }; - lvds@10e10000 { - compatible = "sirf,atlas7-lvdsc"; - reg = <0x10e10000 0x10000>; - interrupts = <0 64 0>; - clocks = <&car 54>; - resets = <&car 29>; - }; - g2d@17010000 { - compatible = "sirf, atlas7-g2d"; - reg = <0x17010000 0x10000>; - interrupts = <0 61 0>; - clocks = <&car 104>; - }; - - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x12000000 0x12000000 0x1000000>; - - graphics@12000000 { - compatible = "powervr,sgx531"; - reg = <0x12000000 0x1000000>; - interrupts = <0 6 0>; - clocks = <&car 126>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts deleted file mode 100644 index 7394f764df65..000000000000 --- a/arch/arm/boot/dts/prima2-evb.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFprimaII Evaluation Board - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/dts-v1/; - -/include/ "prima2.dtsi" - -/ { - model = "CSR SiRFprimaII Evaluation Board"; - compatible = "sirf,prima2", "sirf,prima2-cb"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - axi { - peri-iobg { - uart@b0060000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; - }; - spi@b00d0000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>; - }; - spi@b0170000 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi deleted file mode 100644 index 7d3d93c22ed9..000000000000 --- a/arch/arm/boot/dts/prima2.dtsi +++ /dev/null @@ -1,838 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for CSR SiRFprimaII SoC - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -/ { - compatible = "sirf,prima2"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - clocks = <&clks 12>; - operating-points = < - /* kHz uV */ - 200000 1025000 - 400000 1025000 - 664000 1050000 - 800000 1100000 - >; - clock-latency = <150000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <29>; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - cache-controller@80040000 { - compatible = "arm,pl310-cache"; - reg = <0x80040000 0x1000>; - interrupts = <59>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - arm,filter-ranges = <0 0x40000000>; - }; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clks: clock-controller@88000000 { - compatible = "sirf,prima2-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - #clock-cells = <1>; - }; - - rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - - cphifbg@88030000 { - compatible = "sirf,prima2-cphifbg"; - reg = <0x88030000 0x1000>; - clocks = <&clks 42>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x2000>; - interrupts = <27>; - clocks = <&clks 5>; - }; - - memc-monitor { - compatible = "sirf,prima2-memcmon"; - reg = <0x90002000 0x200>; - interrupts = <4>; - clocks = <&clks 32>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - display@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx531"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - clocks = <&clks 32>; - }; - }; - - multimedia-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - multimedia@a0000000 { - compatible = "sirf,prima2-video-codec"; - reg = <0xa0000000 0x8000000>; - interrupts = <5>; - clocks = <&clks 33>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - resets = <&rstc 1>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - clocks = <&clks 9>; - resets = <&rstc 2>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - clocks = <&clks 8>; - resets = <&rstc 0>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>, - <0x56000000 0x56000000 0x1b00000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - clocks = <&clks 11>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - clocks = <&clks 26>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - clocks = <&clks 27>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x1000>; - interrupts = <17>; - fifosize = <128>; - clocks = <&clks 13>; - dmas = <&dmac1 5>, <&dmac0 2>; - dma-names = "rx", "tx"; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x1000>; - interrupts = <18>; - fifosize = <32>; - clocks = <&clks 14>; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x1000>; - interrupts = <19>; - fifosize = <128>; - clocks = <&clks 15>; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "rx", "tx"; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - fifosize = <128>; - clocks = <&clks 28>; - dmas = <&dmac1 1>, <&dmac1 2>; - dma-names = "rx", "tx"; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - fifosize = <128>; - clocks = <&clks 29>; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "rx", "tx"; - }; - - usp2: usp@b00a0000 { - cell-index = <2>; - compatible = "sirf,prima2-usp"; - reg = <0xb00a0000 0x10000>; - interrupts = <22>; - fifosize = <128>; - clocks = <&clks 30>; - dmas = <&dmac0 10>, <&dmac0 11>; - dma-names = "rx", "tx"; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - clocks = <&clks 24>; - #dma-cells = <1>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - clocks = <&clks 25>; - #dma-cells = <1>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - clocks = <&clks 31>; - interrupts = <14>; - sirf,vip-dma-rx-channel = <16>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac1 9>, - <&dmac1 4>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 19>; - status = "disabled"; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - sirf,spi-num-chipselects = <1>; - dmas = <&dmac0 12>, - <&dmac0 13>; - dma-names = "rx", "tx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clks 20>; - status = "disabled"; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - clocks = <&clks 17>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - clocks = <&clks 18>; - #address-cells = <1>; - #size-cells = <0>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - clocks = <&clks 16>; - }; - - gpio: pinctrl@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,prima2-pinctrl"; - reg = <0xb0120000 0x10000>; - interrupts = <43 44 45 46 47>; - gpio-controller; - interrupt-controller; - - lcd_16pins_a: lcd0@0 { - lcd { - sirf,pins = "lcd_16bitsgrp"; - sirf,function = "lcd_16bits"; - }; - }; - lcd_18pins_a: lcd0@1 { - lcd { - sirf,pins = "lcd_18bitsgrp"; - sirf,function = "lcd_18bits"; - }; - }; - lcd_24pins_a: lcd0@2 { - lcd { - sirf,pins = "lcd_24bitsgrp"; - sirf,function = "lcd_24bits"; - }; - }; - lcdrom_pins_a: lcdrom0@0 { - lcd { - sirf,pins = "lcdromgrp"; - sirf,function = "lcdrom"; - }; - }; - uart0_pins_a: uart0@0 { - uart { - sirf,pins = "uart0grp"; - sirf,function = "uart0"; - }; - }; - uart0_noflow_pins_a: uart0@1 { - uart { - sirf,pins = "uart0_nostreamctrlgrp"; - sirf,function = "uart0_nostreamctrl"; - }; - }; - uart1_pins_a: uart1@0 { - uart { - sirf,pins = "uart1grp"; - sirf,function = "uart1"; - }; - }; - uart2_pins_a: uart2@0 { - uart { - sirf,pins = "uart2grp"; - sirf,function = "uart2"; - }; - }; - uart2_noflow_pins_a: uart2@1 { - uart { - sirf,pins = "uart2_nostreamctrlgrp"; - sirf,function = "uart2_nostreamctrl"; - }; - }; - spi0_pins_a: spi0@0 { - spi { - sirf,pins = "spi0grp"; - sirf,function = "spi0"; - }; - }; - spi1_pins_a: spi1@0 { - spi { - sirf,pins = "spi1grp"; - sirf,function = "spi1"; - }; - }; - i2c0_pins_a: i2c0@0 { - i2c { - sirf,pins = "i2c0grp"; - sirf,function = "i2c0"; - }; - }; - i2c1_pins_a: i2c1@0 { - i2c { - sirf,pins = "i2c1grp"; - sirf,function = "i2c1"; - }; - }; - pwm0_pins_a: pwm0@0 { - pwm { - sirf,pins = "pwm0grp"; - sirf,function = "pwm0"; - }; - }; - pwm1_pins_a: pwm1@0 { - pwm { - sirf,pins = "pwm1grp"; - sirf,function = "pwm1"; - }; - }; - pwm2_pins_a: pwm2@0 { - pwm { - sirf,pins = "pwm2grp"; - sirf,function = "pwm2"; - }; - }; - pwm3_pins_a: pwm3@0 { - pwm { - sirf,pins = "pwm3grp"; - sirf,function = "pwm3"; - }; - }; - gps_pins_a: gps@0 { - gps { - sirf,pins = "gpsgrp"; - sirf,function = "gps"; - }; - }; - vip_pins_a: vip@0 { - vip { - sirf,pins = "vipgrp"; - sirf,function = "vip"; - }; - }; - sdmmc0_pins_a: sdmmc0@0 { - sdmmc0 { - sirf,pins = "sdmmc0grp"; - sirf,function = "sdmmc0"; - }; - }; - sdmmc1_pins_a: sdmmc1@0 { - sdmmc1 { - sirf,pins = "sdmmc1grp"; - sirf,function = "sdmmc1"; - }; - }; - sdmmc2_pins_a: sdmmc2@0 { - sdmmc2 { - sirf,pins = "sdmmc2grp"; - sirf,function = "sdmmc2"; - }; - }; - sdmmc3_pins_a: sdmmc3@0 { - sdmmc3 { - sirf,pins = "sdmmc3grp"; - sirf,function = "sdmmc3"; - }; - }; - sdmmc4_pins_a: sdmmc4@0 { - sdmmc4 { - sirf,pins = "sdmmc4grp"; - sirf,function = "sdmmc4"; - }; - }; - sdmmc5_pins_a: sdmmc5@0 { - sdmmc5 { - sirf,pins = "sdmmc5grp"; - sirf,function = "sdmmc5"; - }; - }; - i2s_mclk_pins_a: i2s_mclk@0 { - i2s_mclk { - sirf,pins = "i2smclkgrp"; - sirf,function = "i2s_mclk"; - }; - }; - i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { - i2s_ext_clk_input { - sirf,pins = "i2s_ext_clk_inputgrp"; - sirf,function = "i2s_ext_clk_input"; - }; - }; - i2s_pins_a: i2s@0 { - i2s { - sirf,pins = "i2sgrp"; - sirf,function = "i2s"; - }; - }; - i2s_no_din_pins_a: i2s_no_din@0 { - i2s_no_din { - sirf,pins = "i2s_no_dingrp"; - sirf,function = "i2s_no_din"; - }; - }; - i2s_6chn_pins_a: i2s_6chn@0 { - i2s_6chn { - sirf,pins = "i2s_6chngrp"; - sirf,function = "i2s_6chn"; - }; - }; - ac97_pins_a: ac97@0 { - ac97 { - sirf,pins = "ac97grp"; - sirf,function = "ac97"; - }; - }; - nand_pins_a: nand@0 { - nand { - sirf,pins = "nandgrp"; - sirf,function = "nand"; - }; - }; - usp0_pins_a: usp0@0 { - usp0 { - sirf,pins = "usp0grp"; - sirf,function = "usp0"; - }; - }; - usp0_uart_nostreamctrl_pins_a: usp0@1 { - usp0 { - sirf,pins = - "usp0_uart_nostreamctrl_grp"; - sirf,function = - "usp0_uart_nostreamctrl"; - }; - }; - usp0_only_utfs_pins_a: usp0@2 { - usp0 { - sirf,pins = "usp0_only_utfs_grp"; - sirf,function = "usp0_only_utfs"; - }; - }; - usp0_only_urfs_pins_a: usp0@3 { - usp0 { - sirf,pins = "usp0_only_urfs_grp"; - sirf,function = "usp0_only_urfs"; - }; - }; - usp1_pins_a: usp1@0 { - usp1 { - sirf,pins = "usp1grp"; - sirf,function = "usp1"; - }; - }; - usp1_uart_nostreamctrl_pins_a: usp1@1 { - usp1 { - sirf,pins = - "usp1_uart_nostreamctrl_grp"; - sirf,function = - "usp1_uart_nostreamctrl"; - }; - }; - usp2_pins_a: usp2@0 { - usp2 { - sirf,pins = "usp2grp"; - sirf,function = "usp2"; - }; - }; - usp2_uart_nostreamctrl_pins_a: usp2@1 { - usp2 { - sirf,pins = - "usp2_uart_nostreamctrl_grp"; - sirf,function = - "usp2_uart_nostreamctrl"; - }; - }; - usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { - usb0_utmi_drvbus { - sirf,pins = "usb0_utmi_drvbusgrp"; - sirf,function = "usb0_utmi_drvbus"; - }; - }; - usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { - usb1_utmi_drvbus { - sirf,pins = "usb1_utmi_drvbusgrp"; - sirf,function = "usb1_utmi_drvbus"; - }; - }; - usb1_dp_dn_pins_a: usb1_dp_dn@0 { - usb1_dp_dn { - sirf,pins = "usb1_dp_dngrp"; - sirf,function = "usb1_dp_dn"; - }; - }; - uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { - uart1_route_io_usb1 { - sirf,pins = "uart1_route_io_usb1grp"; - sirf,function = "uart1_route_io_usb1"; - }; - }; - warm_rst_pins_a: warm_rst@0 { - warm_rst { - sirf,pins = "warm_rstgrp"; - sirf,function = "warm_rst"; - }; - }; - pulse_count_pins_a: pulse_count@0 { - pulse_count { - sirf,pins = "pulse_countgrp"; - sirf,function = "pulse_count"; - }; - }; - cko0_pins_a: cko0@0 { - cko0 { - sirf,pins = "cko0grp"; - sirf,function = "cko0"; - }; - }; - cko1_pins_a: cko1@0 { - cko1 { - sirf,pins = "cko1grp"; - sirf,function = "cko1"; - }; - }; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - clocks = <&clks 21>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - clocks = <&clks 22>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - clocks = <&clks 23>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <8>; - clocks = <&clks 36>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - status = "disabled"; - bus-width = <4>; - clocks = <&clks 36>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - status = "disabled"; - clocks = <&clks 37>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - status = "disabled"; - clocks = <&clks 37>; - }; - - sd4: sdhci@56400000 { - cell-index = <4>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56400000 0x100000>; - interrupts = <39>; - status = "disabled"; - clocks = <&clks 38>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - clocks = <&clks 38>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - minigpsrtc@2000 { - compatible = "sirf,prima2-minigpsrtc"; - reg = <0x2000 0x1000>; - interrupts = <54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - clocks = <&clks 40>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - clocks = <&clks 41>; - }; - - sata@b00f0000 { - compatible = "synopsys,dwc-ahsata"; - reg = <0xb8020000 0x10000>; - interrupts = <37>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - clocks = <&clks 7>; - }; - }; - }; -}; diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig deleted file mode 100644 index be19aa127595..000000000000 --- a/arch/arm/configs/prima2_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_ARCH_SIRF=y -CONFIG_SMP=y -CONFIG_SCHED_MC=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_KEXEC=y -CONFIG_BINFMT_MISC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -CONFIG_SERIAL_SIRFSOC=y -CONFIG_SERIAL_SIRFSOC_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_SIRF=y -CONFIG_SPI=y -CONFIG_SPI_SIRF=y -CONFIG_SPI_SPIDEV=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_USB_GADGET=y -CONFIG_USB_MASS_STORAGE=m -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_SIRF=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_SIRFSOC=y -CONFIG_DMADEVICES=y -CONFIG_DMADEVICES_DEBUG=y -CONFIG_DMADEVICES_VDEBUG=y -CONFIG_SIRF_DMA=y -CONFIG_HWSPINLOCK_SIRF=y -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CRAMFS=y -CONFIG_ROMFS_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_CRC_CCITT=y diff --git a/arch/arm/include/debug/sirf.S b/arch/arm/include/debug/sirf.S deleted file mode 100644 index 3612c7b9cbe7..000000000000 --- a/arch/arm/include/debug/sirf.S +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-prima2/include/mach/debug-macro.S - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#define SIRF_LLUART_TXFIFO_STATUS 0x0114 -#define SIRF_LLUART_TXFIFO_DATA 0x0118 - -#define SIRF_LLUART_TXFIFO_FULL (1 << 5) - -#ifdef CONFIG_DEBUG_SIRFATLAS7_UART0 -#define SIRF_LLUART_TXFIFO_EMPTY (1 << 8) -#else -#define SIRF_LLUART_TXFIFO_EMPTY (1 << 6) -#endif - - - .macro addruart, rp, rv, tmp - ldr \rp, =CONFIG_DEBUG_UART_PHYS @ physical - ldr \rv, =CONFIG_DEBUG_UART_VIRT @ virtual - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #SIRF_LLUART_TXFIFO_DATA] - .endm - - .macro busyuart,rd,rx - .endm - - .macro waituartcts,rd,rx - .endm - - .macro waituarttxrdy,rd,rx -1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS] - tst \rd, #SIRF_LLUART_TXFIFO_EMPTY - beq 1001b - .endm - diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig deleted file mode 100644 index ea077f66372d..000000000000 --- a/arch/arm/mach-prima2/Kconfig +++ /dev/null @@ -1,48 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menuconfig ARCH_SIRF - bool "CSR SiRF" - depends on ARCH_MULTI_V7 - select ARCH_HAS_RESET_CONTROLLER - select RESET_CONTROLLER - select GENERIC_IRQ_CHIP - select GPIOLIB - select NO_IOPORT_MAP - select REGMAP - select PINCTRL - select PINCTRL_SIRF - help - Support for CSR SiRFprimaII/Marco/Polo platforms - -if ARCH_SIRF - -comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features" - -config ARCH_ATLAS6 - bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" - default y - select SIRF_IRQ - help - Support for CSR SiRFSoC ARM Cortex A9 Platform - -config ARCH_ATLAS7 - bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform" - default y - select ARM_GIC - select ATLAS7_TIMER - select HAVE_ARM_SCU if SMP - help - Support for CSR SiRFSoC ARM Cortex A7 Platform - -config ARCH_PRIMA2 - bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" - default y - select SIRF_IRQ - select ZONE_DMA - select PRIMA2_TIMER - help - Support for CSR SiRFSoC ARM Cortex A9 Platform - -config SIRF_IRQ - bool - -endif diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile deleted file mode 100644 index 0fd2763031e9..000000000000 --- a/arch/arm/mach-prima2/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-y += rstc.o -obj-y += common.o -obj-y += rtciobrg.o -obj-$(CONFIG_SUSPEND) += pm.o sleep.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o - -CFLAGS_hotplug.o += -march=armv7-a diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c deleted file mode 100644 index e2d158e331e2..000000000000 --- a/arch/arm/mach-prima2/common.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Defines machines for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/sizes.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <linux/of.h> -#include <linux/of_platform.h> -#include "common.h" - -static void __init __maybe_unused sirfsoc_init_late(void) -{ - sirfsoc_pm_init(); -} - -#ifdef CONFIG_ARCH_ATLAS6 -static const char *const atlas6_dt_match[] __initconst = { - "sirf,atlas6", - NULL -}; - -DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") - /* Maintainer: Barry Song <baohua.song@csr.com> */ - .l2c_aux_val = 0, - .l2c_aux_mask = ~0, - .init_late = sirfsoc_init_late, - .dt_compat = atlas6_dt_match, -MACHINE_END -#endif - -#ifdef CONFIG_ARCH_PRIMA2 -static const char *const prima2_dt_match[] __initconst = { - "sirf,prima2", - NULL -}; - -DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") - /* Maintainer: Barry Song <baohua.song@csr.com> */ - .l2c_aux_val = 0, - .l2c_aux_mask = ~0, - .dma_zone_size = SZ_256M, - .init_late = sirfsoc_init_late, - .dt_compat = prima2_dt_match, -MACHINE_END -#endif - -#ifdef CONFIG_ARCH_ATLAS7 -static const char *const atlas7_dt_match[] __initconst = { - "sirf,atlas7", - NULL -}; - -DT_MACHINE_START(ATLAS7_DT, "Generic ATLAS7 (Flattened Device Tree)") - /* Maintainer: Barry Song <baohua.song@csr.com> */ - .smp = smp_ops(sirfsoc_smp_ops), - .dt_compat = atlas7_dt_match, -MACHINE_END -#endif diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h deleted file mode 100644 index 3bab7e571ded..000000000000 --- a/arch/arm/mach-prima2/common.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * This file contains common function prototypes to avoid externs in the c files. - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#ifndef __MACH_PRIMA2_COMMON_H__ -#define __MACH_PRIMA2_COMMON_H__ - -#include <linux/init.h> -#include <linux/reboot.h> - -#include <asm/mach/time.h> -#include <asm/exception.h> - -extern volatile int prima2_pen_release; - -extern const struct smp_operations sirfsoc_smp_ops; -extern void sirfsoc_secondary_startup(void); -extern void sirfsoc_cpu_die(unsigned int cpu); - -extern void __init sirfsoc_of_irq_init(void); -extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs); - -#ifdef CONFIG_SUSPEND -extern int sirfsoc_pm_init(void); -#else -static inline int sirfsoc_pm_init(void) { return 0; } -#endif - -#endif diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S deleted file mode 100644 index 88ea1243942a..000000000000 --- a/arch/arm/mach-prima2/headsmp.S +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Entry of the second core for CSR Marco dual-core SMP SoCs - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/linkage.h> -#include <linux/init.h> - -/* - * SIRFSOC specific entry point for secondary CPUs. This provides - * a "holding pen" into which all secondary cores are held until we're - * ready for them to initialise. - */ -ENTRY(sirfsoc_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup -ENDPROC(sirfsoc_secondary_startup) - - .align -1: .long . - .long prima2_pen_release diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c deleted file mode 100644 index bc0d957e89ac..000000000000 --- a/arch/arm/mach-prima2/hotplug.c +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * CPU hotplug support for CSR Marco dual-core SMP SoCs - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/smp.h> - -#include <asm/smp_plat.h> -#include "common.h" - -static inline void platform_do_lowpower(unsigned int cpu) -{ - /* we put the platform to just WFI */ - for (;;) { - __asm__ __volatile__("dsb\n\t" "wfi\n\t" - : : : "memory"); - if (prima2_pen_release == cpu_logical_map(cpu)) { - /* - * OK, proper wakeup, we're done - */ - break; - } - } -} - -/* - * platform-specific code to shutdown a CPU - * - * Called with IRQs disabled - */ -void sirfsoc_cpu_die(unsigned int cpu) -{ - platform_do_lowpower(cpu); -} diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c deleted file mode 100644 index 8f7bbb57fb20..000000000000 --- a/arch/arm/mach-prima2/platsmp.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * plat smp support for CSR Marco dual-core SMP SoCs - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/delay.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <asm/page.h> -#include <asm/mach/map.h> -#include <asm/smp_plat.h> -#include <asm/smp_scu.h> -#include <asm/cacheflush.h> -#include <asm/cputype.h> - -#include "common.h" - -static void __iomem *clk_base; - -static DEFINE_SPINLOCK(boot_lock); - -/* XXX prima2_pen_release is cargo culted code - DO NOT COPY XXX */ -volatile int prima2_pen_release = -1; - -static void sirfsoc_secondary_init(unsigned int cpu) -{ - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - prima2_pen_release = -1; - smp_wmb(); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -static const struct of_device_id clk_ids[] = { - { .compatible = "sirf,atlas7-clkc" }, - {}, -}; - -static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - struct device_node *np; - - np = of_find_matching_node(NULL, clk_ids); - if (!np) - return -ENODEV; - - clk_base = of_iomap(np, 0); - if (!clk_base) - return -ENOMEM; - - /* - * write the address of secondary startup into the clkc register - * at offset 0x2bC, then write the magic number 0x3CAF5D62 to the - * clkc register at offset 0x2b8, which is what boot rom code is - * waiting for. This would wake up the secondary core from WFE - */ -#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc - __raw_writel(__pa_symbol(sirfsoc_secondary_startup), - clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); - -#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8 - __raw_writel(0x3CAF5D62, - clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); - - /* make sure write buffer is drained */ - mb(); - - spin_lock(&boot_lock); - - /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting prima2_pen_release. - * - * Note that "prima2_pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. - */ - prima2_pen_release = cpu_logical_map(cpu); - sync_cache_w(&prima2_pen_release); - - /* - * Send the secondary CPU SEV, thereby causing the boot monitor to read - * the JUMPADDR and WAKEMAGIC, and branch to the address found there. - */ - dsb_sev(); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (prima2_pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return prima2_pen_release != -1 ? -ENOSYS : 0; -} - -const struct smp_operations sirfsoc_smp_ops __initconst = { - .smp_secondary_init = sirfsoc_secondary_init, - .smp_boot_secondary = sirfsoc_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_die = sirfsoc_cpu_die, -#endif -}; diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c deleted file mode 100644 index c24bc89f320b..000000000000 --- a/arch/arm/mach-prima2/pm.c +++ /dev/null @@ -1,153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * power management entry for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/kernel.h> -#include <linux/suspend.h> -#include <linux/slab.h> -#include <linux/export.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> -#include <linux/io.h> -#include <linux/rtc/sirfsoc_rtciobrg.h> -#include <asm/outercache.h> -#include <asm/suspend.h> -#include <asm/hardware/cache-l2x0.h> - -#include "pm.h" - -/* - * suspend asm codes will access these to make DRAM become self-refresh and - * system sleep - */ -u32 sirfsoc_pwrc_base; -void __iomem *sirfsoc_memc_base; - -static void sirfsoc_set_wakeup_source(void) -{ - u32 pwr_trigger_en_reg; - pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + - SIRFSOC_PWRC_TRIGGER_EN); -#define X_ON_KEY_B (1 << 0) -#define RTC_ALARM0_B (1 << 2) -#define RTC_ALARM1_B (1 << 3) - sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B | - RTC_ALARM0_B | RTC_ALARM1_B, - sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN); -} - -static void sirfsoc_set_sleep_mode(u32 mode) -{ - u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + - SIRFSOC_PWRC_PDN_CTRL); - sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1); - sleep_mode |= mode << 1; - sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base + - SIRFSOC_PWRC_PDN_CTRL); -} - -static int sirfsoc_pre_suspend_power_off(void) -{ - u32 wakeup_entry = __pa_symbol(cpu_resume); - - sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base + - SIRFSOC_PWRC_SCRATCH_PAD1); - - sirfsoc_set_wakeup_source(); - - sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE); - - return 0; -} - -static int sirfsoc_pm_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_MEM: - sirfsoc_pre_suspend_power_off(); - - outer_disable(); - /* go zzz */ - cpu_suspend(0, sirfsoc_finish_suspend); - outer_resume(); - break; - default: - return -EINVAL; - } - return 0; -} - -static const struct platform_suspend_ops sirfsoc_pm_ops = { - .enter = sirfsoc_pm_enter, - .valid = suspend_valid_only_mem, -}; - -static const struct of_device_id pwrc_ids[] = { - { .compatible = "sirf,prima2-pwrc" }, - {} -}; - -static int __init sirfsoc_of_pwrc_init(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, pwrc_ids); - if (!np) { - pr_err("unable to find compatible sirf pwrc node in dtb\n"); - return -ENOENT; - } - - /* - * pwrc behind rtciobrg is not located in memory space - * though the property is named reg. reg only means base - * offset for pwrc. then of_iomap is not suitable here. - */ - if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base)) - panic("unable to find base address of pwrc node in dtb\n"); - - of_node_put(np); - - return 0; -} - -static const struct of_device_id memc_ids[] = { - { .compatible = "sirf,prima2-memc" }, - {} -}; - -static int sirfsoc_memc_probe(struct platform_device *op) -{ - struct device_node *np = op->dev.of_node; - - sirfsoc_memc_base = of_iomap(np, 0); - if (!sirfsoc_memc_base) - panic("unable to map memc registers\n"); - - return 0; -} - -static struct platform_driver sirfsoc_memc_driver = { - .probe = sirfsoc_memc_probe, - .driver = { - .name = "sirfsoc-memc", - .of_match_table = memc_ids, - }, -}; - -static int __init sirfsoc_memc_init(void) -{ - return platform_driver_register(&sirfsoc_memc_driver); -} - -int __init sirfsoc_pm_init(void) -{ - sirfsoc_of_pwrc_init(); - sirfsoc_memc_init(); - suspend_set_ops(&sirfsoc_pm_ops); - return 0; -} diff --git a/arch/arm/mach-prima2/pm.h b/arch/arm/mach-prima2/pm.h deleted file mode 100644 index 0aff6cb876be..000000000000 --- a/arch/arm/mach-prima2/pm.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-prima2/pm.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#ifndef _MACH_PRIMA2_PM_H_ -#define _MACH_PRIMA2_PM_H_ - -#define SIRFSOC_PWR_SLEEPFORCE 0x01 - -#define SIRFSOC_SLEEP_MODE_MASK 0x3 -#define SIRFSOC_DEEP_SLEEP_MODE 0x1 - -#define SIRFSOC_PWRC_PDN_CTRL 0x0 -#define SIRFSOC_PWRC_PON_OFF 0x4 -#define SIRFSOC_PWRC_TRIGGER_EN 0x8 -#define SIRFSOC_PWRC_PIN_STATUS 0x14 -#define SIRFSOC_PWRC_SCRATCH_PAD1 0x18 -#define SIRFSOC_PWRC_SCRATCH_PAD2 0x1C - -#ifndef __ASSEMBLY__ -extern int sirfsoc_finish_suspend(unsigned long); -#endif - -#endif - diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c deleted file mode 100644 index 9d56606ac87f..000000000000 --- a/arch/arm/mach-prima2/rstc.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * reset controller for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/kernel.h> -#include <linux/mutex.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/device.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/platform_device.h> -#include <linux/reboot.h> -#include <linux/reset-controller.h> - -#include <asm/system_misc.h> - -#define SIRFSOC_RSTBIT_NUM 64 - -static void __iomem *sirfsoc_rstc_base; -static DEFINE_MUTEX(rstc_lock); - -static int sirfsoc_reset_module(struct reset_controller_dev *rcdev, - unsigned long sw_reset_idx) -{ - u32 reset_bit = sw_reset_idx; - - if (reset_bit >= SIRFSOC_RSTBIT_NUM) - return -EINVAL; - - mutex_lock(&rstc_lock); - - /* - * Writing 1 to this bit resets corresponding block. - * Writing 0 to this bit de-asserts reset signal of the - * corresponding block. datasheet doesn't require explicit - * delay between the set and clear of reset bit. it could - * be shorter if tests pass. - */ - writel(readl(sirfsoc_rstc_base + - (reset_bit / 32) * 4) | (1 << reset_bit), - sirfsoc_rstc_base + (reset_bit / 32) * 4); - msleep(20); - writel(readl(sirfsoc_rstc_base + - (reset_bit / 32) * 4) & ~(1 << reset_bit), - sirfsoc_rstc_base + (reset_bit / 32) * 4); - - mutex_unlock(&rstc_lock); - - return 0; -} - -static struct reset_control_ops sirfsoc_rstc_ops = { - .reset = sirfsoc_reset_module, -}; - -static struct reset_controller_dev sirfsoc_reset_controller = { - .ops = &sirfsoc_rstc_ops, - .nr_resets = SIRFSOC_RSTBIT_NUM, -}; - -#define SIRFSOC_SYS_RST_BIT BIT(31) - -static void sirfsoc_restart(enum reboot_mode mode, const char *cmd) -{ - writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base); -} - -static int sirfsoc_rstc_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - sirfsoc_rstc_base = of_iomap(np, 0); - if (!sirfsoc_rstc_base) { - dev_err(&pdev->dev, "unable to map rstc cpu registers\n"); - return -ENOMEM; - } - - sirfsoc_reset_controller.of_node = np; - arm_pm_restart = sirfsoc_restart; - - if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) - reset_controller_register(&sirfsoc_reset_controller); - - return 0; -} - -static const struct of_device_id rstc_ids[] = { - { .compatible = "sirf,prima2-rstc" }, - {}, -}; - -static struct platform_driver sirfsoc_rstc_driver = { - .probe = sirfsoc_rstc_probe, - .driver = { - .name = "sirfsoc_rstc", - .of_match_table = rstc_ids, - }, -}; - -static int __init sirfsoc_rstc_init(void) -{ - return platform_driver_register(&sirfsoc_rstc_driver); -} -subsys_initcall(sirfsoc_rstc_init); diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c deleted file mode 100644 index 97c0e333e3b9..000000000000 --- a/arch/arm/mach-prima2/rtciobrg.c +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * RTC I/O Bridge interfaces for CSR SiRFprimaII/atlas7 - * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/io.h> -#include <linux/regmap.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> - -#define SIRFSOC_CPUIOBRG_CTRL 0x00 -#define SIRFSOC_CPUIOBRG_WRBE 0x04 -#define SIRFSOC_CPUIOBRG_ADDR 0x08 -#define SIRFSOC_CPUIOBRG_DATA 0x0c - -/* - * suspend asm codes will access this address to make system deepsleep - * after DRAM becomes self-refresh - */ -void __iomem *sirfsoc_rtciobrg_base; -static DEFINE_SPINLOCK(rtciobrg_lock); - -/* - * symbols without lock are only used by suspend asm codes - * and these symbols are not exported too - */ -void sirfsoc_rtc_iobrg_wait_sync(void) -{ - while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL)) - cpu_relax(); -} - -void sirfsoc_rtc_iobrg_besyncing(void) -{ - unsigned long flags; - - spin_lock_irqsave(&rtciobrg_lock, flags); - - sirfsoc_rtc_iobrg_wait_sync(); - - spin_unlock_irqrestore(&rtciobrg_lock, flags); -} -EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_besyncing); - -u32 __sirfsoc_rtc_iobrg_readl(u32 addr) -{ - sirfsoc_rtc_iobrg_wait_sync(); - - writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); - writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); - writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); - - sirfsoc_rtc_iobrg_wait_sync(); - - return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); -} - -u32 sirfsoc_rtc_iobrg_readl(u32 addr) -{ - unsigned long flags, val; - - /* TODO: add hwspinlock to sync with M3 */ - spin_lock_irqsave(&rtciobrg_lock, flags); - - val = __sirfsoc_rtc_iobrg_readl(addr); - - spin_unlock_irqrestore(&rtciobrg_lock, flags); - - return val; -} -EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_readl); - -void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr) -{ - sirfsoc_rtc_iobrg_wait_sync(); - - writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); - writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); - - writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); -} - -void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr) -{ - unsigned long flags; - - /* TODO: add hwspinlock to sync with M3 */ - spin_lock_irqsave(&rtciobrg_lock, flags); - - sirfsoc_rtc_iobrg_pre_writel(val, addr); - - writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); - - sirfsoc_rtc_iobrg_wait_sync(); - - spin_unlock_irqrestore(&rtciobrg_lock, flags); -} -EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel); - - -static int regmap_iobg_regwrite(void *context, unsigned int reg, - unsigned int val) -{ - sirfsoc_rtc_iobrg_writel(val, reg); - return 0; -} - -static int regmap_iobg_regread(void *context, unsigned int reg, - unsigned int *val) -{ - *val = (u32)sirfsoc_rtc_iobrg_readl(reg); - return 0; -} - -static struct regmap_bus regmap_iobg = { - .reg_write = regmap_iobg_regwrite, - .reg_read = regmap_iobg_regread, -}; - -/** - * devm_regmap_init_iobg(): Initialise managed register map - * - * @iobg: Device that will be interacted with - * @config: Configuration for register map - * - * The return value will be an ERR_PTR() on error or a valid pointer - * to a struct regmap. The regmap will be automatically freed by the - * device management code. - */ -struct regmap *devm_regmap_init_iobg(struct device *dev, - const struct regmap_config *config) -{ - const struct regmap_bus *bus = ®map_iobg; - - return devm_regmap_init(dev, bus, dev, config); -} -EXPORT_SYMBOL_GPL(devm_regmap_init_iobg); - -static const struct of_device_id rtciobrg_ids[] = { - { .compatible = "sirf,prima2-rtciobg" }, - {} -}; - -static int sirfsoc_rtciobrg_probe(struct platform_device *op) -{ - struct device_node *np = op->dev.of_node; - - sirfsoc_rtciobrg_base = of_iomap(np, 0); - if (!sirfsoc_rtciobrg_base) - panic("unable to map rtc iobrg registers\n"); - - return 0; -} - -static struct platform_driver sirfsoc_rtciobrg_driver = { - .probe = sirfsoc_rtciobrg_probe, - .driver = { - .name = "sirfsoc-rtciobrg", - .of_match_table = rtciobrg_ids, - }, -}; - -static int __init sirfsoc_rtciobrg_init(void) -{ - return platform_driver_register(&sirfsoc_rtciobrg_driver); -} -postcore_initcall(sirfsoc_rtciobrg_init); - -MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>"); -MODULE_AUTHOR("Barry Song <baohua.song@csr.com>"); -MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge"); -MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-prima2/sleep.S b/arch/arm/mach-prima2/sleep.S deleted file mode 100644 index d9bbc5ca39ef..000000000000 --- a/arch/arm/mach-prima2/sleep.S +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * sleep mode for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/linkage.h> -#include <asm/ptrace.h> -#include <asm/assembler.h> - -#include "pm.h" - -#define DENALI_CTL_22_OFF 0x58 -#define DENALI_CTL_112_OFF 0x1c0 - - .text - -ENTRY(sirfsoc_finish_suspend) - @ r5: mem controller - ldr r0, =sirfsoc_memc_base - ldr r5, [r0] - @ r6: pwrc base offset - ldr r0, =sirfsoc_pwrc_base - ldr r6, [r0] - @ r7: rtc iobrg controller - ldr r0, =sirfsoc_rtciobrg_base - ldr r7, [r0] - - @ Read the power control register and set the - @ sleep force bit. - add r0, r6, #SIRFSOC_PWRC_PDN_CTRL - bl __sirfsoc_rtc_iobrg_readl - orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE - add r1, r6, #SIRFSOC_PWRC_PDN_CTRL - bl sirfsoc_rtc_iobrg_pre_writel - mov r1, #0x1 - - @ read the MEM ctl register and set the self - @ refresh bit - - ldr r2, [r5, #DENALI_CTL_22_OFF] - orr r2, r2, #0x1 - - @ Following code has to run from cache since - @ the RAM is going to self refresh mode - .align 5 - str r2, [r5, #DENALI_CTL_22_OFF] - -1: - ldr r4, [r5, #DENALI_CTL_112_OFF] - tst r4, #0x1 - bne 1b - - @ write SLEEPFORCE through rtc iobridge - - str r1, [r7] - @ wait rtc io bridge sync -1: - ldr r3, [r7] - tst r3, #0x01 - bne 1b - b . |