diff options
| -rw-r--r-- | arch/arm/mach-omap2/clkt_clksel.c | 238 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clkt_dpll.c | 50 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clkt_iclk.c | 41 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 784 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clock.h | 221 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clock_common_data.c | 20 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clockdomain.c | 4 |
7 files changed, 2 insertions, 1356 deletions
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 03ceb2efd532..0ec9f6fdf046 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -41,11 +41,7 @@ #include <linux/kernel.h> #include <linux/errno.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/io.h> #include <linux/bug.h> @@ -62,11 +58,7 @@ * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ -#ifdef CONFIG_COMMON_CLK static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, -#else -static const struct clksel *_get_clksel_by_parent(struct clk *clk, -#endif struct clk *src_clk) { const struct clksel *clks; @@ -81,11 +73,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", -#ifdef CONFIG_COMMON_CLK __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); -#else - __clk_get_name(clk), __clk_get_name(src_clk)); -#endif return NULL; } @@ -93,66 +81,6 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, } /** - * _get_div_and_fieldval() - find the new clksel divisor and field value to use - * @src_clk: planned new parent struct clk * - * @clk: struct clk * that is being reparented - * @field_val: pointer to a u32 to contain the register data for the divisor - * - * Given an intended new parent struct clk * @src_clk, and the struct - * clk * @clk to the clock that is being reparented, find the - * appropriate rate divisor for the new clock (returned as the return - * value), and the corresponding register bitfield data to program to - * reach that divisor (returned in the u32 pointed to by @field_val). - * Returns 0 on error, or returns the newly-selected divisor upon - * success (in this latter case, the corresponding register bitfield - * value is passed back in the variable pointed to by @field_val) - */ -#ifndef CONFIG_COMMON_CLK -static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, - u32 *field_val) -{ - const struct clksel *clks; - const struct clksel_rate *clkr, *max_clkr = NULL; - u8 max_div = 0; - - clks = _get_clksel_by_parent(clk, src_clk); - if (!clks) - return 0; - - /* - * Find the highest divisor (e.g., the one resulting in the - * lowest rate) to use as the default. This should avoid - * clock rates that are too high for the device. XXX A better - * solution here would be to try to determine if there is a - * divisor matching the original clock rate before the parent - * switch, and if it cannot be found, to fall back to the - * highest divisor. - */ - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->div > max_div) { - max_div = clkr->div; - max_clkr = clkr; - } - } - - if (max_div == 0) { - /* This indicates an error in the clksel data */ - WARN(1, "clock: %s: could not find divisor for parent %s\n", - __clk_get_name(clk), - __clk_get_name(__clk_get_parent(src_clk))); - return 0; - } - - *field_val = max_clkr->val; - - return max_div; -} -#endif - -/** * _write_clksel_reg() - program a clock's clksel register in hardware * @clk: struct clk * to program * @v: clksel bitfield value to program (with LSB at bit 0) @@ -165,11 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, * take into account any time the hardware might take to switch the * clock source. */ -#ifdef CONFIG_COMMON_CLK static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) -#else -static void _write_clksel_reg(struct clk *clk, u32 field_val) -#endif { u32 v; @@ -192,21 +116,13 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val) * before calling. Returns 0 on error or returns the actual integer divisor * upon success. */ -#ifdef CONFIG_COMMON_CLK static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) -#else -static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) -#endif { const struct clksel *clks; const struct clksel_rate *clkr; struct clk *parent; -#ifdef CONFIG_COMMON_CLK parent = __clk_get_parent(clk->hw.clk); -#else - parent = __clk_get_parent(clk); -#endif clks = _get_clksel_by_parent(clk, parent); if (!clks) @@ -223,12 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", -#ifdef CONFIG_COMMON_CLK __clk_get_name(clk->hw.clk), field_val, __clk_get_name(parent)); -#else - __clk_get_name(clk), field_val, __clk_get_name(parent)); -#endif return 0; } @@ -245,11 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. */ -#ifdef CONFIG_COMMON_CLK static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) -#else -static u32 _divisor_to_clksel(struct clk *clk, u32 div) -#endif { const struct clksel *clks; const struct clksel_rate *clkr; @@ -258,11 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) /* should never happen */ WARN_ON(div == 0); -#ifdef CONFIG_COMMON_CLK parent = __clk_get_parent(clk->hw.clk); -#else - parent = __clk_get_parent(clk); -#endif clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -277,12 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) if (!clkr->div) { pr_err("clock: %s: could not find divisor %d for parent %s\n", -#ifdef CONFIG_COMMON_CLK __clk_get_name(clk->hw.clk), div, __clk_get_name(parent)); -#else - __clk_get_name(clk), div, __clk_get_name(parent)); -#endif return ~0; } @@ -297,11 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ -#ifdef CONFIG_COMMON_CLK static u32 _read_divisor(struct clk_hw_omap *clk) -#else -static u32 _read_divisor(struct clk *clk) -#endif { u32 v; @@ -329,12 +225,8 @@ static u32 _read_divisor(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ -#ifdef CONFIG_COMMON_CLK u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, unsigned long target_rate, -#else -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, -#endif u32 *new_div) { unsigned long test_rate; @@ -345,13 +237,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, unsigned long parent_rate; const char *clk_name; -#ifdef CONFIG_COMMON_CLK parent = __clk_get_parent(clk->hw.clk); clk_name = __clk_get_name(clk->hw.clk); -#else - parent = __clk_get_parent(clk); - clk_name = __clk_get_name(clk); -#endif parent_rate = __clk_get_rate(parent); if (!clk->clksel || !clk->clksel_mask) @@ -402,7 +289,6 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, * (i.e., those used in struct clk field function pointers, etc.) */ -#ifdef CONFIG_COMMON_CLK /** * omap2_clksel_find_parent_index() - return the array index of the current * hardware parent of @hw @@ -457,62 +343,6 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) return ret; } -#else - -/** - * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr - * @clk: OMAP clock struct ptr to use - * - * Given a pointer @clk to a source-selectable struct clk, read the - * hardware register and determine what its parent is currently set - * to. Update @clk's .parent field with the appropriate clk ptr. No - * return value. - */ -void omap2_init_clksel_parent(struct clk *clk) -{ - const struct clksel *clks; - const struct clksel_rate *clkr; - u32 r, found = 0; - struct clk *parent; - const char *clk_name; - - if (!clk->clksel || !clk->clksel_mask) - return; - - parent = __clk_get_parent(clk); - clk_name = __clk_get_name(clk); - - r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; - r >>= __ffs(clk->clksel_mask); - - for (clks = clk->clksel; clks->parent && !found; clks++) { - for (clkr = clks->rates; clkr->div && !found; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->val == r) { - if (parent != clks->parent) { - pr_debug("clock: %s: inited parent to %s (was %s)\n", - clk_name, - __clk_get_name(clks->parent), - ((parent) ? - __clk_get_name(parent) : - "NULL")); - clk_reparent(clk, clks->parent); - } - found = 1; - } - } - } - - /* This indicates a data error */ - WARN(!found, "clock: %s: init parent: could not find regval %0x\n", - clk_name, r); - - return; -} - -#endif /** * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field @@ -523,7 +353,6 @@ void omap2_init_clksel_parent(struct clk *clk) * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) { unsigned long rate; @@ -544,26 +373,6 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) return rate; } -#else -unsigned long omap2_clksel_recalc(struct clk *clk) -{ - unsigned long rate; - u32 div = 0; - struct clk *parent; - - div = _read_divisor(clk); - if (div == 0) - return __clk_get_rate(clk); - - parent = __clk_get_parent(clk); - rate = __clk_get_rate(parent) / div; - - pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", - __clk_get_name(clk), rate, div); - - return rate; -} -#endif /** * omap2_clksel_round_rate() - find rounded rate for the given clock and rate @@ -576,15 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ -#ifdef CONFIG_COMMON_CLK long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) -{ -#endif u32 new_div; return omap2_clksel_round_rate_div(clk, target_rate, &new_div); @@ -605,15 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) * is changed, they will all be affected without any notification. * Returns -EINVAL upon error, or 0 upon success. */ -#ifdef CONFIG_COMMON_CLK int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) -{ -#endif u32 field_val, validrate, new_div = 0; if (!clk->clksel || !clk->clksel_mask) @@ -629,15 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) _write_clksel_reg(clk, field_val); -#ifdef CONFIG_COMMON_CLK pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), __clk_get_rate(hw->clk)); -#else - pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), - __clk_get_rate(clk)); - - clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; -#endif return 0; } @@ -662,7 +454,6 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) * affected without any notification. Returns -EINVAL upon error, or * 0 upon success. */ -#ifdef CONFIG_COMMON_CLK int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); @@ -673,32 +464,3 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) _write_clksel_reg(clk, field_val); return 0; } -#else -int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) -{ - u32 field_val = 0; - u32 parent_div; - - if (!clk->clksel || !clk->clksel_mask) - return -EINVAL; - - parent_div = _get_div_and_fieldval(new_parent, clk, &field_val); - if (!parent_div) - return -EINVAL; - _write_clksel_reg(clk, field_val); - - clk_reparent(clk, new_parent); - - /* CLKSEL clocks follow their parents' rates, divided by a divisor */ - clk->rate = __clk_get_rate(new_parent); - - if (parent_div > 0) - __clk_get_rate(clk) /= parent_div; - pr_debug("clock: %s: set parent to %s (new rate %ld)\n", - __clk_get_name(clk), - __clk_get_name(__clk_get_parent(clk)), - __clk_get_rate(clk)); - - return 0; -} -#endif diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index f343389fc6e8..924c230f8948 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -16,11 +16,7 @@ #include <linux/kernel.h> #include <linux/errno.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/io.h> #include <asm/div64.h> @@ -80,11 +76,7 @@ * (assuming that it is counting N upwards), or -2 if the enclosing loop * should skip to the next iteration (again assuming N is increasing). */ -#ifdef CONFIG_COMMON_CLK static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) -#else -static int _dpll_test_fint(struct clk *clk, u8 n) -#endif { struct dpll_data *dd; long fint, fint_min, fint_max; @@ -93,11 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data; /* DPLL divider must result in a valid jitter correction val */ -#ifdef CONFIG_COMMON_CLK fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; -#else - fint = __clk_get_rate(__clk_get_parent(clk)) / n; -#endif if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -198,24 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, } /* Public functions */ -#ifdef CONFIG_COMMON_CLK u8 omap2_init_dpll_parent(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -void omap2_init_dpll_parent(struct clk *clk) -{ -#endif u32 v; struct dpll_data *dd; dd = clk->dpll_data; if (!dd) -#ifdef CONFIG_COMMON_CLK return -EINVAL; -#else - return; -#endif v = __raw_readl(dd->control_reg); v &= dd->enable_mask; @@ -225,34 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) -#ifdef CONFIG_COMMON_CLK return 1; -#else - clk_reparent(clk, dd->clk_bypass); -#endif } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) -#ifdef CONFIG_COMMON_CLK return 1; -#else - clk_reparent(clk, dd->clk_bypass); -#endif } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) -#ifdef CONFIG_COMMON_CLK return 1; -#else - clk_reparent(clk, dd->clk_bypass); -#endif } -#ifdef CONFIG_COMMON_CLK return 0; -#else - return; -#endif } /** @@ -269,11 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * if the clock @clk is not a DPLL. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) -#else -u32 omap2_get_dpll_rate(struct clk *clk) -#endif { long long dpll_clk; u32 dpll_mult, dpll_div, v; @@ -329,15 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk) * (expensive) function again. Returns ~0 if the target rate cannot * be rounded, or the rounded rate upon success. */ -#ifdef CONFIG_COMMON_CLK long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) -{ -#endif int m, n, r, scaled_max_m; unsigned long scaled_rt_rp; unsigned long new_rate = 0; @@ -351,11 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd = clk->dpll_data; ref_rate = __clk_get_rate(dd->clk_ref); -#ifdef CONFIG_COMMON_CLK clk_name = __clk_get_name(hw->clk); -#else - clk_name = __clk_get_name(clk); -#endif pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", clk_name, target_rate); diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index 650c8c77a573..f10eb03ce3e2 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -11,11 +11,7 @@ #undef DEBUG #include <linux/kernel.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/io.h> @@ -27,11 +23,7 @@ /* Private functions */ /* XXX */ -#ifdef CONFIG_COMMON_CLK void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) -#else -void omap2_clkt_iclk_allow_idle(struct clk *clk) -#endif { u32 v, r; @@ -43,11 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk) } /* XXX */ -#ifdef CONFIG_COMMON_CLK void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) -#else -void omap2_clkt_iclk_deny_idle(struct clk *clk) -#endif { u32 v, r; @@ -60,7 +48,6 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk) /* Public data */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_iclk = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, @@ -72,34 +59,6 @@ const struct clk_hw_omap_ops clkhwops_iclk_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_omap2_iclk_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -const struct clkops clkops_omap2_iclk_dflt = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -const struct clkops clkops_omap2_iclk_idle_only = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -const struct clkops clkops_omap2_mdmclk_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -#endif diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 744e6eb17b26..e4ec3a69ee2e 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -20,11 +20,7 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/delay.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/io.h> #include <linux/bitops.h> @@ -59,13 +55,6 @@ u16 cpu_mask; */ static bool clkdm_control = true; -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -#ifndef CONFIG_COMMON_CLK -static DEFINE_SPINLOCK(clockfw_lock); -#endif - -#ifdef CONFIG_COMMON_CLK static LIST_HEAD(clk_hw_omap_clocks); /* @@ -88,7 +77,6 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, return parent_rate / oclk->fixed_div; } -#endif /* * OMAP2+ specific clock functions @@ -140,11 +128,7 @@ static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest, * belong in the clock code and will be moved in the medium term to * module-dependent code. No return value. */ -#ifdef CONFIG_COMMON_CLK static void _omap2_module_wait_ready(struct clk_hw_omap *clk) -#else -static void _omap2_module_wait_ready(struct clk *clk) -#endif { void __iomem *companion_reg, *idlest_reg; u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; @@ -163,11 +147,7 @@ static void _omap2_module_wait_ready(struct clk *clk) if (r) { /* IDLEST register not in the CM module */ _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, -#ifdef CONFIG_COMMON_CLK __clk_get_name(clk->hw.clk)); -#else - clk->name); -#endif } else { cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); }; @@ -183,25 +163,16 @@ static void _omap2_module_wait_ready(struct clk *clk) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ -#ifdef CONFIG_COMMON_CLK void omap2_init_clk_clkdm(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -void omap2_init_clk_clkdm(struct clk *clk) -{ -#endif struct clockdomain *clkdm; const char *clk_name; if (!clk->clkdm_name) return; -#ifdef CONFIG_COMMON_CLK clk_name = __clk_get_name(hw->clk); -#else - clk_name = __clk_get_name(clk); -#endif clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { @@ -248,11 +219,7 @@ void __init omap2_clk_disable_clkdm_control(void) * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -#ifdef CONFIG_COMMON_CLK void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, -#else -void omap2_clk_dflt_find_companion(struct clk *clk, -#endif void __iomem **other_reg, u8 *other_bit) { u32 r; @@ -281,11 +248,7 @@ void omap2_clk_dflt_find_companion(struct clk *clk, * register address ID (e.g., that CM_FCLKEN2 corresponds to * CM_IDLEST2). This is not true for all modules. No return value. */ -#ifdef CONFIG_COMMON_CLK void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, -#else -void omap2_clk_dflt_find_idlest(struct clk *clk, -#endif void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) { u32 r; @@ -308,7 +271,6 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, } -#ifdef CONFIG_COMMON_CLK /** * omap2_dflt_clk_enable - enable a clock in the hardware * @hw: struct clk_hw * of the clock to enable @@ -605,238 +567,6 @@ const struct clk_hw_omap_ops clkhwops_wait = { .find_idlest = omap2_clk_dflt_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -int omap2_dflt_clk_enable(struct clk *clk) -{ - u32 v; - - if (unlikely(clk->enable_reg == NULL)) { - pr_err("clock.c: Enable for %s without enable code\n", - clk->name); - return 0; /* REVISIT: -EINVAL */ - } - - v = __raw_readl(clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v &= ~(1 << clk->enable_bit); - else - v |= (1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); - v = __raw_readl(clk->enable_reg); /* OCP barrier */ - - if (clk->ops->find_idlest) - _omap2_module_wait_ready(clk); - - return 0; -} - -void omap2_dflt_clk_disable(struct clk *clk) -{ - u32 v; - - if (!clk->enable_reg) { - /* - * 'Independent' here refers to a clock which is not - * controlled by its parent. - */ - pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name); - return; - } - - v = __raw_readl(clk->enable_reg); - if (clk->flags & INVERT_ENABLE) - v |= (1 << clk->enable_bit); - else - v &= ~(1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); - /* No OCP barrier needed here since it is a disable operation */ -} - -const struct clkops clkops_omap2_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -}; - -const struct clkops clkops_omap2_dflt = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, -}; - -/** - * omap2_clk_disable - disable a clock, if the system is not using it - * @clk: struct clk * to disable - * - * Decrements the usecount on struct clk @clk. If there are no users - * left, call the clkops-specific clock disable function to disable it - * in hardware. If the clock is part of a clockdomain (which they all - * should be), request that the clockdomain be disabled. (It too has - * a usecount, and so will not be disabled in the hardware until it no - * longer has any users.) If the clock has a parent clock (most of - * them do), then call ourselves, recursing on the parent clock. This - * can cause an entire branch of the clock tree to be powered off by - * simply disabling one clock. Intended to be called with the clockfw_lock - * spinlock held. No return value. - */ -void omap2_clk_disable(struct clk *clk) -{ - if (clk->usecount == 0) { - WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name); - return; - } - - pr_debug("clock: %s: decrementing usecount\n", clk->name); - - clk->usecount--; - - if (clk->usecount > 0) - return; - - pr_debug("clock: %s: disabling in hardware\n", clk->name); - - if (clk->ops && clk->ops->disable) { - trace_clock_disable(clk->name, 0, smp_processor_id()); - clk->ops->disable(clk); - } - - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); - - if (clk->parent) - omap2_clk_disable(clk->parent); -} - -/** - * omap2_clk_enable - request that the system enable a clock - * @clk: struct clk * to enable - * - * Increments the usecount on struct clk @clk. If there were no users - * previously, then recurse up the clock tree, enabling all of the - * clock's parents and all of the parent clockdomains, and finally, - * enabling @clk's clockdomain, and @clk itself. Intended to be - * called with the clockfw_lock spinlock held. Returns 0 upon success - * or a negative error code upon failure. - */ -int omap2_clk_enable(struct clk *clk) -{ - int ret; - - pr_debug("clock: %s: incrementing usecount\n", clk->name); - - clk->usecount++; - - if (clk->usecount > 1) - return 0; - - pr_debug("clock: %s: enabling in hardware\n", clk->name); - - if (clk->parent) { - ret = omap2_clk_enable(clk->parent); - if (ret) { - WARN(1, "clock: %s: could not enable parent %s: %d\n", - clk->name, clk->parent->name, ret); - goto oce_err1; - } - } - - if (clkdm_control && clk->clkdm) { - ret = clkdm_clk_enable(clk->clkdm, clk); - if (ret) { - WARN(1, "clock: %s: could not enable clockdomain %s: %d\n", - clk->name, clk->clkdm->name, ret); - goto oce_err2; - } - } - - if (clk->ops && clk->ops->enable) { - trace_clock_enable(clk->name, 1, smp_processor_id()); - ret = clk->ops->enable(clk); - if (ret) { - WARN(1, "clock: %s: could not enable: %d\n", - clk->name, ret); - goto oce_err3; - } - } - - return 0; - -oce_err3: - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); -oce_err2: - if (clk->parent) - omap2_clk_disable(clk->parent); -oce_err1: - clk->usecount--; - - return ret; -} - -/* Given a clock and a rate apply a clock specific rounding function */ -long omap2_clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk->round_rate) - return clk->round_rate(clk, rate); - - return clk->rate; -} - -/* Set the clock rate for a clock source */ -int omap2_clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); - - /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ - if (clk->set_rate) { - trace_clock_set_rate(clk->name, rate, smp_processor_id()); - ret = clk->set_rate(clk, rate); - } - - return ret; -} - -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) -{ - if (!clk->clksel) - return -EINVAL; - - if (clk->parent == new_parent) - return 0; - - return omap2_clksel_set_parent(clk, new_parent); -} - -/* - * OMAP2+ clock reset and init functions - */ - -#ifdef CONFIG_OMAP_RESET_CLOCKS -void omap2_clk_disable_unused(struct clk *clk) -{ - u32 regval32, v; - - v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; - - regval32 = __raw_readl(clk->enable_reg); - if ((regval32 & (1 << clk->enable_bit)) == v) - return; - - pr_debug("Disabling unused clock \"%s\"\n", clk->name); - if (cpu_is_omap34xx()) { - omap2_clk_enable(clk); - omap2_clk_disable(clk); - } else { - clk->ops->disable(clk); - } - if (clk->clkdm != NULL) - pwrdm_state_switch(clk->clkdm->pwrdm.ptr); -} -#endif - -#endif /* CONFIG_COMMON_CLK */ /** * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument @@ -874,10 +604,6 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) } calibrate_delay(); -#ifndef CONFIG_COMMON_CLK - recalculate_root_clocks(); -#endif - clk_put(mpurate_ck); return 0; @@ -921,513 +647,3 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(core_ck) / 1000000), (clk_get_rate(mpu_ck) / 1000000)); } - -#ifndef CONFIG_COMMON_CLK -/* Common data */ -int clk_enable(struct clk *clk) -{ - unsigned long flags; - int ret; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap2_clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - pr_err("Trying disable clock %s with 0 usecount\n", - clk->name); - WARN_ON(1); - goto out; - } - - omap2_clk_disable(clk); - -out: - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long flags; - unsigned long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = clk->rate; - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_get_rate); - -/* - * Optional clock functions defined in include/linux/clk.h - */ - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap2_clk_round_rate(clk, rate); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = omap2_clk_set_rate(clk, rate); - if (ret == 0) - propagate_rate(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - ret = omap2_clk_set_parent(clk, parent); - if (ret == 0) - propagate_rate(clk); - } else { - ret = -EBUSY; - } - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -/* - * OMAP specific clock functions shared between omap1 and omap2 - */ - -int __initdata mpurate; - -/* - * By default we use the rate set by the bootloader. - * You can override this with mpurate= cmdline option. - */ -static int __init omap_clk_setup(char *str) -{ - get_option(&str, &mpurate); - - if (!mpurate) - return 1; - - if (mpurate < 1000) - mpurate *= 1000000; - - return 1; -} -__setup("mpurate=", omap_clk_setup); - -/* Used for clocks that always have same value as the parent clock */ -unsigned long followparent_recalc(struct clk *clk) -{ - return clk->parent->rate; -} - -/* - * Used for clocks that have the same value as the parent clock, - * divided by some factor - */ -unsigned long omap_fixed_divisor_recalc(struct clk *clk) -{ - WARN_ON(!clk->fixed_div); - - return clk->parent->rate / clk->fixed_div; -} - -void clk_reparent(struct clk *child, struct clk *parent) -{ - list_del_init(&child->sibling); - if (parent) - list_add(&child->sibling, &parent->children); - child->parent = parent; - - /* now do the debugfs renaming to reattach the child - to the proper parent */ -} - -/* Propagate rate to children */ -void propagate_rate(struct clk *tclk) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &tclk->children, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -static LIST_HEAD(root_clks); - -/** - * recalculate_root_clocks - recalculate and propagate all root clocks - * - * Recalculates all root clocks (clocks with no parent), which if the - * clock's .recalc is set correctly, should also propagate their rates. - * Called at init. - */ -void recalculate_root_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &root_clks, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -/** - * clk_preinit - initialize any fields in the struct clk before clk init - * @clk: struct clk * to initialize - * - * Initialize any struct clk fields needed before normal clk initialization - * can run. No return value. - */ -void clk_preinit(struct clk *clk) -{ - INIT_LIST_HEAD(&clk->children); -} - -int clk_register(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - /* - * trap out already registered clocks - */ - if (clk->node.next || clk->node.prev) - return 0; - - mutex_lock(&clocks_mutex); - if (clk->parent) - list_add(&clk->sibling, &clk->parent->children); - else - list_add(&clk->sibling, &root_clks); - - list_add(&clk->node, &clocks); - if (clk->init) - clk->init(clk); - mutex_unlock(&clocks_mutex); - - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - - mutex_lock(&clocks_mutex); - list_del(&clk->sibling); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -void clk_enable_init_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &clocks, node) - if (clkp->flags & ENABLE_ON_INIT) - clk_enable(clkp); -} - -/** - * omap_clk_get_by_name - locate OMAP struct clk by its name - * @name: name of the struct clk to locate - * - * Locate an OMAP struct clk by its name. Assumes that struct clk - * names are unique. Returns NULL if not found or a pointer to the - * struct clk if found. - */ -struct clk *omap_clk_get_by_name(const char *name) -{ - struct clk *c; - struct clk *ret = NULL; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(c, &clocks, node) { - if (!strcmp(c->name, name)) { - ret = c; - break; - } - } - - mutex_unlock(&clocks_mutex); - - return ret; -} - -int omap_clk_enable_autoidle_all(void) -{ - struct clk *c; - unsigned long flags; - - spin_lock_irqsave(&clockfw_lock, flags); - - list_for_each_entry(c, &clocks, node) - if (c->ops->allow_idle) - c->ops->allow_idle(c); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} - -int omap_clk_disable_autoidle_all(void) -{ - struct clk *c; - unsigned long flags; - - spin_lock_irqsave(&clockfw_lock, flags); - - list_for_each_entry(c, &clocks, node) - if (c->ops->deny_idle) - c->ops->deny_idle(c); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} - -/* - * Low level helpers - */ -static int clkll_enable_null(struct clk *clk) -{ - return 0; -} - -static void clkll_disable_null(struct clk *clk) -{ -} - -const struct clkops clkops_null = { - .enable = clkll_enable_null, - .disable = clkll_disable_null, -}; - -/* - * Dummy clock - * - * Used for clock aliases that are needed on some OMAPs, but not others - */ -struct clk dummy_ck = { - .name = "dummy", - .ops = &clkops_null, -}; - -/* - * - */ - -#ifdef CONFIG_OMAP_RESET_CLOCKS -/* - * Disable any unused clocks left on by the bootloader - */ -static int __init clk_disable_unused(void) -{ - struct clk *ck; - unsigned long flags; - - pr_info("clock: disabling unused clocks to save power\n"); - - spin_lock_irqsave(&clockfw_lock, flags); - list_for_each_entry(ck, &clocks, node) { - if (ck->ops == &clkops_null) - continue; - - if (ck->usecount > 0 || !ck->enable_reg) - continue; - - omap2_clk_disable_unused(ck); - } - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -late_initcall(clk_disable_unused); -late_initcall(omap_clk_enable_autoidle_all); -#endif - -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) -/* - * debugfs support to trace clock tree hierarchy and attributes - */ - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -static struct dentry *clk_debugfs_root; - -static int clk_dbg_show_summary(struct seq_file *s, void *unused) -{ - struct clk *c; - struct clk *pa; - - mutex_lock(&clocks_mutex); - seq_printf(s, "%-30s %-30s %-10s %s\n", - "clock-name", "parent-name", "rate", "use-count"); - - list_for_each_entry(c, &clocks, node) { - pa = c->parent; - seq_printf(s, "%-30s %-30s %-10lu %d\n", - c->name, pa ? pa->name : "none", c->rate, - c->usecount); - } - mutex_unlock(&clocks_mutex); - - return 0; -} - -static int clk_dbg_open(struct inode *inode, struct file *file) -{ - return single_open(file, clk_dbg_show_summary, inode->i_private); -} - -static const struct file_operations debug_clock_fops = { - .open = clk_dbg_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int clk_debugfs_register_one(struct clk *c) -{ - int err; - struct dentry *d; - struct clk *pa = c->parent; - - d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root); - if (!d) - return -ENOMEM; - c->dent = d; - - d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount); - if (!d) { - err = -ENOMEM; - goto err_out; - } - d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); - if (!d) { - err = -ENOMEM; - goto err_out; - } - d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); - if (!d) { - err = -ENOMEM; - goto err_out; - } - return 0; - -err_out: - debugfs_remove_recursive(c->dent); - return err; -} - -static int clk_debugfs_register(struct clk *c) -{ - int err; - struct clk *pa = c->parent; - - if (pa && !pa->dent) { - err = clk_debugfs_register(pa); - if (err) - return err; - } - - if (!c->dent) { - err = clk_debugfs_register_one(c); - if (err) - return err; - } - return 0; -} - -static int __init clk_debugfs_init(void) -{ - struct clk *c; - struct dentry *d; - int err; - - d = debugfs_create_dir("clock", NULL); - if (!d) - return -ENOMEM; - clk_debugfs_root = d; - - list_for_each_entry(c, &clocks, node) { - err = clk_debugfs_register(c); - if (err) - goto err_out; - } - - d = debugfs_create_file("summary", S_IRUGO, - d, NULL, &debug_clock_fops); - if (!d) - return -ENOMEM; - - return 0; -err_out: - debugfs_remove_recursive(clk_debugfs_root); - return err; -} -late_initcall(clk_debugfs_init); - -#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ -#endif /* CONFIG_COMMON_CLK */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index baeaff229506..9917f793c3b6 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -20,6 +20,7 @@ #include <linux/list.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> struct omap_clk { u16 cpu; @@ -52,9 +53,6 @@ struct omap_clk { #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) -#ifdef CONFIG_COMMON_CLK -#include <linux/clk-provider.h> - struct clockdomain; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) @@ -134,48 +132,6 @@ struct clockdomain; }; \ DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); - -#else - -struct module; -struct clk; -struct clockdomain; - -/* Temporary, needed during the common clock framework conversion */ -#define __clk_get_name(clk) (clk->name) -#define __clk_get_parent(clk) (clk->parent) -#define __clk_get_rate(clk) (clk->rate) - -/** - * struct clkops - some clock function pointers - * @enable: fn ptr that enables the current clock in hardware - * @disable: fn ptr that enables the current clock in hardware - * @find_idlest: function returning the IDLEST register for the clock's IP blk - * @find_companion: function returning the "companion" clk reg for the clock - * @allow_idle: fn ptr that enables autoidle for the current clock in hardware - * @deny_idle: fn ptr that disables autoidle for the current clock in hardware - * - * A "companion" clk is an accompanying clock to the one being queried - * that must be enabled for the IP module connected to the clock to - * become accessible by the hardware. Neither @find_idlest nor - * @find_companion should be needed; that information is IP - * block-specific; the hwmod code has been created to handle this, but - * until hwmod data is ready and drivers have been converted to use PM - * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and - * @find_companion must, unfortunately, remain. - */ -struct clkops { - int (*enable)(struct clk *); - void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, - u8 *, u8 *); - void (*find_companion)(struct clk *, void __iomem **, - u8 *); - void (*allow_idle)(struct clk *); - void (*deny_idle)(struct clk *); -}; -#endif - /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) @@ -314,7 +270,6 @@ struct dpll_data { #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ #define CLOCK_CLKOUTX2 (1 << 5) -#ifdef CONFIG_COMMON_CLK /** * struct clk_hw_omap - OMAP struct clk * @node: list_head connecting this clock into the full clock list @@ -367,114 +322,6 @@ struct clk_hw_omap_ops { unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, unsigned long parent_rate); -#else -/** - * struct clk - OMAP struct clk - * @node: list_head connecting this clock into the full clock list - * @ops: struct clkops * for this clock - * @name: the name of the clock in the hardware (used in hwmod data and debug) - * @parent: pointer to this clock's parent struct clk - * @children: list_head connecting to the child clks' @sibling list_heads - * @sibling: list_head connecting this clk to its parent clk's @children - * @rate: current clock rate - * @enable_reg: register to write to enable the clock (see @enable_bit) - * @recalc: fn ptr that returns the clock's current rate - * @set_rate: fn ptr that can change the clock's current rate - * @round_rate: fn ptr that can round the clock's current rate - * @init: fn ptr to do clock-specific initialization - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) - * @usecount: number of users that have requested this clock to be enabled - * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div - * @flags: see "struct clk.flags possibilities" above - * @clksel_reg: for clksel clks, register va containing src/divisor select - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector - * @clksel: for clksel clks, pointer to struct clksel for this clock - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock - * @clkdm_name: clockdomain name that this clock is contained in - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) - * @src_offset: bitshift for source selection bitfield (OMAP1 only) - * - * XXX @rate_offset, @src_offset should probably be removed and OMAP1 - * clock code converted to use clksel. - * - * XXX @usecount is poorly named. It should be "enable_count" or - * something similar. "users" in the description refers to kernel - * code (core code or drivers) that have called clk_enable() and not - * yet called clk_disable(); the usecount of parent clocks is also - * incremented by the clock code when clk_enable() is called on child - * clocks and decremented by the clock code when clk_disable() is - * called on child clocks. - * - * XXX @clkdm, @usecount, @children, @sibling should be marked for - * internal use only. - * - * @children and @sibling are used to optimize parent-to-child clock - * tree traversals. (child-to-parent traversals use @parent.) - * - * XXX The notion of the clock's current rate probably needs to be - * separated from the clock's target rate. - */ -struct clk { - struct list_head node; - const struct clkops *ops; - const char *name; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ - unsigned long rate; - void __iomem *enable_reg; - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - void (*init)(struct clk *); - u8 enable_bit; - s8 usecount; - u8 fixed_div; - u8 flags; - void __iomem *clksel_reg; - u32 clksel_mask; - const struct clksel *clksel; - struct dpll_data *dpll_data; - const char *clkdm_name; - struct clockdomain *clkdm; -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ -#endif -}; - -struct clk_functions { - int (*clk_enable)(struct clk *clk); - void (*clk_disable)(struct clk *clk); - long (*clk_round_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_parent)(struct clk *clk, struct clk *parent); - void (*clk_allow_idle)(struct clk *clk); - void (*clk_deny_idle)(struct clk *clk); - void (*clk_disable_unused)(struct clk *clk); -}; - -extern int mpurate; - -extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_preinit(struct clk *clk); -extern int clk_register(struct clk *clk); -extern void clk_reparent(struct clk *child, struct clk *parent); -extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk); -extern void recalculate_root_clocks(void); -extern unsigned long followparent_recalc(struct clk *clk); -extern void clk_enable_init_clocks(void); -unsigned long omap_fixed_divisor_recalc(struct clk *clk); -extern struct clk *omap_clk_get_by_name(const char *name); -extern int omap_clk_enable_autoidle_all(void); -extern int omap_clk_disable_autoidle_all(void); - -extern const struct clkops clkops_null; - -extern struct clk dummy_ck; - -#endif /* CONFIG_COMMON_CLK */ /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 @@ -505,15 +352,6 @@ extern struct clk dummy_ck; /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 -#ifndef CONFIG_COMMON_CLK -int omap2_clk_enable(struct clk *clk); -void omap2_clk_disable(struct clk *clk); -long omap2_clk_round_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); -#endif /* CONFIG_COMMON_CLK */ - -#ifdef CONFIG_COMMON_CLK long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); @@ -534,37 +372,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); -#else -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap3_dpll_recalc(struct clk *clk); -unsigned long omap3_clkoutx2_recalc(struct clk *clk); -void omap3_dpll_allow_idle(struct clk *clk); -void omap3_dpll_deny_idle(struct clk *clk); -u32 omap3_dpll_autoidle_read(struct clk *clk); -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); -int omap3_noncore_dpll_enable(struct clk *clk); -void omap3_noncore_dpll_disable(struct clk *clk); -int omap4_dpllmx_gatectrl_read(struct clk *clk); -void omap4_dpllmx_allow_gatectrl(struct clk *clk); -void omap4_dpllmx_deny_gatectrl(struct clk *clk); -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); -#endif -#ifdef CONFIG_OMAP_RESET_CLOCKS -void omap2_clk_disable_unused(struct clk *clk); -#else -#define omap2_clk_disable_unused NULL -#endif -#ifdef CONFIG_COMMON_CLK void omap2_init_clk_clkdm(struct clk_hw *clk); -#else -void omap2_init_clk_clkdm(struct clk *clk); -#endif void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ -#ifdef CONFIG_COMMON_CLK u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, unsigned long target_rate, u32 *new_div); @@ -575,29 +387,14 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); -#else -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, - u32 *new_div); -void omap2_init_clksel_parent(struct clk *clk); -unsigned long omap2_clksel_recalc(struct clk *clk); -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); -int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); -#endif /* clkt_iclk.c public functions */ extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -#ifdef CONFIG_COMMON_CLK u8 omap2_init_dpll_parent(struct clk_hw *hw); unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); -#else -u32 omap2_get_dpll_rate(struct clk *clk); -void omap2_init_dpll_parent(struct clk *clk); -#endif -#ifdef CONFIG_COMMON_CLK int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); @@ -611,14 +408,6 @@ void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); int omap2_clk_disable_autoidle_all(void); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); -#else -int omap2_dflt_clk_enable(struct clk *clk); -void omap2_dflt_clk_disable(struct clk *clk); -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit); -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val); -#endif int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -665,17 +454,9 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; -#ifndef CONFIG_COMMON_CLK -/* clocks shared between various OMAP SoCs */ -extern struct clk virt_19200000_ck; -extern struct clk virt_26000000_ck; -#endif - extern int am33xx_clk_init(void); -#ifdef CONFIG_COMMON_CLK extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); -#endif #endif diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index c0d02a97b768..ef4d21bfb964 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -16,6 +16,7 @@ * OMAP3xxx clock definition files. */ +#include <linux/clk-private.h> #include "clock.h" /* clksel_rate data common to 24xx/343x */ @@ -115,9 +116,6 @@ const struct clksel_rate div31_1to31_rates[] = { }; /* Clocks shared between various OMAP SoCs */ -#ifdef CONFIG_COMMON_CLK - -#include <linux/clk-private.h> static struct clk_ops dummy_ck_ops = {}; @@ -126,19 +124,3 @@ struct clk dummy_ck = { .ops = &dummy_ck_ops, .flags = CLK_IS_BASIC, }; - -#else - -struct clk virt_19200000_ck = { - .name = "virt_19200000_ck", - .ops = &clkops_null, - .rate = 19200000, -}; - -struct clk virt_26000000_ck = { - .name = "virt_26000000_ck", - .ops = &clkops_null, - .rate = 26000000, -}; - -#endif diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index be6fe356ddba..384873580b23 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -997,11 +997,9 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) spin_lock_irqsave(&clkdm->lock, flags); -#ifdef CONFIG_COMMON_CLK /* corner case: disabling unused clocks */ if (__clk_get_enable_count(clk) == 0) goto ccd_exit; -#endif if (atomic_read(&clkdm->usecount) == 0) { spin_unlock_irqrestore(&clkdm->lock, flags); @@ -1019,9 +1017,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) pr_debug("clockdomain: %s: disabled\n", clkdm->name); -#ifdef CONFIG_COMMON_CLK ccd_exit: -#endif spin_unlock_irqrestore(&clkdm->lock, flags); return 0; |