diff options
Diffstat (limited to 'Documentation/ABI/stable/sysfs-driver-mlxreg-io')
| -rw-r--r-- | Documentation/ABI/stable/sysfs-driver-mlxreg-io | 273 |
1 files changed, 272 insertions, 1 deletions
diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io index af0cbf143c48..f59461111221 100644 --- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io +++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io @@ -522,7 +522,6 @@ Description: These files allow to each of ASICs by writing 1. The files are write only. - What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/comm_chnl_ready Date: July 2022 KernelVersion: 5.20 @@ -542,3 +541,275 @@ Description: The file indicates COME module hardware configuration. The purpose is to expose some minor BOM changes for the same system SKU. The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_pwr_converter_fail +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file shows the system reset cause due to power converter + devices failure. + Value 1 in file means this is reset cause, 0 - otherwise. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_ap_reset +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_ap_reset +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files aim to monitor the status of the External Root of Trust (EROT) + processor's RESET output to the Application Processor (AP). + By reading this file, could be determined if the EROT has invalidated or + revoked AP Firmware, at which point it will hold the AP in RESET until a + valid firmware is loaded. This protects the AP from running an + unauthorized firmware. In the normal flow, the AP reset should be released + after the EROT validates the integrity of the FW, and it should be done so + as quickly as possible so that the AP boots before the CPU starts to + communicate to each ASIC. + + The files are read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_recovery +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_recovery +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_reset +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_reset +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files aim to perform External Root of Trust (EROT) recovery + sequence after EROT device failure. + These EROT devices protect ASICs from unauthorized access and in normal + flow their reset should be released with system power – earliest power + up stage, so that EROTs can begin boot and authentication process before + CPU starts to communicate to ASICs. + Issuing a reset to the EROT while asserting the recovery signal will cause + the EROT Application Processor to enter recovery mode so that the EROT FW + can be updated/recovered. + For reset/recovery the related file should be toggled by 1/0. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_wp +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_wp +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files allow access to External Root of Trust (EROT) for reset + and recovery sequence after EROT device failure. + Default is 0 (programming disabled). + If the system is in locked-down mode writing this file will not be allowed. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/spi_chnl_select +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file allows SPI chip selection for External Root of Trust (EROT) + device Out-of-Band recovery. + File can be written with 0 or with 1. It selects which EROT can be accessed + through SPI device. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_pg_fail +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak vadimp@nvidia.com +Description: This file shows ASIC Power Good status. + Value 1 in file means ASIC Power Good failed, 0 - otherwise. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd1_boot_fail +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd2_boot_fail +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_fail +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak vadimp@nvidia.com +Description: These files are related to clock boards status in system. + - clk_brd1_boot_fail: warning about 1-st clock board failed to boot from CI. + - clk_brd2_boot_fail: warning about 2-nd clock board failed to boot from CI. + - clk_brd_fail: error about common clock board boot failure. + + The files are read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_prog_en +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file enables programming of clock boards. + Default is 0 (programming disabled). + If the system is in locked-down mode writing this file will not be allowed. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_converter_prog_en +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file enables programming of power converters. + Default is 0 (programming disabled). + If the system is in locked-down mode writing this file will not be allowed. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_ac_ok_fail +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file shows the system reset cause due to AC power failure. + Value 1 in file means this is reset cause, 0 - otherwise. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_pn +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version_min +Date: August 2023 +KernelVersion: 6.6 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files show with which CPLD part numbers, version and minor + versions have been burned the 5-th CPLD device equipped on a + system. + + The files are read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_cap +Date: August 2023 +KernelVersion: 6.6 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file indicates the available method of CPLD/FPGA devices + field update through the JTAG chain: + + b00 - field update through LPC bus register memory space. + b01 - Reserved. + b10 - Reserved. + b11 - field update through CPU GPIOs bit-banging. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lid_open +Date: August 2023 +KernelVersion: 6.6 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: 1 - indicates that system lid is opened, otherwise 0. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_long_pwr_pb +Date: August 2023 +KernelVersion: 6.6 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file if set 1 indicates that system has been reset by + long press of power button. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_swb_dc_dc_pwr_fail +Date: August 2023 +KernelVersion: 6.6 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file shows 1 in case the system reset happened due to the + failure of any DC-DC power converter devices equipped on the + switch board. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/global_wp_request +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file when written 1 activates request to allow access to + the write protected flashes. Such request can be performed only + for system equipped with BMC (Board Management Controller), + which can grant access to protected flashes. In case BMC allows + access - it will respond with "global_wp_response". BMC decides + regarding time window of granted access. After granted window is + expired, BMC will change value back to 0. + Default value is 0. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/global_wp_response +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file, when set 1, indicates that access to protected + flashes have been granted to host CPU by BMC. + Default value is 0. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/shutdown_unlock +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: When ASICs are getting overheated, system protection + hardware mechanism enforces system reboot. After system + reboot ASICs come up in locked state. To unlock ASICs, + this file should be written 1 + Default value is 0. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/boot_progress +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files show the Data Process Unit board boot progress + state. Valid states are: + - 4 : OS starting. + - 5 : OS running. + - 6 : Low-Power Standby. + + The file is read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/dpu_id +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file shows hardware Id of Data Process Unit board. + + The file is read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_reload +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_dpu_thermal +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/reset_from_main_board +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files expose the cause of the most recent reset of the Data + Processing Unit (DPU) board. The possible causes are: + - Power auxiliary outage or power reload. + - Thermal shutdown. + - Reset request from the main board. + Value 1 in file means this is reset cause, 0 - otherwise. Only one of + the above causes could be 1 at the same time, representing only last + reset cause. + + The files are read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/perst_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/phy_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/tpm_rst +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/usbphy_rst +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files allow to reset hardware components of Data Process + Unit board. Respectively PCI, Ethernet PHY, TPM and USB PHY + resets. + Default values for all the attributes is 1. Writing 0 will + cause reset of the related component. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/*-00**/mlxreg-io.*/hwmon/hwmon*/ufm_upgrade +Date: May 2025 +KernelVersion: 6.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files show status of Unified Fabric Manager upgrade. + state. 0 - means upgrade is done, 1 - otherwise. + + The file is read only. |