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-rw-r--r--Documentation/devicetree/bindings/arm/cpus.yaml33
1 files changed, 33 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 490ce99010b6..a01814765ddb 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -300,6 +300,39 @@ properties:
While optional, it is the preferred way to get access to
the cpu-core power-domains.
+ secondary-boot-reg:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: |
+ Required for systems that have an "enable-method" property value of
+ "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
+
+ This includes the following SoCs: |
+ BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
+ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+ The secondary-boot-reg property is a u32 value that specifies the
+ physical address of the register used to request the ROM holding pen
+ code release a secondary CPU. The value written to the register is
+ formed by encoding the target CPU id into the low bits of the
+ physical start address it should jump to.
+
+if:
+ # If the enable-method property contains one of those values
+ properties:
+ enable-method:
+ contains:
+ enum:
+ - brcm,bcm11351-cpu-method
+ - brcm,bcm23550
+ - brcm,bcm-nsp-smp
+ # and if enable-method is present
+ required:
+ - enable-method
+
+then:
+ required:
+ - secondary-boot-reg
+
required:
- device_type
- reg