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Diffstat (limited to 'Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml | 159 |
1 files changed, 159 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml new file mode 100644 index 000000000000..502cd723511f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC9860 clock + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + compatible: + enum: + - sprd,sc9860-agcp-gate + - sprd,sc9860-aonsecure-clk + - sprd,sc9860-aon-gate + - sprd,sc9860-aon-prediv + - sprd,sc9860-apahb-gate + - sprd,sc9860-apapb-gate + - sprd,sc9860-ap-clk + - sprd,sc9860-cam-clk + - sprd,sc9860-cam-gate + - sprd,sc9860-disp-clk + - sprd,sc9860-disp-gate + - sprd,sc9860-gpu-clk + - sprd,sc9860-pll + - sprd,sc9860-pmu-gate + - sprd,sc9860-vsp-clk + - sprd,sc9860-vsp-gate + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + '#clock-cells': + const: 1 + + sprd,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the syscon which is in the same address area with the + clock, and so we can get regmap for the clocks from the syscon device + +required: + - compatible + - clocks + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-agcp-gate + - sprd,sc9860-aon-gate + - sprd,sc9860-apahb-gate + - sprd,sc9860-apapb-gate + - sprd,sc9860-cam-gate + - sprd,sc9860-disp-gate + - sprd,sc9860-gpu-clk + - sprd,sc9860-pll + - sprd,sc9860-pmu-gate + - sprd,sc9860-vsp-gate + then: + properties: + clocks: + maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-aonsecure-clk + - sprd,sc9860-cam-clk + - sprd,sc9860-disp-clk + - sprd,sc9860-vsp-clk + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-aon-prediv + - sprd,sc9860-ap-clk + then: + properties: + clocks: + minItems: 3 + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-aonsecure-clk + - sprd,sc9860-aon-prediv + - sprd,sc9860-ap-clk + - sprd,sc9860-cam-clk + - sprd,sc9860-disp-clk + - sprd,sc9860-gpu-clk + - sprd,sc9860-vsp-clk + then: + required: + - reg + properties: + sprd,syscon: false + - if: + properties: + compatible: + contains: + enum: + - sprd,sc9860-agcp-gate + - sprd,sc9860-aon-gate + - sprd,sc9860-apahb-gate + - sprd,sc9860-apapb-gate + - sprd,sc9860-cam-gate + - sprd,sc9860-disp-gate + - sprd,sc9860-pll + - sprd,sc9860-pmu-gate + - sprd,sc9860-vsp-gate + then: + required: + - sprd,syscon + properties: + reg: false + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pmu-gate { + compatible = "sprd,sc9860-pmu-gate"; + clocks = <&ext_26m>; + #clock-cells = <1>; + sprd,syscon = <&pmu_regs>; + }; + + clock-controller@20000000 { + compatible = "sprd,sc9860-ap-clk"; + reg = <0 0x20000000 0 0x400>; + clocks = <&ext_26m>, <&pll 0>, <&pmu_gate 0>; + #clock-cells = <1>; + }; + }; +... |