diff options
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 39 |
1 files changed, 28 insertions, 11 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index 9f7d3e11aacb..bfd30aae682b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -49,7 +49,7 @@ properties: The 2nd cell contains the interrupt number for the interrupt type. SPI interrupts are in the range [0-987]. PPI interrupts are in the - range [0-15]. Extented SPI interrupts are in the range [0-1023]. + range [0-15]. Extended SPI interrupts are in the range [0-1023]. Extended PPI interrupts are in the range [0-127]. The 3rd cell is the flags, encoded as follows: @@ -60,7 +60,7 @@ properties: The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For - interrupt types other than PPI or PPIs that are not partitionned, + interrupt types other than PPI or PPIs that are not partitioned, this cell must be zero. See the "ppi-partitions" node description below. @@ -106,9 +106,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 4096 + dma-noncoherent: + description: + Present if the GIC redistributors permit programming shareability + and cacheability attributes but are connected to a non-coherent + downstream interconnect. + msi-controller: description: - Only present if the Message Based Interrupt functionnality is + Only present if the Message Based Interrupt functionality is being exposed by the HW, and the mbi-ranges property present. mbi-ranges: @@ -126,19 +132,20 @@ properties: Address property. Base address of an alias of the GICD region containing only the {SET,CLR}SPI registers to be used if isolation is required, and if supported by the HW. - $ref: /schemas/types.yaml#/definitions/uint32-array - items: - minItems: 1 - maxItems: 2 + oneOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - $ref: /schemas/types.yaml#/definitions/uint64 ppi-partitions: type: object + additionalProperties: false description: PPI affinity can be expressed as a single "ppi-partitions" node, containing a set of sub-nodes. patternProperties: "^interrupt-partition-[0-9]+$": type: object + additionalProperties: false properties: affinity: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -164,6 +171,12 @@ properties: resets: maxItems: 1 + mediatek,broken-save-restore-fw: + type: boolean + description: + Asserts that the firmware on this device has issues saving and restoring + GICR registers when the GIC redistributors are powered off. + dependencies: mbi-ranges: [ msi-controller ] msi-controller: [ mbi-ranges ] @@ -185,6 +198,12 @@ patternProperties: compatible: const: arm,gic-v3-its + dma-noncoherent: + description: + Present if the GIC ITS permits programming shareability and + cacheability attributes but is connected to a non-coherent + downstream interconnect. + msi-controller: true "#msi-cells": @@ -203,9 +222,8 @@ patternProperties: (u32, u32) tuple describing the untranslated address and size of the pre-ITS window. $ref: /schemas/types.yaml#/definitions/uint32-array - items: - minItems: 2 - maxItems: 2 + minItems: 2 + maxItems: 2 required: - compatible @@ -287,7 +305,6 @@ examples: }; }; - device@0 { reg = <0 4>; interrupts = <1 1 4 &part0>; |