diff options
Diffstat (limited to 'Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 3fe981b14e2c..587af4968255 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -10,7 +10,7 @@ maintainers: - Rob Herring <robh@kernel.org> allOf: - - $ref: "mtd.yaml#" + - $ref: mtd.yaml# - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: @@ -20,7 +20,7 @@ properties: - pattern: "^((((micron|spansion|st),)?\ (m25p(40|80|16|32|64|128)|\ n25q(32b|064|128a11|128a13|256a|512a|164k)))|\ - atmel,at25df(321a|641|081a)|\ + atmel,at(25|26)df(321a|641|081a)|\ everspin,mr25h(10|40|128|256)|\ (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\ (mxicy|macronix),mx25u(4033|4035)|\ @@ -43,13 +43,18 @@ properties: - const: jedec,spi-nor - const: jedec,spi-nor description: - Must also include "jedec,spi-nor" for any SPI NOR flash that can be - identified by the JEDEC READ ID opcode (0x9F). + SPI NOR flashes compatible with the JEDEC SFDP standard or which may be + identified with the READ ID opcode (0x9F) do not deserve a specific + compatible. They should instead only be matched against the generic + "jedec,spi-nor" compatible. reg: minItems: 1 maxItems: 2 + interrupts: + maxItems: 1 + m25p,fast-read: type: boolean description: @@ -70,12 +75,38 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. + no-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, combined + with the WP# signal, provides hardware data protection for the device. When + the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard + strapped to LOW, the status register nonvolatile bits become read-only and + the WRITE STATUS REGISTER operation will not execute. The only way to exit + this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the + flash device is not connected or is wrongly tied to GND (that includes internal + pull-downs) then status register permanently becomes read-only as the SRWD bit + cannot be reset. This boolean flag can be used on such systems to avoid setting + the SRWD bit while writing the status register. WP# signal hard strapped to GND + can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. If "broken-flash-reset" is present then having this property does not make any difference. + vcc-supply: + description: + Supply for the SPI NOR power. + + spi-cpol: true + spi-cpha: true + +dependencies: + spi-cpol: [ spi-cpha ] + spi-cpha: [ spi-cpol ] + unevaluatedProperties: false examples: |